xref: /netbsd-src/sys/arch/i386/include/pte.h (revision b2809c5e007e9832fa5c6bd6975b29b0152fb05d)
1 /*	$NetBSD: pte.h,v 1.36 2022/08/21 09:12:43 riastradh Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Frank van der Linden for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *      This product includes software developed for the NetBSD Project by
20  *      Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Copyright (c) 1997 Charles D. Cranor and Washington University.
40  * All rights reserved.
41  *
42  * Redistribution and use in source and binary forms, with or without
43  * modification, are permitted provided that the following conditions
44  * are met:
45  * 1. Redistributions of source code must retain the above copyright
46  *    notice, this list of conditions and the following disclaimer.
47  * 2. Redistributions in binary form must reproduce the above copyright
48  *    notice, this list of conditions and the following disclaimer in the
49  *    documentation and/or other materials provided with the distribution.
50  *
51  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
53  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
55  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
56  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
60  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61  */
62 
63 #ifndef _I386_PTE_H_
64 #define _I386_PTE_H_
65 #ifdef _KERNEL_OPT
66 #include "opt_xen.h"
67 #endif
68 
69 /*
70  * The PAE extension extends the size of the PTE to 64 bits (52bits physical
71  * address) and is compatible with the amd64 PTE format. The first level
72  * maps 2M, the second 1G, so a third level page table is introduced to
73  * map the 4GB virtual address space. This PD has only 4 entries.
74  * We can't use recursive mapping at level 3 to map the PD pages, as this
75  * would eat one GB of address space. In addition, Xen imposes restrictions
76  * on the entries we put in the L3 page (for example, the page pointed to by
77  * the last slot can't be shared among different L3 pages), which makes
78  * handling this L3 page in the same way we do for L2 on i386 (or L4 on amd64)
79  * difficult. For most things we'll just pretend to have only 2 levels,
80  * with the 2 high bits of the L2 index being in fact the index in the
81  * L3.
82  */
83 
84 #if !defined(_LOCORE)
85 
86 /*
87  * here we define the data types for PDEs and PTEs
88  */
89 #include <sys/stdint.h>
90 #ifdef PAE
91 typedef uint64_t pd_entry_t;		/* PDE */
92 typedef uint64_t pt_entry_t;		/* PTE */
93 #else
94 typedef uint32_t pd_entry_t;		/* PDE */
95 typedef uint32_t pt_entry_t;		/* PTE */
96 #endif
97 
98 #endif
99 
100 /*
101  * Mask to get rid of the sign-extended part of addresses.
102  */
103 #define VA_SIGN_MASK		0
104 #define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
105 /*
106  * XXXfvdl this one's not right.
107  */
108 #define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
109 
110 #ifdef PAE
111 #define L1_SHIFT	12
112 #define L2_SHIFT	21
113 #define L3_SHIFT	30
114 #define NBPD_L1		(1ULL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
115 #define NBPD_L2		(1ULL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
116 #define NBPD_L3		(1ULL << L3_SHIFT) /* # bytes mapped by L3 ent (1GB) */
117 
118 #define L3_MASK		0xc0000000
119 #define L2_REALMASK	0x3fe00000
120 #define L2_MASK		(L2_REALMASK | L3_MASK)
121 #define L1_MASK		0x001ff000
122 
123 #define L3_FRAME	(L3_MASK)
124 #define L2_FRAME	(L3_FRAME | L2_MASK)
125 #define L1_FRAME	(L2_FRAME|L1_MASK)
126 
127 #define PTE_4KFRAME	0x000ffffffffff000ULL
128 #define PTE_2MFRAME	0x000fffffffe00000ULL
129 
130 #define PTE_FRAME	PTE_4KFRAME
131 #define PTE_LGFRAME	PTE_2MFRAME
132 
133 /* macros to get real L2 and L3 index, from our "extended" L2 index */
134 #define l2tol3(idx)	((idx) >> (L3_SHIFT - L2_SHIFT))
135 #define l2tol2(idx)	((idx) & (L2_REALMASK >>  L2_SHIFT))
136 
137 #else /* PAE */
138 
139 #define L1_SHIFT	12
140 #define L2_SHIFT	22
141 #define NBPD_L1		(1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
142 #define NBPD_L2		(1UL << L2_SHIFT) /* # bytes mapped by L2 ent (4MB) */
143 
144 #define L2_MASK		0xffc00000
145 #define L1_MASK		0x003ff000
146 
147 #define L2_FRAME	(L2_MASK)
148 #define L1_FRAME	(L2_FRAME|L1_MASK)
149 
150 #define PTE_4KFRAME	0xfffff000
151 #define PTE_4MFRAME	0xffc00000
152 
153 #define PTE_FRAME	PTE_4KFRAME
154 #define PTE_LGFRAME	PTE_4MFRAME
155 
156 #endif /* PAE */
157 
158 /*
159  * x86 PTE/PDE bits.
160  */
161 #define PTE_P		0x00000001	/* Present */
162 #define PTE_W		0x00000002	/* Write */
163 #define PTE_U		0x00000004	/* User */
164 #define PTE_PWT		0x00000008	/* Write-Through */
165 #define PTE_PCD		0x00000010	/* Cache-Disable */
166 #define PTE_A		0x00000020	/* Accessed */
167 #define PTE_D		0x00000040	/* Dirty */
168 #define PTE_PAT		0x00000080	/* PAT on 4KB Pages */
169 #define PTE_PS		0x00000080	/* Large Page Size */
170 #define PTE_G		0x00000100	/* Global Translation */
171 #define PTE_AVL1	0x00000200	/* Ignored by Hardware */
172 #define PTE_AVL2	0x00000400	/* Ignored by Hardware */
173 #define PTE_AVL3	0x00000800	/* Ignored by Hardware */
174 #define PTE_LGPAT	0x00001000	/* PAT on Large Pages */
175 #ifdef PAE
176 #define PTE_NX	0x8000000000000000ULL	/* No Execute */
177 #else
178 #define PTE_NX		0		/* Dummy */
179 #endif
180 
181 #define	_MACHINE_PTE_H_X86
182 #include <x86/pte.h>
183 #undef	_MACHINE_PTE_H_X86
184 
185 #endif /* _I386_PTE_H_ */
186