xref: /netbsd-src/sys/dev/pci/if_jme.c (revision 481d3881954fd794ca5f2d880b68c53a5db8620e)
1 /*	$NetBSD: if_jme.c,v 1.57 2024/07/05 04:31:51 rin Exp $	*/
2 
3 /*
4  * Copyright (c) 2008 Manuel Bouyer.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 /*-
28  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
29  * All rights reserved.
30  *
31  * Redistribution and use in source and binary forms, with or without
32  * modification, are permitted provided that the following conditions
33  * are met:
34  * 1. Redistributions of source code must retain the above copyright
35  *    notice unmodified, this list of conditions, and the following
36  *    disclaimer.
37  * 2. Redistributions in binary form must reproduce the above copyright
38  *    notice, this list of conditions and the following disclaimer in the
39  *    documentation and/or other materials provided with the distribution.
40  *
41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51  * SUCH DAMAGE.
52  */
53 
54 
55 /*
56  * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast)
57  * Ethernet Controllers.
58  */
59 
60 #include <sys/cdefs.h>
61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.57 2024/07/05 04:31:51 rin Exp $");
62 
63 
64 #include <sys/param.h>
65 #include <sys/systm.h>
66 #include <sys/mbuf.h>
67 #include <sys/protosw.h>
68 #include <sys/socket.h>
69 #include <sys/ioctl.h>
70 #include <sys/errno.h>
71 #include <sys/kernel.h>
72 #include <sys/proc.h>	/* only for declaration of wakeup() used by vm.h */
73 #include <sys/device.h>
74 #include <sys/syslog.h>
75 #include <sys/sysctl.h>
76 
77 #include <net/if.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_dl.h>
81 #include <net/route.h>
82 #include <net/bpf.h>
83 
84 #include <sys/rndsource.h>
85 
86 #include <netinet/in.h>
87 #include <netinet/in_systm.h>
88 #include <netinet/ip.h>
89 #include <netinet/ip_var.h>
90 
91 #include <netinet6/ip6_var.h>
92 
93 #ifdef INET
94 #include <netinet/in_var.h>
95 #endif
96 
97 #include <netinet/tcp.h>
98 #include <netinet/tcp_timer.h>
99 #include <netinet/tcp_var.h>
100 
101 #include <net/if_ether.h>
102 #if defined(INET)
103 #include <netinet/if_inarp.h>
104 #endif
105 
106 #include <sys/bus.h>
107 #include <sys/intr.h>
108 
109 #include <dev/pci/pcireg.h>
110 #include <dev/pci/pcivar.h>
111 #include <dev/pci/pcidevs.h>
112 #include <dev/pci/if_jmereg.h>
113 
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
116 
117 /* number of entries in transmit and receive rings */
118 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc))
119 
120 #define JME_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
121 
122 /* Water mark to kick reclaiming Tx buffers. */
123 #define JME_TX_DESC_HIWAT	(JME_NBUFS - (((JME_NBUFS) * 3) / 10))
124 
125 
126 struct jme_softc {
127 	device_t jme_dev;		/* base device */
128 	bus_space_tag_t jme_bt_mac;
129 	bus_space_handle_t jme_bh_mac;	/* Mac registers */
130 	bus_space_tag_t jme_bt_phy;
131 	bus_space_handle_t jme_bh_phy;	/* PHY registers */
132 	bus_space_tag_t jme_bt_misc;
133 	bus_space_handle_t jme_bh_misc; /* Misc registers */
134 	bus_dma_tag_t jme_dmatag;
135 	bus_dma_segment_t jme_txseg;	/* transmit ring seg */
136 	bus_dmamap_t jme_txmap;		/* transmit ring DMA map */
137 	struct jme_desc* jme_txring;	/* transmit ring */
138 	bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */
139 	struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */
140 	int jme_tx_cons;		/* transmit ring consumer */
141 	int jme_tx_prod;		/* transmit ring producer */
142 	int jme_tx_cnt;			/* transmit ring active count */
143 	bus_dma_segment_t jme_rxseg;	/* receive ring seg */
144 	bus_dmamap_t jme_rxmap;		/* receive ring DMA map */
145 	struct jme_desc* jme_rxring;	/* receive ring */
146 	bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */
147 	struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */
148 	int jme_rx_cons;		/* receive ring consumer */
149 	int jme_rx_prod;		/* receive ring producer */
150 	void* jme_ih;			/* our interrupt */
151 	struct ethercom jme_ec;
152 	struct callout jme_tick_ch;	/* tick callout */
153 	uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */
154 	uint8_t jme_phyaddr;		/* address of integrated phy */
155 	uint8_t jme_chip_rev;		/* chip revision */
156 	uint8_t jme_rev;		/* PCI revision */
157 	mii_data_t jme_mii;		/* mii bus */
158 	uint32_t jme_flags;		/* device features, see below */
159 	uint32_t jme_txcsr;		/* TX config register */
160 	uint32_t jme_rxcsr;		/* RX config register */
161 	krndsource_t rnd_source;
162 	/* interrupt coalition parameters */
163 	struct sysctllog *jme_clog;
164 	int jme_intrxto;		/* interrupt RX timeout */
165 	int jme_intrxct;		/* interrupt RX packets counter */
166 	int jme_inttxto;		/* interrupt TX timeout */
167 	int jme_inttxct;		/* interrupt TX packets counter */
168 };
169 
170 #define JME_FLAG_FPGA	0x0001 /* FPGA version */
171 #define JME_FLAG_GIGA	0x0002 /* giga Ethernet capable */
172 
173 
174 #define jme_if	jme_ec.ec_if
175 #define jme_bpf	jme_if.if_bpf
176 
177 typedef struct jme_softc jme_softc_t;
178 typedef u_long ioctl_cmd_t;
179 
180 static int jme_pci_match(device_t, cfdata_t, void *);
181 static void jme_pci_attach(device_t, device_t, void *);
182 static void jme_intr_rx(jme_softc_t *);
183 static int jme_intr(void *);
184 
185 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
186 static int jme_mediachange(struct ifnet *);
187 static void jme_ifwatchdog(struct ifnet *);
188 static bool jme_shutdown(device_t, int);
189 
190 static void jme_txeof(struct jme_softc *);
191 static void jme_ifstart(struct ifnet *);
192 static void jme_reset(jme_softc_t *);
193 static int  jme_ifinit(struct ifnet *);
194 static int  jme_init(struct ifnet *, int);
195 static void jme_stop(struct ifnet *, int);
196 // static void jme_restart(void *);
197 static void jme_ticks(void *);
198 static void jme_mac_config(jme_softc_t *);
199 static void jme_set_filter(jme_softc_t *);
200 
201 static int jme_mii_read(device_t, int, int, uint16_t *);
202 static int jme_mii_write(device_t, int, int, uint16_t);
203 static void jme_statchg(struct ifnet *);
204 
205 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
206 static int jme_eeprom_macaddr(struct jme_softc *);
207 static int jme_reg_macaddr(struct jme_softc *);
208 
209 #define JME_TIMEOUT		1000
210 #define JME_PHY_TIMEOUT		1000
211 #define JME_EEPROM_TIMEOUT	1000
212 
213 static int jme_sysctl_intrxto(SYSCTLFN_PROTO);
214 static int jme_sysctl_intrxct(SYSCTLFN_PROTO);
215 static int jme_sysctl_inttxto(SYSCTLFN_PROTO);
216 static int jme_sysctl_inttxct(SYSCTLFN_PROTO);
217 static int jme_root_num;
218 
219 
220 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t),
221     jme_pci_match, jme_pci_attach, NULL, NULL);
222 
223 static const struct device_compatible_entry compat_data[] = {
224 	{ .id = PCI_ID_CODE(PCI_VENDOR_JMICRON,
225 		PCI_PRODUCT_JMICRON_JMC250),
226 	  .data = "JMicron JMC250 Gigabit Ethernet Controller" },
227 
228 	{ .id = PCI_ID_CODE(PCI_VENDOR_JMICRON,
229 		PCI_PRODUCT_JMICRON_JMC260),
230 	  .data = "JMicron JMC260 Gigabit Ethernet Controller" },
231 
232 	PCI_COMPAT_EOL
233 };
234 
235 static int
jme_pci_match(device_t parent,cfdata_t cf,void * aux)236 jme_pci_match(device_t parent, cfdata_t cf, void *aux)
237 {
238 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
239 
240 	return pci_compatible_match(pa, compat_data);
241 }
242 
243 static void
jme_pci_attach(device_t parent,device_t self,void * aux)244 jme_pci_attach(device_t parent, device_t self, void *aux)
245 {
246 	jme_softc_t *sc = device_private(self);
247 	struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
248 	const struct device_compatible_entry *dce;
249 	struct ifnet * const ifp = &sc->jme_if;
250 	struct mii_data * const mii = &sc->jme_mii;
251 	bus_space_tag_t iot1, iot2, memt;
252 	bus_space_handle_t ioh1, ioh2, memh;
253 	bus_size_t size, size2;
254 	pci_intr_handle_t intrhandle;
255 	const char *intrstr;
256 	pcireg_t csr;
257 	int nsegs, i;
258 	const struct sysctlnode *node;
259 	int jme_nodenum;
260 	char intrbuf[PCI_INTRSTR_LEN];
261 
262 	sc->jme_dev = self;
263 	aprint_normal("\n");
264 	callout_init(&sc->jme_tick_ch, 0);
265 	callout_setfunc(&sc->jme_tick_ch, jme_ticks, sc);
266 
267 	dce = pci_compatible_lookup(pa, compat_data);
268 	KASSERT(dce != NULL);
269 
270 	if (PCI_PRODUCT(dce->id) == PCI_PRODUCT_JMICRON_JMC250)
271 		sc->jme_flags = JME_FLAG_GIGA;
272 
273 	/*
274 	 * Map the card space. Try Mem first.
275 	 */
276 	if (pci_mapreg_map(pa, JME_PCI_BAR0,
277 	    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
278 	    0, &memt, &memh, NULL, &size) == 0) {
279 		sc->jme_bt_mac = memt;
280 		sc->jme_bh_mac = memh;
281 		sc->jme_bt_phy = memt;
282 		if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF,
283 		    JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) {
284 			aprint_error_dev(self, "can't subregion PHY space\n");
285 			bus_space_unmap(memt, memh, size);
286 			return;
287 		}
288 		sc->jme_bt_misc = memt;
289 		if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF,
290 		    JME_MISC_SIZE, &sc->jme_bh_misc) != 0) {
291 			aprint_error_dev(self, "can't subregion misc space\n");
292 			bus_space_unmap(memt, memh, size);
293 			return;
294 		}
295 	} else {
296 		if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO,
297 		    0, &iot1, &ioh1, NULL, &size) != 0) {
298 			aprint_error_dev(self, "can't map I/O space 1\n");
299 			return;
300 		}
301 		sc->jme_bt_mac = iot1;
302 		sc->jme_bh_mac = ioh1;
303 		if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO,
304 		    0, &iot2, &ioh2, NULL, &size2) != 0) {
305 			aprint_error_dev(self, "can't map I/O space 2\n");
306 			bus_space_unmap(iot1, ioh1, size);
307 			return;
308 		}
309 		sc->jme_bt_phy = iot2;
310 		sc->jme_bh_phy = ioh2;
311 		sc->jme_bt_misc = iot2;
312 		if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF,
313 		    JME_MISC_SIZE, &sc->jme_bh_misc) != 0) {
314 			aprint_error_dev(self, "can't subregion misc space\n");
315 			bus_space_unmap(iot1, ioh1, size);
316 			bus_space_unmap(iot2, ioh2, size2);
317 			return;
318 		}
319 	}
320 
321 	if (pci_dma64_available(pa))
322 		sc->jme_dmatag = pa->pa_dmat64;
323 	else
324 		sc->jme_dmatag = pa->pa_dmat;
325 
326 	/* Enable the device. */
327 	csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
328 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
329 	    csr | PCI_COMMAND_MASTER_ENABLE);
330 
331 	aprint_normal_dev(self, "%s\n", (const char *)dce->data);
332 
333 	sc->jme_rev = PCI_REVISION(pa->pa_class);
334 
335 	csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE);
336 	if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
337 	    CHIPMODE_NOT_FPGA)
338 		sc->jme_flags |= JME_FLAG_FPGA;
339 	sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
340 	aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: "
341 	    "0x%x", sc->jme_rev, sc->jme_chip_rev);
342 	if (sc->jme_flags & JME_FLAG_FPGA)
343 		aprint_verbose(" FPGA revision: 0x%x",
344 		    (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT);
345 	aprint_verbose("\n");
346 
347 	/*
348 	 * Save PHY address.
349 	 * Integrated JR0211 has fixed PHY address whereas FPGA version
350 	 * requires PHY probing to get correct PHY address.
351 	 */
352 	if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
353 		sc->jme_phyaddr =
354 		    bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
355 				     JME_GPREG0) & GPREG0_PHY_ADDR_MASK;
356 	} else
357 		sc->jme_phyaddr = 0;
358 
359 
360 	jme_reset(sc);
361 
362 	/* read mac addr */
363 	if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) {
364 		aprint_error_dev(self, "error reading Ethernet address\n");
365 		/* return; */
366 	}
367 	aprint_normal_dev(self, "Ethernet address %s\n",
368 	    ether_sprintf(sc->jme_enaddr));
369 
370 	/* Map and establish interrupts */
371 	if (pci_intr_map(pa, &intrhandle)) {
372 		aprint_error_dev(self, "couldn't map interrupt\n");
373 		return;
374 	}
375 	intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
376 	sc->jme_if.if_softc = sc;
377 	sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET,
378 	    jme_intr, sc, device_xname(self));
379 	if (sc->jme_ih == NULL) {
380 		aprint_error_dev(self, "couldn't establish interrupt");
381 		if (intrstr != NULL)
382 			aprint_error(" at %s", intrstr);
383 		aprint_error("\n");
384 		return;
385 	}
386 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
387 
388 	/* allocate and map DMA-safe memory for transmit ring */
389 	if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
390 	    &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 ||
391 	    bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg,
392 	    nsegs, PAGE_SIZE, (void **)&sc->jme_txring,
393 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 ||
394 	    bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0,
395 	    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 ||
396 	    bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring,
397 	    PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) {
398 		aprint_error_dev(self, "can't allocate DMA memory TX ring\n");
399 		return;
400 	}
401 	/* allocate and map DMA-safe memory for receive ring */
402 	if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
403 	      &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 ||
404 	    bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg,
405 	      nsegs, PAGE_SIZE, (void **)&sc->jme_rxring,
406 	      BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 ||
407 	    bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0,
408 	      BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 ||
409 	    bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring,
410 	      PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) {
411 		aprint_error_dev(self, "can't allocate DMA memory RX ring\n");
412 		return;
413 	}
414 	for (i = 0; i < JME_NBUFS; i++) {
415 		sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL;
416 		if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN,
417 		    JME_NBUFS, JME_MAX_TX_LEN, 0,
418 		    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
419 		    &sc->jme_txmbufm[i]) != 0) {
420 			aprint_error_dev(self, "can't allocate DMA TX map\n");
421 			return;
422 		}
423 		if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN,
424 		    1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
425 		    &sc->jme_rxmbufm[i]) != 0) {
426 			aprint_error_dev(self, "can't allocate DMA RX map\n");
427 			return;
428 		}
429 	}
430 	/*
431 	 * Initialize our media structures and probe the MII.
432 	 *
433 	 * Note that we don't care about the media instance.  We
434 	 * are expecting to have multiple PHYs on the 10/100 cards,
435 	 * and on those cards we exclude the internal PHY from providing
436 	 * 10baseT.  By ignoring the instance, it allows us to not have
437 	 * to specify it on the command line when switching media.
438 	 */
439 	mii->mii_ifp = ifp;
440 	mii->mii_readreg = jme_mii_read;
441 	mii->mii_writereg = jme_mii_write;
442 	mii->mii_statchg = jme_statchg;
443 	sc->jme_ec.ec_mii = mii;
444 	ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange,
445 	    ether_mediastatus);
446 	mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
447 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
448 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
449 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
450 	} else
451 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
452 
453 	/*
454 	 * We can support 802.1Q VLAN-sized frames.
455 	 */
456 	sc->jme_ec.ec_capabilities |=
457 	    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
458 	sc->jme_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
459 
460 	if (sc->jme_flags & JME_FLAG_GIGA)
461 		sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU;
462 
463 
464 	strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
465 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
466 	ifp->if_ioctl = jme_ifioctl;
467 	ifp->if_start = jme_ifstart;
468 	ifp->if_watchdog = jme_ifwatchdog;
469 	ifp->if_init = jme_ifinit;
470 	ifp->if_stop = jme_stop;
471 	ifp->if_timer = 0;
472 	ifp->if_capabilities |=
473 	    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
474 	    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
475 	    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
476 	    IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */
477 	    IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */
478 	    IFCAP_TSOv4 | IFCAP_TSOv6;
479 	IFQ_SET_READY(&ifp->if_snd);
480 	if_attach(ifp);
481 	ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr);
482 
483 	/*
484 	 * Add shutdown hook so that DMA is disabled prior to reboot.
485 	 */
486 	if (pmf_device_register1(self, NULL, NULL, jme_shutdown))
487 		pmf_class_network_register(self, ifp);
488 	else
489 		aprint_error_dev(self, "couldn't establish power handler\n");
490 
491 	rnd_attach_source(&sc->rnd_source, device_xname(self),
492 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
493 
494 	sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT;
495 	sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT;
496 	sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT;
497 	sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT;
498 	if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
499 	    0, CTLTYPE_NODE, device_xname(sc->jme_dev),
500 	    SYSCTL_DESCR("jme per-controller controls"),
501 	    NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE,
502 	    CTL_EOL) != 0) {
503 		aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n");
504 		return;
505 	}
506 	jme_nodenum = node->sysctl_num;
507 
508 	/* interrupt moderation sysctls */
509 	if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
510 	    CTLFLAG_READWRITE,
511 	    CTLTYPE_INT, "int_rxto",
512 	    SYSCTL_DESCR("jme RX interrupt moderation timer"),
513 	    jme_sysctl_intrxto, 0, (void *)sc,
514 	    0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
515 	    CTL_EOL) != 0) {
516 		aprint_normal_dev(sc->jme_dev,
517 		    "couldn't create int_rxto sysctl node\n");
518 	}
519 	if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
520 	    CTLFLAG_READWRITE,
521 	    CTLTYPE_INT, "int_rxct",
522 	    SYSCTL_DESCR("jme RX interrupt moderation packet counter"),
523 	    jme_sysctl_intrxct, 0, (void *)sc,
524 	    0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
525 	    CTL_EOL) != 0) {
526 		aprint_normal_dev(sc->jme_dev,
527 		    "couldn't create int_rxct sysctl node\n");
528 	}
529 	if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
530 	    CTLFLAG_READWRITE,
531 	    CTLTYPE_INT, "int_txto",
532 	    SYSCTL_DESCR("jme TX interrupt moderation timer"),
533 	    jme_sysctl_inttxto, 0, (void *)sc,
534 	    0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
535 	    CTL_EOL) != 0) {
536 		aprint_normal_dev(sc->jme_dev,
537 		    "couldn't create int_txto sysctl node\n");
538 	}
539 	if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
540 	    CTLFLAG_READWRITE,
541 	    CTLTYPE_INT, "int_txct",
542 	    SYSCTL_DESCR("jme TX interrupt moderation packet counter"),
543 	    jme_sysctl_inttxct, 0, (void *)sc,
544 	    0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
545 	    CTL_EOL) != 0) {
546 		aprint_normal_dev(sc->jme_dev,
547 		    "couldn't create int_txct sysctl node\n");
548 	}
549 }
550 
551 static void
jme_stop_rx(jme_softc_t * sc)552 jme_stop_rx(jme_softc_t *sc)
553 {
554 	uint32_t reg;
555 	int i;
556 
557 	reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR);
558 	if ((reg & RXCSR_RX_ENB) == 0)
559 		return;
560 	reg &= ~RXCSR_RX_ENB;
561 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg);
562 	for (i = JME_TIMEOUT / 10; i > 0; i--) {
563 		DELAY(10);
564 		if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
565 		    JME_RXCSR) & RXCSR_RX_ENB) == 0)
566 			break;
567 	}
568 	if (i == 0)
569 		aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n");
570 
571 }
572 
573 static void
jme_stop_tx(jme_softc_t * sc)574 jme_stop_tx(jme_softc_t *sc)
575 {
576 	uint32_t reg;
577 	int i;
578 
579 	reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR);
580 	if ((reg & TXCSR_TX_ENB) == 0)
581 		return;
582 	reg &= ~TXCSR_TX_ENB;
583 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg);
584 	for (i = JME_TIMEOUT / 10; i > 0; i--) {
585 		DELAY(10);
586 		if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
587 		    JME_TXCSR) & TXCSR_TX_ENB) == 0)
588 			break;
589 	}
590 	if (i == 0)
591 		aprint_error_dev(sc->jme_dev,
592 		    "stopping transmitter timeout!\n");
593 }
594 
595 static void
jme_reset(jme_softc_t * sc)596 jme_reset(jme_softc_t *sc)
597 {
598 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET);
599 	DELAY(10);
600 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0);
601 }
602 
603 static bool
jme_shutdown(device_t self,int howto)604 jme_shutdown(device_t self, int howto)
605 {
606 	jme_softc_t *sc;
607 	struct ifnet *ifp;
608 
609 	sc = device_private(self);
610 	ifp = &sc->jme_if;
611 	jme_stop(ifp, 1);
612 
613 	return true;
614 }
615 
616 static void
jme_stop(struct ifnet * ifp,int disable)617 jme_stop(struct ifnet *ifp, int disable)
618 {
619 	jme_softc_t *sc = ifp->if_softc;
620 	int i;
621 	/* Stop receiver, transmitter. */
622 	jme_stop_rx(sc);
623 	jme_stop_tx(sc);
624 	/* free receive mbufs */
625 	for (i = 0; i < JME_NBUFS; i++) {
626 		if (sc->jme_rxmbuf[i]) {
627 			bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]);
628 			m_freem(sc->jme_rxmbuf[i]);
629 		}
630 		sc->jme_rxmbuf[i] = NULL;
631 	}
632 	/* process completed transmits */
633 	jme_txeof(sc);
634 	/* free abort pending transmits */
635 	for (i = 0; i < JME_NBUFS; i++) {
636 		if (sc->jme_txmbuf[i]) {
637 			bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]);
638 			m_freem(sc->jme_txmbuf[i]);
639 			sc->jme_txmbuf[i] = NULL;
640 		}
641 	}
642 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
643 	ifp->if_timer = 0;
644 }
645 
646 #if 0
647 static void
648 jme_restart(void *v)
649 {
650 
651 	jme_init(v);
652 }
653 #endif
654 
655 static int
jme_add_rxbuf(jme_softc_t * sc,struct mbuf * m)656 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m)
657 {
658 	int error;
659 	bus_dmamap_t map;
660 	int i = sc->jme_rx_prod;
661 
662 	if (sc->jme_rxmbuf[i] != NULL) {
663 		aprint_error_dev(sc->jme_dev,
664 		    "mbuf already here: rxprod %d rxcons %d\n",
665 		    sc->jme_rx_prod, sc->jme_rx_cons);
666 		m_freem(m);
667 		return EINVAL;
668 	}
669 
670 	if (m == NULL) {
671 		sc->jme_rxmbuf[i] = NULL;
672 		MGETHDR(m, M_DONTWAIT, MT_DATA);
673 		if (m == NULL)
674 			return (ENOBUFS);
675 		MCLGET(m, M_DONTWAIT);
676 		if ((m->m_flags & M_EXT) == 0) {
677 			m_freem(m);
678 			return (ENOBUFS);
679 		}
680 	}
681 	map = sc->jme_rxmbufm[i];
682 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
683 	KASSERT(m->m_len == MCLBYTES);
684 
685 	error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m,
686 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
687 	if (error) {
688 		sc->jme_rxmbuf[i] = NULL;
689 		aprint_error_dev(sc->jme_dev,
690 		    "unable to load rx DMA map %d, error = %d\n",
691 		    i, error);
692 		m_freem(m);
693 		return (error);
694 	}
695 	bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize,
696 	    BUS_DMASYNC_PREREAD);
697 
698 	sc->jme_rxmbuf[i] = m;
699 
700 	sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len);
701 	sc->jme_rxring[i].addr_lo =
702 	    htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr));
703 	sc->jme_rxring[i].addr_hi =
704 	    htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr));
705 	sc->jme_rxring[i].flags =
706 	    htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
707 	bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap,
708 	    i * sizeof(struct jme_desc), sizeof(struct jme_desc),
709 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
710 	JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS);
711 	return (0);
712 }
713 
714 static int
jme_ifinit(struct ifnet * ifp)715 jme_ifinit(struct ifnet *ifp)
716 {
717 	return jme_init(ifp, 1);
718 }
719 
720 static int
jme_init(struct ifnet * ifp,int do_ifinit)721 jme_init(struct ifnet *ifp, int do_ifinit)
722 {
723 	jme_softc_t *sc = ifp->if_softc;
724 	int i, s;
725 	uint8_t eaddr[ETHER_ADDR_LEN];
726 	uint32_t reg;
727 
728 	s = splnet();
729 	/* cancel any pending IO */
730 	jme_stop(ifp, 1);
731 	jme_reset(sc);
732 	if ((sc->jme_if.if_flags & IFF_UP) == 0) {
733 		splx(s);
734 		return 0;
735 	}
736 	/* allocate receive ring */
737 	sc->jme_rx_prod = 0;
738 	for (i = 0; i < JME_NBUFS; i++) {
739 		if (jme_add_rxbuf(sc, NULL) < 0) {
740 			aprint_error_dev(sc->jme_dev,
741 			    "can't allocate rx mbuf\n");
742 			for (i--; i >= 0; i--) {
743 				bus_dmamap_unload(sc->jme_dmatag,
744 				    sc->jme_rxmbufm[i]);
745 				m_freem(sc->jme_rxmbuf[i]);
746 				sc->jme_rxmbuf[i] = NULL;
747 			}
748 			splx(s);
749 			return ENOMEM;
750 		}
751 	}
752 	/* init TX ring */
753 	memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc));
754 	bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
755 	    0, JME_NBUFS * sizeof(struct jme_desc),
756 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
757 	for (i = 0; i < JME_NBUFS; i++)
758 		sc->jme_txmbuf[i] = NULL;
759 	sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0;
760 
761 	/* Reprogram the station address. */
762 	memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN);
763 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0,
764 	    eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
765 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
766 	    JME_PAR1, eaddr[5] << 8 | eaddr[4]);
767 
768 	/*
769 	 * Configure Tx queue.
770 	 *  Tx priority queue weight value : 0
771 	 *  Tx FIFO threshold for processing next packet : 16QW
772 	 *  Maximum Tx DMA length : 512
773 	 *  Allow Tx DMA burst.
774 	 */
775 	sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
776 	sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
777 	sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
778 	sc->jme_txcsr |= TXCSR_DMA_SIZE_512;
779 	sc->jme_txcsr |= TXCSR_DMA_BURST;
780 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
781 	     JME_TXCSR, sc->jme_txcsr);
782 
783 	/* Set Tx descriptor counter. */
784 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
785 	     JME_TXQDC, JME_NBUFS);
786 
787 	/* Set Tx ring address to the hardware. */
788 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI,
789 	    JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr));
790 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO,
791 	    JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr));
792 
793 	/* Configure TxMAC parameters. */
794 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC,
795 	    TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB |
796 	    TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB);
797 
798 	/*
799 	 * Configure Rx queue.
800 	 *  FIFO full threshold for transmitting Tx pause packet : 128T
801 	 *  FIFO threshold for processing next packet : 128QW
802 	 *  Rx queue 0 select
803 	 *  Max Rx DMA length : 128
804 	 *  Rx descriptor retry : 32
805 	 *  Rx descriptor retry time gap : 256ns
806 	 *  Don't receive runt/bad frame.
807 	 */
808 	sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
809 	/*
810 	 * Since Rx FIFO size is 4K bytes, receiving frames larger
811 	 * than 4K bytes will suffer from Rx FIFO overruns. So
812 	 * decrease FIFO threshold to reduce the FIFO overruns for
813 	 * frames larger than 4000 bytes.
814 	 * For best performance of standard MTU sized frames use
815 	 * maximum allowable FIFO threshold, 128QW.
816 	 */
817 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
818 	    ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
819 		sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
820 	else
821 		sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
822 	sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
823 	sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
824 	sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
825 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
826 	     JME_RXCSR, sc->jme_rxcsr);
827 
828 	/* Set Rx descriptor counter. */
829 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
830 	     JME_RXQDC, JME_NBUFS);
831 
832 	/* Set Rx ring address to the hardware. */
833 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI,
834 	    JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr));
835 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO,
836 	    JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr));
837 
838 	/* Clear receive filter. */
839 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0);
840 	/* Set up the receive filter. */
841 	jme_set_filter(sc);
842 
843 	/*
844 	 * Disable all WOL bits as WOL can interfere normal Rx
845 	 * operation. Also clear WOL detection status bits.
846 	 */
847 	reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS);
848 	reg &= ~PMCS_WOL_ENB_MASK;
849 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg);
850 
851 	reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
852 	/*
853 	 * Pad 10bytes right before received frame. This will greatly
854 	 * help Rx performance on strict-alignment architectures as
855 	 * it does not need to copy the frame to align the payload.
856 	 */
857 	reg |= RXMAC_PAD_10BYTES;
858 	if ((ifp->if_capenable &
859 	    (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
860 	     IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0)
861 		reg |= RXMAC_CSUM_ENB;
862 	reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */
863 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg);
864 
865 	/* Configure general purpose reg0 */
866 	reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0);
867 	reg &= ~GPREG0_PCC_UNIT_MASK;
868 	/* Set PCC timer resolution to micro-seconds unit. */
869 	reg |= GPREG0_PCC_UNIT_US;
870 	/*
871 	 * Disable all shadow register posting as we have to read
872 	 * JME_INTR_STATUS register in jme_int_task. Also it seems
873 	 * that it's hard to synchronize interrupt status between
874 	 * hardware and software with shadow posting due to
875 	 * requirements of bus_dmamap_sync(9).
876 	 */
877 	reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
878 	    GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
879 	    GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
880 	    GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
881 	/* Disable posting of DW0. */
882 	reg &= ~GPREG0_POST_DW0_ENB;
883 	/* Clear PME message. */
884 	reg &= ~GPREG0_PME_ENB;
885 	/* Set PHY address. */
886 	reg &= ~GPREG0_PHY_ADDR_MASK;
887 	reg |= sc->jme_phyaddr;
888 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg);
889 
890 	/* Configure Tx queue 0 packet completion coalescing. */
891 	reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
892 	reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
893 	reg |= PCCTX_COAL_TXQ0;
894 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
895 
896 	/* Configure Rx queue 0 packet completion coalescing. */
897 	reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
898 	reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
899 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
900 
901 	/* Disable Timers */
902 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0);
903 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0);
904 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0);
905 
906 	/* Configure retry transmit period, retry limit value. */
907 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
908 	    ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
909 	    TXTRHD_RT_PERIOD_MASK) |
910 	    ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
911 	    TXTRHD_RT_LIMIT_SHIFT));
912 
913 	/* Disable RSS. */
914 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
915 	    JME_RSSC, RSSC_DIS_RSS);
916 
917 	/* Initialize the interrupt mask. */
918 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
919 	     JME_INTR_MASK_SET, JME_INTRS_ENABLE);
920 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
921 	     JME_INTR_STATUS, 0xFFFFFFFF);
922 
923 	/* set media, if not already handling a media change */
924 	if (do_ifinit) {
925 		int error;
926 		if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO)
927 			error = 0;
928 		else if (error != 0) {
929 			aprint_error_dev(sc->jme_dev, "could not set media\n");
930 			splx(s);
931 			return error;
932 		}
933 	}
934 
935 	/* Program MAC with resolved speed/duplex/flow-control. */
936 	jme_mac_config(sc);
937 
938 	/* Start receiver/transmitter. */
939 	sc->jme_rx_cons = 0;
940 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR,
941 	    sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START);
942 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR,
943 	    sc->jme_txcsr | TXCSR_TX_ENB);
944 
945 	/* start ticks calls */
946 	callout_schedule(&sc->jme_tick_ch, hz);
947 	sc->jme_if.if_flags |= IFF_RUNNING;
948 	sc->jme_if.if_flags &= ~IFF_OACTIVE;
949 	splx(s);
950 	return 0;
951 }
952 
953 static int
jme_mii_read(device_t self,int phy,int reg,uint16_t * val)954 jme_mii_read(device_t self, int phy, int reg, uint16_t *val)
955 {
956 	struct jme_softc *sc = device_private(self);
957 	int data, i;
958 
959 	/* For FPGA version, PHY address 0 should be ignored. */
960 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
961 		if (phy == 0)
962 			return -1;
963 	} else {
964 		if (sc->jme_phyaddr != phy)
965 			return -1;
966 	}
967 
968 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI,
969 	    SMI_OP_READ | SMI_OP_EXECUTE |
970 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
971 	for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) {
972 		delay(10);
973 		if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
974 		    JME_SMI)) & SMI_OP_EXECUTE) == 0)
975 			break;
976 	}
977 
978 	if (i == 0) {
979 		aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg);
980 		return ETIMEDOUT;
981 	}
982 
983 	*val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
984 	return 0;
985 }
986 
987 static int
jme_mii_write(device_t self,int phy,int reg,uint16_t val)988 jme_mii_write(device_t self, int phy, int reg, uint16_t val)
989 {
990 	struct jme_softc *sc = device_private(self);
991 	int i;
992 
993 	/* For FPGA version, PHY address 0 should be ignored. */
994 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
995 		if (phy == 0)
996 			return -1;
997 	} else {
998 		if (sc->jme_phyaddr != phy)
999 			return -1;
1000 	}
1001 
1002 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI,
1003 	    SMI_OP_WRITE | SMI_OP_EXECUTE |
1004 	    (((uint32_t)val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
1005 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
1006 	for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) {
1007 		delay(10);
1008 		if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
1009 		    JME_SMI)) & SMI_OP_EXECUTE) == 0)
1010 			break;
1011 	}
1012 
1013 	if (i == 0) {
1014 		aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg);
1015 		return ETIMEDOUT;
1016 	}
1017 
1018 	return 0;
1019 }
1020 
1021 static void
jme_statchg(struct ifnet * ifp)1022 jme_statchg(struct ifnet *ifp)
1023 {
1024 	if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1025 		jme_init(ifp, 0);
1026 }
1027 
1028 static void
jme_intr_rx(jme_softc_t * sc)1029 jme_intr_rx(jme_softc_t *sc) {
1030 	struct mbuf *m, *mhead;
1031 	bus_dmamap_t mmap;
1032 	struct ifnet *ifp = &sc->jme_if;
1033 	uint32_t flags,	 buflen;
1034 	int i, ipackets, nsegs, seg, error;
1035 	struct jme_desc *desc;
1036 
1037 	bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0,
1038 	    sizeof(struct jme_desc) * JME_NBUFS,
1039 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1040 #ifdef JMEDEBUG_RX
1041 	printf("rxintr sc->jme_rx_cons %d flags 0x%x\n",
1042 	    sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags));
1043 #endif
1044 	ipackets = 0;
1045 	while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN)
1046 	    == 0) {
1047 		i = sc->jme_rx_cons;
1048 		desc = &sc->jme_rxring[i];
1049 #ifdef JMEDEBUG_RX
1050 		printf("rxintr i %d flags 0x%x buflen 0x%x\n",
1051 		    i, le32toh(desc->flags), le32toh(desc->buflen));
1052 #endif
1053 		if (sc->jme_rxmbuf[i] == NULL) {
1054 			if ((error = jme_add_rxbuf(sc, NULL)) != 0) {
1055 				aprint_error_dev(sc->jme_dev,
1056 				    "can't add new mbuf to empty slot: %d\n",
1057 				    error);
1058 				break;
1059 			}
1060 			JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1061 			i = sc->jme_rx_cons;
1062 			continue;
1063 		}
1064 		if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
1065 			break;
1066 
1067 		buflen = le32toh(desc->buflen);
1068 		nsegs = JME_RX_NSEGS(buflen);
1069 		flags = le32toh(desc->flags);
1070 		if ((buflen & JME_RX_ERR_STAT) != 0 ||
1071 		    JME_RX_BYTES(buflen) < sizeof(struct ether_header) ||
1072 		    JME_RX_BYTES(buflen) >
1073 		    (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) {
1074 #ifdef JMEDEBUG_RX
1075 			printf("rx error flags 0x%x buflen 0x%x\n",
1076 			    flags, buflen);
1077 #endif
1078 			if_statinc(ifp, if_ierrors);
1079 			/* reuse the mbufs */
1080 			for (seg = 0; seg < nsegs; seg++) {
1081 				m = sc->jme_rxmbuf[i];
1082 				sc->jme_rxmbuf[i] = NULL;
1083 				mmap = sc->jme_rxmbufm[i];
1084 				bus_dmamap_sync(sc->jme_dmatag, mmap, 0,
1085 				    mmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1086 				bus_dmamap_unload(sc->jme_dmatag, mmap);
1087 				if ((error = jme_add_rxbuf(sc, m)) != 0)
1088 					aprint_error_dev(sc->jme_dev,
1089 					    "can't reuse mbuf: %d\n", error);
1090 				JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1091 				i = sc->jme_rx_cons;
1092 			}
1093 			continue;
1094 		}
1095 		/* receive this packet */
1096 		mhead = m = sc->jme_rxmbuf[i];
1097 		sc->jme_rxmbuf[i] = NULL;
1098 		mmap = sc->jme_rxmbufm[i];
1099 		bus_dmamap_sync(sc->jme_dmatag, mmap, 0,
1100 		    mmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1101 		bus_dmamap_unload(sc->jme_dmatag, mmap);
1102 		/* add a new buffer to chain */
1103 		if (jme_add_rxbuf(sc, NULL) != 0) {
1104 			if ((error = jme_add_rxbuf(sc, m)) != 0)
1105 				aprint_error_dev(sc->jme_dev,
1106 				    "can't reuse mbuf: %d\n", error);
1107 			JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1108 			i = sc->jme_rx_cons;
1109 			for (seg = 1; seg < nsegs; seg++) {
1110 				m = sc->jme_rxmbuf[i];
1111 				sc->jme_rxmbuf[i] = NULL;
1112 				mmap = sc->jme_rxmbufm[i];
1113 				bus_dmamap_sync(sc->jme_dmatag, mmap, 0,
1114 				    mmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1115 				bus_dmamap_unload(sc->jme_dmatag, mmap);
1116 				if ((error = jme_add_rxbuf(sc, m)) != 0)
1117 					aprint_error_dev(sc->jme_dev,
1118 					    "can't reuse mbuf: %d\n", error);
1119 				JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1120 				i = sc->jme_rx_cons;
1121 			}
1122 			if_statinc(ifp, if_ierrors);
1123 			continue;
1124 		}
1125 
1126 		/* build mbuf chain: head, then remaining segments */
1127 		m_set_rcvif(m, ifp);
1128 		m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES;
1129 		m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) :
1130 		    m->m_pkthdr.len;
1131 		m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES;
1132 		JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1133 		for (seg = 1; seg < nsegs; seg++) {
1134 			i = sc->jme_rx_cons;
1135 			m = sc->jme_rxmbuf[i];
1136 			sc->jme_rxmbuf[i] = NULL;
1137 			mmap = sc->jme_rxmbufm[i];
1138 			bus_dmamap_sync(sc->jme_dmatag, mmap, 0,
1139 			    mmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1140 			bus_dmamap_unload(sc->jme_dmatag, mmap);
1141 			if ((error = jme_add_rxbuf(sc, NULL)) != 0)
1142 				aprint_error_dev(sc->jme_dev,
1143 				    "can't add new mbuf: %d\n", error);
1144 			m->m_flags &= ~M_PKTHDR;
1145 			m_cat(mhead, m);
1146 			JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1147 		}
1148 		/* and adjust last mbuf's size */
1149 		if (nsegs > 1) {
1150 			m->m_len =
1151 			    JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1));
1152 		}
1153 		ipackets++;
1154 
1155 		if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) &&
1156 		    (flags & JME_RD_IPV4)) {
1157 			mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1158 			if (!(flags & JME_RD_IPCSUM))
1159 				mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1160 		}
1161 		if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) &&
1162 		    (flags & JME_RD_TCPV4) == JME_RD_TCPV4) {
1163 			mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1164 			if (!(flags & JME_RD_TCPCSUM))
1165 				mhead->m_pkthdr.csum_flags |=
1166 				    M_CSUM_TCP_UDP_BAD;
1167 		}
1168 		if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) &&
1169 		    (flags & JME_RD_UDPV4) == JME_RD_UDPV4) {
1170 			mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1171 			if (!(flags & JME_RD_UDPCSUM))
1172 				mhead->m_pkthdr.csum_flags |=
1173 				    M_CSUM_TCP_UDP_BAD;
1174 		}
1175 		if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) &&
1176 		    (flags & JME_RD_TCPV6) == JME_RD_TCPV6) {
1177 			mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6;
1178 			if (!(flags & JME_RD_TCPCSUM))
1179 				mhead->m_pkthdr.csum_flags |=
1180 				    M_CSUM_TCP_UDP_BAD;
1181 		}
1182 		if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) &&
1183 		    (flags & JME_RD_UDPV6) == JME_RD_UDPV6) {
1184 			m->m_pkthdr.csum_flags |= M_CSUM_UDPv6;
1185 			if (!(flags & JME_RD_UDPCSUM))
1186 				mhead->m_pkthdr.csum_flags |=
1187 				    M_CSUM_TCP_UDP_BAD;
1188 		}
1189 		if (flags & JME_RD_VLAN_TAG) {
1190 			/* pass to vlan_input() */
1191 			vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK));
1192 		}
1193 		if_percpuq_enqueue(ifp->if_percpuq, mhead);
1194 	}
1195 	if (ipackets)
1196 		rnd_add_uint32(&sc->rnd_source, ipackets);
1197 }
1198 
1199 static int
jme_intr(void * v)1200 jme_intr(void *v)
1201 {
1202 	jme_softc_t *sc = v;
1203 	uint32_t istatus;
1204 
1205 	istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1206 	     JME_INTR_STATUS);
1207 	if (istatus == 0 || istatus == 0xFFFFFFFF)
1208 		return 0;
1209 	/* Disable interrupts. */
1210 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1211 	    JME_INTR_MASK_CLR, 0xFFFFFFFF);
1212 again:
1213 	/* and update istatus */
1214 	istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1215 	     JME_INTR_STATUS);
1216 	if ((istatus & JME_INTRS_CHECK) == 0)
1217 		goto done;
1218 	/* Reset PCC counter/timer and Ack interrupts. */
1219 	if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
1220 		istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1221 	if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
1222 		istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
1223 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1224 	     JME_INTR_STATUS, istatus);
1225 
1226 	if ((sc->jme_if.if_flags & IFF_RUNNING) == 0)
1227 		goto done;
1228 #ifdef JMEDEBUG_RX
1229 	printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x  0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus,
1230 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR),
1231 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO),
1232 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI),
1233 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC),
1234 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA),
1235 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC));
1236 	printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n",
1237 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0),
1238 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1),
1239 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0),
1240 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1),
1241 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC));
1242 #endif
1243 	if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
1244 		jme_intr_rx(sc);
1245 	if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) {
1246 		/*
1247 		 * Notify hardware availability of new Rx
1248 		 * buffers.
1249 		 * Reading RXCSR takes very long time under
1250 		 * heavy load so cache RXCSR value and writes
1251 		 * the ORed value with the kick command to
1252 		 * the RXCSR. This saves one register access
1253 		 * cycle.
1254 		 */
1255 		sc->jme_rx_cons = 0;
1256 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1257 		    JME_RXCSR,
1258 		    sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START);
1259 	}
1260 	if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
1261 		jme_ifstart(&sc->jme_if);
1262 
1263 	goto again;
1264 
1265 done:
1266 	/* enable interrupts. */
1267 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1268 	    JME_INTR_MASK_SET, JME_INTRS_ENABLE);
1269 	return 1;
1270 }
1271 
1272 
1273 static int
jme_ifioctl(struct ifnet * ifp,unsigned long cmd,void * data)1274 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1275 {
1276 	struct jme_softc *sc = ifp->if_softc;
1277 	int s, error;
1278 	struct ifreq *ifr;
1279 	struct ifcapreq *ifcr;
1280 
1281 	s = splnet();
1282 	/*
1283 	 * we can't support at the same time jumbo frames and
1284 	 * TX checksums offload/TSO
1285 	 */
1286 	switch (cmd) {
1287 	case SIOCSIFMTU:
1288 		ifr = data;
1289 		if (ifr->ifr_mtu > JME_TX_FIFO_SIZE &&
1290 		    (ifp->if_capenable & (
1291 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx |
1292 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx |
1293 		    IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) {
1294 			splx(s);
1295 			return EINVAL;
1296 		}
1297 		break;
1298 	case SIOCSIFCAP:
1299 		ifcr = data;
1300 		if (ifp->if_mtu > JME_TX_FIFO_SIZE &&
1301 		    (ifcr->ifcr_capenable & (
1302 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx |
1303 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx |
1304 		    IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) {
1305 			splx(s);
1306 			return EINVAL;
1307 		}
1308 		break;
1309 	}
1310 
1311 	error = ether_ioctl(ifp, cmd, data);
1312 	if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) {
1313 		if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) {
1314 			jme_set_filter(sc);
1315 			error = 0;
1316 		} else {
1317 			error = jme_init(ifp, 0);
1318 		}
1319 	}
1320 	splx(s);
1321 	return error;
1322 }
1323 
1324 static int
jme_encap(struct jme_softc * sc,struct mbuf * const m)1325 jme_encap(struct jme_softc *sc, struct mbuf * const m)
1326 {
1327 	struct jme_desc *desc;
1328 	int error, i, prod, headdsc, nsegs;
1329 	uint32_t cflags, tso_segsz;
1330 
1331 	if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
1332 		/*
1333 		 * Due to the adherence to NDIS specification JMC250
1334 		 * assumes upper stack computed TCP pseudo checksum
1335 		 * without including payload length. This breaks
1336 		 * checksum offload for TSO case so recompute TCP
1337 		 * pseudo checksum for JMC250. Hopefully this wouldn't
1338 		 * be much burden on modern CPUs.
1339 		 */
1340 		bool v4 = (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
1341 		int iphl = v4 ?
1342 		    M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) :
1343 		    M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data);
1344 		/*
1345 		 * note: we support vlan offloading, so we should never have
1346 		 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always
1347 		 * right.
1348 		 */
1349 		int hlen = ETHER_HDR_LEN + iphl;
1350 
1351 		if (__predict_false(m->m_len <
1352 		    (hlen + sizeof(struct tcphdr)))) {
1353 			/*
1354 			 *
1355 			 * TCP/IP headers are not in the first mbuf; we need
1356 			 * to do this the slow and painful way.  Let's just
1357 			 * hope this doesn't happen very often.
1358 			 */
1359 			struct tcphdr th;
1360 
1361 			m_copydata(m, hlen, sizeof(th), &th);
1362 			if (v4) {
1363 				struct ip ip;
1364 
1365 				m_copydata(m, ETHER_HDR_LEN, sizeof(ip), &ip);
1366 				ip.ip_len = 0;
1367 				m_copyback(m,
1368 				    ETHER_HDR_LEN + offsetof(struct ip, ip_len),
1369 				    sizeof(ip.ip_len), &ip.ip_len);
1370 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
1371 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
1372 			} else {
1373 #if INET6
1374 				struct ip6_hdr ip6;
1375 
1376 				m_copydata(m, ETHER_HDR_LEN,
1377 				    sizeof(ip6), &ip6);
1378 				ip6.ip6_plen = 0;
1379 				m_copyback(m, ETHER_HDR_LEN +
1380 				    offsetof(struct ip6_hdr, ip6_plen),
1381 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
1382 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
1383 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
1384 #endif /* INET6 */
1385 			}
1386 			m_copyback(m, hlen + offsetof(struct tcphdr, th_sum),
1387 			    sizeof(th.th_sum), &th.th_sum);
1388 
1389 			hlen += th.th_off << 2;
1390 		} else {
1391 			/*
1392 			 * TCP/IP headers are in the first mbuf; we can do
1393 			 * this the easy way.
1394 			 */
1395 			struct tcphdr *th;
1396 
1397 			if (v4) {
1398 				struct ip *ip =
1399 				    (void *)(mtod(m, char *) +
1400 				    ETHER_HDR_LEN);
1401 				th = (void *)(mtod(m, char *) + hlen);
1402 
1403 				ip->ip_len = 0;
1404 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
1405 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1406 			} else {
1407 #if INET6
1408 				struct ip6_hdr *ip6 =
1409 				    (void *)(mtod(m, char *) +
1410 				    ETHER_HDR_LEN);
1411 				th = (void *)(mtod(m, char *) + hlen);
1412 
1413 				ip6->ip6_plen = 0;
1414 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
1415 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
1416 #endif /* INET6 */
1417 			}
1418 			hlen += th->th_off << 2;
1419 		}
1420 	}
1421 
1422 	prod = sc->jme_tx_prod;
1423 
1424 	error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod],
1425 	    m, BUS_DMA_NOWAIT | BUS_DMA_WRITE);
1426 	if (error) {
1427 		if (error == EFBIG) {
1428 			log(LOG_ERR, "%s: Tx packet consumes too many "
1429 			    "DMA segments, dropping...\n",
1430 			    device_xname(sc->jme_dev));
1431 			/* Caller will free the packet. */
1432 		}
1433 		return (error);
1434 	}
1435 	/*
1436 	 * Check descriptor overrun. Leave one free descriptor.
1437 	 * Since we always use 64bit address mode for transmitting,
1438 	 * each Tx request requires one more dummy descriptor.
1439 	 */
1440 	nsegs = sc->jme_txmbufm[prod]->dm_nsegs;
1441 #ifdef JMEDEBUG_TX
1442 	printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt);
1443 #endif
1444 	if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) {
1445 		bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]);
1446 		return (ENOBUFS);
1447 	}
1448 	bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod],
1449 	    0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE);
1450 
1451 	cflags = 0;
1452 	tso_segsz = 0;
1453 	/* Configure checksum offload and TSO. */
1454 	if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
1455 		tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT;
1456 		cflags |= JME_TD_TSO;
1457 	} else {
1458 		if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0)
1459 			cflags |= JME_TD_IPCSUM;
1460 		if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6))
1461 		    != 0)
1462 			cflags |= JME_TD_TCPCSUM;
1463 		if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6))
1464 		    != 0)
1465 			cflags |= JME_TD_UDPCSUM;
1466 	}
1467 	/* Configure VLAN. */
1468 	if (vlan_has_tag(m)) {
1469 		cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK);
1470 		cflags |= JME_TD_VLAN_TAG;
1471 	}
1472 
1473 	desc = &sc->jme_txring[prod];
1474 	desc->flags = htole32(cflags);
1475 	desc->buflen = htole32(tso_segsz);
1476 	desc->addr_hi = htole32(m->m_pkthdr.len);
1477 	desc->addr_lo = 0;
1478 	headdsc = prod;
1479 	sc->jme_tx_cnt++;
1480 	JME_DESC_INC(prod, JME_NBUFS);
1481 	for (i = 0; i < nsegs; i++) {
1482 		desc = &sc->jme_txring[prod];
1483 		desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1484 		desc->buflen =
1485 		    htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len);
1486 		desc->addr_hi = htole32(
1487 		    JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr));
1488 		desc->addr_lo = htole32(
1489 		    JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr));
1490 		bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1491 		    prod * sizeof(struct jme_desc), sizeof(struct jme_desc),
1492 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1493 		sc->jme_txmbuf[prod] = NULL;
1494 		sc->jme_tx_cnt++;
1495 		JME_DESC_INC(prod, JME_NBUFS);
1496 	}
1497 
1498 	/* Update producer index. */
1499 	sc->jme_tx_prod = prod;
1500 #ifdef JMEDEBUG_TX
1501 	printf("jme_encap prod now %d\n", sc->jme_tx_prod);
1502 #endif
1503 	/*
1504 	 * Finally request interrupt and give the first descriptor
1505 	 * ownership to hardware.
1506 	 */
1507 	desc = &sc->jme_txring[headdsc];
1508 	desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1509 	bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1510 	    headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc),
1511 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1512 
1513 	sc->jme_txmbuf[headdsc] = m;
1514 	return (0);
1515 }
1516 
1517 static void
jme_txeof(struct jme_softc * sc)1518 jme_txeof(struct jme_softc *sc)
1519 {
1520 	struct ifnet *ifp;
1521 	struct jme_desc *desc;
1522 	uint32_t status;
1523 	int cons, cons0, nsegs, seg;
1524 
1525 	ifp = &sc->jme_if;
1526 
1527 #ifdef JMEDEBUG_TX
1528 	printf("jme_txeof cons %d prod %d\n",
1529 	    sc->jme_tx_cons, sc->jme_tx_prod);
1530 	printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x "
1531 	    "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x "
1532 	    "JME_TXTRHD 0x%x\n",
1533 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR),
1534 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO),
1535 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI),
1536 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC),
1537 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA),
1538 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC),
1539 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC),
1540 	    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD));
1541 	for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) {
1542 		desc = &sc->jme_txring[cons];
1543 		printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons,
1544 		    desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo);
1545 		JME_DESC_INC(cons, JME_NBUFS);
1546 	}
1547 #endif
1548 
1549 	cons = sc->jme_tx_cons;
1550 	if (cons == sc->jme_tx_prod)
1551 		return;
1552 
1553 	/*
1554 	 * Go through our Tx list and free mbufs for those
1555 	 * frames which have been transmitted.
1556 	 */
1557 	for (; cons != sc->jme_tx_prod;) {
1558 		bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1559 		    cons * sizeof(struct jme_desc), sizeof(struct jme_desc),
1560 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1561 
1562 		desc = &sc->jme_txring[cons];
1563 		status = le32toh(desc->flags);
1564 #ifdef JMEDEBUG_TX
1565 		printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status,
1566 		    sc->jme_txmbufm[cons]->dm_nsegs);
1567 #endif
1568 		if (status & JME_TD_OWN)
1569 			break;
1570 
1571 		if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
1572 			if_statinc(ifp, if_oerrors);
1573 		else {
1574 			if_statinc(ifp, if_opackets);
1575 			if ((status & JME_TD_COLLISION) != 0) {
1576 				if_statadd(ifp, if_collisions,
1577 				    le32toh(desc->buflen) &
1578 				    JME_TD_BUF_LEN_MASK);
1579 			}
1580 		}
1581 		/*
1582 		 * Only the first descriptor of multi-descriptor
1583 		 * transmission is updated so driver have to skip entire
1584 		 * chained buffers for the transmitted frame. In other
1585 		 * words, JME_TD_OWN bit is valid only at the first
1586 		 * descriptor of a multi-descriptor transmission.
1587 		 */
1588 		nsegs = sc->jme_txmbufm[cons]->dm_nsegs;
1589 		cons0 = cons;
1590 		JME_DESC_INC(cons, JME_NBUFS);
1591 		for (seg = 1; seg < nsegs + 1; seg++) {
1592 			bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1593 			    cons * sizeof(struct jme_desc),
1594 			    sizeof(struct jme_desc),
1595 			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1596 			sc->jme_txring[cons].flags = 0;
1597 			JME_DESC_INC(cons, JME_NBUFS);
1598 		}
1599 		/* Reclaim transferred mbufs. */
1600 		bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0],
1601 		    0, sc->jme_txmbufm[cons0]->dm_mapsize,
1602 		    BUS_DMASYNC_POSTWRITE);
1603 		bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]);
1604 
1605 		KASSERT(sc->jme_txmbuf[cons0] != NULL);
1606 		m_freem(sc->jme_txmbuf[cons0]);
1607 		sc->jme_txmbuf[cons0] = NULL;
1608 		sc->jme_tx_cnt -= nsegs + 1;
1609 		KASSERT(sc->jme_tx_cnt >= 0);
1610 		sc->jme_if.if_flags &= ~IFF_OACTIVE;
1611 	}
1612 	sc->jme_tx_cons = cons;
1613 	/* Unarm watchdog timer when there are no pending descriptors in queue. */
1614 	if (sc->jme_tx_cnt == 0)
1615 		ifp->if_timer = 0;
1616 #ifdef JMEDEBUG_TX
1617 	printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt);
1618 #endif
1619 }
1620 
1621 static void
jme_ifstart(struct ifnet * ifp)1622 jme_ifstart(struct ifnet *ifp)
1623 {
1624 	jme_softc_t *sc = ifp->if_softc;
1625 	struct mbuf *mb_head;
1626 	int enq, error;
1627 
1628 	/*
1629 	 * check if we can free some desc.
1630 	 * Clear TX interrupt status to reset TX coalescing counters.
1631 	 */
1632 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1633 	     JME_INTR_STATUS, INTR_TXQ_COMP);
1634 	jme_txeof(sc);
1635 
1636 	if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1637 		return;
1638 	for (enq = 0;; enq++) {
1639 nexttx:
1640 		/* Grab a paquet for output */
1641 		IFQ_POLL(&ifp->if_snd, mb_head);
1642 		if (mb_head == NULL) {
1643 #ifdef JMEDEBUG_TX
1644 			printf("%s: nothing to send\n", __func__);
1645 #endif
1646 			break;
1647 		}
1648 		/* try to add this mbuf to the TX ring */
1649 		if ((error = jme_encap(sc, mb_head)) != 0) {
1650 			if (error == EFBIG) {
1651 				/* This error is fatal to the packet. */
1652 				IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1653 				m_freem(mb_head);
1654 				if_statinc(ifp, if_oerrors);
1655 				goto nexttx;
1656 			}
1657 			/* resource shortage, try again later */
1658 			ifp->if_flags |= IFF_OACTIVE;
1659 			break;
1660 		}
1661 		IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1662 
1663 		/* Pass packet to bpf if there is a listener */
1664 		bpf_mtap(ifp, mb_head, BPF_D_OUT);
1665 	}
1666 #ifdef JMEDEBUG_TX
1667 	printf("jme_ifstart enq %d\n", enq);
1668 #endif
1669 	if (enq) {
1670 		/*
1671 		 * Set a 5 second timer just in case we don't hear from
1672 		 * the card again.
1673 		 */
1674 		ifp->if_timer = 5;
1675 		/*
1676 		 * Reading TXCSR takes very long time under heavy load
1677 		 * so cache TXCSR value and writes the ORed value with
1678 		 * the kick command to the TXCSR. This saves one register
1679 		 * access cycle.
1680 		 */
1681 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR,
1682 		  sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0));
1683 #ifdef JMEDEBUG_TX
1684 		printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x "
1685 		    "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x "
1686 		    "JME_TXTRHD 0x%x\n",
1687 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR),
1688 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO),
1689 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI),
1690 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC),
1691 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA),
1692 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC),
1693 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC),
1694 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD));
1695 #endif
1696 	}
1697 }
1698 
1699 static void
jme_ifwatchdog(struct ifnet * ifp)1700 jme_ifwatchdog(struct ifnet *ifp)
1701 {
1702 	jme_softc_t *sc = ifp->if_softc;
1703 
1704 	if ((ifp->if_flags & IFF_RUNNING) == 0)
1705 		return;
1706 	printf("%s: device timeout\n", device_xname(sc->jme_dev));
1707 	if_statinc(ifp, if_oerrors);
1708 	jme_init(ifp, 0);
1709 }
1710 
1711 static int
jme_mediachange(struct ifnet * ifp)1712 jme_mediachange(struct ifnet *ifp)
1713 {
1714 	int error;
1715 	jme_softc_t *sc = ifp->if_softc;
1716 
1717 	if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO)
1718 		error = 0;
1719 	else if (error != 0) {
1720 		aprint_error_dev(sc->jme_dev, "could not set media\n");
1721 		return error;
1722 	}
1723 	return 0;
1724 }
1725 
1726 static void
jme_ticks(void * v)1727 jme_ticks(void *v)
1728 {
1729 	jme_softc_t *sc = v;
1730 	int s = splnet();
1731 
1732 	/* Tick the MII. */
1733 	mii_tick(&sc->jme_mii);
1734 
1735 	/* every seconds */
1736 	callout_schedule(&sc->jme_tick_ch, hz);
1737 	splx(s);
1738 }
1739 
1740 static void
jme_mac_config(jme_softc_t * sc)1741 jme_mac_config(jme_softc_t *sc)
1742 {
1743 	uint32_t ghc, gpreg, rxmac, txmac, txpause;
1744 	struct mii_data *mii = &sc->jme_mii;
1745 
1746 	ghc = 0;
1747 	rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
1748 	rxmac &= ~RXMAC_FC_ENB;
1749 	txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC);
1750 	txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1751 	txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC);
1752 	txpause &= ~TXPFC_PAUSE_ENB;
1753 
1754 	if (mii->mii_media_active & IFM_FDX) {
1755 		ghc |= GHC_FULL_DUPLEX;
1756 		rxmac &= ~RXMAC_COLL_DET_ENB;
1757 		txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1758 		    TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1759 		    TXMAC_FRAME_BURST);
1760 		/* Disable retry transmit timer/retry limit. */
1761 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
1762 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)
1763 		    & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1764 	} else {
1765 		rxmac |= RXMAC_COLL_DET_ENB;
1766 		txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1767 		/* Enable retry transmit timer/retry limit. */
1768 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
1769 		    bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)		    | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1770 	}
1771 	/* Reprogram Tx/Rx MACs with resolved speed/duplex. */
1772 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1773 	case IFM_10_T:
1774 		ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100;
1775 		break;
1776 	case IFM_100_TX:
1777 		ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100;
1778 		break;
1779 	case IFM_1000_T:
1780 		ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000;
1781 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1782 			txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1783 		break;
1784 	default:
1785 		break;
1786 	}
1787 	if ((sc->jme_flags & JME_FLAG_GIGA) &&
1788 	    sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
1789 		/*
1790 		 * Workaround occasional packet loss issue of JMC250 A2
1791 		 * when it runs on half-duplex media.
1792 		 */
1793 #ifdef JMEDEBUG
1794 		printf("JME250 A2 workaround\n");
1795 #endif
1796 		gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1797 		    JME_GPREG1);
1798 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1799 			gpreg &= ~GPREG1_HDPX_FIX;
1800 		else
1801 			gpreg |= GPREG1_HDPX_FIX;
1802 		bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1803 		    JME_GPREG1, gpreg);
1804 		/* Workaround CRC errors at 100Mbps on JMC250 A2. */
1805 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
1806 			/* Extend interface FIFO depth. */
1807 			jme_mii_write(sc->jme_dev, sc->jme_phyaddr,
1808 			    0x1B, 0x0000);
1809 		} else {
1810 			/* Select default interface FIFO depth. */
1811 			jme_mii_write(sc->jme_dev, sc->jme_phyaddr,
1812 			    0x1B, 0x0004);
1813 		}
1814 	}
1815 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc);
1816 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac);
1817 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac);
1818 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause);
1819 }
1820 
1821 static void
jme_set_filter(jme_softc_t * sc)1822 jme_set_filter(jme_softc_t *sc)
1823 {
1824 	struct ethercom *ec = &sc->jme_ec;
1825 	struct ifnet *ifp = &sc->jme_if;
1826 	struct ether_multistep step;
1827 	struct ether_multi *enm;
1828 	uint32_t hash[2] = {0, 0};
1829 	int i;
1830 	uint32_t rxcfg;
1831 
1832 	rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
1833 	rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
1834 	    RXMAC_ALLMULTI);
1835 	/* Always accept frames destined to our station address. */
1836 	rxcfg |= RXMAC_UNICAST;
1837 	if ((ifp->if_flags & IFF_BROADCAST) != 0)
1838 		rxcfg |= RXMAC_BROADCAST;
1839 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1840 		if ((ifp->if_flags & IFF_PROMISC) != 0)
1841 			rxcfg |= RXMAC_PROMISC;
1842 		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
1843 			rxcfg |= RXMAC_ALLMULTI;
1844 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1845 		     JME_MAR0, 0xFFFFFFFF);
1846 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1847 		     JME_MAR1, 0xFFFFFFFF);
1848 		bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1849 		     JME_RXMAC, rxcfg);
1850 		return;
1851 	}
1852 	/*
1853 	 * Set up the multicast address filter by passing all multicast
1854 	 * addresses through a CRC generator, and then using the low-order
1855 	 * 6 bits as an index into the 64 bit multicast hash table.  The
1856 	 * high order bits select the register, while the rest of the bits
1857 	 * select the bit within the register.
1858 	 */
1859 	rxcfg |= RXMAC_MULTICAST;
1860 	memset(hash, 0, sizeof(hash));
1861 
1862 	ETHER_LOCK(ec);
1863 	ETHER_FIRST_MULTI(step, ec, enm);
1864 	while (enm != NULL) {
1865 #ifdef JEMDBUG
1866 		printf("%s: addrs %s %s\n", __func__,
1867 		   ether_sprintf(enm->enm_addrlo),
1868 		   ether_sprintf(enm->enm_addrhi));
1869 #endif
1870 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1871 			i = ether_crc32_be(enm->enm_addrlo, 6);
1872 			/* Just want the 6 least significant bits. */
1873 			i &= 0x3f;
1874 			hash[i / 32] |= 1 << (i%32);
1875 		} else {
1876 			hash[0] = hash[1] = 0xffffffff;
1877 			sc->jme_if.if_flags |= IFF_ALLMULTI;
1878 			break;
1879 		}
1880 		ETHER_NEXT_MULTI(step, enm);
1881 	}
1882 	ETHER_UNLOCK(ec);
1883 #ifdef JMEDEBUG
1884 	printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1885 #endif
1886 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]);
1887 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]);
1888 	bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg);
1889 }
1890 
1891 #if 0
1892 static int
1893 jme_multicast_hash(uint8_t *a)
1894 {
1895 	int hash;
1896 
1897 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1898 #define xor8(a,b,c,d,e,f,g,h)						\
1899 	(((a != 0) + (b != 0) + (c != 0) + (d != 0) +			\
1900 	  (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1901 
1902 	hash  = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1903 	    DA(a,36), DA(a,42));
1904 	hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1905 	    DA(a,37), DA(a,43)) << 1;
1906 	hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1907 	    DA(a,38), DA(a,44)) << 2;
1908 	hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1909 	    DA(a,39), DA(a,45)) << 3;
1910 	hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1911 	    DA(a,40), DA(a,46)) << 4;
1912 	hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1913 	    DA(a,41), DA(a,47)) << 5;
1914 
1915 	return hash;
1916 }
1917 #endif
1918 
1919 static int
jme_eeprom_read_byte(struct jme_softc * sc,uint8_t addr,uint8_t * val)1920 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
1921 {
1922 	 uint32_t reg;
1923 	 int i;
1924 
1925 	 *val = 0;
1926 	 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) {
1927 		  reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,
1928 		      JME_SMBCSR);
1929 		  if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
1930 			   break;
1931 		  delay(10);
1932 	 }
1933 
1934 	 if (i == 0) {
1935 		  aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n");
1936 		  return (ETIMEDOUT);
1937 	 }
1938 
1939 	 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
1940 	 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy,
1941 	     JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
1942 	 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) {
1943 		  delay(10);
1944 		  reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,
1945 		      JME_SMBINTF);
1946 		  if ((reg & SMBINTF_CMD_TRIGGER) == 0)
1947 			   break;
1948 	 }
1949 
1950 	 if (i == 0) {
1951 		  aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n");
1952 		  return (ETIMEDOUT);
1953 	 }
1954 
1955 	 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF);
1956 	 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
1957 	 return (0);
1958 }
1959 
1960 
1961 static int
jme_eeprom_macaddr(struct jme_softc * sc)1962 jme_eeprom_macaddr(struct jme_softc *sc)
1963 {
1964 	uint8_t eaddr[ETHER_ADDR_LEN];
1965 	uint8_t fup, reg, val;
1966 	uint32_t offset;
1967 	int match;
1968 
1969 	offset = 0;
1970 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
1971 	    fup != JME_EEPROM_SIG0)
1972 		return (ENOENT);
1973 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
1974 	    fup != JME_EEPROM_SIG1)
1975 		return (ENOENT);
1976 	match = 0;
1977 	do {
1978 		if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
1979 			break;
1980 		if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1)
1981 		    == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
1982 			if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
1983 				break;
1984 			if (reg >= JME_PAR0 &&
1985 			    reg < JME_PAR0 + ETHER_ADDR_LEN) {
1986 				if (jme_eeprom_read_byte(sc, offset + 2,
1987 				    &val) != 0)
1988 					break;
1989 				eaddr[reg - JME_PAR0] = val;
1990 				match++;
1991 			}
1992 		}
1993 		if (fup & JME_EEPROM_DESC_END)
1994 			break;
1995 
1996 		/* Try next eeprom descriptor. */
1997 		offset += JME_EEPROM_DESC_BYTES;
1998 	} while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
1999 
2000 	if (match == ETHER_ADDR_LEN) {
2001 		memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN);
2002 		return (0);
2003 	}
2004 
2005 	return (ENOENT);
2006 }
2007 
2008 static int
jme_reg_macaddr(struct jme_softc * sc)2009 jme_reg_macaddr(struct jme_softc *sc)
2010 {
2011 	uint32_t par0, par1;
2012 
2013 	par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0);
2014 	par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1);
2015 	par1 &= 0xffff;
2016 	if ((par0 == 0 && par1 == 0) ||
2017 	    (par0 == 0xffffffff && par1 == 0xffff)) {
2018 		return (ENOENT);
2019 	} else {
2020 		sc->jme_enaddr[0] = (par0 >> 0) & 0xff;
2021 		sc->jme_enaddr[1] = (par0 >> 8) & 0xff;
2022 		sc->jme_enaddr[2] = (par0 >> 16) & 0xff;
2023 		sc->jme_enaddr[3] = (par0 >> 24) & 0xff;
2024 		sc->jme_enaddr[4] = (par1 >> 0) & 0xff;
2025 		sc->jme_enaddr[5] = (par1 >> 8) & 0xff;
2026 	}
2027 	return (0);
2028 }
2029 
2030 /*
2031  * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be
2032  * set up in jme_pci_attach()
2033  */
2034 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup")
2035 {
2036 	int rc;
2037 	const struct sysctlnode *node;
2038 
2039 	if ((rc = sysctl_createv(clog, 0, NULL, &node,
2040 	    0, CTLTYPE_NODE, "jme",
2041 	    SYSCTL_DESCR("jme interface controls"),
2042 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2043 		goto err;
2044 	}
2045 
2046 	jme_root_num = node->sysctl_num;
2047 	return;
2048 
2049 err:
2050 	aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2051 }
2052 
2053 static int
jme_sysctl_intrxto(SYSCTLFN_ARGS)2054 jme_sysctl_intrxto(SYSCTLFN_ARGS)
2055 {
2056 	int error, t;
2057 	struct sysctlnode node;
2058 	struct jme_softc *sc;
2059 	uint32_t reg;
2060 
2061 	node = *rnode;
2062 	sc = node.sysctl_data;
2063 	t = sc->jme_intrxto;
2064 	node.sysctl_data = &t;
2065 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
2066 	if (error || newp == NULL)
2067 		return error;
2068 
2069 	if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX)
2070 		return EINVAL;
2071 
2072 	/*
2073 	 * update the softc with sysctl-changed value, and mark
2074 	 * for hardware update
2075 	 */
2076 	sc->jme_intrxto = t;
2077 	/* Configure Rx queue 0 packet completion coalescing. */
2078 	reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
2079 	reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
2080 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
2081 	return 0;
2082 }
2083 
2084 static int
jme_sysctl_intrxct(SYSCTLFN_ARGS)2085 jme_sysctl_intrxct(SYSCTLFN_ARGS)
2086 {
2087 	int error, t;
2088 	struct sysctlnode node;
2089 	struct jme_softc *sc;
2090 	uint32_t reg;
2091 
2092 	node = *rnode;
2093 	sc = node.sysctl_data;
2094 	t = sc->jme_intrxct;
2095 	node.sysctl_data = &t;
2096 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
2097 	if (error || newp == NULL)
2098 		return error;
2099 
2100 	if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX)
2101 		return EINVAL;
2102 
2103 	/*
2104 	 * update the softc with sysctl-changed value, and mark
2105 	 * for hardware update
2106 	 */
2107 	sc->jme_intrxct = t;
2108 	/* Configure Rx queue 0 packet completion coalescing. */
2109 	reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
2110 	reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
2111 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
2112 	return 0;
2113 }
2114 
2115 static int
jme_sysctl_inttxto(SYSCTLFN_ARGS)2116 jme_sysctl_inttxto(SYSCTLFN_ARGS)
2117 {
2118 	int error, t;
2119 	struct sysctlnode node;
2120 	struct jme_softc *sc;
2121 	uint32_t reg;
2122 
2123 	node = *rnode;
2124 	sc = node.sysctl_data;
2125 	t = sc->jme_inttxto;
2126 	node.sysctl_data = &t;
2127 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
2128 	if (error || newp == NULL)
2129 		return error;
2130 
2131 	if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX)
2132 		return EINVAL;
2133 
2134 	/*
2135 	 * update the softc with sysctl-changed value, and mark
2136 	 * for hardware update
2137 	 */
2138 	sc->jme_inttxto = t;
2139 	/* Configure Tx queue 0 packet completion coalescing. */
2140 	reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
2141 	reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
2142 	reg |= PCCTX_COAL_TXQ0;
2143 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
2144 	return 0;
2145 }
2146 
2147 static int
jme_sysctl_inttxct(SYSCTLFN_ARGS)2148 jme_sysctl_inttxct(SYSCTLFN_ARGS)
2149 {
2150 	int error, t;
2151 	struct sysctlnode node;
2152 	struct jme_softc *sc;
2153 	uint32_t reg;
2154 
2155 	node = *rnode;
2156 	sc = node.sysctl_data;
2157 	t = sc->jme_inttxct;
2158 	node.sysctl_data = &t;
2159 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
2160 	if (error || newp == NULL)
2161 		return error;
2162 
2163 	if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX)
2164 		return EINVAL;
2165 
2166 	/*
2167 	 * update the softc with sysctl-changed value, and mark
2168 	 * for hardware update
2169 	 */
2170 	sc->jme_inttxct = t;
2171 	/* Configure Tx queue 0 packet completion coalescing. */
2172 	reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
2173 	reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
2174 	reg |= PCCTX_COAL_TXQ0;
2175 	bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
2176 	return 0;
2177 }
2178