1 /* $NetBSD: smu10_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU10_HWMGR_H 27 #define SMU10_HWMGR_H 28 29 #include "hwmgr.h" 30 #include "smu10_inc.h" 31 #include "smu10_driver_if.h" 32 #include "rv_ppsmc.h" 33 34 35 #define SMU10_MAX_HARDWARE_POWERLEVELS 8 36 #define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 37 38 #define DPMFlags_SCLK_Enabled 0x00000001 39 #define DPMFlags_UVD_Enabled 0x00000002 40 #define DPMFlags_VCE_Enabled 0x00000004 41 #define DPMFlags_ACP_Enabled 0x00000008 42 #define DPMFlags_ForceHighestValid 0x40000000 43 44 /* Do not change the following, it is also defined in SMU8.h */ 45 #define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 46 #define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 47 #define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000 48 #define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000 49 50 #define SMU_PHYID_SHIFT 8 51 52 #define SMU10_PCIE_POWERGATING_TARGET_GFX 0 53 #define SMU10_PCIE_POWERGATING_TARGET_DDI 1 54 #define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2 55 #define SMU10_PCIE_POWERGATING_TARGET_PHY 3 56 57 enum VQ_TYPE { 58 CLOCK_TYPE_DCLK = 0L, 59 CLOCK_TYPE_ECLK, 60 CLOCK_TYPE_SCLK, 61 CLOCK_TYPE_CCLK, 62 VQ_GFX_CU 63 }; 64 65 #define SUSTAINABLE_SCLK_MASK 0x00ffffff 66 #define SUSTAINABLE_SCLK_SHIFT 0 67 #define SUSTAINABLE_CU_MASK 0xff000000 68 #define SUSTAINABLE_CU_SHIFT 24 69 70 struct smu10_dpm_entry { 71 uint32_t soft_min_clk; 72 uint32_t hard_min_clk; 73 uint32_t soft_max_clk; 74 uint32_t hard_max_clk; 75 }; 76 77 struct smu10_power_level { 78 uint32_t engine_clock; 79 uint8_t vddc_index; 80 uint8_t ds_divider_index; 81 uint8_t ss_divider_index; 82 uint8_t allow_gnb_slow; 83 uint8_t force_nbp_state; 84 uint8_t display_wm; 85 uint8_t vce_wm; 86 uint8_t num_simd_to_powerdown; 87 uint8_t hysteresis_up; 88 uint8_t rsv[3]; 89 }; 90 91 /*used for the nbpsFlags field in smu10_power state*/ 92 #define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) 93 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) 94 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) 95 96 #define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) 97 98 struct smu10_uvd_clocks { 99 uint32_t vclk; 100 uint32_t dclk; 101 uint32_t vclk_low_divider; 102 uint32_t vclk_high_divider; 103 uint32_t dclk_low_divider; 104 uint32_t dclk_high_divider; 105 }; 106 107 struct pp_disable_nbpslo_flags { 108 union { 109 struct { 110 uint32_t entry : 1; 111 uint32_t display : 1; 112 uint32_t driver: 1; 113 uint32_t vce : 1; 114 uint32_t uvd : 1; 115 uint32_t acp : 1; 116 uint32_t reserved: 26; 117 } bits; 118 uint32_t u32All; 119 }; 120 }; 121 122 123 enum smu10_pstate_previous_action { 124 DO_NOTHING = 1, 125 FORCE_HIGH, 126 CANCEL_FORCE_HIGH 127 }; 128 129 struct smu10_power_state { 130 unsigned int magic; 131 uint32_t level; 132 struct smu10_uvd_clocks uvd_clocks; 133 uint32_t evclk; 134 uint32_t ecclk; 135 uint32_t samclk; 136 uint32_t acpclk; 137 bool need_dfs_bypass; 138 139 uint32_t nbps_flags; 140 uint32_t bapm_flags; 141 uint8_t dpm0_pg_nbps_low; 142 uint8_t dpm0_pg_nbps_high; 143 uint8_t dpm_x_nbps_low; 144 uint8_t dpm_x_nbps_high; 145 146 enum smu10_pstate_previous_action action; 147 148 struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS]; 149 struct pp_disable_nbpslo_flags nbpslo_flags; 150 }; 151 152 #define SMU10_NUM_NBPSTATES 4 153 #define SMU10_NUM_NBPMEMORYCLOCK 2 154 155 156 struct smu10_display_phy_info_entry { 157 uint8_t phy_present; 158 uint8_t active_lane_mapping; 159 uint8_t display_config_type; 160 uint8_t active_num_of_lanes; 161 }; 162 163 #define SMU10_MAX_DISPLAYPHY_IDS 10 164 165 struct smu10_display_phy_info { 166 bool display_phy_access_initialized; 167 struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS]; 168 }; 169 170 #define MAX_DISPLAY_CLOCK_LEVEL 8 171 172 struct smu10_system_info{ 173 uint8_t htc_tmp_lmt; 174 uint8_t htc_hyst_lmt; 175 }; 176 177 #define MAX_REGULAR_DPM_NUMBER 8 178 179 struct smu10_mclk_latency_entries { 180 uint32_t frequency; 181 uint32_t latency; 182 }; 183 184 struct smu10_mclk_latency_table { 185 uint32_t count; 186 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 187 }; 188 189 struct smu10_clock_voltage_dependency_record { 190 uint32_t clk; 191 uint32_t vol; 192 }; 193 194 195 struct smu10_voltage_dependency_table { 196 uint32_t count; 197 struct smu10_clock_voltage_dependency_record entries[1]; 198 }; 199 200 struct smu10_clock_voltage_information { 201 struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk; 202 struct smu10_voltage_dependency_table *vdd_dep_on_socclk; 203 struct smu10_voltage_dependency_table *vdd_dep_on_fclk; 204 struct smu10_voltage_dependency_table *vdd_dep_on_mclk; 205 struct smu10_voltage_dependency_table *vdd_dep_on_dispclk; 206 struct smu10_voltage_dependency_table *vdd_dep_on_dppclk; 207 struct smu10_voltage_dependency_table *vdd_dep_on_phyclk; 208 }; 209 210 struct smu10_hwmgr { 211 uint32_t disable_driver_thermal_policy; 212 uint32_t thermal_auto_throttling_treshold; 213 struct smu10_system_info sys_info; 214 struct smu10_mclk_latency_table mclk_latency_table; 215 216 uint32_t ddi_power_gating_disabled; 217 218 struct smu10_display_phy_info_entry display_phy_info; 219 uint32_t dce_slow_sclk_threshold; 220 221 bool disp_clk_bypass; 222 bool disp_clk_bypass_pending; 223 uint32_t bapm_enabled; 224 225 bool video_start; 226 bool battery_state; 227 228 uint32_t is_nb_dpm_enabled; 229 uint32_t is_voltage_island_enabled; 230 uint32_t disable_smu_acp_s3_handshake; 231 uint32_t disable_notify_smu_vpu_recovery; 232 bool in_vpu_recovery; 233 bool pg_acp_init; 234 uint8_t disp_config; 235 236 /* PowerTune */ 237 uint32_t power_containment_features; 238 bool cac_enabled; 239 bool disable_uvd_power_tune_feature; 240 bool enable_bapm_feature; 241 bool enable_tdc_limit_feature; 242 243 244 /* SMC SRAM Address of firmware header tables */ 245 uint32_t sram_end; 246 uint32_t dpm_table_start; 247 uint32_t soft_regs_start; 248 249 /* start of SMU7_Fusion_DpmTable */ 250 251 uint8_t uvd_level_count; 252 uint8_t vce_level_count; 253 uint8_t acp_level_count; 254 uint8_t samu_level_count; 255 256 uint32_t fps_high_threshold; 257 uint32_t fps_low_threshold; 258 259 uint32_t dpm_flags; 260 struct smu10_dpm_entry sclk_dpm; 261 struct smu10_dpm_entry uvd_dpm; 262 struct smu10_dpm_entry vce_dpm; 263 struct smu10_dpm_entry acp_dpm; 264 bool acp_power_up_no_dsp; 265 266 uint32_t max_sclk_level; 267 uint32_t num_of_clk_entries; 268 269 /* CPU Power State */ 270 uint32_t separation_time; 271 bool cc6_disable; 272 bool pstate_disable; 273 bool cc6_setting_changed; 274 275 uint32_t ulTotalActiveCUs; 276 277 bool isp_tileA_power_gated; 278 bool isp_tileB_power_gated; 279 uint32_t isp_actual_hard_min_freq; 280 uint32_t soc_actual_hard_min_freq; 281 uint32_t dcf_actual_hard_min_freq; 282 283 uint32_t f_actual_hard_min_freq; 284 uint32_t fabric_actual_soft_min_freq; 285 uint32_t vclk_soft_min; 286 uint32_t dclk_soft_min; 287 uint32_t gfx_actual_soft_min_freq; 288 uint32_t gfx_min_freq_limit; 289 uint32_t gfx_max_freq_limit; 290 291 bool vcn_power_gated; 292 bool vcn_dpg_mode; 293 294 bool gfx_off_controled_by_driver; 295 bool water_marks_exist; 296 Watermarks_t water_marks_table; 297 struct smu10_clock_voltage_information clock_vol_info; 298 DpmClocks_t clock_table; 299 300 uint32_t active_process_mask; 301 bool need_min_deep_sleep_dcefclk; 302 uint32_t deep_sleep_dcefclk; 303 uint32_t num_active_display; 304 }; 305 306 struct pp_hwmgr; 307 308 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr); 309 310 /* UMD PState SMU10 Msg Parameters in MHz */ 311 #define SMU10_UMD_PSTATE_GFXCLK 700 312 #define SMU10_UMD_PSTATE_SOCCLK 626 313 #define SMU10_UMD_PSTATE_FCLK 933 314 #define SMU10_UMD_PSTATE_VCE 0x03C00320 315 316 #define SMU10_UMD_PSTATE_PEAK_SOCCLK 757 317 #define SMU10_UMD_PSTATE_PEAK_FCLK 1200 318 319 #define SMU10_UMD_PSTATE_MIN_FCLK 400 320 #define SMU10_UMD_PSTATE_MIN_SOCCLK 200 321 #define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C 322 323 #endif 324