1 /* $NetBSD: isa_machdep.c,v 1.24 2021/08/13 11:40:43 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the
9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*-
34 * Copyright (c) 1991 The Regents of the University of California.
35 * All rights reserved.
36 *
37 * This code is derived from software contributed to Berkeley by
38 * William Jolitz.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in the
47 * documentation and/or other materials provided with the distribution.
48 * 3. Neither the name of the University nor the names of its contributors
49 * may be used to endorse or promote products derived from this software
50 * without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE.
63 *
64 * @(#)isa.c 7.2 (Berkeley) 5/13/91
65 */
66
67 #include <sys/cdefs.h>
68 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.24 2021/08/13 11:40:43 skrll Exp $");
69
70 #include "opt_irqstats.h"
71
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/kernel.h>
75 #include <sys/syslog.h>
76 #include <sys/device.h>
77 #include <sys/kmem.h>
78 #include <sys/proc.h>
79
80 #define _ARM32_BUS_DMA_PRIVATE
81 #include <sys/bus.h>
82
83 #include <machine/intr.h>
84 #include <machine/pio.h>
85 #include <machine/bootconfig.h>
86 #include <machine/isa_machdep.h>
87
88 #include <dev/isa/isareg.h>
89 #include <dev/isa/isavar.h>
90 #include <dev/isa/isadmareg.h>
91 #include <dev/isa/isadmavar.h>
92 #include <arm/footbridge/isa/icu.h>
93 #include <arm/footbridge/dc21285reg.h>
94 #include <arm/footbridge/dc21285mem.h>
95
96 #include <uvm/uvm_extern.h>
97
98 #include "isadma.h"
99
100 /* prototypes */
101 static void isa_icu_init(void);
102
103 struct arm32_isa_chipset isa_chipset_tag;
104
105 void isa_strayintr(int);
106 void intr_calculatemasks(void);
107 int fakeintr(void *);
108
109 int isa_irqdispatch(void *arg);
110
111 u_int imask[NIPL];
112 unsigned imen;
113
114 #define AUTO_EOI_1
115 #define AUTO_EOI_2
116
117 /*
118 * Fill in default interrupt table (in case of spuruious interrupt
119 * during configuration of kernel, setup interrupt control unit
120 */
121 static void
isa_icu_init(void)122 isa_icu_init(void)
123 {
124 /* initialize 8259's */
125 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
126 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
127 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
128 #ifdef AUTO_EOI_1
129 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
130 #else
131 outb(IO_ICU1+1, 1); /* 8086 mode */
132 #endif
133 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
134 outb(IO_ICU1, 0x68); /* special mask mode (if available) */
135 outb(IO_ICU1, 0x0a); /* Read IRR by default. */
136 #ifdef REORDER_IRQ
137 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
138 #endif
139
140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
141 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
142 outb(IO_ICU2+1, IRQ_SLAVE);
143 #ifdef AUTO_EOI_2
144 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
145 #else
146 outb(IO_ICU2+1, 1); /* 8086 mode */
147 #endif
148 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
149 outb(IO_ICU2, 0x68); /* special mask mode (if available) */
150 outb(IO_ICU2, 0x0a); /* Read IRR by default. */
151 }
152
153 /*
154 * Caught a stray interrupt, notify
155 */
156 void
isa_strayintr(int irq)157 isa_strayintr(int irq)
158 {
159 static u_long strays;
160
161 /*
162 * Stray interrupts on irq 7 occur when an interrupt line is raised
163 * and then lowered before the CPU acknowledges it. This generally
164 * means either the device is screwed or something is cli'ing too
165 * long and it's timing out.
166 */
167 if (++strays <= 5)
168 log(LOG_ERR, "stray interrupt %d%s\n", irq,
169 strays >= 5 ? "; stopped logging" : "");
170 }
171
172 static struct intrq isa_intrq[ICU_LEN];
173
174 /*
175 * Recalculate the interrupt masks from scratch.
176 * We could code special registry and deregistry versions of this function that
177 * would be faster, but the code would be nastier, and we don't expect this to
178 * happen very much anyway.
179 */
180 void
intr_calculatemasks(void)181 intr_calculatemasks(void)
182 {
183 int irq, level;
184 struct intrq *iq;
185 struct intrhand *ih;
186
187 /* First, figure out which levels each IRQ uses. */
188 for (irq = 0; irq < ICU_LEN; irq++) {
189 int levels = 0;
190 iq = &isa_intrq[irq];
191 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
192 ih = TAILQ_NEXT(ih, ih_list))
193 levels |= (1U << ih->ih_ipl);
194 iq->iq_levels = levels;
195 }
196
197 /* Then figure out which IRQs use each level. */
198 for (level = 0; level < NIPL; level++) {
199 int irqs = 0;
200 for (irq = 0; irq < ICU_LEN; irq++)
201 if (isa_intrq[irq].iq_levels & (1U << level))
202 irqs |= (1U << irq);
203 imask[level] = irqs;
204 }
205
206 imask[IPL_SCHED] |= imask[IPL_VM];
207 imask[IPL_HIGH] |= imask[IPL_SCHED];
208
209 /* And eventually calculate the complete masks. */
210 for (irq = 0; irq < ICU_LEN; irq++) {
211 int irqs = 1 << irq;
212 iq = &isa_intrq[irq];
213 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
214 ih = TAILQ_NEXT(ih, ih_list))
215 irqs |= imask[ih->ih_ipl];
216 iq->iq_mask = irqs;
217 }
218
219 /* Lastly, determine which IRQs are actually in use. */
220 {
221 int irqs = 0;
222 for (irq = 0; irq < ICU_LEN; irq++)
223 if (!TAILQ_EMPTY(&isa_intrq[irq].iq_list))
224 irqs |= (1U << irq);
225 if (irqs >= 0x100) /* any IRQs >= 8 in use */
226 irqs |= 1 << IRQ_SLAVE;
227 imen = ~irqs;
228 SET_ICUS();
229 }
230 #if 0
231 printf("type\tmask\tlevel\thand\n");
232 for (irq = 0; irq < ICU_LEN; irq++) {
233 printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq],
234 intrlevel[irq], intrhand[irq]);
235 }
236 for (level = 0; level < IPL_LEVELS; ++level)
237 printf("%d: %08x\n", level, imask[level]);
238 #endif
239 }
240
241 int
fakeintr(void * arg)242 fakeintr(void *arg)
243 {
244
245 return 0;
246 }
247
248 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
249
250 int
isa_intr_alloc(isa_chipset_tag_t ic,int mask,int type,int * irq)251 isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq)
252 {
253 int i, tmp, bestirq, count;
254 struct intrq *iq;
255 struct intrhand *ih;
256
257 if (type == IST_NONE)
258 panic("intr_alloc: bogus type");
259
260 bestirq = -1;
261 count = -1;
262
263 /* some interrupts should never be dynamically allocated */
264 mask &= 0xdef8;
265
266 /*
267 * XXX some interrupts will be used later (6 for fdc, 12 for pms).
268 * the right answer is to do "breadth-first" searching of devices.
269 */
270 mask &= 0xefbf;
271
272 for (i = 0; i < ICU_LEN; i++) {
273 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
274 continue;
275
276 iq = &isa_intrq[i];
277 switch(iq->iq_ist) {
278 case IST_NONE:
279 /*
280 * if nothing's using the irq, just return it
281 */
282 *irq = i;
283 return (0);
284
285 case IST_EDGE:
286 case IST_LEVEL:
287 if (type != iq->iq_ist)
288 continue;
289 /*
290 * if the irq is shareable, count the number of other
291 * handlers, and if it's smaller than the last irq like
292 * this, remember it
293 *
294 * XXX We should probably also consider the
295 * interrupt level and stick IPL_TTY with other
296 * IPL_TTY, etc.
297 */
298 tmp = 0;
299 TAILQ_FOREACH(ih, &(iq->iq_list), ih_list)
300 tmp++;
301 if ((bestirq == -1) || (count > tmp)) {
302 bestirq = i;
303 count = tmp;
304 }
305 break;
306
307 case IST_PULSE:
308 /* this just isn't shareable */
309 continue;
310 }
311 }
312
313 if (bestirq == -1)
314 return (1);
315
316 *irq = bestirq;
317
318 return (0);
319 }
320
321 const struct evcnt *
isa_intr_evcnt(isa_chipset_tag_t ic,int irq)322 isa_intr_evcnt(isa_chipset_tag_t ic, int irq)
323 {
324 return &isa_intrq[irq].iq_ev;
325 }
326
327 /*
328 * Set up an interrupt handler to start being called.
329 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM.
330 */
331 void *
isa_intr_establish(isa_chipset_tag_t ic,int irq,int type,int level,int (* ih_fun)(void *),void * ih_arg)332 isa_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg)
333 {
334 struct intrq *iq;
335 struct intrhand *ih;
336 u_int oldirqstate;
337
338 #if 0
339 printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level);
340 #endif
341 ih = kmem_alloc(sizeof *ih, KM_SLEEP);
342
343 if (!LEGAL_IRQ(irq) || type == IST_NONE)
344 panic("intr_establish: bogus irq or type");
345
346 iq = &isa_intrq[irq];
347
348 switch (iq->iq_ist) {
349 case IST_NONE:
350 iq->iq_ist = type;
351 #if 0
352 printf("Setting irq %d to type %d - ", irq, type);
353 #endif
354 if (irq < 8) {
355 outb(0x4d0, (inb(0x4d0) & ~(1 << irq))
356 | ((type == IST_LEVEL) ? (1 << irq) : 0));
357 /* printf("%02x\n", inb(0x4d0));*/
358 } else {
359 outb(0x4d1, (inb(0x4d1) & ~(1 << irq))
360 | ((type == IST_LEVEL) ? (1 << irq) : 0));
361 /* printf("%02x\n", inb(0x4d1));*/
362 }
363 break;
364 case IST_EDGE:
365 case IST_LEVEL:
366 if (iq->iq_ist == type)
367 break;
368 case IST_PULSE:
369 if (type != IST_NONE)
370 panic("intr_establish: can't share %s with %s",
371 isa_intr_typename(iq->iq_ist),
372 isa_intr_typename(type));
373 break;
374 }
375
376 ih->ih_func = ih_fun;
377 ih->ih_arg = ih_arg;
378 ih->ih_ipl = level;
379 ih->ih_irq = irq;
380
381 /* do not stop us */
382 oldirqstate = disable_interrupts(I32_bit);
383
384 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
385
386 intr_calculatemasks();
387 restore_interrupts(oldirqstate);
388
389 return (ih);
390 }
391
392 /*
393 * Deregister an interrupt handler.
394 */
395 void
isa_intr_disestablish(isa_chipset_tag_t ic,void * arg)396 isa_intr_disestablish(isa_chipset_tag_t ic, void *arg)
397 {
398 struct intrhand *ih = arg;
399 struct intrq *iq = &isa_intrq[ih->ih_irq];
400 int irq = ih->ih_irq;
401 u_int oldirqstate;
402
403 if (!LEGAL_IRQ(irq))
404 panic("intr_disestablish: bogus irq");
405
406 oldirqstate = disable_interrupts(I32_bit);
407
408 TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
409
410 intr_calculatemasks();
411
412 restore_interrupts(oldirqstate);
413
414 kmem_free(ih, sizeof(*ih));
415
416 if (TAILQ_EMPTY(&(iq->iq_list)))
417 iq->iq_ist = IST_NONE;
418 }
419
420 /*
421 * isa_intr_init()
422 *
423 * Initialise the ISA ICU and attach an ISA interrupt handler to the
424 * ISA interrupt line on the footbridge.
425 */
426 void
isa_intr_init(void)427 isa_intr_init(void)
428 {
429 struct intrq *iq;
430 int i;
431
432 /*
433 * should get the parent here, but initialisation order being so
434 * strange I need to check if it's available
435 */
436 for (i = 0; i < ICU_LEN; i++) {
437 iq = &isa_intrq[i];
438 TAILQ_INIT(&iq->iq_list);
439
440 snprintf(iq->iq_name, sizeof(iq->iq_name), "irq %d", i);
441 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
442 NULL, "isa", iq->iq_name);
443 }
444
445 isa_icu_init();
446 intr_calculatemasks();
447 /* something to break the build in an informative way */
448 #ifndef ISA_FOOTBRIDGE_IRQ
449 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ
450 #endif
451 footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_BIO, "isabus",
452 isa_irqdispatch, NULL);
453
454 }
455
456 /* Static array of ISA DMA segments. We only have one on CATS */
457 #if NISADMA > 0
458 struct arm32_dma_range machdep_isa_dma_ranges[1];
459 #endif
460
461 void
isa_footbridge_init(u_int iobase,u_int membase)462 isa_footbridge_init(u_int iobase, u_int membase)
463 {
464 #if NISADMA > 0
465 extern struct arm32_dma_range *footbridge_isa_dma_ranges;
466 extern int footbridge_isa_dma_nranges;
467
468 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address;
469 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address;
470 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024);
471
472 footbridge_isa_dma_ranges = machdep_isa_dma_ranges;
473 footbridge_isa_dma_nranges = 1;
474 #endif
475
476 isa_io_init(iobase, membase);
477 }
478
479 void
isa_attach_hook(device_t parent,device_t self,struct isabus_attach_args * iba)480 isa_attach_hook(device_t parent, device_t self, struct isabus_attach_args *iba)
481 {
482 /*
483 * Since we can only have one ISA bus, we just use a single
484 * statically allocated ISA chipset structure. Pass it up
485 * now.
486 */
487 iba->iba_ic = &isa_chipset_tag;
488 #if NISADMA > 0
489 isa_dma_init();
490 #endif
491 }
492
493 void
isa_detach_hook(isa_chipset_tag_t ic,device_t self)494 isa_detach_hook(isa_chipset_tag_t ic, device_t self)
495 {
496 #if NISADMA > 0
497 isa_dmadestroy(ic);
498 #endif
499 }
500
501 int
isa_irqdispatch(void * arg)502 isa_irqdispatch(void *arg)
503 {
504 struct clockframe *frame = arg;
505 int irq;
506 struct intrq *iq;
507 struct intrhand *ih;
508 u_int iack;
509 int res = 0;
510
511 iack = *((u_int *)(DC21285_PCI_IACK_VBASE));
512 iack &= 0xff;
513 if (iack < 0x20 || iack > 0x2f) {
514 printf("isa_irqdispatch: %x\n", iack);
515 return(0);
516 }
517
518 irq = iack & 0x0f;
519 iq = &isa_intrq[irq];
520 iq->iq_ev.ev_count++;
521 for (ih = TAILQ_FIRST(&iq->iq_list); res != 1 && ih != NULL;
522 ih = TAILQ_NEXT(ih, ih_list)) {
523 res = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
524 }
525 return res;
526 }
527
528
529 void
isa_fillw(u_int val,void * addr,size_t len)530 isa_fillw(u_int val, void *addr, size_t len)
531 {
532 if ((u_int)addr >= isa_mem_data_vaddr()
533 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) {
534 bus_size_t offset = ((u_int)addr) & 0xfffff;
535 bus_space_set_region_2(&isa_mem_bs_tag,
536 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset,
537 val, len);
538 } else {
539 u_short *ptr = addr;
540
541 while (len > 0) {
542 *ptr++ = val;
543 --len;
544 }
545 }
546 }
547