1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
3 */
4
5 #ifndef _IFPGA_HW_H_
6 #define _IFPGA_HW_H_
7
8 #include "ifpga_defines.h"
9 #include "opae_ifpga_hw_api.h"
10 #include "opae_eth_group.h"
11
12 /** List of private feateues */
13 TAILQ_HEAD(ifpga_feature_list, ifpga_feature);
14
15 enum ifpga_feature_state {
16 IFPGA_FEATURE_UNUSED = 0,
17 IFPGA_FEATURE_ATTACHED,
18 IFPGA_FEATURE_INITED
19 };
20
21 enum feature_type {
22 FEATURE_FME_TYPE = 0,
23 FEATURE_PORT_TYPE,
24 };
25
26 struct feature_irq_ctx {
27 int eventfd;
28 int idx;
29 };
30
31 struct ifpga_feature {
32 TAILQ_ENTRY(ifpga_feature)next;
33 enum ifpga_feature_state state;
34 enum feature_type type;
35 const char *name;
36 u64 id;
37 u8 *addr;
38 uint64_t phys_addr;
39 u32 size;
40 int revision;
41 u64 cap;
42 int vfio_dev_fd;
43 struct feature_irq_ctx *ctx;
44 unsigned int ctx_num;
45
46 void *parent; /* to parent hw data structure */
47
48 struct ifpga_feature_ops *ops;/* callback to this private feature */
49 unsigned int vec_start;
50 unsigned int vec_cnt;
51 };
52
53 struct ifpga_feature_ops {
54 int (*init)(struct ifpga_feature *feature);
55 void (*uinit)(struct ifpga_feature *feature);
56 int (*get_prop)(struct ifpga_feature *feature,
57 struct feature_prop *prop);
58 int (*set_prop)(struct ifpga_feature *feature,
59 struct feature_prop *prop);
60 int (*set_irq)(struct ifpga_feature *feature, void *irq_set);
61 };
62
63 enum ifpga_fme_state {
64 IFPGA_FME_UNUSED = 0,
65 IFPGA_FME_IMPLEMENTED,
66 };
67
68 struct ifpga_fme_hw {
69 enum ifpga_fme_state state;
70
71 struct ifpga_feature_list feature_list;
72 spinlock_t lock; /* protect hardware access */
73
74 void *parent; /* pointer to ifpga_hw */
75
76 /* provied by HEADER feature */
77 u32 port_num;
78 struct uuid bitstream_id;
79 u64 bitstream_md;
80 size_t pr_bandwidth;
81 u32 socket_id;
82 u32 fabric_version_id;
83 u32 cache_size;
84
85 u32 capability;
86
87 void *max10_dev; /* MAX10 device */
88 void *i2c_master; /* I2C Master device */
89 void *eth_dev[MAX_ETH_GROUP_DEVICES];
90 struct opae_reg_region
91 eth_group_region[MAX_ETH_GROUP_DEVICES];
92 struct opae_board_info board_info;
93 int nums_eth_dev;
94 unsigned int nums_acc_region;
95 void *sec_mgr;
96 };
97
98 enum ifpga_port_state {
99 IFPGA_PORT_UNUSED = 0,
100 IFPGA_PORT_ATTACHED,
101 IFPGA_PORT_DETACHED,
102 };
103
104 struct ifpga_port_hw {
105 enum ifpga_port_state state;
106
107 struct ifpga_feature_list feature_list;
108 spinlock_t lock; /* protect access to hw */
109
110 void *parent; /* pointer to ifpga_hw */
111
112 int port_id; /* provied by HEADER feature */
113 struct uuid afu_id; /* provied by User AFU feature */
114
115 unsigned int disable_count;
116
117 u32 capability;
118 u32 num_umsgs; /* The number of allocated umsgs */
119 u32 num_uafu_irqs; /* The number of uafu interrupts */
120 u8 *stp_addr;
121 u32 stp_size;
122 };
123
124 #define AFU_MAX_REGION 1
125
126 struct ifpga_afu_info {
127 struct opae_reg_region region[AFU_MAX_REGION];
128 unsigned int num_regions;
129 unsigned int num_irqs;
130 };
131
132 struct ifpga_hw {
133 struct opae_adapter *adapter;
134 struct opae_adapter_data_pci *pci_data;
135
136 struct ifpga_fme_hw fme;
137 struct ifpga_port_hw port[MAX_FPGA_PORT_NUM];
138 int num_afus;
139 };
140
is_ifpga_hw_pf(struct ifpga_hw * hw)141 static inline bool is_ifpga_hw_pf(struct ifpga_hw *hw)
142 {
143 return hw->fme.state != IFPGA_FME_UNUSED;
144 }
145
is_valid_port_id(struct ifpga_hw * hw,u32 port_id)146 static inline bool is_valid_port_id(struct ifpga_hw *hw, u32 port_id)
147 {
148 if (port_id >= MAX_FPGA_PORT_NUM ||
149 hw->port[port_id].state != IFPGA_PORT_ATTACHED)
150 return false;
151
152 return true;
153 }
154 #endif /* _IFPGA_HW_H_ */
155