1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "MCTargetDesc/PPCMCTargetDesc.h" 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/ADT/SmallSet.h" 20 #include "llvm/CodeGen/LiveVariables.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "PPCGenInstrInfo.inc" 25 26 namespace llvm { 27 28 // Instructions that have an immediate form might be convertible to that 29 // form if the correct input is a result of a load immediate. In order to 30 // know whether the transformation is special, we might need to know some 31 // of the details of the two forms. 32 struct ImmInstrInfo { 33 // Is the immediate field in the immediate form signed or unsigned? 34 uint64_t SignedImm : 1; 35 // Does the immediate need to be a multiple of some value? 36 uint64_t ImmMustBeMultipleOf : 5; 37 // Is R0/X0 treated specially by the original r+r instruction? 38 // If so, in which operand? 39 uint64_t ZeroIsSpecialOrig : 3; 40 // Is R0/X0 treated specially by the new r+i instruction? 41 // If so, in which operand? 42 uint64_t ZeroIsSpecialNew : 3; 43 // Is the operation commutative? 44 uint64_t IsCommutative : 1; 45 // The operand number to check for add-immediate def. 46 uint64_t OpNoForForwarding : 3; 47 // The operand number for the immediate. 48 uint64_t ImmOpNo : 3; 49 // The opcode of the new instruction. 50 uint64_t ImmOpcode : 16; 51 // The size of the immediate. 52 uint64_t ImmWidth : 5; 53 // The immediate should be truncated to N bits. 54 uint64_t TruncateImmTo : 5; 55 // Is the instruction summing the operand 56 uint64_t IsSummingOperands : 1; 57 }; 58 59 // Information required to convert an instruction to just a materialized 60 // immediate. 61 struct LoadImmediateInfo { 62 unsigned Imm : 16; 63 unsigned Is64Bit : 1; 64 unsigned SetCR : 1; 65 }; 66 67 // Index into the OpcodesForSpill array. 68 enum SpillOpcodeKey { 69 SOK_Int4Spill, 70 SOK_Int8Spill, 71 SOK_Float8Spill, 72 SOK_Float4Spill, 73 SOK_CRSpill, 74 SOK_CRBitSpill, 75 SOK_VRVectorSpill, 76 SOK_VSXVectorSpill, 77 SOK_VectorFloat8Spill, 78 SOK_VectorFloat4Spill, 79 SOK_SpillToVSR, 80 SOK_PairedVecSpill, 81 SOK_AccumulatorSpill, 82 SOK_UAccumulatorSpill, 83 SOK_WAccumulatorSpill, 84 SOK_SPESpill, 85 SOK_PairedG8Spill, 86 SOK_LastOpcodeSpill // This must be last on the enum. 87 }; 88 89 // PPC MachineCombiner patterns 90 enum PPCMachineCombinerPattern : unsigned { 91 // These are patterns matched by the PowerPC to reassociate FMA chains. 92 REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START, 93 REASSOC_XMM_AMM_BMM, 94 95 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to 96 // reduce register pressure. 97 REASSOC_XY_BCA, 98 REASSOC_XY_BAC, 99 100 }; 101 102 // Define list of load and store spill opcodes. 103 #define NoInstr PPC::INSTRUCTION_LIST_END 104 #define Pwr8LoadOpcodes \ 105 { \ 106 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 107 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 108 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \ 109 PPC::RESTORE_QUADWORD \ 110 } 111 112 #define Pwr9LoadOpcodes \ 113 { \ 114 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 115 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 116 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \ 117 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \ 118 } 119 120 #define Pwr10LoadOpcodes \ 121 { \ 122 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 123 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 124 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \ 125 PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \ 126 } 127 128 #define FutureLoadOpcodes \ 129 { \ 130 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 131 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 132 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \ 133 PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \ 134 } 135 136 #define Pwr8StoreOpcodes \ 137 { \ 138 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 139 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \ 140 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \ 141 PPC::SPILL_QUADWORD \ 142 } 143 144 #define Pwr9StoreOpcodes \ 145 { \ 146 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 147 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 148 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \ 149 PPC::SPILL_QUADWORD \ 150 } 151 152 #define Pwr10StoreOpcodes \ 153 { \ 154 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 155 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 156 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \ 157 NoInstr, NoInstr, PPC::SPILL_QUADWORD \ 158 } 159 160 #define FutureStoreOpcodes \ 161 { \ 162 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 163 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 164 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \ 165 PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \ 166 } 167 168 // Initialize arrays for load and store spill opcodes on supported subtargets. 169 #define StoreOpcodesForSpill \ 170 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes } 171 #define LoadOpcodesForSpill \ 172 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes } 173 174 class PPCSubtarget; 175 class PPCInstrInfo : public PPCGenInstrInfo { 176 PPCSubtarget &Subtarget; 177 const PPCRegisterInfo RI; 178 const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] = 179 StoreOpcodesForSpill; 180 const unsigned LoadSpillOpcodesArray[4][SOK_LastOpcodeSpill] = 181 LoadOpcodesForSpill; 182 183 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 184 int FrameIdx, const TargetRegisterClass *RC, 185 SmallVectorImpl<MachineInstr *> &NewMIs) const; 186 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 187 unsigned DestReg, int FrameIdx, 188 const TargetRegisterClass *RC, 189 SmallVectorImpl<MachineInstr *> &NewMIs) const; 190 191 // Replace the instruction with single LI if possible. \p DefMI must be LI or 192 // LI8. 193 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 194 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 195 // If the inst is imm-form and its register operand is produced by a ADDI, put 196 // the imm into the inst directly and remove the ADDI if possible. 197 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 198 unsigned OpNoForForwarding) const; 199 // If the inst is x-form and has imm-form and one of its operand is produced 200 // by a LI, put the imm into the inst directly and remove the LI if possible. 201 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 202 unsigned ConstantOpNo, 203 MachineInstr &DefMI) const; 204 // If the inst is x-form and has imm-form and one of its operand is produced 205 // by an add-immediate, try to transform it when possible. 206 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 207 unsigned ConstantOpNo, MachineInstr &DefMI, 208 bool KillDefMI) const; 209 // Try to find that, if the instruction 'MI' contains any operand that 210 // could be forwarded from some inst that feeds it. If yes, return the 211 // Def of that operand. And OpNoForForwarding is the operand index in 212 // the 'MI' for that 'Def'. If we see another use of this Def between 213 // the Def and the MI, SeenIntermediateUse becomes 'true'. 214 MachineInstr *getForwardingDefMI(MachineInstr &MI, 215 unsigned &OpNoForForwarding, 216 bool &SeenIntermediateUse) const; 217 218 // Can the user MI have it's source at index \p OpNoForForwarding 219 // forwarded from an add-immediate that feeds it? 220 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 221 unsigned OpNoForForwarding) const; 222 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 223 const ImmInstrInfo &III, 224 MachineOperand *&ImmMO, 225 MachineOperand *&RegMO) const; 226 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 227 const MachineInstr &DefMI, 228 const ImmInstrInfo &III, 229 int64_t &Imm, 230 int64_t BaseImm = 0) const; 231 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 232 const MachineInstr &DefMI, 233 const MachineInstr &MI, bool KillDefMI, 234 bool &IsFwdFeederRegKilled, 235 bool &SeenIntermediateUse) const; 236 unsigned getSpillTarget() const; 237 ArrayRef<unsigned> getStoreOpcodesForSpillArray() const; 238 ArrayRef<unsigned> getLoadOpcodesForSpillArray() const; 239 unsigned getSpillIndex(const TargetRegisterClass *RC) const; 240 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 241 void reassociateFMA(MachineInstr &Root, unsigned Pattern, 242 SmallVectorImpl<MachineInstr *> &InsInstrs, 243 SmallVectorImpl<MachineInstr *> &DelInstrs, 244 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 245 Register 246 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty, 247 SmallVectorImpl<MachineInstr *> &InsInstrs) const; 248 virtual void anchor(); 249 250 protected: 251 /// Commutes the operands in the given instruction. 252 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 253 /// 254 /// Do not call this method for a non-commutable instruction or for 255 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 256 /// Even though the instruction is commutable, the method may still 257 /// fail to commute the operands, null pointer is returned in such cases. 258 /// 259 /// For example, we can commute rlwimi instructions, but only if the 260 /// rotate amt is zero. We also have to munge the immediates a bit. 261 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 262 unsigned OpIdx1, 263 unsigned OpIdx2) const override; 264 265 public: 266 explicit PPCInstrInfo(PPCSubtarget &STI); 267 268 bool isLoadFromConstantPool(MachineInstr *I) const; 269 const Constant *getConstantFromConstantPool(MachineInstr *I) const; 270 271 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 272 /// such, whenever a client has an instance of instruction info, it should 273 /// always be able to get register info as well (through this method). 274 /// 275 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 276 277 bool isXFormMemOp(unsigned Opcode) const { 278 return get(Opcode).TSFlags & PPCII::XFormMemOp; 279 } 280 bool isPrefixed(unsigned Opcode) const { 281 return get(Opcode).TSFlags & PPCII::Prefixed; 282 } 283 bool isSExt32To64(unsigned Opcode) const { 284 return get(Opcode).TSFlags & PPCII::SExt32To64; 285 } 286 bool isZExt32To64(unsigned Opcode) const { 287 return get(Opcode).TSFlags & PPCII::ZExt32To64; 288 } 289 bool isMemriOp(unsigned Opcode) const { 290 return get(Opcode).TSFlags & PPCII::MemriOp; 291 } 292 293 static bool isSameClassPhysRegCopy(unsigned Opcode) { 294 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, 295 PPC::VOR, PPC::XXLOR, PPC::XXLORf, 296 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR, 297 PPC::EVOR, -1U}; 298 for (int i = 0; CopyOpcodes[i] != -1U; i++) 299 if (Opcode == CopyOpcodes[i]) 300 return true; 301 return false; 302 } 303 304 static bool hasPCRelFlag(unsigned TF) { 305 return TF == PPCII::MO_PCREL_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG || 306 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG || 307 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || 308 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG || 309 TF == PPCII::MO_GOT_PCREL_FLAG; 310 } 311 312 static bool hasGOTFlag(unsigned TF) { 313 return TF == PPCII::MO_GOT_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG || 314 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG || 315 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || 316 TF == PPCII::MO_GOT_PCREL_FLAG; 317 } 318 319 static bool hasTLSFlag(unsigned TF) { 320 return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG || 321 TF == PPCII::MO_TLSLD_FLAG || TF == PPCII::MO_TLSGDM_FLAG || 322 TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG || 323 TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG || 324 TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || TF == PPCII::MO_TPREL_LO || 325 TF == PPCII::MO_TPREL_HA || TF == PPCII::MO_DTPREL_LO || 326 TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS || 327 TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG; 328 } 329 330 ScheduleHazardRecognizer * 331 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 332 const ScheduleDAG *DAG) const override; 333 ScheduleHazardRecognizer * 334 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 335 const ScheduleDAG *DAG) const override; 336 337 unsigned getInstrLatency(const InstrItineraryData *ItinData, 338 const MachineInstr &MI, 339 unsigned *PredCost = nullptr) const override; 340 341 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, 342 const MachineInstr &DefMI, 343 unsigned DefIdx, 344 const MachineInstr &UseMI, 345 unsigned UseIdx) const override; 346 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, 347 SDNode *DefNode, unsigned DefIdx, 348 SDNode *UseNode, 349 unsigned UseIdx) const override { 350 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 351 UseNode, UseIdx); 352 } 353 354 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 355 const MachineInstr &DefMI, 356 unsigned DefIdx) const override { 357 // Machine LICM should hoist all instructions in low-register-pressure 358 // situations; none are sufficiently free to justify leaving in a loop 359 // body. 360 return false; 361 } 362 363 bool useMachineCombiner() const override { 364 return true; 365 } 366 367 /// When getMachineCombinerPatterns() finds patterns, this function generates 368 /// the instructions that could replace the original code sequence 369 void genAlternativeCodeSequence( 370 MachineInstr &Root, unsigned Pattern, 371 SmallVectorImpl<MachineInstr *> &InsInstrs, 372 SmallVectorImpl<MachineInstr *> &DelInstrs, 373 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 374 375 /// Return true when there is potentially a faster code sequence for a fma 376 /// chain ending in \p Root. All potential patterns are output in the \p 377 /// P array. 378 bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns, 379 bool DoRegPressureReduce) const; 380 381 CombinerObjective getCombinerObjective(unsigned Pattern) const override; 382 383 /// Return true when there is potentially a faster code sequence 384 /// for an instruction chain ending in <Root>. All potential patterns are 385 /// output in the <Pattern> array. 386 bool getMachineCombinerPatterns(MachineInstr &Root, 387 SmallVectorImpl<unsigned> &Patterns, 388 bool DoRegPressureReduce) const override; 389 390 /// On PowerPC, we leverage machine combiner pass to reduce register pressure 391 /// when the register pressure is high for one BB. 392 /// Return true if register pressure for \p MBB is high and ABI is supported 393 /// to reduce register pressure. Otherwise return false. 394 bool shouldReduceRegisterPressure( 395 const MachineBasicBlock *MBB, 396 const RegisterClassInfo *RegClassInfo) const override; 397 398 /// Fixup the placeholders we put in genAlternativeCodeSequence() for 399 /// MachineCombiner. 400 void 401 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, 402 SmallVectorImpl<MachineInstr *> &InsInstrs) const override; 403 404 bool isAssociativeAndCommutative(const MachineInstr &Inst, 405 bool Invert) const override; 406 407 /// On PowerPC, we try to reassociate FMA chain which will increase 408 /// instruction size. Set extension resource length limit to 1 for edge case. 409 /// Resource Length is calculated by scaled resource usage in getCycles(). 410 /// Because of the division in getCycles(), it returns different cycles due to 411 /// legacy scaled resource usage. So new resource length may be same with 412 /// legacy or 1 bigger than legacy. 413 /// We need to execlude the 1 bigger case even the resource length is not 414 /// perserved for more FMA chain reassociations on PowerPC. 415 int getExtendResourceLenLimit() const override { return 1; } 416 417 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI 418 // and clears nuw, nsw, and exact flags. 419 using TargetInstrInfo::setSpecialOperandAttr; 420 void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const; 421 422 bool isCoalescableExtInstr(const MachineInstr &MI, 423 Register &SrcReg, Register &DstReg, 424 unsigned &SubIdx) const override; 425 Register isLoadFromStackSlot(const MachineInstr &MI, 426 int &FrameIndex) const override; 427 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 428 Register isStoreToStackSlot(const MachineInstr &MI, 429 int &FrameIndex) const override; 430 431 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 432 unsigned &SrcOpIdx2) const override; 433 434 void insertNoop(MachineBasicBlock &MBB, 435 MachineBasicBlock::iterator MI) const override; 436 437 438 // Branch analysis. 439 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 440 MachineBasicBlock *&FBB, 441 SmallVectorImpl<MachineOperand> &Cond, 442 bool AllowModify) const override; 443 unsigned removeBranch(MachineBasicBlock &MBB, 444 int *BytesRemoved = nullptr) const override; 445 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 446 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 447 const DebugLoc &DL, 448 int *BytesAdded = nullptr) const override; 449 450 // Select analysis. 451 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 452 Register, Register, Register, int &, int &, 453 int &) const override; 454 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 455 const DebugLoc &DL, Register DstReg, 456 ArrayRef<MachineOperand> Cond, Register TrueReg, 457 Register FalseReg) const override; 458 459 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 460 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 461 bool KillSrc, bool RenamableDest = false, 462 bool RenamableSrc = false) const override; 463 464 void storeRegToStackSlot( 465 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, 466 bool isKill, int FrameIndex, const TargetRegisterClass *RC, 467 const TargetRegisterInfo *TRI, Register VReg, 468 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 469 470 // Emits a register spill without updating the register class for vector 471 // registers. This ensures that when we spill a vector register the 472 // element order in the register is the same as it was in memory. 473 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 474 MachineBasicBlock::iterator MBBI, 475 unsigned SrcReg, bool isKill, int FrameIndex, 476 const TargetRegisterClass *RC, 477 const TargetRegisterInfo *TRI) const; 478 479 void loadRegFromStackSlot( 480 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 481 Register DestReg, int FrameIndex, const TargetRegisterClass *RC, 482 const TargetRegisterInfo *TRI, Register VReg, 483 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 484 485 // Emits a register reload without updating the register class for vector 486 // registers. This ensures that when we reload a vector register the 487 // element order in the register is the same as it was in memory. 488 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 489 MachineBasicBlock::iterator MBBI, 490 unsigned DestReg, int FrameIndex, 491 const TargetRegisterClass *RC, 492 const TargetRegisterInfo *TRI) const; 493 494 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 495 496 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 497 498 bool 499 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 500 501 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 502 MachineRegisterInfo *MRI) const override; 503 504 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 505 Register Reg) const; 506 507 // If conversion by predication (only supported by some branch instructions). 508 // All of the profitability checks always return true; it is always 509 // profitable to use the predicated branches. 510 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 511 unsigned NumCycles, unsigned ExtraPredCycles, 512 BranchProbability Probability) const override { 513 return true; 514 } 515 516 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 517 unsigned NumT, unsigned ExtraT, 518 MachineBasicBlock &FMBB, 519 unsigned NumF, unsigned ExtraF, 520 BranchProbability Probability) const override; 521 522 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 523 BranchProbability Probability) const override { 524 return true; 525 } 526 527 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 528 MachineBasicBlock &FMBB) const override { 529 return false; 530 } 531 532 // Predication support. 533 bool isPredicated(const MachineInstr &MI) const override; 534 535 bool isSchedulingBoundary(const MachineInstr &MI, 536 const MachineBasicBlock *MBB, 537 const MachineFunction &MF) const override; 538 539 bool PredicateInstruction(MachineInstr &MI, 540 ArrayRef<MachineOperand> Pred) const override; 541 542 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 543 ArrayRef<MachineOperand> Pred2) const override; 544 545 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 546 bool SkipDead) const override; 547 548 // Comparison optimization. 549 550 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 551 Register &SrcReg2, int64_t &Mask, 552 int64_t &Value) const override; 553 554 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 555 Register SrcReg2, int64_t Mask, int64_t Value, 556 const MachineRegisterInfo *MRI) const override; 557 558 559 /// Return true if get the base operand, byte offset of an instruction and 560 /// the memory width. Width is the size of memory that is being 561 /// loaded/stored (e.g. 1, 2, 4, 8). 562 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 563 const MachineOperand *&BaseOp, 564 int64_t &Offset, LocationSize &Width, 565 const TargetRegisterInfo *TRI) const; 566 567 bool optimizeCmpPostRA(MachineInstr &MI) const; 568 569 /// Get the base operand and byte offset of an instruction that reads/writes 570 /// memory. 571 bool getMemOperandsWithOffsetWidth( 572 const MachineInstr &LdSt, 573 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 574 bool &OffsetIsScalable, LocationSize &Width, 575 const TargetRegisterInfo *TRI) const override; 576 577 /// Returns true if the two given memory operations should be scheduled 578 /// adjacent. 579 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 580 int64_t Offset1, bool OffsetIsScalable1, 581 ArrayRef<const MachineOperand *> BaseOps2, 582 int64_t Offset2, bool OffsetIsScalable2, 583 unsigned ClusterSize, 584 unsigned NumBytes) const override; 585 586 /// Return true if two MIs access different memory addresses and false 587 /// otherwise 588 bool 589 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 590 const MachineInstr &MIb) const override; 591 592 /// GetInstSize - Return the number of bytes of code the specified 593 /// instruction may be. This returns the maximum number of bytes. 594 /// 595 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 596 597 MCInst getNop() const override; 598 599 std::pair<unsigned, unsigned> 600 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 601 602 ArrayRef<std::pair<unsigned, const char *>> 603 getSerializableDirectMachineOperandTargetFlags() const override; 604 605 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 606 bool expandVSXMemPseudo(MachineInstr &MI) const; 607 608 // Lower pseudo instructions after register allocation. 609 bool expandPostRAPseudo(MachineInstr &MI) const override; 610 611 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 612 static int getRecordFormOpcode(unsigned Opcode); 613 614 bool isTOCSaveMI(const MachineInstr &MI) const; 615 616 std::pair<bool, bool> 617 isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, 618 const MachineRegisterInfo *MRI) const; 619 620 // Return true if the register is sign-extended from 32 to 64 bits. 621 bool isSignExtended(const unsigned Reg, 622 const MachineRegisterInfo *MRI) const { 623 return isSignOrZeroExtended(Reg, 0, MRI).first; 624 } 625 626 // Return true if the register is zero-extended from 32 to 64 bits. 627 bool isZeroExtended(const unsigned Reg, 628 const MachineRegisterInfo *MRI) const { 629 return isSignOrZeroExtended(Reg, 0, MRI).second; 630 } 631 void promoteInstr32To64ForElimEXTSW(const Register &Reg, 632 MachineRegisterInfo *MRI, 633 unsigned BinOpDepth, 634 LiveVariables *LV) const; 635 636 bool convertToImmediateForm(MachineInstr &MI, 637 SmallSet<Register, 4> &RegsToUpdate, 638 MachineInstr **KilledDef = nullptr) const; 639 bool foldFrameOffset(MachineInstr &MI) const; 640 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const; 641 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 642 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 643 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 644 unsigned &XFormOpcode, 645 int64_t &OffsetOfImmInstr, 646 ImmInstrInfo &III) const; 647 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 648 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 649 int64_t OffsetImm) const; 650 651 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 652 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 653 int64_t Imm) const; 654 655 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 656 bool PostRA) const; 657 658 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 659 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 660 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 661 bool &SeenIntermediateUse) const; 662 663 // Materialize immediate after RA. 664 void materializeImmPostRA(MachineBasicBlock &MBB, 665 MachineBasicBlock::iterator MBBI, 666 const DebugLoc &DL, Register Reg, 667 int64_t Imm) const; 668 669 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 670 bool isBDNZ(unsigned Opcode) const; 671 672 /// Find the hardware loop instruction used to set-up the specified loop. 673 /// On PPC, we have two instructions used to set-up the hardware loop 674 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 675 /// instructions to indicate the end of a loop. 676 MachineInstr * 677 findLoopInstr(MachineBasicBlock &PreHeader, 678 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 679 680 /// Analyze loop L, which must be a single-basic-block loop, and if the 681 /// conditions can be understood enough produce a PipelinerLoopInfo object. 682 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 683 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 684 }; 685 686 } 687 688 #endif 689