1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Lanai implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 14 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 15 16 #include "LanaiRegisterInfo.h" 17 #include "MCTargetDesc/LanaiMCTargetDesc.h" 18 #include "llvm/CodeGen/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "LanaiGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class LanaiInstrInfo : public LanaiGenInstrInfo { 26 const LanaiRegisterInfo RegisterInfo; 27 28 public: 29 LanaiInstrInfo(); 30 31 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 32 // such, whenever a client has an instance of instruction info, it should 33 // always be able to get register info as well (through this method). 34 virtual const LanaiRegisterInfo &getRegisterInfo() const { 35 return RegisterInfo; 36 } 37 38 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 39 const MachineInstr &MIb) const override; 40 41 Register isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const override; 43 44 Register isLoadFromStackSlotPostFE(const MachineInstr &MI, 45 int &FrameIndex) const override; 46 47 Register isStoreToStackSlot(const MachineInstr &MI, 48 int &FrameIndex) const override; 49 50 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, 51 const DebugLoc &DL, MCRegister DestinationRegister, 52 MCRegister SourceRegister, bool KillSource, 53 bool RenamableDest = false, 54 bool RenamableSrc = false) const override; 55 56 void storeRegToStackSlot( 57 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, 58 Register SourceRegister, bool IsKill, int FrameIndex, 59 const TargetRegisterClass *RegisterClass, 60 const TargetRegisterInfo *RegisterInfo, Register VReg, 61 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 62 63 void loadRegFromStackSlot( 64 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, 65 Register DestinationRegister, int FrameIndex, 66 const TargetRegisterClass *RegisterClass, 67 const TargetRegisterInfo *RegisterInfo, Register VReg, 68 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 69 70 bool expandPostRAPseudo(MachineInstr &MI) const override; 71 72 bool getMemOperandsWithOffsetWidth( 73 const MachineInstr &LdSt, 74 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 75 bool &OffsetIsScalable, LocationSize &Width, 76 const TargetRegisterInfo *TRI) const override; 77 78 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 79 const MachineOperand *&BaseOp, 80 int64_t &Offset, LocationSize &Width, 81 const TargetRegisterInfo *TRI) const; 82 83 std::pair<unsigned, unsigned> 84 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 85 86 ArrayRef<std::pair<unsigned, const char *>> 87 getSerializableDirectMachineOperandTargetFlags() const override; 88 89 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, 90 MachineBasicBlock *&FalseBlock, 91 SmallVectorImpl<MachineOperand> &Condition, 92 bool AllowModify) const override; 93 94 unsigned removeBranch(MachineBasicBlock &MBB, 95 int *BytesRemoved = nullptr) const override; 96 97 // For a comparison instruction, return the source registers in SrcReg and 98 // SrcReg2 if having two register operands, and the value it compares against 99 // in CmpValue. Return true if the comparison instruction can be analyzed. 100 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 101 Register &SrcReg2, int64_t &CmpMask, 102 int64_t &CmpValue) const override; 103 104 // See if the comparison instruction can be converted into something more 105 // efficient. E.g., on Lanai register-register instructions can set the flag 106 // register, obviating the need for a separate compare. 107 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 108 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 109 const MachineRegisterInfo *MRI) const override; 110 111 // Analyze the given select instruction, returning true if it cannot be 112 // understood. It is assumed that MI->isSelect() is true. 113 // 114 // When successful, return the controlling condition and the operands that 115 // determine the true and false result values. 116 // 117 // Result = SELECT Cond, TrueOp, FalseOp 118 // 119 // Lanai can optimize certain select instructions, for example by predicating 120 // the instruction defining one of the operands and sets Optimizable to true. 121 bool analyzeSelect(const MachineInstr &MI, 122 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 123 unsigned &FalseOp, bool &Optimizable) const override; 124 125 // Given a select instruction that was understood by analyzeSelect and 126 // returned Optimizable = true, attempt to optimize MI by merging it with one 127 // of its operands. Returns NULL on failure. 128 // 129 // When successful, returns the new select instruction. The client is 130 // responsible for deleting MI. 131 // 132 // If both sides of the select can be optimized, the TrueOp is modifed. 133 // PreferFalse is not used. 134 MachineInstr *optimizeSelect(MachineInstr &MI, 135 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 136 bool PreferFalse) const override; 137 138 bool reverseBranchCondition( 139 SmallVectorImpl<MachineOperand> &Condition) const override; 140 141 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, 142 MachineBasicBlock *FalseBlock, 143 ArrayRef<MachineOperand> Condition, 144 const DebugLoc &DL, 145 int *BytesAdded = nullptr) const override; 146 }; 147 148 static inline bool isSPLSOpcode(unsigned Opcode) { 149 switch (Opcode) { 150 case Lanai::LDBs_RI: 151 case Lanai::LDBz_RI: 152 case Lanai::LDHs_RI: 153 case Lanai::LDHz_RI: 154 case Lanai::STB_RI: 155 case Lanai::STH_RI: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static inline bool isRMOpcode(unsigned Opcode) { 163 switch (Opcode) { 164 case Lanai::LDW_RI: 165 case Lanai::SW_RI: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static inline bool isRRMOpcode(unsigned Opcode) { 173 switch (Opcode) { 174 case Lanai::LDBs_RR: 175 case Lanai::LDBz_RR: 176 case Lanai::LDHs_RR: 177 case Lanai::LDHz_RR: 178 case Lanai::LDWz_RR: 179 case Lanai::LDW_RR: 180 case Lanai::STB_RR: 181 case Lanai::STH_RR: 182 case Lanai::SW_RR: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 } // namespace llvm 190 191 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 192