1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares codegen opcodes and related utilities. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_ISDOPCODES_H 14 #define LLVM_CODEGEN_ISDOPCODES_H 15 16 #include "llvm/CodeGen/ValueTypes.h" 17 18 namespace llvm { 19 20 /// ISD namespace - This namespace contains an enum which represents all of the 21 /// SelectionDAG node types and value types. 22 /// 23 namespace ISD { 24 25 //===--------------------------------------------------------------------===// 26 /// ISD::NodeType enum - This enum defines the target-independent operators 27 /// for a SelectionDAG. 28 /// 29 /// Targets may also define target-dependent operator codes for SDNodes. For 30 /// example, on x86, these are the enum values in the X86ISD namespace. 31 /// Targets should aim to use target-independent operators to model their 32 /// instruction sets as much as possible, and only use target-dependent 33 /// operators when they have special requirements. 34 /// 35 /// Finally, during and after selection proper, SNodes may use special 36 /// operator codes that correspond directly with MachineInstr opcodes. These 37 /// are used to represent selected instructions. See the isMachineOpcode() 38 /// and getMachineOpcode() member functions of SDNode. 39 /// 40 enum NodeType { 41 42 /// DELETED_NODE - This is an illegal value that is used to catch 43 /// errors. This opcode is not a legal opcode for any node. 44 DELETED_NODE, 45 46 /// EntryToken - This is the marker used to indicate the start of a region. 47 EntryToken, 48 49 /// TokenFactor - This node takes multiple tokens as input and produces a 50 /// single token result. This is used to represent the fact that the operand 51 /// operators are independent of each other. 52 TokenFactor, 53 54 /// AssertSext, AssertZext - These nodes record if a register contains a 55 /// value that has already been zero or sign extended from a narrower type. 56 /// These nodes take two operands. The first is the node that has already 57 /// been extended, and the second is a value type node indicating the width 58 /// of the extension. 59 /// NOTE: In case of the source value (or any vector element value) is 60 /// poisoned the assertion will not be true for that value. 61 AssertSext, 62 AssertZext, 63 64 /// AssertAlign - These nodes record if a register contains a value that 65 /// has a known alignment and the trailing bits are known to be zero. 66 /// NOTE: In case of the source value (or any vector element value) is 67 /// poisoned the assertion will not be true for that value. 68 AssertAlign, 69 70 /// Various leaf nodes. 71 BasicBlock, 72 VALUETYPE, 73 CONDCODE, 74 Register, 75 RegisterMask, 76 Constant, 77 ConstantFP, 78 GlobalAddress, 79 GlobalTLSAddress, 80 FrameIndex, 81 JumpTable, 82 ConstantPool, 83 ExternalSymbol, 84 BlockAddress, 85 86 /// A ptrauth constant. 87 /// ptr, key, addr-disc, disc 88 /// Note that the addr-disc can be a non-constant value, to allow representing 89 /// a constant global address signed using address-diversification, in code. 90 PtrAuthGlobalAddress, 91 92 /// The address of the GOT 93 GLOBAL_OFFSET_TABLE, 94 95 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 96 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 97 /// of the frame or return address to return. An index of zero corresponds 98 /// to the current function's frame or return address, an index of one to 99 /// the parent's frame or return address, and so on. 100 FRAMEADDR, 101 RETURNADDR, 102 103 /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic. 104 /// This node takes no operand, returns a target-specific pointer to the 105 /// place in the stack frame where the return address of the current 106 /// function is stored. 107 ADDROFRETURNADDR, 108 109 /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument 110 /// and returns the stack pointer value at the entry of the current 111 /// function calling this intrinsic. 112 SPONENTRY, 113 114 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 115 /// Materializes the offset from the local object pointer of another 116 /// function to a particular local object passed to llvm.localescape. The 117 /// operand is the MCSymbol label used to represent this offset, since 118 /// typically the offset is not known until after code generation of the 119 /// parent. 120 LOCAL_RECOVER, 121 122 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 123 /// the DAG, which implements the named register global variables extension. 124 READ_REGISTER, 125 WRITE_REGISTER, 126 127 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 128 /// first (possible) on-stack argument. This is needed for correct stack 129 /// adjustment during unwind. 130 FRAME_TO_ARGS_OFFSET, 131 132 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical 133 /// Frame Address (CFA), generally the value of the stack pointer at the 134 /// call site in the previous frame. 135 EH_DWARF_CFA, 136 137 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 138 /// 'eh_return' gcc dwarf builtin, which is used to return from 139 /// exception. The general meaning is: adjust stack by OFFSET and pass 140 /// execution to HANDLER. Many platform-related details also :) 141 EH_RETURN, 142 143 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 144 /// This corresponds to the eh.sjlj.setjmp intrinsic. 145 /// It takes an input chain and a pointer to the jump buffer as inputs 146 /// and returns an outchain. 147 EH_SJLJ_SETJMP, 148 149 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 150 /// This corresponds to the eh.sjlj.longjmp intrinsic. 151 /// It takes an input chain and a pointer to the jump buffer as inputs 152 /// and returns an outchain. 153 EH_SJLJ_LONGJMP, 154 155 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 156 /// The target initializes the dispatch table here. 157 EH_SJLJ_SETUP_DISPATCH, 158 159 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 160 /// simplification, or lowering of the constant. They are used for constants 161 /// which are known to fit in the immediate fields of their users, or for 162 /// carrying magic numbers which are not values which need to be 163 /// materialized in registers. 164 TargetConstant, 165 TargetConstantFP, 166 167 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 168 /// anything else with this node, and this is valid in the target-specific 169 /// dag, turning into a GlobalAddress operand. 170 TargetGlobalAddress, 171 TargetGlobalTLSAddress, 172 TargetFrameIndex, 173 TargetJumpTable, 174 TargetConstantPool, 175 TargetExternalSymbol, 176 TargetBlockAddress, 177 178 MCSymbol, 179 180 /// TargetIndex - Like a constant pool entry, but with completely 181 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 182 /// 64-bit index. Targets can use this however they like. 183 TargetIndex, 184 185 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 186 /// This node represents a target intrinsic function with no side effects. 187 /// The first operand is the ID number of the intrinsic from the 188 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 189 /// node returns the result of the intrinsic. 190 INTRINSIC_WO_CHAIN, 191 192 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 193 /// This node represents a target intrinsic function with side effects that 194 /// returns a result. The first operand is a chain pointer. The second is 195 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 196 /// operands to the intrinsic follow. The node has two results, the result 197 /// of the intrinsic and an output chain. 198 INTRINSIC_W_CHAIN, 199 200 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 201 /// This node represents a target intrinsic function with side effects that 202 /// does not return a result. The first operand is a chain pointer. The 203 /// second is the ID number of the intrinsic from the llvm::Intrinsic 204 /// namespace. The operands to the intrinsic follow. 205 INTRINSIC_VOID, 206 207 /// CopyToReg - This node has three operands: a chain, a register number to 208 /// set to this value, and a value. 209 CopyToReg, 210 211 /// CopyFromReg - This node indicates that the input value is a virtual or 212 /// physical register that is defined outside of the scope of this 213 /// SelectionDAG. The register is available from the RegisterSDNode object. 214 /// Note that CopyFromReg is considered as also freezing the value. 215 CopyFromReg, 216 217 /// UNDEF - An undefined node. 218 UNDEF, 219 220 /// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or 221 /// is evaluated to UNDEF), or returns VAL otherwise. Note that each 222 /// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot. 223 FREEZE, 224 225 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 226 /// a Constant, which is required to be operand #1) half of the integer or 227 /// float value specified as operand #0. This is only for use before 228 /// legalization, for values that will be broken into multiple registers. 229 EXTRACT_ELEMENT, 230 231 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 232 /// Given two values of the same integer value type, this produces a value 233 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 234 /// legalization. The lower part of the composite value should be in 235 /// element 0 and the upper part should be in element 1. 236 BUILD_PAIR, 237 238 /// MERGE_VALUES - This node takes multiple discrete operands and returns 239 /// them all as its individual results. This nodes has exactly the same 240 /// number of inputs and outputs. This node is useful for some pieces of the 241 /// code generator that want to think about a single node with multiple 242 /// results, not multiple nodes. 243 MERGE_VALUES, 244 245 /// Simple integer binary arithmetic operators. 246 ADD, 247 SUB, 248 MUL, 249 SDIV, 250 UDIV, 251 SREM, 252 UREM, 253 254 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 255 /// a signed/unsigned value of type i[2*N], and return the full value as 256 /// two results, each of type iN. 257 SMUL_LOHI, 258 UMUL_LOHI, 259 260 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 261 /// remainder result. 262 SDIVREM, 263 UDIVREM, 264 265 /// CARRY_FALSE - This node is used when folding other nodes, 266 /// like ADDC/SUBC, which indicate the carry result is always false. 267 CARRY_FALSE, 268 269 /// Carry-setting nodes for multiple precision addition and subtraction. 270 /// These nodes take two operands of the same value type, and produce two 271 /// results. The first result is the normal add or sub result, the second 272 /// result is the carry flag result. 273 /// FIXME: These nodes are deprecated in favor of UADDO_CARRY and USUBO_CARRY. 274 /// They are kept around for now to provide a smooth transition path 275 /// toward the use of UADDO_CARRY/USUBO_CARRY and will eventually be removed. 276 ADDC, 277 SUBC, 278 279 /// Carry-using nodes for multiple precision addition and subtraction. These 280 /// nodes take three operands: The first two are the normal lhs and rhs to 281 /// the add or sub, and the third is the input carry flag. These nodes 282 /// produce two results; the normal result of the add or sub, and the output 283 /// carry flag. These nodes both read and write a carry flag to allow them 284 /// to them to be chained together for add and sub of arbitrarily large 285 /// values. 286 ADDE, 287 SUBE, 288 289 /// Carry-using nodes for multiple precision addition and subtraction. 290 /// These nodes take three operands: The first two are the normal lhs and 291 /// rhs to the add or sub, and the third is a boolean value that is 1 if and 292 /// only if there is an incoming carry/borrow. These nodes produce two 293 /// results: the normal result of the add or sub, and a boolean value that is 294 /// 1 if and only if there is an outgoing carry/borrow. 295 /// 296 /// Care must be taken if these opcodes are lowered to hardware instructions 297 /// that use the inverse logic -- 0 if and only if there is an 298 /// incoming/outgoing carry/borrow. In such cases, you must preserve the 299 /// semantics of these opcodes by inverting the incoming carry/borrow, feeding 300 /// it to the add/sub hardware instruction, and then inverting the outgoing 301 /// carry/borrow. 302 /// 303 /// The use of these opcodes is preferable to ADDE/SUBE if the target supports 304 /// it, as the carry is a regular value rather than a glue, which allows 305 /// further optimisation. 306 /// 307 /// These opcodes are different from [US]{ADD,SUB}O in that 308 /// U{ADD,SUB}O_CARRY consume and produce a carry/borrow, whereas 309 /// [US]{ADD,SUB}O produce an overflow. 310 UADDO_CARRY, 311 USUBO_CARRY, 312 313 /// Carry-using overflow-aware nodes for multiple precision addition and 314 /// subtraction. These nodes take three operands: The first two are normal lhs 315 /// and rhs to the add or sub, and the third is a boolean indicating if there 316 /// is an incoming carry. They produce two results: the normal result of the 317 /// add or sub, and a boolean that indicates if an overflow occurred (*not* 318 /// flag, because it may be a store to memory, etc.). If the type of the 319 /// boolean is not i1 then the high bits conform to getBooleanContents. 320 SADDO_CARRY, 321 SSUBO_CARRY, 322 323 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 324 /// These nodes take two operands: the normal LHS and RHS to the add. They 325 /// produce two results: the normal result of the add, and a boolean that 326 /// indicates if an overflow occurred (*not* a flag, because it may be store 327 /// to memory, etc.). If the type of the boolean is not i1 then the high 328 /// bits conform to getBooleanContents. 329 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 330 SADDO, 331 UADDO, 332 333 /// Same for subtraction. 334 SSUBO, 335 USUBO, 336 337 /// Same for multiplication. 338 SMULO, 339 UMULO, 340 341 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 342 /// integers with the same bit width (W). If the true value of LHS + RHS 343 /// exceeds the largest value that can be represented by W bits, the 344 /// resulting value is this maximum value. Otherwise, if this value is less 345 /// than the smallest value that can be represented by W bits, the 346 /// resulting value is this minimum value. 347 SADDSAT, 348 UADDSAT, 349 350 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 351 /// integers with the same bit width (W). If the true value of LHS - RHS 352 /// exceeds the largest value that can be represented by W bits, the 353 /// resulting value is this maximum value. Otherwise, if this value is less 354 /// than the smallest value that can be represented by W bits, the 355 /// resulting value is this minimum value. 356 SSUBSAT, 357 USUBSAT, 358 359 /// RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift. The first 360 /// operand is the value to be shifted, and the second argument is the amount 361 /// to shift by. Both must be integers of the same bit width (W). If the true 362 /// value of LHS << RHS exceeds the largest value that can be represented by 363 /// W bits, the resulting value is this maximum value, Otherwise, if this 364 /// value is less than the smallest value that can be represented by W bits, 365 /// the resulting value is this minimum value. 366 SSHLSAT, 367 USHLSAT, 368 369 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication 370 /// on 2 integers with the same width and scale. SCALE represents the scale 371 /// of both operands as fixed point numbers. This SCALE parameter must be a 372 /// constant integer. A scale of zero is effectively performing 373 /// multiplication on 2 integers. 374 SMULFIX, 375 UMULFIX, 376 377 /// Same as the corresponding unsaturated fixed point instructions, but the 378 /// result is clamped between the min and max values representable by the 379 /// bits of the first 2 operands. 380 SMULFIXSAT, 381 UMULFIXSAT, 382 383 /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 384 /// 2 integers with the same width and scale. SCALE represents the scale 385 /// of both operands as fixed point numbers. This SCALE parameter must be a 386 /// constant integer. 387 SDIVFIX, 388 UDIVFIX, 389 390 /// Same as the corresponding unsaturated fixed point instructions, but the 391 /// result is clamped between the min and max values representable by the 392 /// bits of the first 2 operands. 393 SDIVFIXSAT, 394 UDIVFIXSAT, 395 396 /// Simple binary floating point operators. 397 FADD, 398 FSUB, 399 FMUL, 400 FDIV, 401 FREM, 402 403 /// Constrained versions of the binary floating point operators. 404 /// These will be lowered to the simple operators before final selection. 405 /// They are used to limit optimizations while the DAG is being 406 /// optimized. 407 STRICT_FADD, 408 STRICT_FSUB, 409 STRICT_FMUL, 410 STRICT_FDIV, 411 STRICT_FREM, 412 STRICT_FMA, 413 414 /// Constrained versions of libm-equivalent floating point intrinsics. 415 /// These will be lowered to the equivalent non-constrained pseudo-op 416 /// (or expanded to the equivalent library call) before final selection. 417 /// They are used to limit optimizations while the DAG is being optimized. 418 STRICT_FSQRT, 419 STRICT_FPOW, 420 STRICT_FPOWI, 421 STRICT_FLDEXP, 422 STRICT_FSIN, 423 STRICT_FCOS, 424 STRICT_FTAN, 425 STRICT_FASIN, 426 STRICT_FACOS, 427 STRICT_FATAN, 428 STRICT_FATAN2, 429 STRICT_FSINH, 430 STRICT_FCOSH, 431 STRICT_FTANH, 432 STRICT_FEXP, 433 STRICT_FEXP2, 434 STRICT_FLOG, 435 STRICT_FLOG10, 436 STRICT_FLOG2, 437 STRICT_FRINT, 438 STRICT_FNEARBYINT, 439 STRICT_FMAXNUM, 440 STRICT_FMINNUM, 441 STRICT_FCEIL, 442 STRICT_FFLOOR, 443 STRICT_FROUND, 444 STRICT_FROUNDEVEN, 445 STRICT_FTRUNC, 446 STRICT_LROUND, 447 STRICT_LLROUND, 448 STRICT_LRINT, 449 STRICT_LLRINT, 450 STRICT_FMAXIMUM, 451 STRICT_FMINIMUM, 452 453 /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or 454 /// unsigned integer. These have the same semantics as fptosi and fptoui 455 /// in IR. 456 /// They are used to limit optimizations while the DAG is being optimized. 457 STRICT_FP_TO_SINT, 458 STRICT_FP_TO_UINT, 459 460 /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to 461 /// a floating point value. These have the same semantics as sitofp and 462 /// uitofp in IR. 463 /// They are used to limit optimizations while the DAG is being optimized. 464 STRICT_SINT_TO_FP, 465 STRICT_UINT_TO_FP, 466 467 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating 468 /// point type down to the precision of the destination VT. TRUNC is a 469 /// flag, which is always an integer that is zero or one. If TRUNC is 0, 470 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not 471 /// change the value of Y. 472 /// 473 /// The TRUNC = 1 case is used in cases where we know that the value will 474 /// not be modified by the node, because Y is not using any of the extra 475 /// precision of source type. This allows certain transformations like 476 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for 477 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't 478 /// removed. 479 /// It is used to limit optimizations while the DAG is being optimized. 480 STRICT_FP_ROUND, 481 482 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP 483 /// type. 484 /// It is used to limit optimizations while the DAG is being optimized. 485 STRICT_FP_EXTEND, 486 487 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used 488 /// for floating-point operands only. STRICT_FSETCC performs a quiet 489 /// comparison operation, while STRICT_FSETCCS performs a signaling 490 /// comparison operation. 491 STRICT_FSETCC, 492 STRICT_FSETCCS, 493 494 /// FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic. 495 FPTRUNC_ROUND, 496 497 /// FMA - Perform a * b + c with no intermediate rounding step. 498 FMA, 499 500 /// FMAD - Perform a * b + c, while getting the same result as the 501 /// separately rounded operations. 502 FMAD, 503 504 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 505 /// DAG node does not require that X and Y have the same type, just that 506 /// they are both floating point. X and the result must have the same type. 507 /// FCOPYSIGN(f32, f64) is allowed. 508 FCOPYSIGN, 509 510 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 511 /// value as an integer 0/1 value. 512 FGETSIGN, 513 514 /// Returns platform specific canonical encoding of a floating point number. 515 FCANONICALIZE, 516 517 /// Performs a check of floating point class property, defined by IEEE-754. 518 /// The first operand is the floating point value to check. The second operand 519 /// specifies the checked property and is a TargetConstant which specifies 520 /// test in the same way as intrinsic 'is_fpclass'. 521 /// Returns boolean value. 522 IS_FPCLASS, 523 524 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector 525 /// with the specified, possibly variable, elements. The types of the 526 /// operands must match the vector element type, except that integer types 527 /// are allowed to be larger than the element type, in which case the 528 /// operands are implicitly truncated. The types of the operands must all 529 /// be the same. 530 BUILD_VECTOR, 531 532 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 533 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 534 /// element type then VAL is truncated before replacement. 535 /// 536 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum 537 /// vector width. IDX is not first scaled by the runtime scaling factor of 538 /// VECTOR. 539 INSERT_VECTOR_ELT, 540 541 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 542 /// identified by the (potentially variable) element number IDX. If the return 543 /// type is an integer type larger than the element type of the vector, the 544 /// result is extended to the width of the return type. In that case, the high 545 /// bits are undefined. 546 /// 547 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum 548 /// vector width. IDX is not first scaled by the runtime scaling factor of 549 /// VECTOR. 550 EXTRACT_VECTOR_ELT, 551 552 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 553 /// vector type with the same length and element type, this produces a 554 /// concatenated vector result value, with length equal to the sum of the 555 /// lengths of the input vectors. If VECTOR0 is a fixed-width vector, then 556 /// VECTOR1..VECTORN must all be fixed-width vectors. Similarly, if VECTOR0 557 /// is a scalable vector, then VECTOR1..VECTORN must all be scalable vectors. 558 CONCAT_VECTORS, 559 560 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 561 /// inserted into VECTOR1. IDX represents the starting element number at which 562 /// VECTOR2 will be inserted. IDX must be a constant multiple of T's known 563 /// minimum vector length. Let the type of VECTOR2 be T, then if T is a 564 /// scalable vector, IDX is first scaled by the runtime scaling factor of T. 565 /// The elements of VECTOR1 starting at IDX are overwritten with VECTOR2. 566 /// Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR1 567 /// indices. If this condition cannot be determined statically but is false at 568 /// runtime, then the result vector is undefined. The IDX parameter must be a 569 /// vector index constant type, which for most targets will be an integer 570 /// pointer type. 571 /// 572 /// This operation supports inserting a fixed-width vector into a scalable 573 /// vector, but not the other way around. 574 INSERT_SUBVECTOR, 575 576 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR. 577 /// Let the result type be T, then IDX represents the starting element number 578 /// from which a subvector of type T is extracted. IDX must be a constant 579 /// multiple of T's known minimum vector length. If T is a scalable vector, 580 /// IDX is first scaled by the runtime scaling factor of T. Elements IDX 581 /// through (IDX + num_elements(T) - 1) must be valid VECTOR indices. If this 582 /// condition cannot be determined statically but is false at runtime, then 583 /// the result vector is undefined. The IDX parameter must be a vector index 584 /// constant type, which for most targets will be an integer pointer type. 585 /// 586 /// This operation supports extracting a fixed-width vector from a scalable 587 /// vector, but not the other way around. 588 EXTRACT_SUBVECTOR, 589 590 /// VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and 591 /// output vectors having the same type. The first output contains the even 592 /// indices from CONCAT_VECTORS(VEC1, VEC2), with the second output 593 /// containing the odd indices. The relative order of elements within an 594 /// output match that of the concatenated input. 595 VECTOR_DEINTERLEAVE, 596 597 /// VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and 598 /// output vectors having the same type. The first output contains the 599 /// result of interleaving the low half of CONCAT_VECTORS(VEC1, VEC2), with 600 /// the second output containing the result of interleaving the high half. 601 VECTOR_INTERLEAVE, 602 603 /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, 604 /// whose elements are shuffled using the following algorithm: 605 /// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i] 606 VECTOR_REVERSE, 607 608 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 609 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 610 /// values that indicate which value (or undef) each result element will 611 /// get. These constant ints are accessible through the 612 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 613 /// 'vperm' instruction, except that the indices must be constants and are 614 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 615 VECTOR_SHUFFLE, 616 617 /// VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as 618 /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways. 619 /// Let the result type be T, if IMM is positive it represents the starting 620 /// element number (an index) from which a subvector of type T is extracted 621 /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count 622 /// specifying the number of trailing elements to extract from VEC1, where the 623 /// elements of T are selected using the following algorithm: 624 /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i] 625 /// If IMM is not in the range [-VL, VL-1] the result vector is undefined. IMM 626 /// is a constant integer. 627 VECTOR_SPLICE, 628 629 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 630 /// scalar value into element 0 of the resultant vector type. The top 631 /// elements 1 to N-1 of the N-element vector are undefined. The type 632 /// of the operand must match the vector element type, except when they 633 /// are integer types. In this case the operand is allowed to be wider 634 /// than the vector element type, and is implicitly truncated to it. 635 SCALAR_TO_VECTOR, 636 637 /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL 638 /// duplicated in all lanes. The type of the operand must match the vector 639 /// element type, except when they are integer types. In this case the 640 /// operand is allowed to be wider than the vector element type, and is 641 /// implicitly truncated to it. 642 SPLAT_VECTOR, 643 644 /// SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the 645 /// scalar values joined together and then duplicated in all lanes. This 646 /// represents a SPLAT_VECTOR that has had its scalar operand expanded. This 647 /// allows representing a 64-bit splat on a target with 32-bit integers. The 648 /// total width of the scalars must cover the element width. SCALAR1 contains 649 /// the least significant bits of the value regardless of endianness and all 650 /// scalars should have the same type. 651 SPLAT_VECTOR_PARTS, 652 653 /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised 654 /// of a linear sequence of unsigned values starting from 0 with a step of 655 /// IMM, where IMM must be a TargetConstant with type equal to the vector 656 /// element type. The arithmetic is performed modulo the bitwidth of the 657 /// element. 658 /// 659 /// The operation does not support returning fixed-width vectors or 660 /// non-constant operands. 661 STEP_VECTOR, 662 663 /// VECTOR_COMPRESS(Vec, Mask, Passthru) 664 /// consecutively place vector elements based on mask 665 /// e.g., vec = {A, B, C, D} and mask = {1, 0, 1, 0} 666 /// --> {A, C, ?, ?} where ? is undefined 667 /// If passthru is defined, ?s are replaced with elements from passthru. 668 /// If passthru is undef, ?s remain undefined. 669 VECTOR_COMPRESS, 670 671 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 672 /// producing an unsigned/signed value of type i[2*N], then return the top 673 /// part. 674 MULHU, 675 MULHS, 676 677 /// AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of 678 /// type i[N+1], halving the result by shifting it one bit right. 679 /// shr(add(ext(X), ext(Y)), 1) 680 AVGFLOORS, 681 AVGFLOORU, 682 /// AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an 683 /// integer of type i[N+2], add 1 and halve the result by shifting it one bit 684 /// right. shr(add(ext(X), ext(Y), 1), 1) 685 AVGCEILS, 686 AVGCEILU, 687 688 /// ABDS/ABDU - Absolute difference - Return the absolute difference between 689 /// two numbers interpreted as signed/unsigned. 690 /// i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1) 691 /// or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1) 692 ABDS, 693 ABDU, 694 695 /// [US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned 696 /// integers. 697 SMIN, 698 SMAX, 699 UMIN, 700 UMAX, 701 702 /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0, 703 /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type 704 /// different to the result. 705 SCMP, 706 UCMP, 707 708 /// Bitwise operators - logical and, logical or, logical xor. 709 AND, 710 OR, 711 XOR, 712 713 /// ABS - Determine the unsigned absolute value of a signed integer value of 714 /// the same bitwidth. 715 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow 716 /// is performed. 717 ABS, 718 719 /// Shift and rotation operations. After legalization, the type of the 720 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 721 /// the shift amount can be any type, but care must be taken to ensure it is 722 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 723 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 724 /// to represent the shift amount. 725 /// When the 1st operand is a vector, the shift amount must be in the same 726 /// type. (TLI.getShiftAmountTy() will return the same type when the input 727 /// type is a vector.) 728 /// For rotates and funnel shifts, the shift amount is treated as an unsigned 729 /// amount modulo the element size of the first operand. 730 /// 731 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. 732 /// 733 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 734 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 735 SHL, 736 SRA, 737 SRL, 738 ROTL, 739 ROTR, 740 FSHL, 741 FSHR, 742 743 /// Byte Swap and Counting operators. 744 BSWAP, 745 CTTZ, 746 CTLZ, 747 CTPOP, 748 BITREVERSE, 749 PARITY, 750 751 /// Bit counting operators with an undefined result for zero inputs. 752 CTTZ_ZERO_UNDEF, 753 CTLZ_ZERO_UNDEF, 754 755 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 756 /// i1 then the high bits must conform to getBooleanContents. 757 SELECT, 758 759 /// Select with a vector condition (op #0) and two vector operands (ops #1 760 /// and #2), returning a vector result. All vectors have the same length. 761 /// Much like the scalar select and setcc, each bit in the condition selects 762 /// whether the corresponding result element is taken from op #1 or op #2. 763 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 764 /// change the condition type in order to match the VSELECT node using a 765 /// pattern. The condition follows the BooleanContent format of the target. 766 VSELECT, 767 768 /// Select with condition operator - This selects between a true value and 769 /// a false value (ops #2 and #3) based on the boolean result of comparing 770 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 771 /// condition code in op #4, a CondCodeSDNode. 772 SELECT_CC, 773 774 /// SetCC operator - This evaluates to a true value iff the condition is 775 /// true. If the result value type is not i1 then the high bits conform 776 /// to getBooleanContents. The operands to this are the left and right 777 /// operands to compare (ops #0, and #1) and the condition code to compare 778 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 779 /// then the result type must also be a vector type. 780 SETCC, 781 782 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 783 /// op #2 is a boolean indicating if there is an incoming carry. This 784 /// operator checks the result of "LHS - RHS - Carry", and can be used to 785 /// compare two wide integers: 786 /// (setcccarry lhshi rhshi (usubo_carry lhslo rhslo) cc). 787 /// Only valid for integers. 788 SETCCCARRY, 789 790 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 791 /// integer shift operations. The operation ordering is: 792 /// 793 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 794 SHL_PARTS, 795 SRA_PARTS, 796 SRL_PARTS, 797 798 /// Conversion operators. These are all single input single output 799 /// operations. For all of these, the result type must be strictly 800 /// wider or narrower (depending on the operation) than the source 801 /// type. 802 803 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 804 /// into new bits. 805 SIGN_EXTEND, 806 807 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. Can carry 808 /// the NonNeg SDNodeFlag to indicate that the input is known to be 809 /// non-negative. If the flag is present and the input is negative, the result 810 /// is poison. 811 ZERO_EXTEND, 812 813 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 814 ANY_EXTEND, 815 816 /// TRUNCATE - Completely drop the high bits. 817 TRUNCATE, 818 /// TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand 819 /// [SU] located in middle, prefix for `SAT` means indicates whether 820 /// existing truncate target was a signed operation. For examples, 821 /// If `truncate(smin(smax(x, C), C))` was saturated then become `S`. 822 /// If `truncate(umin(x, C))` was saturated then become `U`. 823 /// [SU] located in last indicates whether range of truncated values is 824 /// sign-saturated. For example, if `truncate(smin(smax(x, C), C))` is a 825 /// truncation to `i8`, then if value of C ranges from `-128 to 127`, it will 826 /// be saturated against signed values, resulting in `S`, which will combine 827 /// to `TRUNCATE_SSAT_S`. If the value of C ranges from `0 to 255`, it will 828 /// be saturated against unsigned values, resulting in `U`, which will 829 /// combine to `TRUNCATE_SSAT_U`. Similarly, in `truncate(umin(x, C))`, if 830 /// value of C ranges from `0 to 255`, it becomes `U` because it is saturated 831 /// for unsigned values. As a result, it combines to `TRUNCATE_USAT_U`. 832 TRUNCATE_SSAT_S, // saturate signed input to signed result - 833 // truncate(smin(smax(x, C), C)) 834 TRUNCATE_SSAT_U, // saturate signed input to unsigned result - 835 // truncate(smin(smax(x, 0), C)) 836 TRUNCATE_USAT_U, // saturate unsigned input to unsigned result - 837 // truncate(umin(x, C)) 838 839 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 840 /// depends on the first letter) to floating point. 841 SINT_TO_FP, 842 UINT_TO_FP, 843 844 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 845 /// sign extend a small value in a large integer register (e.g. sign 846 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 847 /// with the 7th bit). The size of the smaller type is indicated by the 1th 848 /// operand, a ValueType node. 849 SIGN_EXTEND_INREG, 850 851 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 852 /// in-register any-extension of the low lanes of an integer vector. The 853 /// result type must have fewer elements than the operand type, and those 854 /// elements must be larger integer types such that the total size of the 855 /// operand type is less than or equal to the size of the result type. Each 856 /// of the low operand elements is any-extended into the corresponding, 857 /// wider result elements with the high bits becoming undef. 858 /// NOTE: The type legalizer prefers to make the operand and result size 859 /// the same to allow expansion to shuffle vector during op legalization. 860 ANY_EXTEND_VECTOR_INREG, 861 862 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 863 /// in-register sign-extension of the low lanes of an integer vector. The 864 /// result type must have fewer elements than the operand type, and those 865 /// elements must be larger integer types such that the total size of the 866 /// operand type is less than or equal to the size of the result type. Each 867 /// of the low operand elements is sign-extended into the corresponding, 868 /// wider result elements. 869 /// NOTE: The type legalizer prefers to make the operand and result size 870 /// the same to allow expansion to shuffle vector during op legalization. 871 SIGN_EXTEND_VECTOR_INREG, 872 873 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 874 /// in-register zero-extension of the low lanes of an integer vector. The 875 /// result type must have fewer elements than the operand type, and those 876 /// elements must be larger integer types such that the total size of the 877 /// operand type is less than or equal to the size of the result type. Each 878 /// of the low operand elements is zero-extended into the corresponding, 879 /// wider result elements. 880 /// NOTE: The type legalizer prefers to make the operand and result size 881 /// the same to allow expansion to shuffle vector during op legalization. 882 ZERO_EXTEND_VECTOR_INREG, 883 884 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 885 /// integer. These have the same semantics as fptosi and fptoui in IR. If 886 /// the FP value cannot fit in the integer type, the results are undefined. 887 FP_TO_SINT, 888 FP_TO_UINT, 889 890 /// FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a 891 /// signed or unsigned scalar integer type given in operand 1 with the 892 /// following semantics: 893 /// 894 /// * If the value is NaN, zero is returned. 895 /// * If the value is larger/smaller than the largest/smallest integer, 896 /// the largest/smallest integer is returned (saturation). 897 /// * Otherwise the result of rounding the value towards zero is returned. 898 /// 899 /// The scalar width of the type given in operand 1 must be equal to, or 900 /// smaller than, the scalar result type width. It may end up being smaller 901 /// than the result width as a result of integer type legalization. 902 /// 903 /// After converting to the scalar integer type in operand 1, the value is 904 /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT 905 /// zero extends. 906 FP_TO_SINT_SAT, 907 FP_TO_UINT_SAT, 908 909 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 910 /// down to the precision of the destination VT. TRUNC is a flag, which is 911 /// always an integer that is zero or one. If TRUNC is 0, this is a 912 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 913 /// value of Y. 914 /// 915 /// The TRUNC = 1 case is used in cases where we know that the value will 916 /// not be modified by the node, because Y is not using any of the extra 917 /// precision of source type. This allows certain transformations like 918 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 919 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 920 FP_ROUND, 921 922 /// Returns current rounding mode: 923 /// -1 Undefined 924 /// 0 Round to 0 925 /// 1 Round to nearest, ties to even 926 /// 2 Round to +inf 927 /// 3 Round to -inf 928 /// 4 Round to nearest, ties to zero 929 /// Other values are target dependent. 930 /// Result is rounding mode and chain. Input is a chain. 931 GET_ROUNDING, 932 933 /// Set rounding mode. 934 /// The first operand is a chain pointer. The second specifies the required 935 /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'. 936 SET_ROUNDING, 937 938 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 939 FP_EXTEND, 940 941 /// BITCAST - This operator converts between integer, vector and FP 942 /// values, as if the value was stored to memory with one type and loaded 943 /// from the same address with the other type (or equivalently for vector 944 /// format conversions, etc). The source and result are required to have 945 /// the same bit size (e.g. f32 <-> i32). This can also be used for 946 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 947 /// getNode(). 948 /// 949 /// This operator is subtly different from the bitcast instruction from 950 /// LLVM-IR since this node may change the bits in the register. For 951 /// example, this occurs on big-endian NEON and big-endian MSA where the 952 /// layout of the bits in the register depends on the vector type and this 953 /// operator acts as a shuffle operation for some vector type combinations. 954 BITCAST, 955 956 /// ADDRSPACECAST - This operator converts between pointers of different 957 /// address spaces. 958 ADDRSPACECAST, 959 960 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 961 /// and truncation for half-precision (16 bit) floating numbers. These nodes 962 /// form a semi-softened interface for dealing with f16 (as an i16), which 963 /// is often a storage-only type but has native conversions. 964 FP16_TO_FP, 965 FP_TO_FP16, 966 STRICT_FP16_TO_FP, 967 STRICT_FP_TO_FP16, 968 969 /// BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions 970 /// and truncation for bfloat16. These nodes form a semi-softened interface 971 /// for dealing with bf16 (as an i16), which is often a storage-only type but 972 /// has native conversions. 973 BF16_TO_FP, 974 FP_TO_BF16, 975 STRICT_BF16_TO_FP, 976 STRICT_FP_TO_BF16, 977 978 /// Perform various unary floating-point operations inspired by libm. For 979 /// FPOWI, the result is undefined if the integer operand doesn't fit into 980 /// sizeof(int). 981 FNEG, 982 FABS, 983 FSQRT, 984 FCBRT, 985 FSIN, 986 FCOS, 987 FTAN, 988 FASIN, 989 FACOS, 990 FATAN, 991 FSINH, 992 FCOSH, 993 FTANH, 994 FPOW, 995 FPOWI, 996 /// FLDEXP - ldexp, inspired by libm (op0 * 2**op1). 997 FLDEXP, 998 /// FATAN2 - atan2, inspired by libm. 999 FATAN2, 1000 1001 /// FFREXP - frexp, extract fractional and exponent component of a 1002 /// floating-point value. Returns the two components as separate return 1003 /// values. 1004 FFREXP, 1005 1006 FLOG, 1007 FLOG2, 1008 FLOG10, 1009 FEXP, 1010 FEXP2, 1011 FEXP10, 1012 FCEIL, 1013 FTRUNC, 1014 FRINT, 1015 FNEARBYINT, 1016 FROUND, 1017 FROUNDEVEN, 1018 FFLOOR, 1019 LROUND, 1020 LLROUND, 1021 LRINT, 1022 LLRINT, 1023 1024 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 1025 /// values. 1026 /// 1027 /// In the case where a single input is a NaN (either signaling or quiet), 1028 /// the non-NaN input is returned. 1029 /// 1030 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 1031 FMINNUM, 1032 FMAXNUM, 1033 1034 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or 1035 /// maximumNumber on two values, following IEEE-754 definitions. This differs 1036 /// from FMINNUM/FMAXNUM in the handling of signaling NaNs, and signed zero. 1037 /// 1038 /// If one input is a signaling NaN, returns a quiet NaN. This matches 1039 /// IEEE-754 2008's minnum/maxnum behavior for signaling NaNs (which differs 1040 /// from 2019). 1041 /// 1042 /// These treat -0 as ordered less than +0, matching the behavior of IEEE-754 1043 /// 2019's minimumNumber/maximumNumber. 1044 FMINNUM_IEEE, 1045 FMAXNUM_IEEE, 1046 1047 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 1048 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008 1049 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2019 semantics. 1050 FMINIMUM, 1051 FMAXIMUM, 1052 1053 /// FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with 1054 /// FMINNUM_IEEE and FMAXNUM_IEEE besides if either operand is sNaN. 1055 FMINIMUMNUM, 1056 FMAXIMUMNUM, 1057 1058 /// FSINCOS - Compute both fsin and fcos as a single operation. 1059 FSINCOS, 1060 1061 /// Gets the current floating-point environment. The first operand is a token 1062 /// chain. The results are FP environment, represented by an integer value, 1063 /// and a token chain. 1064 GET_FPENV, 1065 1066 /// Sets the current floating-point environment. The first operand is a token 1067 /// chain, the second is FP environment, represented by an integer value. The 1068 /// result is a token chain. 1069 SET_FPENV, 1070 1071 /// Set floating-point environment to default state. The first operand and the 1072 /// result are token chains. 1073 RESET_FPENV, 1074 1075 /// Gets the current floating-point environment. The first operand is a token 1076 /// chain, the second is a pointer to memory, where FP environment is stored 1077 /// to. The result is a token chain. 1078 GET_FPENV_MEM, 1079 1080 /// Sets the current floating point environment. The first operand is a token 1081 /// chain, the second is a pointer to memory, where FP environment is loaded 1082 /// from. The result is a token chain. 1083 SET_FPENV_MEM, 1084 1085 /// Reads the current dynamic floating-point control modes. The operand is 1086 /// a token chain. 1087 GET_FPMODE, 1088 1089 /// Sets the current dynamic floating-point control modes. The first operand 1090 /// is a token chain, the second is control modes set represented as integer 1091 /// value. 1092 SET_FPMODE, 1093 1094 /// Sets default dynamic floating-point control modes. The operand is a 1095 /// token chain. 1096 RESET_FPMODE, 1097 1098 /// LOAD and STORE have token chains as their first operand, then the same 1099 /// operands as an LLVM load/store instruction, then an offset node that 1100 /// is added / subtracted from the base pointer to form the address (for 1101 /// indexed memory ops). 1102 LOAD, 1103 STORE, 1104 1105 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 1106 /// to a specified boundary. This node always has two return values: a new 1107 /// stack pointer value and a chain. The first operand is the token chain, 1108 /// the second is the number of bytes to allocate, and the third is the 1109 /// alignment boundary. The size is guaranteed to be a multiple of the 1110 /// stack alignment, and the alignment is guaranteed to be bigger than the 1111 /// stack alignment (if required) or 0 to get standard stack alignment. 1112 DYNAMIC_STACKALLOC, 1113 1114 /// Control flow instructions. These all have token chains. 1115 1116 /// BR - Unconditional branch. The first operand is the chain 1117 /// operand, the second is the MBB to branch to. 1118 BR, 1119 1120 /// BRIND - Indirect branch. The first operand is the chain, the second 1121 /// is the value to branch to, which must be of the same type as the 1122 /// target's pointer type. 1123 BRIND, 1124 1125 /// BR_JT - Jumptable branch. The first operand is the chain, the second 1126 /// is the jumptable index, the last one is the jumptable entry index. 1127 BR_JT, 1128 1129 /// JUMP_TABLE_DEBUG_INFO - Jumptable debug info. The first operand is the 1130 /// chain, the second is the jumptable index. 1131 JUMP_TABLE_DEBUG_INFO, 1132 1133 /// BRCOND - Conditional branch. The first operand is the chain, the 1134 /// second is the condition, the third is the block to branch to if the 1135 /// condition is true. If the type of the condition is not i1, then the 1136 /// high bits must conform to getBooleanContents. If the condition is undef, 1137 /// it nondeterministically jumps to the block. 1138 /// TODO: Its semantics w.r.t undef requires further discussion; we need to 1139 /// make it sure that it is consistent with optimizations in MIR & the 1140 /// meaning of IMPLICIT_DEF. See https://reviews.llvm.org/D92015 1141 BRCOND, 1142 1143 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 1144 /// that the condition is represented as condition code, and two nodes to 1145 /// compare, rather than as a combined SetCC node. The operands in order 1146 /// are chain, cc, lhs, rhs, block to branch to if condition is true. If 1147 /// condition is undef, it nondeterministically jumps to the block. 1148 BR_CC, 1149 1150 /// INLINEASM - Represents an inline asm block. This node always has two 1151 /// return values: a chain and a flag result. The inputs are as follows: 1152 /// Operand #0 : Input chain. 1153 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 1154 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 1155 /// Operand #3 : HasSideEffect, IsAlignStack bits. 1156 /// After this, it is followed by a list of operands with this format: 1157 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 1158 /// of operands that follow, etc. See InlineAsm.h. 1159 /// ... however many operands ... 1160 /// Operand #last: Optional, an incoming flag. 1161 /// 1162 /// The variable width operands are required to represent target addressing 1163 /// modes as a single "operand", even though they may have multiple 1164 /// SDOperands. 1165 INLINEASM, 1166 1167 /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto. 1168 INLINEASM_BR, 1169 1170 /// EH_LABEL - Represents a label in mid basic block used to track 1171 /// locations needed for debug and exception handling tables. These nodes 1172 /// take a chain as input and return a chain. 1173 EH_LABEL, 1174 1175 /// ANNOTATION_LABEL - Represents a mid basic block label used by 1176 /// annotations. This should remain within the basic block and be ordered 1177 /// with respect to other call instructions, but loads and stores may float 1178 /// past it. 1179 ANNOTATION_LABEL, 1180 1181 /// CATCHRET - Represents a return from a catch block funclet. Used for 1182 /// MSVC compatible exception handling. Takes a chain operand and a 1183 /// destination basic block operand. 1184 CATCHRET, 1185 1186 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 1187 /// MSVC compatible exception handling. Takes only a chain operand. 1188 CLEANUPRET, 1189 1190 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 1191 /// value, the same type as the pointer type for the system, and an output 1192 /// chain. 1193 STACKSAVE, 1194 1195 /// STACKRESTORE has two operands, an input chain and a pointer to restore 1196 /// to it returns an output chain. 1197 STACKRESTORE, 1198 1199 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 1200 /// of a call sequence, and carry arbitrary information that target might 1201 /// want to know. The first operand is a chain, the rest are specified by 1202 /// the target and not touched by the DAG optimizers. 1203 /// Targets that may use stack to pass call arguments define additional 1204 /// operands: 1205 /// - size of the call frame part that must be set up within the 1206 /// CALLSEQ_START..CALLSEQ_END pair, 1207 /// - part of the call frame prepared prior to CALLSEQ_START. 1208 /// Both these parameters must be constants, their sum is the total call 1209 /// frame size. 1210 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 1211 CALLSEQ_START, // Beginning of a call sequence 1212 CALLSEQ_END, // End of a call sequence 1213 1214 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 1215 /// and the alignment. It returns a pair of values: the vaarg value and a 1216 /// new chain. 1217 VAARG, 1218 1219 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 1220 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 1221 /// source. 1222 VACOPY, 1223 1224 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 1225 /// pointer, and a SRCVALUE. 1226 VAEND, 1227 VASTART, 1228 1229 /// PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE 1230 /// with the preallocated call Value. 1231 PREALLOCATED_SETUP, 1232 /// PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE 1233 /// with the preallocated call Value, and a constant int. 1234 PREALLOCATED_ARG, 1235 1236 /// SRCVALUE - This is a node type that holds a Value* that is used to 1237 /// make reference to a value in the LLVM IR. 1238 SRCVALUE, 1239 1240 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 1241 /// reference metadata in the IR. 1242 MDNODE_SDNODE, 1243 1244 /// PCMARKER - This corresponds to the pcmarker intrinsic. 1245 PCMARKER, 1246 1247 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 1248 /// It produces a chain and one i64 value. The only operand is a chain. 1249 /// If i64 is not legal, the result will be expanded into smaller values. 1250 /// Still, it returns an i64, so targets should set legality for i64. 1251 /// The result is the content of the architecture-specific cycle 1252 /// counter-like register (or other high accuracy low latency clock source). 1253 READCYCLECOUNTER, 1254 1255 /// READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic. 1256 /// It has the same semantics as the READCYCLECOUNTER implementation except 1257 /// that the result is the content of the architecture-specific fixed 1258 /// frequency counter suitable for measuring elapsed time. 1259 READSTEADYCOUNTER, 1260 1261 /// HANDLENODE node - Used as a handle for various purposes. 1262 HANDLENODE, 1263 1264 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 1265 /// takes as input a token chain, the pointer to the trampoline, the pointer 1266 /// to the nested function, the pointer to pass for the 'nest' parameter, a 1267 /// SRCVALUE for the trampoline and another for the nested function 1268 /// (allowing targets to access the original Function*). 1269 /// It produces a token chain as output. 1270 INIT_TRAMPOLINE, 1271 1272 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 1273 /// It takes a pointer to the trampoline and produces a (possibly) new 1274 /// pointer to the same trampoline with platform-specific adjustments 1275 /// applied. The pointer it returns points to an executable block of code. 1276 ADJUST_TRAMPOLINE, 1277 1278 /// TRAP - Trapping instruction 1279 TRAP, 1280 1281 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 1282 DEBUGTRAP, 1283 1284 /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer 1285 /// failure. 1286 UBSANTRAP, 1287 1288 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 1289 /// is the chain. The other operands are the address to prefetch, 1290 /// read / write specifier, locality specifier and instruction / data cache 1291 /// specifier. 1292 PREFETCH, 1293 1294 /// ARITH_FENCE - This corresponds to a arithmetic fence intrinsic. Both its 1295 /// operand and output are the same floating type. 1296 ARITH_FENCE, 1297 1298 /// MEMBARRIER - Compiler barrier only; generate a no-op. 1299 MEMBARRIER, 1300 1301 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 1302 /// This corresponds to the fence instruction. It takes an input chain, and 1303 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 1304 ATOMIC_FENCE, 1305 1306 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 1307 /// This corresponds to "load atomic" instruction. 1308 ATOMIC_LOAD, 1309 1310 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, val, ptr) 1311 /// This corresponds to "store atomic" instruction. 1312 ATOMIC_STORE, 1313 1314 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 1315 /// For double-word atomic operations: 1316 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 1317 /// swapLo, swapHi) 1318 /// This corresponds to the cmpxchg instruction. 1319 ATOMIC_CMP_SWAP, 1320 1321 /// Val, Success, OUTCHAIN 1322 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 1323 /// N.b. this is still a strong cmpxchg operation, so 1324 /// Success == "Val == cmp". 1325 ATOMIC_CMP_SWAP_WITH_SUCCESS, 1326 1327 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 1328 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 1329 /// For double-word atomic operations: 1330 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 1331 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 1332 /// These correspond to the atomicrmw instruction. 1333 ATOMIC_SWAP, 1334 ATOMIC_LOAD_ADD, 1335 ATOMIC_LOAD_SUB, 1336 ATOMIC_LOAD_AND, 1337 ATOMIC_LOAD_CLR, 1338 ATOMIC_LOAD_OR, 1339 ATOMIC_LOAD_XOR, 1340 ATOMIC_LOAD_NAND, 1341 ATOMIC_LOAD_MIN, 1342 ATOMIC_LOAD_MAX, 1343 ATOMIC_LOAD_UMIN, 1344 ATOMIC_LOAD_UMAX, 1345 ATOMIC_LOAD_FADD, 1346 ATOMIC_LOAD_FSUB, 1347 ATOMIC_LOAD_FMAX, 1348 ATOMIC_LOAD_FMIN, 1349 ATOMIC_LOAD_UINC_WRAP, 1350 ATOMIC_LOAD_UDEC_WRAP, 1351 ATOMIC_LOAD_USUB_COND, 1352 ATOMIC_LOAD_USUB_SAT, 1353 1354 /// Masked load and store - consecutive vector load and store operations 1355 /// with additional mask operand that prevents memory accesses to the 1356 /// masked-off lanes. 1357 /// 1358 /// Val, OutChain = MLOAD(BasePtr, Mask, PassThru) 1359 /// OutChain = MSTORE(Value, BasePtr, Mask) 1360 MLOAD, 1361 MSTORE, 1362 1363 /// Masked gather and scatter - load and store operations for a vector of 1364 /// random addresses with additional mask operand that prevents memory 1365 /// accesses to the masked-off lanes. 1366 /// 1367 /// Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale) 1368 /// OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale) 1369 /// 1370 /// The Index operand can have more vector elements than the other operands 1371 /// due to type legalization. The extra elements are ignored. 1372 MGATHER, 1373 MSCATTER, 1374 1375 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 1376 /// is the chain and the second operand is the alloca pointer. 1377 LIFETIME_START, 1378 LIFETIME_END, 1379 1380 /// FAKE_USE represents a use of the operand but does not do anything. 1381 /// Its purpose is the extension of the operand's lifetime mainly for 1382 /// debugging purposes. 1383 FAKE_USE, 1384 1385 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 1386 /// beginning and end of GC transition sequence, and carry arbitrary 1387 /// information that target might need for lowering. The first operand is 1388 /// a chain, the rest are specified by the target and not touched by the DAG 1389 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 1390 /// nested. 1391 GC_TRANSITION_START, 1392 GC_TRANSITION_END, 1393 1394 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 1395 /// the most recent dynamic alloca. For most targets that would be 0, but 1396 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 1397 /// known nonzero constant. The only operand here is the chain. 1398 GET_DYNAMIC_AREA_OFFSET, 1399 1400 /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve 1401 /// the sample counts quality. 1402 PSEUDO_PROBE, 1403 1404 /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the 1405 /// number of elements within a scalable vector. IMM is a constant integer 1406 /// multiplier that is applied to the runtime value. 1407 VSCALE, 1408 1409 /// Generic reduction nodes. These nodes represent horizontal vector 1410 /// reduction operations, producing a scalar result. 1411 /// The SEQ variants perform reductions in sequential order. The first 1412 /// operand is an initial scalar accumulator value, and the second operand 1413 /// is the vector to reduce. 1414 /// E.g. RES = VECREDUCE_SEQ_FADD f32 ACC, <4 x f32> SRC_VEC 1415 /// ... is equivalent to 1416 /// RES = (((ACC + SRC_VEC[0]) + SRC_VEC[1]) + SRC_VEC[2]) + SRC_VEC[3] 1417 VECREDUCE_SEQ_FADD, 1418 VECREDUCE_SEQ_FMUL, 1419 1420 /// These reductions have relaxed evaluation order semantics, and have a 1421 /// single vector operand. The order of evaluation is unspecified. For 1422 /// pow-of-2 vectors, one valid legalizer expansion is to use a tree 1423 /// reduction, i.e.: 1424 /// For RES = VECREDUCE_FADD <8 x f16> SRC_VEC 1425 /// 1426 /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7] 1427 /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3] 1428 /// RES = FADD PART_RDX2[0], PART_RDX2[1] 1429 /// 1430 /// For non-pow-2 vectors, this can be computed by extracting each element 1431 /// and performing the operation as if it were scalarized. 1432 VECREDUCE_FADD, 1433 VECREDUCE_FMUL, 1434 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. 1435 VECREDUCE_FMAX, 1436 VECREDUCE_FMIN, 1437 /// FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the 1438 /// llvm.minimum and llvm.maximum semantics. 1439 VECREDUCE_FMAXIMUM, 1440 VECREDUCE_FMINIMUM, 1441 /// Integer reductions may have a result type larger than the vector element 1442 /// type. However, the reduction is performed using the vector element type 1443 /// and the value in the top bits is unspecified. 1444 VECREDUCE_ADD, 1445 VECREDUCE_MUL, 1446 VECREDUCE_AND, 1447 VECREDUCE_OR, 1448 VECREDUCE_XOR, 1449 VECREDUCE_SMAX, 1450 VECREDUCE_SMIN, 1451 VECREDUCE_UMAX, 1452 VECREDUCE_UMIN, 1453 1454 // The `llvm.experimental.stackmap` intrinsic. 1455 // Operands: input chain, glue, <id>, <numShadowBytes>, [live0[, live1...]] 1456 // Outputs: output chain, glue 1457 STACKMAP, 1458 1459 // The `llvm.experimental.patchpoint.*` intrinsic. 1460 // Operands: input chain, [glue], reg-mask, <id>, <numShadowBytes>, callee, 1461 // <numArgs>, cc, ... 1462 // Outputs: [rv], output chain, glue 1463 PATCHPOINT, 1464 1465 // Vector Predication 1466 #define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...) VPSDID, 1467 #include "llvm/IR/VPIntrinsics.def" 1468 1469 // The `llvm.experimental.convergence.*` intrinsics. 1470 CONVERGENCECTRL_ANCHOR, 1471 CONVERGENCECTRL_ENTRY, 1472 CONVERGENCECTRL_LOOP, 1473 // This does not correspond to any convergence control intrinsic. It is used 1474 // to glue a convergence control token to a convergent operation in the DAG, 1475 // which is later translated to an implicit use in the MIR. 1476 CONVERGENCECTRL_GLUE, 1477 1478 // Experimental vector histogram intrinsic 1479 // Operands: Input Chain, Inc, Mask, Base, Index, Scale, ID 1480 // Output: Output Chain 1481 EXPERIMENTAL_VECTOR_HISTOGRAM, 1482 1483 // Finds the index of the last active mask element 1484 // Operands: Mask 1485 VECTOR_FIND_LAST_ACTIVE, 1486 1487 // llvm.clear_cache intrinsic 1488 // Operands: Input Chain, Start Addres, End Address 1489 // Outputs: Output Chain 1490 CLEAR_CACHE, 1491 1492 /// BUILTIN_OP_END - This must be the last enum value in this list. 1493 /// The target-specific pre-isel opcode values start here. 1494 BUILTIN_OP_END 1495 }; 1496 1497 /// Whether this is bitwise logic opcode. 1498 inline bool isBitwiseLogicOp(unsigned Opcode) { 1499 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; 1500 } 1501 1502 /// Given a \p MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns 1503 /// ISD::(U|S)MAX and ISD::(U|S)MIN, respectively. 1504 NodeType getInverseMinMaxOpcode(unsigned MinMaxOpc); 1505 1506 /// Get underlying scalar opcode for VECREDUCE opcode. 1507 /// For example ISD::AND for ISD::VECREDUCE_AND. 1508 NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode); 1509 1510 /// Whether this is a vector-predicated Opcode. 1511 bool isVPOpcode(unsigned Opcode); 1512 1513 /// Whether this is a vector-predicated binary operation opcode. 1514 bool isVPBinaryOp(unsigned Opcode); 1515 1516 /// Whether this is a vector-predicated reduction opcode. 1517 bool isVPReduction(unsigned Opcode); 1518 1519 /// The operand position of the vector mask. 1520 std::optional<unsigned> getVPMaskIdx(unsigned Opcode); 1521 1522 /// The operand position of the explicit vector length parameter. 1523 std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode); 1524 1525 /// Translate this VP Opcode to its corresponding non-VP Opcode. 1526 std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept); 1527 1528 /// Translate this non-VP Opcode to its corresponding VP Opcode. 1529 std::optional<unsigned> getVPForBaseOpcode(unsigned Opcode); 1530 1531 //===--------------------------------------------------------------------===// 1532 /// MemIndexedMode enum - This enum defines the load / store indexed 1533 /// addressing modes. 1534 /// 1535 /// UNINDEXED "Normal" load / store. The effective address is already 1536 /// computed and is available in the base pointer. The offset 1537 /// operand is always undefined. In addition to producing a 1538 /// chain, an unindexed load produces one value (result of the 1539 /// load); an unindexed store does not produce a value. 1540 /// 1541 /// PRE_INC Similar to the unindexed mode where the effective address is 1542 /// PRE_DEC the value of the base pointer add / subtract the offset. 1543 /// It considers the computation as being folded into the load / 1544 /// store operation (i.e. the load / store does the address 1545 /// computation as well as performing the memory transaction). 1546 /// The base operand is always undefined. In addition to 1547 /// producing a chain, pre-indexed load produces two values 1548 /// (result of the load and the result of the address 1549 /// computation); a pre-indexed store produces one value (result 1550 /// of the address computation). 1551 /// 1552 /// POST_INC The effective address is the value of the base pointer. The 1553 /// POST_DEC value of the offset operand is then added to / subtracted 1554 /// from the base after memory transaction. In addition to 1555 /// producing a chain, post-indexed load produces two values 1556 /// (the result of the load and the result of the base +/- offset 1557 /// computation); a post-indexed store produces one value (the 1558 /// the result of the base +/- offset computation). 1559 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; 1560 1561 static const int LAST_INDEXED_MODE = POST_DEC + 1; 1562 1563 //===--------------------------------------------------------------------===// 1564 /// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's 1565 /// index parameter when calculating addresses. 1566 /// 1567 /// SIGNED_SCALED Addr = Base + ((signed)Index * Scale) 1568 /// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * Scale) 1569 /// 1570 /// NOTE: The value of Scale is typically only known to the node owning the 1571 /// IndexType, with a value of 1 the equivalent of being unscaled. 1572 enum MemIndexType { SIGNED_SCALED = 0, UNSIGNED_SCALED }; 1573 1574 static const int LAST_MEM_INDEX_TYPE = UNSIGNED_SCALED + 1; 1575 1576 inline bool isIndexTypeSigned(MemIndexType IndexType) { 1577 return IndexType == SIGNED_SCALED; 1578 } 1579 1580 //===--------------------------------------------------------------------===// 1581 /// LoadExtType enum - This enum defines the three variants of LOADEXT 1582 /// (load with extension). 1583 /// 1584 /// SEXTLOAD loads the integer operand and sign extends it to a larger 1585 /// integer result type. 1586 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 1587 /// integer result type. 1588 /// EXTLOAD is used for two things: floating point extending loads and 1589 /// integer extending loads [the top bits are undefined]. 1590 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; 1591 1592 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1; 1593 1594 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 1595 1596 //===--------------------------------------------------------------------===// 1597 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 1598 /// below work out, when considering SETFALSE (something that never exists 1599 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 1600 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 1601 /// to. If the "N" column is 1, the result of the comparison is undefined if 1602 /// the input is a NAN. 1603 /// 1604 /// All of these (except for the 'always folded ops') should be handled for 1605 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 1606 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 1607 /// 1608 /// Note that these are laid out in a specific order to allow bit-twiddling 1609 /// to transform conditions. 1610 enum CondCode { 1611 // Opcode N U L G E Intuitive operation 1612 SETFALSE, // 0 0 0 0 Always false (always folded) 1613 SETOEQ, // 0 0 0 1 True if ordered and equal 1614 SETOGT, // 0 0 1 0 True if ordered and greater than 1615 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 1616 SETOLT, // 0 1 0 0 True if ordered and less than 1617 SETOLE, // 0 1 0 1 True if ordered and less than or equal 1618 SETONE, // 0 1 1 0 True if ordered and operands are unequal 1619 SETO, // 0 1 1 1 True if ordered (no nans) 1620 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 1621 SETUEQ, // 1 0 0 1 True if unordered or equal 1622 SETUGT, // 1 0 1 0 True if unordered or greater than 1623 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 1624 SETULT, // 1 1 0 0 True if unordered or less than 1625 SETULE, // 1 1 0 1 True if unordered, less than, or equal 1626 SETUNE, // 1 1 1 0 True if unordered or not equal 1627 SETTRUE, // 1 1 1 1 Always true (always folded) 1628 // Don't care operations: undefined if the input is a nan. 1629 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 1630 SETEQ, // 1 X 0 0 1 True if equal 1631 SETGT, // 1 X 0 1 0 True if greater than 1632 SETGE, // 1 X 0 1 1 True if greater than or equal 1633 SETLT, // 1 X 1 0 0 True if less than 1634 SETLE, // 1 X 1 0 1 True if less than or equal 1635 SETNE, // 1 X 1 1 0 True if not equal 1636 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 1637 1638 SETCC_INVALID // Marker value. 1639 }; 1640 1641 /// Return true if this is a setcc instruction that performs a signed 1642 /// comparison when used with integer operands. 1643 inline bool isSignedIntSetCC(CondCode Code) { 1644 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 1645 } 1646 1647 /// Return true if this is a setcc instruction that performs an unsigned 1648 /// comparison when used with integer operands. 1649 inline bool isUnsignedIntSetCC(CondCode Code) { 1650 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 1651 } 1652 1653 /// Return true if this is a setcc instruction that performs an equality 1654 /// comparison when used with integer operands. 1655 inline bool isIntEqualitySetCC(CondCode Code) { 1656 return Code == SETEQ || Code == SETNE; 1657 } 1658 1659 /// Return true if this is a setcc instruction that performs an equality 1660 /// comparison when used with floating point operands. 1661 inline bool isFPEqualitySetCC(CondCode Code) { 1662 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE; 1663 } 1664 1665 /// Return true if the specified condition returns true if the two operands to 1666 /// the condition are equal. Note that if one of the two operands is a NaN, 1667 /// this value is meaningless. 1668 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; } 1669 1670 /// This function returns 0 if the condition is always false if an operand is 1671 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 1672 /// the condition is undefined if the operand is a NaN. 1673 inline unsigned getUnorderedFlavor(CondCode Cond) { 1674 return ((int)Cond >> 3) & 3; 1675 } 1676 1677 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 1678 /// SetCC operation. 1679 CondCode getSetCCInverse(CondCode Operation, EVT Type); 1680 1681 inline bool isExtOpcode(unsigned Opcode) { 1682 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || 1683 Opcode == ISD::SIGN_EXTEND; 1684 } 1685 1686 inline bool isExtVecInRegOpcode(unsigned Opcode) { 1687 return Opcode == ISD::ANY_EXTEND_VECTOR_INREG || 1688 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || 1689 Opcode == ISD::SIGN_EXTEND_VECTOR_INREG; 1690 } 1691 1692 namespace GlobalISel { 1693 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 1694 /// SetCC operation. The U bit of the condition code has different meanings 1695 /// between floating point and integer comparisons and LLT's don't provide 1696 /// this distinction. As such we need to be told whether the comparison is 1697 /// floating point or integer-like. Pointers should use integer-like 1698 /// comparisons. 1699 CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike); 1700 } // end namespace GlobalISel 1701 1702 /// Return the operation corresponding to (Y op X) when given the operation 1703 /// for (X op Y). 1704 CondCode getSetCCSwappedOperands(CondCode Operation); 1705 1706 /// Return the result of a logical OR between different comparisons of 1707 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 1708 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1709 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type); 1710 1711 /// Return the result of a logical AND between different comparisons of 1712 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 1713 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 1714 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type); 1715 1716 } // namespace ISD 1717 1718 } // namespace llvm 1719 1720 #endif 1721