1 typedef struct Conf Conf; 2 typedef struct Confmem Confmem; 3 typedef struct FPsave FPsave; 4 typedef struct ISAConf ISAConf; 5 typedef struct Label Label; 6 typedef struct Lock Lock; 7 typedef struct Memcache Memcache; 8 typedef struct MMMU MMMU; 9 typedef struct Mach Mach; 10 typedef struct Notsave Notsave; 11 typedef struct Page Page; 12 typedef struct Pcidev Pcidev; 13 typedef struct PhysUart PhysUart; 14 typedef struct PMMU PMMU; 15 typedef struct Proc Proc; 16 typedef u32int PTE; 17 typedef struct Soc Soc; 18 typedef struct Uart Uart; 19 typedef struct Ureg Ureg; 20 typedef uvlong Tval; 21 22 #pragma incomplete Pcidev 23 #pragma incomplete Ureg 24 25 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 26 27 /* 28 * parameters for sysproc.c 29 */ 30 #define AOUT_MAGIC (E_MAGIC) 31 32 struct Lock 33 { 34 ulong key; 35 u32int sr; 36 uintptr pc; 37 Proc* p; 38 Mach* m; 39 int isilock; 40 }; 41 42 struct Label 43 { 44 uintptr sp; 45 uintptr pc; 46 }; 47 48 /* 49 * emulated floating point 50 */ 51 struct FPsave 52 { 53 ulong status; 54 ulong control; 55 ulong regs[8][3]; 56 57 int fpstate; 58 }; 59 60 /* 61 * FPsave.status 62 */ 63 enum 64 { 65 FPinit, 66 FPactive, 67 FPinactive, 68 69 /* bit or'd with the state */ 70 FPillegal= 0x100, 71 }; 72 73 struct Confmem 74 { 75 uintptr base; 76 usize npage; 77 uintptr limit; 78 uintptr kbase; 79 uintptr klimit; 80 }; 81 82 struct Conf 83 { 84 ulong nmach; /* processors */ 85 ulong nproc; /* processes */ 86 ulong monitor; /* has monitor? */ 87 Confmem mem[1]; /* physical memory */ 88 ulong npage; /* total physical pages of memory */ 89 usize upages; /* user page pool */ 90 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 91 ulong ialloc; /* max interrupt time allocation in bytes */ 92 ulong pipeqsize; /* size in bytes of pipe queues */ 93 ulong nimage; /* number of page cache image headers */ 94 ulong nswap; /* number of swap pages */ 95 int nswppo; /* max # of pageouts per segment pass */ 96 // ulong hz; /* processor cycle freq */ 97 // ulong mhz; 98 }; 99 100 /* 101 * things saved in the Proc structure during a notify 102 */ 103 struct Notsave { 104 int emptiness; 105 }; 106 107 /* 108 * MMU stuff in Mach. 109 */ 110 struct MMMU 111 { 112 PTE* mmul1; /* l1 for this processor */ 113 int mmul1lo; 114 int mmul1hi; 115 int mmupid; 116 }; 117 118 /* 119 * MMU stuff in proc 120 */ 121 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 122 struct PMMU 123 { 124 Page* mmul2; 125 Page* mmul2cache; /* free mmu pages */ 126 }; 127 128 #include "../port/portdat.h" 129 130 struct Mach 131 { 132 int machno; /* physical id of processor */ 133 uintptr splpc; /* pc of last caller to splhi */ 134 135 Proc* proc; /* current process */ 136 137 MMMU; 138 int flushmmu; /* flush current proc mmu state */ 139 140 ulong ticks; /* of the clock since boot time */ 141 Label sched; /* scheduler wakeup */ 142 Lock alarmlock; /* access to alarm list */ 143 void* alarm; /* alarms bound to this clock */ 144 int inclockintr; 145 146 Proc* readied; /* for runproc */ 147 ulong schedticks; /* next forced context switch */ 148 149 int cputype; 150 int socrev; /* system-on-chip revision */ 151 ulong delayloop; 152 153 /* stats */ 154 int tlbfault; 155 int tlbpurge; 156 int pfault; 157 int cs; 158 int syscall; 159 int load; 160 int intr; 161 vlong fastclock; /* last sampled value */ 162 ulong spuriousintr; 163 int lastintr; 164 int ilockdepth; 165 Perf perf; /* performance counters */ 166 167 uvlong cpuhz; /* speed of cpu */ 168 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 169 170 /* save areas for exceptions */ 171 u32int sfiq[5]; 172 u32int sirq[5]; 173 u32int sund[5]; 174 u32int sabt[5]; 175 #define fiqstack sfiq 176 #define irqstack sirq 177 #define abtstack sabt 178 #define undstack sund 179 180 int stack[1]; 181 }; 182 183 /* 184 * Fake kmap. 185 */ 186 typedef void KMap; 187 #define VA(k) ((uintptr)(k)) 188 #define kmap(p) (KMap*)((p)->pa|kseg0) 189 #define kunmap(k) 190 191 struct 192 { 193 Lock; 194 int machs; /* bitmap of active CPUs */ 195 int exiting; /* shutdown */ 196 int ispanic; /* shutdown in response to a panic */ 197 }active; 198 199 enum { 200 Frequency = 1200*1000*1000, /* the processor clock */ 201 }; 202 203 extern register Mach* m; /* R10 */ 204 extern register Proc* up; /* R9 */ 205 206 extern uintptr kseg0; 207 extern Mach* machaddr[MAXMACH]; 208 extern ulong memsize; 209 210 enum { 211 Nvec = 8, /* # of vectors at start of lexception.s */ 212 }; 213 214 /* 215 * Layout of physical 0. 216 */ 217 typedef struct Vectorpage { 218 void (*vectors[Nvec])(void); 219 uint vtable[Nvec]; 220 } Vectorpage; 221 222 /* 223 * a parsed plan9.ini line 224 */ 225 #define NISAOPT 8 226 227 struct ISAConf { 228 char *type; 229 ulong port; 230 int irq; 231 ulong dma; 232 ulong mem; 233 ulong size; 234 ulong freq; 235 236 int nopt; 237 char *opt[NISAOPT]; 238 }; 239 240 #define MACHP(n) (machaddr[n]) 241 242 /* 243 * Horrid. But the alternative is 'defined'. 244 */ 245 #ifdef _DBGC_ 246 #define DBGFLG (dbgflg[_DBGC_]) 247 #else 248 #define DBGFLG (0) 249 #endif /* _DBGC_ */ 250 251 int vflag; 252 extern char dbgflg[256]; 253 254 #define dbgprint print /* for now */ 255 256 /* 257 * hardware info about a device 258 */ 259 typedef struct { 260 ulong port; 261 int size; 262 } Devport; 263 264 struct DevConf 265 { 266 ulong intnum; /* interrupt number */ 267 char *type; /* card type, malloced */ 268 int nports; /* Number of ports */ 269 Devport *ports; /* The ports themselves */ 270 }; 271 272 enum { 273 Dcache, 274 Icache, 275 Unified, 276 }; 277 278 /* characteristics of a given cache level */ 279 struct Memcache { 280 uint level; /* 1 is nearest processor, 2 further away */ 281 uint kind; /* I, D or unified */ 282 283 uint size; 284 uint nways; /* associativity */ 285 uint nsets; 286 uint linelen; /* bytes per cache line */ 287 uint setsways; 288 289 uint log2linelen; 290 uint waysh; /* shifts for set/way register */ 291 uint setsh; 292 }; 293 294 struct Soc { /* addr's of SoC controllers */ 295 uintptr cpu; 296 uintptr devid; 297 uintptr l2cache; 298 uintptr sdramc; 299 300 uintptr iocfg; 301 uintptr addrmap; 302 uintptr intr; 303 uintptr nand; 304 uintptr cesa; /* crypto accel. */ 305 uintptr ehci; 306 uintptr spi; 307 uintptr twsi; 308 309 uintptr analog; 310 uintptr pci; 311 uintptr pcibase; 312 313 uintptr rtc; /* real-time clock */ 314 uintptr clock; 315 316 uintptr ether[2]; 317 uintptr sata[3]; 318 uintptr uart[2]; 319 uintptr gpio[2]; 320 } soc; 321 extern Soc soc; 322