1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
11 * www.cavium.com
12 */
13
14 #ifndef __BNX2X_H__
15 #define __BNX2X_H__
16
17 #include <rte_byteorder.h>
18 #include <rte_spinlock.h>
19 #include <bus_pci_driver.h>
20 #include <rte_io.h>
21
22 #include "bnx2x_osal.h"
23 #include "bnx2x_ethdev.h"
24 #include "ecore_mfw_req.h"
25 #include "ecore_fw_defs.h"
26 #include "ecore_hsi.h"
27 #include "ecore_reg.h"
28 #include "bnx2x_stats.h"
29 #include "bnx2x_vfpf.h"
30
31 #include "elink.h"
32
33 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
34 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
35 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
36
37 #ifndef ARRAY_SIZE
38 #define ARRAY_SIZE(arr) RTE_DIM(arr)
39 #endif
40 #ifndef DIV_ROUND_UP
41 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
42 #endif
43 #ifndef roundup
44 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
45 #endif
46 #ifndef ilog2
47 static inline
bnx2x_ilog2(int x)48 int bnx2x_ilog2(int x)
49 {
50 int log = 0;
51 x >>= 1;
52
53 while(x) {
54 log++;
55 x >>= 1;
56 }
57 return log;
58 }
59 #define ilog2(x) bnx2x_ilog2(x)
60 #endif
61
62 #define BNX2X_BC_VER 0x040200
63
64 #include "ecore_sp.h"
65
66 struct bnx2x_device_type {
67 uint16_t bnx2x_vid;
68 uint16_t bnx2x_did;
69 uint16_t bnx2x_svid;
70 uint16_t bnx2x_sdid;
71 char *bnx2x_name;
72 };
73
74 #define BNX2X_PAGE_SHIFT 12
75 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
76 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
77 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
78
79 #if BNX2X_PAGE_SIZE != 4096
80 #error Page sizes other than 4KB are unsupported!
81 #endif
82
83 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
84 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
85 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
86
87 /* dropless fc FW/HW related params */
88 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
89 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
90 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
91 #define FW_PREFETCH_CNT 16U
92 #define DROPLESS_FC_HEADROOM 100
93
94 /*
95 * Transmit Buffer Descriptor (tx_bd) definitions*
96 */
97 /* NUM_TX_PAGES must be a power of 2. */
98 #define NUM_TX_PAGES 16
99 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
100 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
101
102 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
103 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
104 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
105 #define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2)
106 #define NEXT_TX_BD(x) \
107 ((((x) & USABLE_TX_BD_PER_PAGE) == \
108 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
109
110 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
111 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
112 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
113
114 #define BDS_PER_TX_PKT (3)
115
116 /*
117 * Trigger pending transmits when the number of available BDs is greater
118 * than 1/8 of the total number of usable BDs.
119 */
120 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
121 #define BNX2X_TX_TIMEOUT 5
122
123 /*
124 * Receive Buffer Descriptor (rx_bd) definitions*
125 */
126 #define MAX_RX_PAGES 8
127 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
128 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
129 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
130 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
131 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
132 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
133 #define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2)
134 #define RX_BD_NEXT_PAGE_DESC_CNT 2
135
136 #define NEXT_RX_BD(x) \
137 ((((x) & RX_BD_PER_PAGE_MASK) == \
138 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
139
140 /* x & 0x3ff */
141 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
142 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
143 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
144
145 /*
146 * Receive Completion Queue definitions*
147 */
148 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
149 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
150 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
151 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
152 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
153 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
154 #define RCQ_NEXT_PAGE_DESC_CNT 1
155
156 #define NEXT_RCQ_IDX(x) \
157 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
158 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
159
160 #define CQE_BD_REL \
161 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
162
163 #define RCQ_BD_PAGES(q) \
164 (q->nb_rx_pages * CQE_BD_REL)
165
166 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
167 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
168 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
169
170 /*
171 * dropless fc calculations for BDs
172 * Number of BDs should be as number of buffers in BRB:
173 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
174 * "next" elements on each page
175 */
176 #define NUM_BD_REQ(sc) \
177 BRB_SIZE(sc)
178 #define NUM_BD_PG_REQ(sc) \
179 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
180 #define BD_TH_LO(sc) \
181 (NUM_BD_REQ(sc) + \
182 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
183 FW_DROP_LEVEL(sc))
184 #define BD_TH_HI(sc) \
185 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
186 #define MIN_RX_AVAIL(sc) \
187 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
188
189 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
190 #define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\
191 (uint32_t)MIN_RX_AVAIL(sc)))
192
193 /*
194 * dropless fc calculations for RCQs
195 * Number of RCQs should be as number of buffers in BRB:
196 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
197 * "next" elements on each page
198 */
199 #define NUM_RCQ_REQ(sc) \
200 BRB_SIZE(sc)
201 #define NUM_RCQ_PG_REQ(sc) \
202 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
203 #define RCQ_TH_LO(sc) \
204 (NUM_RCQ_REQ(sc) + \
205 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
206 FW_DROP_LEVEL(sc))
207 #define RCQ_TH_HI(sc) \
208 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
209
210 /* Load / Unload modes */
211 #define LOAD_NORMAL 0
212 #define LOAD_OPEN 1
213 #define LOAD_DIAG 2
214 #define LOAD_LOOPBACK_EXT 3
215 #define UNLOAD_NORMAL 0
216 #define UNLOAD_CLOSE 1
217 #define UNLOAD_RECOVERY 2
218
219 /* Some constants... */
220 //#define MAX_PATH_NUM 2
221 //#define E2_MAX_NUM_OF_VFS 64
222 //#define E1H_FUNC_MAX 8
223 //#define E2_FUNC_MAX 4 /* per path */
224 #define MAX_VNIC_NUM 4
225 #define MAX_FUNC_NUM 8 /* common to all chips */
226 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
227 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
228 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
229
230 #define ILT_NUM_PAGE_ENTRIES 3072
231 /*
232 * 57711 we use whole table since we have 8 functions.
233 * 57712 we have only 4 functions, but use same size per func, so only half
234 * of the table is used.
235 */
236 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
237 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
238 /*
239 * the phys address is shifted right 12 bits and has an added
240 * 1=valid bit added to the 53rd bit
241 * then since this is a wide register(TM)
242 * we split it into two 32 bit writes
243 */
244 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
245 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
246
247 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
248 #define ETH_HLEN 14
249 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
250 #define ETH_MIN_PACKET_SIZE 60
251 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
252 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
253 /* TCP with Timestamp Option (32) + IPv6 (40) */
254
255 /* max supported alignment is 256 (8 shift) */
256 #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
257
258 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
259
260 struct bnx2x_bar {
261 void *base_addr;
262 };
263
264 /* Used to manage DMA allocations. */
265 struct bnx2x_dma {
266 struct bnx2x_softc *sc;
267 rte_iova_t paddr;
268 void *vaddr;
269 int nseg;
270 const void *mzone;
271 char msg[RTE_MEMZONE_NAMESIZE - 6];
272 };
273
274 /* attn group wiring */
275 #define MAX_DYNAMIC_ATTN_GRPS 8
276
277 struct attn_route {
278 uint32_t sig[5];
279 };
280
281 struct iro {
282 uint32_t base;
283 uint16_t m1;
284 uint16_t m2;
285 uint16_t m3;
286 uint16_t size;
287 };
288
289 union bnx2x_host_hc_status_block {
290 /* pointer to fp status block e2 */
291 struct host_hc_status_block_e2 *e2_sb;
292 /* pointer to fp status block e1x */
293 struct host_hc_status_block_e1x *e1x_sb;
294 };
295
296 union bnx2x_db_prod {
297 struct doorbell_set_prod data;
298 uint32_t raw;
299 };
300
301 struct bnx2x_sw_tx_bd {
302 struct mbuf *m;
303 uint16_t first_bd;
304 uint8_t flags;
305 /* set on the first BD descriptor when there is a split BD */
306 #define BNX2X_TSO_SPLIT_BD (1 << 0)
307 };
308
309 /*
310 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
311 * instances of the fastpath structure when using multiple queues.
312 */
313 struct bnx2x_fastpath {
314 /* pointer back to parent structure */
315 struct bnx2x_softc *sc;
316
317 /* Used to synchronize fastpath Rx access */
318 rte_spinlock_t rx_mtx;
319
320 /* status block */
321 struct bnx2x_dma sb_dma;
322 union bnx2x_host_hc_status_block status_block;
323
324 rte_iova_t tx_desc_mapping;
325
326 rte_iova_t rx_desc_mapping;
327 rte_iova_t rx_comp_mapping;
328
329 uint16_t *sb_index_values;
330 uint16_t *sb_running_index;
331 uint32_t ustorm_rx_prods_offset;
332
333 uint8_t igu_sb_id; /* status block number in HW */
334 uint8_t fw_sb_id; /* status block number in FW */
335
336 uint32_t rx_buf_size;
337
338 int state;
339 #define BNX2X_FP_STATE_CLOSED 0x01
340 #define BNX2X_FP_STATE_IRQ 0x02
341 #define BNX2X_FP_STATE_OPENING 0x04
342 #define BNX2X_FP_STATE_OPEN 0x08
343 #define BNX2X_FP_STATE_HALTING 0x10
344 #define BNX2X_FP_STATE_HALTED 0x20
345
346 /* reference back to this fastpath queue number */
347 uint8_t index; /* this is also the 'cid' */
348 #define FP_IDX(fp) (fp->index)
349
350 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
351 uint8_t cl_id;
352 #define FP_CL_ID(fp) (fp->cl_id)
353 uint8_t cl_qzone_id;
354
355 uint16_t fp_hc_idx;
356
357 union bnx2x_db_prod tx_db;
358
359 struct tstorm_per_queue_stats old_tclient;
360 struct ustorm_per_queue_stats old_uclient;
361 struct xstorm_per_queue_stats old_xclient;
362 struct bnx2x_eth_q_stats eth_q_stats;
363 struct bnx2x_eth_q_stats_old eth_q_stats_old;
364
365 /* Pointer to the receive consumer in the status block */
366 uint16_t *rx_cq_cons_sb;
367
368 /* Pointer to the transmit consumer in the status block */
369 uint16_t *tx_cons_sb;
370
371 /* transmit timeout until chip reset */
372 int watchdog_timer;
373
374 }; /* struct bnx2x_fastpath */
375
376 #define BNX2X_MAX_NUM_OF_VFS 64
377 #define BNX2X_VF_ID_INVALID 0xFF
378
379 /* maximum number of fast-path interrupt contexts */
380 #define FP_SB_MAX_E1x 16
381 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
382
383 union cdu_context {
384 struct eth_context eth;
385 char pad[1024];
386 };
387
388 /* CDU host DB constants */
389 #define CDU_ILT_PAGE_SZ_HW 2
390 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
391 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
392
393 #define CNIC_ISCSI_CID_MAX 256
394 #define CNIC_FCOE_CID_MAX 2048
395 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
396 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
397
398 #define QM_ILT_PAGE_SZ_HW 0
399 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
400 #define QM_CID_ROUND 1024
401
402 /* TM (timers) host DB constants */
403 #define TM_ILT_PAGE_SZ_HW 0
404 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
405 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
406 #define TM_CONN_NUM 1024
407 #define TM_ILT_SZ (8 * TM_CONN_NUM)
408 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
409
410 /* SRC (Searcher) host DB constants */
411 #define SRC_ILT_PAGE_SZ_HW 0
412 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
413 #define SRC_HASH_BITS 10
414 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
415 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
416 #define SRC_T2_SZ SRC_ILT_SZ
417 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
418
419 struct hw_context {
420 struct bnx2x_dma vcxt_dma;
421 union cdu_context *vcxt;
422 //rte_iova_t cxt_mapping;
423 size_t size;
424 };
425
426 #define SM_RX_ID 0
427 #define SM_TX_ID 1
428
429 /* defines for multiple tx priority indices */
430 #define FIRST_TX_ONLY_COS_INDEX 1
431 #define FIRST_TX_COS_INDEX 0
432
433 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
434
435 #define HC_INDEX_ETH_RX_CQ_CONS 1
436 #define HC_INDEX_OOO_TX_CQ_CONS 4
437 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
438 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
439 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
440 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
441
442 /* congestion management fairness mode */
443 #define CMNG_FNS_NONE 0
444 #define CMNG_FNS_MINMAX 1
445
446 /* CMNG constants, as derived from system spec calculations */
447 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
448 #define DEF_MIN_RATE 100
449 /* resolution of the rate shaping timer - 400 usec */
450 #define RS_PERIODIC_TIMEOUT_USEC 400
451 /* number of bytes in single QM arbitration cycle -
452 * coefficient for calculating the fairness timer */
453 #define QM_ARB_BYTES 160000
454 /* resolution of Min algorithm 1:100 */
455 #define MIN_RES 100
456 /* how many bytes above threshold for the minimal credit of Min algorithm*/
457 #define MIN_ABOVE_THRESH 32768
458 /* fairness algorithm integration time coefficient -
459 * for calculating the actual Tfair */
460 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
461 /* memory of fairness algorithm - 2 cycles */
462 #define FAIR_MEM 2
463
464 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
465 #define HC_SEG_ACCESS_ATTN 4
466 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
467
468 /*
469 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
470 * control by the number of fast-path status blocks supported by the
471 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
472 * status block represents an independent interrupts context that can
473 * serve a regular L2 networking queue. However special L2 queues such
474 * as the FCoE queue do not require a FP-SB and other components like
475 * the CNIC may consume FP-SB reducing the number of possible L2 queues
476 *
477 * If the maximum number of FP-SB available is X then:
478 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
479 * regular L2 queues is Y=X-1
480 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
481 * c. If the FCoE L2 queue is supported the actual number of L2 queues
482 * is Y+1
483 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
484 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
485 * FP interrupt context for the CNIC).
486 * e. The number of HW context (CID count) is always X or X+1 if FCoE
487 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
488 *
489 * So this is quite simple for now as no ULPs are supported yet. :-)
490 */
491 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
492 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
493 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
494 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
495
496 #define FOR_EACH_QUEUE(sc, var) \
497 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
498
499 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
500 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
501
502 #define FOR_EACH_ETH_QUEUE(sc, var) \
503 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
504
505 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
506 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
507
508 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
509 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
510
511 #define FOR_EACH_CNIC_QUEUE(sc, var) \
512 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
513 (var) < BNX2X_NUM_QUEUES(sc); \
514 (var)++)
515
516 enum {
517 OOO_IDX_OFFSET,
518 FCOE_IDX_OFFSET,
519 FWD_IDX_OFFSET,
520 };
521
522 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
523 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
524 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
525 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
526 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
527 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
528
529 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
530 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
531 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
532 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
533 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
534
535 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
536 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
537 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
538 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
539 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
540 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
541
542 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
543 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
544 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
545 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
546 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
547 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
548 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
549
550 enum {
551 BNX2X_PORT_QUERY_IDX,
552 BNX2X_PF_QUERY_IDX,
553 BNX2X_FCOE_QUERY_IDX,
554 BNX2X_FIRST_QUEUE_QUERY_IDX,
555 };
556
557 struct bnx2x_fw_stats_req {
558 struct stats_query_header hdr;
559 struct stats_query_entry query[FP_SB_MAX_E1x +
560 BNX2X_FIRST_QUEUE_QUERY_IDX];
561 };
562
563 struct bnx2x_fw_stats_data {
564 struct stats_counter storm_counters;
565 struct per_port_stats port;
566 struct per_pf_stats pf;
567 struct per_queue_stats queue_stats[1];
568 };
569
570 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
571 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
572 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
573
574 #define MAX_DMAE_C 8
575
576 /*
577 * This is the slowpath data structure. It is mapped into non-paged memory
578 * so that the hardware can access it's contents directly and must be page
579 * aligned.
580 */
581 struct bnx2x_slowpath {
582
583 /* used by the DMAE command executer */
584 struct dmae_command dmae[MAX_DMAE_C];
585
586 /* statistics completion */
587 uint32_t stats_comp;
588
589 /* firmware defined statistics blocks */
590 union mac_stats mac_stats;
591 struct nig_stats nig_stats;
592 struct host_port_stats port_stats;
593 struct host_func_stats func_stats;
594
595 /* DMAE completion value and data source/sink */
596 uint32_t wb_comp;
597 uint32_t wb_data[4];
598
599 union {
600 struct mac_configuration_cmd e1x;
601 struct eth_classify_rules_ramrod_data e2;
602 } mac_rdata;
603
604 union {
605 struct tstorm_eth_mac_filter_config e1x;
606 struct eth_filter_rules_ramrod_data e2;
607 } rx_mode_rdata;
608
609 struct eth_rss_update_ramrod_data rss_rdata;
610
611 union {
612 struct mac_configuration_cmd e1;
613 struct eth_multicast_rules_ramrod_data e2;
614 } mcast_rdata;
615
616 union {
617 struct function_start_data func_start;
618 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
619 } func_rdata;
620
621 /* Queue State related ramrods */
622 union {
623 struct client_init_ramrod_data init_data;
624 struct client_update_ramrod_data update_data;
625 } q_rdata;
626
627 /*
628 * AFEX ramrod can not be a part of func_rdata union because these
629 * events might arrive in parallel to other events from func_rdata.
630 * If they were defined in the same union the data can get corrupted.
631 */
632 struct afex_vif_list_ramrod_data func_afex_rdata;
633
634 union drv_info_to_mcp drv_info_to_mcp;
635 }; /* struct bnx2x_slowpath */
636
637 /*
638 * Port specific data structure.
639 */
640 struct bnx2x_port {
641 /*
642 * Port Management Function (for 57711E only).
643 * When this field is set the driver instance is
644 * responsible for managing port specific
645 * configurations such as handling link attentions.
646 */
647 uint32_t pmf;
648
649 /* Ethernet maximum transmission unit. */
650 uint16_t ether_mtu;
651
652 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
653
654 uint32_t ext_phy_config;
655
656 /* Port feature config.*/
657 uint32_t config;
658
659 /* Defines the features supported by the PHY. */
660 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
661
662 /* Defines the features advertised by the PHY. */
663 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
664 #define ADVERTISED_10baseT_Half (1 << 1)
665 #define ADVERTISED_10baseT_Full (1 << 2)
666 #define ADVERTISED_100baseT_Half (1 << 3)
667 #define ADVERTISED_100baseT_Full (1 << 4)
668 #define ADVERTISED_1000baseT_Half (1 << 5)
669 #define ADVERTISED_1000baseT_Full (1 << 6)
670 #define ADVERTISED_TP (1 << 7)
671 #define ADVERTISED_FIBRE (1 << 8)
672 #define ADVERTISED_Autoneg (1 << 9)
673 #define ADVERTISED_Asym_Pause (1 << 10)
674 #define ADVERTISED_Pause (1 << 11)
675 #define ADVERTISED_2500baseX_Full (1 << 15)
676 #define ADVERTISED_10000baseT_Full (1 << 16)
677
678 uint32_t phy_addr;
679
680 /* Used to synchronize phy accesses. */
681 rte_spinlock_t phy_mtx;
682 char phy_mtx_name[32];
683
684 #define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
685 #define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
686
687 /*
688 * MCP scratchpad address for port specific statistics.
689 * The device is responsible for writing statistics
690 * back to the MCP for use with management firmware such
691 * as UMP/NC-SI.
692 */
693 uint32_t port_stx;
694
695 struct nig_stats old_nig_stats;
696 }; /* struct bnx2x_port */
697
698 struct bnx2x_mf_info {
699 uint32_t mf_config[E1HVN_MAX];
700
701 uint32_t vnics_per_port; /* 1, 2 or 4 */
702 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
703 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
704
705 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
706 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
707 #define VNICS_PER_PATH(sc) \
708 ((sc)->devinfo.mf_info.vnics_per_port * \
709 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
710
711 uint8_t min_bw[MAX_VNIC_NUM];
712 uint8_t max_bw[MAX_VNIC_NUM];
713
714 uint16_t ext_id; /* vnic outer vlan or VIF ID */
715 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
716 #define INVALID_VIF_ID 0xFFFF
717 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
718 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
719
720 uint16_t default_vlan;
721 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
722
723 uint8_t niv_allowed_priorities;
724 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
725
726 uint8_t niv_default_cos;
727 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
728
729 uint8_t niv_mba_enabled;
730
731 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
732 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
733 int afex_def_vlan_tag;
734 uint32_t pending_max;
735
736 uint16_t flags;
737 #define MF_INFO_VALID_MAC 0x0001
738
739 uint16_t mf_ov;
740 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
741 #define IS_MF(sc) \
742 (IS_MULTI_VNIC(sc) && \
743 ((sc)->devinfo.mf_info.mf_mode != 0))
744 #define IS_MF_SD(sc) \
745 (IS_MULTI_VNIC(sc) && \
746 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
747 #define IS_MF_SI(sc) \
748 (IS_MULTI_VNIC(sc) && \
749 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
750 #define IS_MF_AFEX(sc) \
751 (IS_MULTI_VNIC(sc) && \
752 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
753 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
754 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
755 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
756
757 uint32_t mf_protos_supported;
758 #define MF_PROTO_SUPPORT_ETHERNET 0x1
759 #define MF_PROTO_SUPPORT_ISCSI 0x2
760 #define MF_PROTO_SUPPORT_FCOE 0x4
761 }; /* struct bnx2x_mf_info */
762
763 /* Device information data structure. */
764 struct bnx2x_devinfo {
765 #if 1
766 #define NAME_SIZE 128
767 char name[NAME_SIZE];
768 #endif
769 /* PCIe info */
770 uint16_t vendor_id;
771 uint16_t device_id;
772 uint16_t subvendor_id;
773 uint16_t subdevice_id;
774
775 /*
776 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
777 * C = Chip Number (bits 16-31)
778 * R = Chip Revision (bits 12-15)
779 * M = Chip Metal (bits 4-11)
780 * B = Chip Bond ID (bits 0-3)
781 */
782 uint32_t chip_id;
783 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
784 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
785 /* device ids */
786 #define CHIP_NUM_57710 0x164e
787 #define CHIP_NUM_57711 0x164f
788 #define CHIP_NUM_57711E 0x1650
789 #define CHIP_NUM_57712 0x1662
790 #define CHIP_NUM_57712_MF 0x1663
791 #define CHIP_NUM_57712_VF 0x166f
792 #define CHIP_NUM_57800 0x168a
793 #define CHIP_NUM_57800_MF 0x16a5
794 #define CHIP_NUM_57800_VF 0x16a9
795 #define CHIP_NUM_57810 0x168e
796 #define CHIP_NUM_57810_MF 0x16ae
797 #define CHIP_NUM_57810_VF 0x16af
798 #define CHIP_NUM_57811 0x163d
799 #define CHIP_NUM_57811_MF 0x163e
800 #define CHIP_NUM_57811_VF 0x163f
801 #define CHIP_NUM_57840_OBS 0x168d
802 #define CHIP_NUM_57840_OBS_MF 0x16ab
803 #define CHIP_NUM_57840_4_10 0x16a1
804 #define CHIP_NUM_57840_2_20 0x16a2
805 #define CHIP_NUM_57840_MF 0x16a4
806 #define CHIP_NUM_57840_VF 0x16ad
807
808 #define CHIP_REV_SHIFT 12
809 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
810 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
811
812 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
813 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
814 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
815
816 #define CHIP_REV_IS_SLOW(sc) \
817 (CHIP_REV(sc) > 0x00005000)
818 #define CHIP_REV_IS_FPGA(sc) \
819 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
820 #define CHIP_REV_IS_EMUL(sc) \
821 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
822 #define CHIP_REV_IS_ASIC(sc) \
823 (!CHIP_REV_IS_SLOW(sc))
824
825 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
826 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
827
828 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
829 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
830 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
831 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
832 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
833 (CHIP_IS_57711E(sc)))
834 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
835
836 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
837 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
838 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
839 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
840 CHIP_IS_57712_MF(sc))
841
842 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
843 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
844 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
845 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
846 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
847 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
848 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
849 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
850 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
851 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
852 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
853 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
854 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
855 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
856 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
857
858 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
859 CHIP_IS_57800_MF(sc) || \
860 CHIP_IS_57800_VF(sc) || \
861 CHIP_IS_57810(sc) || \
862 CHIP_IS_57810_MF(sc) || \
863 CHIP_IS_57810_VF(sc) || \
864 CHIP_IS_57811(sc) || \
865 CHIP_IS_57811_MF(sc) || \
866 CHIP_IS_57811_VF(sc) || \
867 CHIP_IS_57840(sc) || \
868 CHIP_IS_57840_MF(sc) || \
869 CHIP_IS_57840_VF(sc))
870 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
871 (CHIP_REV(sc) == CHIP_REV_Ax))
872 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
873 (CHIP_REV(sc) == CHIP_REV_Bx))
874
875 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
876 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
877 CHIP_IS_E3(sc))
878
879 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
880 CHIP_IS_57712_MF(sc) || \
881 CHIP_IS_E3(sc))
882
883 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
884 #define IS_PF(sc) (!IS_VF(sc))
885
886 /*
887 * This define is used in two main places:
888 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
889 * to nic-only mode or to offload mode. Offload mode is configured if either
890 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
891 * already registered for this port (which means that the user wants storage
892 * services).
893 * 2. During cnic-related load, to know if offload mode is already configured
894 * in the HW or needs to be configured. Since the transition from nic-mode to
895 * offload-mode in HW causes traffic corruption, nic-mode is configured only
896 * in ports on which storage services where never requested.
897 */
898 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
899
900 uint8_t chip_port_mode;
901 #define CHIP_4_PORT_MODE 0x0
902 #define CHIP_2_PORT_MODE 0x1
903 #define CHIP_PORT_MODE_NONE 0x2
904 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
905 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
906
907 uint8_t int_block;
908 #define INT_BLOCK_HC 0
909 #define INT_BLOCK_IGU 1
910 #define INT_BLOCK_MODE_NORMAL 0
911 #define INT_BLOCK_MODE_BW_COMP 2
912 #define CHIP_INT_MODE_IS_NBC(sc) \
913 (!CHIP_IS_E1x(sc) && \
914 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
915 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
916
917 uint32_t shmem_base;
918 uint32_t shmem2_base;
919 uint32_t bc_ver;
920 char bc_ver_str[32];
921 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
922 struct bnx2x_mf_info mf_info;
923
924 uint32_t flash_size;
925 #define NVRAM_1MB_SIZE 0x20000
926 #define NVRAM_TIMEOUT_COUNT 30000
927 #define NVRAM_PAGE_SIZE 256
928
929 /* PCIe capability information */
930 uint32_t pcie_cap_flags;
931 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
932 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
933 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
934 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
935 uint16_t pcie_pm_cap_reg;
936 uint16_t pcie_link_width;
937 uint16_t pcie_link_speed;
938 uint16_t pcie_msi_cap_reg;
939 uint16_t pcie_msix_cap_reg;
940
941 /* device configuration read from bootcode shared memory */
942 uint32_t hw_config;
943 uint32_t hw_config2;
944 }; /* struct bnx2x_devinfo */
945
946 struct bnx2x_sp_objs {
947 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
948 struct ecore_queue_sp_obj q_obj; /* Queue State object */
949 }; /* struct bnx2x_sp_objs */
950
951 /*
952 * Data that will be used to create a link report message. We will keep the
953 * data used for the last link report in order to prevent reporting the same
954 * link parameters twice.
955 */
956 struct bnx2x_link_report_data {
957 uint16_t line_speed; /* Effective line speed */
958 uint32_t link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
959 };
960
961 enum {
962 BNX2X_LINK_REPORT_FULL_DUPLEX,
963 BNX2X_LINK_REPORT_LINK_DOWN,
964 BNX2X_LINK_REPORT_RX_FC_ON,
965 BNX2X_LINK_REPORT_TX_FC_ON
966 };
967
968 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
969
970 struct bnx2x_pci_cap {
971 struct bnx2x_pci_cap *next;
972 uint16_t id;
973 uint16_t type;
974 uint16_t addr;
975 };
976
977 struct ecore_ilt;
978
979 struct bnx2x_vfdb;
980
981 /* Top level device private data structure. */
982 struct bnx2x_softc {
983
984 void **rx_queues;
985 void **tx_queues;
986 uint32_t max_tx_queues;
987 uint32_t max_rx_queues;
988 const struct rte_pci_device *pci_dev;
989 uint32_t pci_val;
990 struct bnx2x_pci_cap *pci_caps;
991 #define BNX2X_INTRS_POLL_PERIOD 1
992
993 void *firmware;
994 uint64_t fw_len;
995
996 /* MAC address operations */
997 struct bnx2x_mac_ops mac_ops;
998
999 /* structures for VF mbox/response/bulletin */
1000 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1001 struct bnx2x_dma vf2pf_mbox_mapping;
1002 struct vf_acquire_resp_tlv acquire_resp;
1003 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1004 struct bnx2x_dma pf2vf_bulletin_mapping;
1005 struct bnx2x_vf_bulletin old_bulletin;
1006 rte_spinlock_t vf2pf_lock;
1007
1008 int media;
1009
1010 int state; /* device state */
1011 #define BNX2X_STATE_CLOSED 0x0000
1012 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1013 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1014 #define BNX2X_STATE_OPEN 0x3000
1015 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1016 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1017 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1018 #define BNX2X_STATE_DISABLED 0xD000
1019 #define BNX2X_STATE_DIAG 0xE000
1020 #define BNX2X_STATE_ERROR 0xF000
1021
1022 int flags;
1023 #define BNX2X_ONE_PORT_FLAG 0x1
1024 #define BNX2X_NO_FCOE_FLAG 0x2
1025 #define BNX2X_NO_WOL_FLAG 0x4
1026 #define BNX2X_NO_MCP_FLAG 0x8
1027 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1028 #define BNX2X_NO_ISCSI_FLAG 0x20
1029 #define BNX2X_MF_FUNC_DIS 0x40
1030 #define BNX2X_TX_SWITCHING 0x80
1031 #define BNX2X_IS_VF_FLAG 0x100
1032
1033 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1034 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1035 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1036
1037 #define MAX_BARS 5
1038 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1039
1040 uint16_t doorbell_size;
1041
1042 /* periodic timer callout */
1043 #define PERIODIC_STOP 0
1044 #define PERIODIC_GO 1
1045 volatile unsigned long periodic_flags;
1046 rte_atomic32_t scan_fp;
1047 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1048 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1049
1050 uint8_t unit; /* driver instance number */
1051
1052 int pcie_bus; /* PCIe bus number */
1053 int pcie_device; /* PCIe device/slot number */
1054 int pcie_func; /* PCIe function number */
1055
1056 uint8_t pfunc_rel; /* function relative */
1057 uint8_t pfunc_abs; /* function absolute */
1058 uint8_t path_id; /* function absolute */
1059 #define SC_PATH(sc) (sc->path_id)
1060 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1061 #define SC_FUNC(sc) (sc->pfunc_rel)
1062 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1063 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1064 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1065 #define PORT_ID(sc) SC_PORT(sc)
1066 #define PATH_ID(sc) SC_PATH(sc)
1067 #define VNIC_ID(sc) SC_VN(sc)
1068 #define FUNC_ID(sc) SC_FUNC(sc)
1069 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1070 #define SC_FW_MB_IDX_VN(sc, vn) \
1071 (SC_PORT(sc) + (vn) * \
1072 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1073 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1074
1075 int if_capen; /* enabled interface capabilities */
1076
1077 struct bnx2x_devinfo devinfo;
1078 char fw_ver_str[32];
1079 char mf_mode_str[32];
1080 char pci_link_str[32];
1081
1082 struct iro *iro_array;
1083
1084 int dmae_ready;
1085 #define DMAE_READY(sc) (sc->dmae_ready)
1086
1087 struct ecore_credit_pool_obj vlans_pool;
1088 struct ecore_credit_pool_obj macs_pool;
1089 struct ecore_rx_mode_obj rx_mode_obj;
1090 struct ecore_mcast_obj mcast_obj;
1091 struct ecore_rss_config_obj rss_conf_obj;
1092 struct ecore_func_sp_obj func_obj;
1093
1094 uint16_t fw_seq;
1095 uint16_t fw_drv_pulse_wr_seq;
1096 uint32_t func_stx;
1097
1098 struct elink_params link_params;
1099 struct elink_vars link_vars;
1100 uint32_t link_cnt;
1101 struct bnx2x_link_report_data last_reported_link;
1102 char mac_addr_str[32];
1103
1104 uint32_t tx_ring_size;
1105 uint32_t rx_ring_size;
1106 int wol;
1107
1108 int is_leader;
1109 int recovery_state;
1110 #define BNX2X_RECOVERY_DONE 1
1111 #define BNX2X_RECOVERY_INIT 2
1112 #define BNX2X_RECOVERY_WAIT 3
1113 #define BNX2X_RECOVERY_FAILED 4
1114 #define BNX2X_RECOVERY_NIC_LOADING 5
1115
1116 uint32_t rx_mode;
1117 #define BNX2X_RX_MODE_NONE 0
1118 #define BNX2X_RX_MODE_NORMAL 1
1119 #define BNX2X_RX_MODE_ALLMULTI 2
1120 #define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
1121 #define BNX2X_RX_MODE_PROMISC 4
1122 #define BNX2X_MAX_MULTICAST 64
1123
1124 struct bnx2x_port port;
1125
1126 struct cmng_init cmng;
1127
1128 /* user configs */
1129 uint8_t num_queues;
1130 int hc_rx_ticks;
1131 int hc_tx_ticks;
1132 uint32_t rx_budget;
1133 int interrupt_mode;
1134 #define INTR_MODE_INTX 0
1135 #define INTR_MODE_MSI 1
1136 #define INTR_MODE_MSIX 2
1137 #define INTR_MODE_SINGLE_MSIX 3
1138 int udp_rss;
1139
1140 uint8_t igu_dsb_id;
1141 uint8_t igu_base_sb;
1142 uint8_t igu_sb_cnt;
1143 uint32_t igu_base_addr;
1144 uint8_t base_fw_ndsb;
1145 #define DEF_SB_IGU_ID 16
1146 #define DEF_SB_ID HC_SP_SB_ID
1147
1148 /* default status block */
1149 struct bnx2x_dma def_sb_dma;
1150 struct host_sp_status_block *def_sb;
1151 uint16_t def_idx;
1152 uint16_t def_att_idx;
1153 uint32_t attn_state;
1154 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1155
1156 /* general SP events - stats query, cfc delete, etc */
1157 #define HC_SP_INDEX_ETH_DEF_CONS 3
1158 /* EQ completions */
1159 #define HC_SP_INDEX_EQ_CONS 7
1160 /* FCoE L2 connection completions */
1161 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1162 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1163 /* iSCSI L2 */
1164 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1165 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1166
1167 /* event queue */
1168 struct bnx2x_dma eq_dma;
1169 union event_ring_elem *eq;
1170 uint16_t eq_prod;
1171 uint16_t eq_cons;
1172 uint16_t *eq_cons_sb;
1173 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1174 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1175 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1176 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1177 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1178 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1179 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1180 #define NEXT_EQ_IDX(x) \
1181 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1182 ((x) + 2) : ((x) + 1))
1183 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1184 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1185
1186 /* slow path */
1187 struct bnx2x_dma sp_dma;
1188 struct bnx2x_slowpath *sp;
1189 uint32_t sp_state;
1190
1191 /* slow path queue */
1192 struct bnx2x_dma spq_dma;
1193 struct eth_spe *spq;
1194 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1195 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1196 #define MAX_SPQ_PENDING 8
1197
1198 uint16_t spq_prod_idx;
1199 struct eth_spe *spq_prod_bd;
1200 struct eth_spe *spq_last_bd;
1201 uint16_t *dsb_sp_prod;
1202
1203 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1204 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1205
1206 /* fw decompression buffer */
1207 struct bnx2x_dma gz_buf_dma;
1208 void *gz_buf;
1209 uint32_t gz_outlen;
1210 #define GUNZIP_BUF(sc) (sc->gz_buf)
1211 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1212 #define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr)
1213 #define FW_BUF_SIZE 0x40000
1214
1215 struct raw_op *init_ops;
1216 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1217 uint32_t *init_data; /* data blob, 32 bit granularity */
1218 uint32_t init_mode_flags;
1219 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1220 /* PRAM blobs - raw data */
1221 const uint8_t *tsem_int_table_data;
1222 const uint8_t *tsem_pram_data;
1223 const uint8_t *usem_int_table_data;
1224 const uint8_t *usem_pram_data;
1225 const uint8_t *xsem_int_table_data;
1226 const uint8_t *xsem_pram_data;
1227 const uint8_t *csem_int_table_data;
1228 const uint8_t *csem_pram_data;
1229 #define INIT_OPS(sc) (sc->init_ops)
1230 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1231 #define INIT_DATA(sc) (sc->init_data)
1232 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1233 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1234 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1235 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1236 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1237 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1238 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1239 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1240
1241 #define PHY_FW_VER_LEN 20
1242 char fw_ver[32];
1243
1244 /* ILT
1245 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1246 * context size we need 8 ILT entries.
1247 */
1248 #define ILT_MAX_L2_LINES 8
1249 struct hw_context context[ILT_MAX_L2_LINES];
1250 struct ecore_ilt *ilt;
1251 #define ILT_MAX_LINES 256
1252
1253 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1254 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1255 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1256 #define BNX2X_L2_MAX_CID(sc) \
1257 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1258 #define BNX2X_L2_CID_COUNT(sc) \
1259 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1260 #define L2_ILT_LINES(sc) \
1261 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1262
1263 int qm_cid_count;
1264
1265 uint8_t dropless_fc;
1266
1267 /* total number of FW statistics requests */
1268 uint8_t fw_stats_num;
1269 /*
1270 * This is a memory buffer that will contain both statistics ramrod
1271 * request and data.
1272 */
1273 struct bnx2x_dma fw_stats_dma;
1274 /*
1275 * FW statistics request shortcut (points at the beginning of fw_stats
1276 * buffer).
1277 */
1278 int fw_stats_req_size;
1279 struct bnx2x_fw_stats_req *fw_stats_req;
1280 rte_iova_t fw_stats_req_mapping;
1281 /*
1282 * FW statistics data shortcut (points at the beginning of fw_stats
1283 * buffer + fw_stats_req_size).
1284 */
1285 int fw_stats_data_size;
1286 struct bnx2x_fw_stats_data *fw_stats_data;
1287 rte_iova_t fw_stats_data_mapping;
1288
1289 /* tracking a pending STAT_QUERY ramrod */
1290 uint16_t stats_pending;
1291 /* number of completed statistics ramrods */
1292 uint16_t stats_comp;
1293 uint16_t stats_counter;
1294 uint8_t stats_init;
1295 int stats_state;
1296
1297 struct bnx2x_eth_stats eth_stats;
1298 struct host_func_stats func_stats;
1299 struct bnx2x_eth_stats_old eth_stats_old;
1300 struct bnx2x_net_stats_old net_stats_old;
1301 struct bnx2x_fw_port_stats_old fw_stats_old;
1302
1303 struct dmae_command stats_dmae; /* used by dmae command loader */
1304 int executer_idx;
1305
1306 int mtu;
1307
1308 /* DCB support on/off */
1309 int dcb_state;
1310 #define BNX2X_DCB_STATE_OFF 0
1311 #define BNX2X_DCB_STATE_ON 1
1312 /* DCBX engine mode */
1313 int dcbx_enabled;
1314 #define BNX2X_DCBX_ENABLED_OFF 0
1315 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1316 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1317 #define BNX2X_DCBX_ENABLED_INVALID -1
1318
1319 uint8_t cnic_support;
1320 uint8_t cnic_enabled;
1321 uint8_t cnic_loaded;
1322 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1323 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1324 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1325
1326 /* multiple tx classes of service */
1327 uint8_t max_cos;
1328 #define BNX2X_MAX_PRIORITY 8
1329 /* priority to cos mapping */
1330 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1331
1332 int panic;
1333 /* Array of Multicast addrs */
1334 struct rte_ether_addr mc_addrs[VF_MAX_MULTICAST_PER_VF];
1335 /* Multicast mac addresses number */
1336 uint16_t mc_addrs_num;
1337 }; /* struct bnx2x_softc */
1338
1339 /* IOCTL sub-commands for edebug and firmware upgrade */
1340 #define BNX2X_IOC_RD_NVRAM 1
1341 #define BNX2X_IOC_WR_NVRAM 2
1342 #define BNX2X_IOC_STATS_SHOW_NUM 3
1343 #define BNX2X_IOC_STATS_SHOW_STR 4
1344 #define BNX2X_IOC_STATS_SHOW_CNT 5
1345
1346 struct bnx2x_nvram_data {
1347 uint32_t op; /* ioctl sub-command */
1348 uint32_t offset;
1349 uint32_t len;
1350 uint32_t value[1]; /* variable */
1351 };
1352
1353 union bnx2x_stats_show_data {
1354 uint32_t op; /* ioctl sub-command */
1355
1356 struct {
1357 uint32_t num; /* return number of stats */
1358 uint32_t len; /* length of each string item */
1359 } desc;
1360
1361 /* variable length... */
1362 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1363
1364 /* variable length... */
1365 uint64_t stats[1]; /* holds all stats */
1366 };
1367
1368 /* function init flags */
1369 #define FUNC_FLG_RSS 0x0001
1370 #define FUNC_FLG_STATS 0x0002
1371 /* FUNC_FLG_UNMATCHED 0x0004 */
1372 #define FUNC_FLG_SPQ 0x0010
1373 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1374
1375 struct bnx2x_func_init_params {
1376 rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1377 rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1378 uint16_t func_flgs;
1379 uint16_t func_id; /* abs function id */
1380 uint16_t pf_id;
1381 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1382 };
1383
1384 /* memory resources reside at BARs 0, 2, 4 */
1385 /* Run `pciconf -lb` to see mappings */
1386 #define BAR0 0
1387 #define BAR1 2
1388 #define BAR2 4
1389
1390 static inline void
bnx2x_reg_write8(struct bnx2x_softc * sc,size_t offset,uint8_t val)1391 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
1392 {
1393 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1394 (unsigned long)offset, val);
1395 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1396 }
1397
1398 static inline void
bnx2x_reg_write16(struct bnx2x_softc * sc,size_t offset,uint16_t val)1399 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
1400 {
1401 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1402 if ((offset % 2) != 0)
1403 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
1404 (unsigned long)offset);
1405 #endif
1406 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
1407 (unsigned long)offset, val);
1408 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1409
1410 }
1411
1412 static inline void
bnx2x_reg_write32(struct bnx2x_softc * sc,size_t offset,uint32_t val)1413 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
1414 {
1415 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1416 if ((offset % 4) != 0)
1417 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
1418 (unsigned long)offset);
1419 #endif
1420
1421 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1422 (unsigned long)offset, val);
1423 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1424 }
1425
1426 static inline uint8_t
bnx2x_reg_read8(struct bnx2x_softc * sc,size_t offset)1427 bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
1428 {
1429 uint8_t val;
1430
1431 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
1432 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1433 (unsigned long)offset, val);
1434
1435 return val;
1436 }
1437
1438 static inline uint16_t
bnx2x_reg_read16(struct bnx2x_softc * sc,size_t offset)1439 bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
1440 {
1441 uint16_t val;
1442
1443 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1444 if ((offset % 2) != 0)
1445 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
1446 (unsigned long)offset);
1447 #endif
1448
1449 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1450 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1451 (unsigned long)offset, val);
1452
1453 return val;
1454 }
1455
1456 static inline uint32_t
bnx2x_reg_read32(struct bnx2x_softc * sc,size_t offset)1457 bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
1458 {
1459 uint32_t val;
1460
1461 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1462 if ((offset % 4) != 0)
1463 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
1464 (unsigned long)offset);
1465 #endif
1466
1467 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1468 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1469 (unsigned long)offset, val);
1470
1471 return val;
1472 }
1473
1474 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1475
1476 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1477 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1478 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1479
1480 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1481 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1482 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1483
1484 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1485 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1486
1487 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1488 #define BNX2X_SP_MAPPING(sc, var) \
1489 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1490
1491 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1492 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1493
1494 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1495
1496 #define REG_RD_DMAE(sc, offset, valp, len32) \
1497 do { \
1498 (void)bnx2x_read_dmae(sc, offset, len32); \
1499 rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1500 } while (0)
1501
1502 #define REG_WR_DMAE(sc, offset, valp, len32) \
1503 do { \
1504 rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1505 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1506 } while (0)
1507
1508 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1509 REG_WR_DMAE(sc, offset, valp, len32)
1510
1511 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1512 REG_RD_DMAE(sc, offset, valp, len32)
1513
1514 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1515 do { \
1516 /* if (le32_swap) { */ \
1517 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1518 /* } */ \
1519 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1520 ecore_write_big_buf_wb(sc, addr, len32); \
1521 } while (0)
1522
1523 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1524 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1525 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1526 #error "Minimum DB doorbell stride is 8"
1527 #endif
1528 #define DPM_TRIGGER_TYPE 0x40
1529
1530 /* Doorbell macro */
1531 #define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
1532
1533 #define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
1534
1535 #define DOORBELL_ADDR(sc, offset) \
1536 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1537
1538 #define DOORBELL(sc, cid, val) \
1539 if (IS_PF(sc)) \
1540 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1541 else \
1542 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1543
1544 #define SHMEM_ADDR(sc, field) \
1545 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1546 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1547 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1548 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1549
1550 #define SHMEM2_ADDR(sc, field) \
1551 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1552 #define SHMEM2_HAS(sc, field) \
1553 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1554 offsetof(struct shmem2_region, field)))
1555 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1556 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1557
1558 #define MFCFG_ADDR(sc, field) \
1559 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1560 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1561 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1562 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1563
1564 /* DMAE command defines */
1565
1566 #define DMAE_TIMEOUT -1
1567 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1568 #define DMAE_NOT_RDY -3
1569 #define DMAE_PCI_ERR_FLAG 0x80000000
1570
1571 #define DMAE_SRC_PCI 0
1572 #define DMAE_SRC_GRC 1
1573
1574 #define DMAE_DST_NONE 0
1575 #define DMAE_DST_PCI 1
1576 #define DMAE_DST_GRC 2
1577
1578 #define DMAE_COMP_PCI 0
1579 #define DMAE_COMP_GRC 1
1580
1581 #define DMAE_COMP_REGULAR 0
1582 #define DMAE_COM_SET_ERR 1
1583
1584 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1585 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1586 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1587 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1588
1589 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1590 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1591
1592 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1593 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1594 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1595 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1596
1597 #define DMAE_CMD_PORT_0 0
1598 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1599
1600 #define DMAE_SRC_PF 0
1601 #define DMAE_SRC_VF 1
1602
1603 #define DMAE_DST_PF 0
1604 #define DMAE_DST_VF 1
1605
1606 #define DMAE_C_SRC 0
1607 #define DMAE_C_DST 1
1608
1609 #define DMAE_LEN32_RD_MAX 0x80
1610 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1611
1612 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1613
1614 #define MAX_DMAE_C_PER_PORT 8
1615 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1616 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1617
1618 static const uint32_t dmae_reg_go_c[] = {
1619 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1620 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1621 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1622 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1623 };
1624
1625 #define ATTN_NIG_FOR_FUNC (1L << 8)
1626 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1627 #define GPIO_2_FUNC (1L << 10)
1628 #define GPIO_3_FUNC (1L << 11)
1629 #define GPIO_4_FUNC (1L << 12)
1630 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1631 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1632 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1633 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1634 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1635 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1636 #define ATTN_HARD_WIRED_MASK 0xff00
1637 #define ATTENTION_ID 4
1638
1639 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1640 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1641
1642 #define MAX_IGU_ATTN_ACK_TO 100
1643
1644 #define STORM_ASSERT_ARRAY_SIZE 50
1645
1646 #define BNX2X_PMF_LINK_ASSERT(sc) \
1647 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1648
1649 #define BNX2X_MC_ASSERT_BITS \
1650 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1651 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1652 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1653 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1654
1655 #define BNX2X_MCP_ASSERT \
1656 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1657
1658 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1659 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1660 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1661 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1662 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1663 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1664 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1665
1666 #define HW_INTERRUT_ASSERT_SET_0 \
1667 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1668 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1669 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1670 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
1671 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1672 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1673 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1674 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1675 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1676 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1677 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1678 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1679 #define HW_INTERRUT_ASSERT_SET_1 \
1680 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1681 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1682 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1683 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1684 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1685 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1686 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1687 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1688 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1689 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1690 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1691 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1692 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1693 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1694 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1695 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1696 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1697 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1698 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1699 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1700 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1701 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1702 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1703 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1704 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1705 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1706 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1707 #define HW_INTERRUT_ASSERT_SET_2 \
1708 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1709 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1710 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1711 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1712 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1713 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1714 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1715 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1716 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1717 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1718 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1719 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1720 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1721
1722 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
1723 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1724 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1725 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
1726
1727 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
1728 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1729
1730 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1731 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1732
1733 #define MULTI_MASK 0x7f
1734
1735 #define PFS_PER_PORT(sc) \
1736 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1737 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1738
1739 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1740 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1741 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1742
1743 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1744 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1745 (i) < MAX_FUNC_NUM; \
1746 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1747
1748 #define BNX2X_SWCID_SHIFT 17
1749 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1750
1751 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1752 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1753
1754 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1755 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1756 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1757 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1758 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1759
1760 /* must be used on a CID before placing it on a HW ring */
1761 #define HW_CID(sc, x) \
1762 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1763
1764 #define SPEED_10 10
1765 #define SPEED_100 100
1766 #define SPEED_1000 1000
1767 #define SPEED_2500 2500
1768 #define SPEED_10000 10000
1769
1770 #define PCI_PM_D0 1
1771 #define PCI_PM_D3hot 2
1772
1773 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1774
1775 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1776 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1777 void bnx2x_dma_free(struct bnx2x_dma *dma);
1778 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1779 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1780 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1781 uint8_t dst_type, uint8_t with_comp,
1782 uint8_t comp_type);
1783 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1784 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1785 void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr,
1786 uint32_t dst_addr, uint32_t len32);
1787 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1788 uint32_t cid);
1789 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1790 uint8_t sb_index, uint8_t disable,
1791 uint16_t usec);
1792
1793 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1794 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1795
1796 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1797 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1798
1799 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1800 size_t size, uint32_t *data);
1801
1802 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1803 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1804
1805 #define BNX2X_MAC_FMT "%pM"
1806 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1807
1808 /***********/
1809 /* INLINES */
1810 /***********/
1811
1812 static inline uint32_t
reg_poll(struct bnx2x_softc * sc,uint32_t reg,uint32_t expected,int ms,int wait)1813 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1814 {
1815 uint32_t val;
1816 do {
1817 val = REG_RD(sc, reg);
1818 if (val == expected) {
1819 break;
1820 }
1821 ms -= wait;
1822 DELAY(wait * 1000);
1823 } while (ms > 0);
1824
1825 return val;
1826 }
1827
1828 static inline void
bnx2x_update_fp_sb_idx(struct bnx2x_fastpath * fp)1829 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1830 {
1831 mb(); /* status block is written to by the chip */
1832 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1833 }
1834
1835 static inline void
bnx2x_igu_ack_sb_gen(struct bnx2x_softc * sc,uint8_t segment,uint16_t index,uint8_t op,uint8_t update,uint32_t igu_addr)1836 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1837 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1838 {
1839 struct igu_regular cmd_data = {0};
1840
1841 cmd_data.sb_id_and_flags =
1842 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1843 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1844 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1845 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1846
1847 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1848
1849 /* Make sure that ACK is written */
1850 mb();
1851 }
1852
1853 static inline void
bnx2x_hc_ack_sb(struct bnx2x_softc * sc,uint8_t sb_id,uint8_t storm,uint16_t index,uint8_t op,uint8_t update)1854 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1855 uint16_t index, uint8_t op, uint8_t update)
1856 {
1857 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1858 COMMAND_REG_INT_ACK);
1859 union {
1860 struct igu_ack_register igu_ack;
1861 uint32_t val;
1862 } val;
1863
1864 val.igu_ack.status_block_index = index;
1865 val.igu_ack.sb_id_and_flags =
1866 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1867 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1868 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1869 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1870
1871 REG_WR(sc, hc_addr, val.val);
1872
1873 /* Make sure that ACK is written */
1874 mb();
1875 }
1876
1877 static inline uint32_t
bnx2x_hc_ack_int(struct bnx2x_softc * sc)1878 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1879 {
1880 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1881 COMMAND_REG_SIMD_MASK);
1882 uint32_t result = REG_RD(sc, hc_addr);
1883
1884 mb();
1885 return result;
1886 }
1887
1888 static inline uint32_t
bnx2x_igu_ack_int(struct bnx2x_softc * sc)1889 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1890 {
1891 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1892 uint32_t result = REG_RD(sc, igu_addr);
1893
1894 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1895 result, igu_addr); */
1896
1897 mb();
1898 return result;
1899 }
1900
1901 static inline uint32_t
bnx2x_ack_int(struct bnx2x_softc * sc)1902 bnx2x_ack_int(struct bnx2x_softc *sc)
1903 {
1904 mb();
1905 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1906 return bnx2x_hc_ack_int(sc);
1907 } else {
1908 return bnx2x_igu_ack_int(sc);
1909 }
1910 }
1911
1912 static inline int
func_by_vn(struct bnx2x_softc * sc,int vn)1913 func_by_vn(struct bnx2x_softc *sc, int vn)
1914 {
1915 return 2 * vn + SC_PORT(sc);
1916 }
1917
1918 /*
1919 * send notification to other functions.
1920 */
1921 static inline void
bnx2x_link_sync_notify(struct bnx2x_softc * sc)1922 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1923 {
1924 int func, vn;
1925
1926 /* Set the attention towards other drivers on the same port */
1927 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1928 if (vn == SC_VN(sc))
1929 continue;
1930
1931 func = func_by_vn(sc, vn);
1932 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1933 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1934 }
1935 }
1936
1937 /*
1938 * Statistics ID are global per chip/path, while Client IDs for E1x
1939 * are per port.
1940 */
1941 static inline uint8_t
bnx2x_stats_id(struct bnx2x_fastpath * fp)1942 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1943 {
1944 struct bnx2x_softc *sc = fp->sc;
1945
1946 if (!CHIP_IS_E1x(sc)) {
1947 return fp->cl_id;
1948 }
1949
1950 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1951 }
1952
1953 int bnx2x_init(struct bnx2x_softc *sc);
1954 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1955 int bnx2x_attach(struct bnx2x_softc *sc);
1956 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1957 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1958 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1959 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1960 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1961 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
1962 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1963 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1964 void bnx2x_print_device_info(struct bnx2x_softc *sc);
1965 int bnx2x_intr_legacy(struct bnx2x_softc *sc);
1966 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1967 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1968 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1969 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1970 void bnx2x_periodic_stop(void *param);
1971
1972 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1973 void bnx2x_vf_close(struct bnx2x_softc *sc);
1974 int bnx2x_vf_init(struct bnx2x_softc *sc);
1975 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1976 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1977 int leading);
1978 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1979 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1980 int bnx2x_check_bull(struct bnx2x_softc *sc);
1981
1982 //#define BNX2X_PULSE
1983
1984 #define BNX2X_PCI_CAP 1
1985 #define BNX2X_PCI_ECAP 2
1986
1987 static inline struct bnx2x_pci_cap*
pci_find_cap(struct bnx2x_softc * sc,uint8_t id,uint8_t type)1988 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1989 {
1990 struct bnx2x_pci_cap *cap = sc->pci_caps;
1991
1992 while (cap) {
1993 if (cap->id == id && cap->type == type)
1994 return cap;
1995 cap = cap->next;
1996 }
1997
1998 return NULL;
1999 }
2000
2001 static inline void
bnx2x_set_rx_mode(struct bnx2x_softc * sc)2002 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
2003 {
2004 if (sc->state == BNX2X_STATE_OPEN) {
2005 if (IS_PF(sc)) {
2006 bnx2x_set_storm_rx_mode(sc);
2007 } else {
2008 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
2009 bnx2x_vf_set_rx_mode(sc);
2010 }
2011 } else {
2012 PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode");
2013 }
2014 }
2015
pci_read(struct bnx2x_softc * sc,size_t addr,void * val,uint8_t size)2016 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
2017 void *val, uint8_t size)
2018 {
2019 if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
2020 PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
2021 return ENXIO;
2022 }
2023
2024 return 0;
2025 }
2026
pci_write_word(struct bnx2x_softc * sc,size_t addr,off_t val)2027 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
2028 {
2029 uint16_t val16 = val;
2030
2031 if (rte_pci_write_config(sc->pci_dev, &val16,
2032 sizeof(val16), addr) <= 0) {
2033 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2034 return ENXIO;
2035 }
2036
2037 return 0;
2038 }
2039
pci_write_long(struct bnx2x_softc * sc,size_t addr,off_t val)2040 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
2041 {
2042 uint32_t val32 = val;
2043 if (rte_pci_write_config(sc->pci_dev, &val32,
2044 sizeof(val32), addr) <= 0) {
2045 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2046 return ENXIO;
2047 }
2048
2049 return 0;
2050 }
2051
2052 #endif /* __BNX2X_H__ */
2053