1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #ifndef _VNIC_ENIC_H_ 7 #define _VNIC_ENIC_H_ 8 9 /* Hardware intr coalesce timer is in units of 1.5us */ 10 #define INTR_COALESCE_USEC_TO_HW(usec) ((usec) * 2 / 3) 11 #define INTR_COALESCE_HW_TO_USEC(usec) ((usec) * 3 / 2) 12 13 /* Device-specific region: enet configuration */ 14 struct vnic_enet_config { 15 uint32_t flags; 16 uint32_t wq_desc_count; 17 uint32_t rq_desc_count; 18 uint16_t mtu; 19 uint16_t intr_timer_deprecated; 20 uint8_t intr_timer_type; 21 uint8_t intr_mode; 22 char devname[16]; 23 uint32_t intr_timer_usec; 24 uint16_t loop_tag; 25 uint16_t vf_rq_count; 26 uint16_t num_arfs; 27 uint64_t mem_paddr; 28 uint16_t rdma_qp_id; 29 uint16_t rdma_qp_count; 30 uint16_t rdma_resgrp; 31 uint32_t rdma_mr_id; 32 uint32_t rdma_mr_count; 33 uint32_t max_pkt_size; 34 uint16_t vf_subvnic_count; 35 uint16_t mq_subvnic_count; 36 uint32_t mq_flags; 37 38 /* the following 3 fields are per-MQ-vnic counts */ 39 uint32_t mq_rdma_mr_count; 40 uint16_t mq_rdma_qp_count; 41 uint16_t mq_rdma_resgrp; 42 43 uint16_t rdma_max_sq_ring_sz; 44 uint16_t rdma_max_rq_ring_sz; 45 uint32_t rdma_max_cq_ring_sz; 46 uint16_t rdma_max_wr_sge; 47 uint16_t rdma_max_mr_sge; 48 uint8_t rdma_max_rd_per_qp; 49 uint8_t unused; /* available */ 50 uint16_t mq_rdma_engine_count; 51 uint32_t intr_coal_tick_ns; /* coalescing timer tick in nsec */ 52 uint32_t max_rq_ring; /* MAX RQ ring size */ 53 uint32_t max_wq_ring; /* MAX WQ ring size */ 54 uint32_t max_cq_ring; /* MAX CQ ring size */ 55 uint32_t rdma_rsvd_lkey; /* Reserved (privileged) LKey */ 56 }; 57 58 #define VENETF_TSO 0x1 /* TSO enabled */ 59 #define VENETF_LRO 0x2 /* LRO enabled */ 60 #define VENETF_RXCSUM 0x4 /* RX csum enabled */ 61 #define VENETF_TXCSUM 0x8 /* TX csum enabled */ 62 #define VENETF_RSS 0x10 /* RSS enabled */ 63 #define VENETF_RSSHASH_IPV4 0x20 /* Hash on IPv4 fields */ 64 #define VENETF_RSSHASH_TCPIPV4 0x40 /* Hash on TCP + IPv4 fields */ 65 #define VENETF_RSSHASH_IPV6 0x80 /* Hash on IPv6 fields */ 66 #define VENETF_RSSHASH_TCPIPV6 0x100 /* Hash on TCP + IPv6 fields */ 67 #define VENETF_RSSHASH_IPV6_EX 0x200 /* Hash on IPv6 extended fields */ 68 #define VENETF_RSSHASH_TCPIPV6_EX 0x400 /* Hash on TCP + IPv6 ext. fields */ 69 #define VENETF_LOOP 0x800 /* Loopback enabled */ 70 #define VENETF_FAILOVER 0x1000 /* Fabric failover enabled */ 71 #define VENETF_USPACE_NIC 0x2000 /* vHPC enabled */ 72 #define VENETF_VMQ 0x4000 /* VMQ enabled */ 73 #define VENETF_ARFS 0x8000 /* ARFS enabled */ 74 #define VENETF_VXLAN 0x10000 /* VxLAN offload */ 75 #define VENETF_NVGRE 0x20000 /* NVGRE offload */ 76 #define VENETF_GRPINTR 0x40000 /* group interrupt */ 77 #define VENETF_NICSWITCH 0x80000 /* NICSWITCH enabled */ 78 #define VENETF_RSSHASH_UDPIPV4 0x100000 /* Hash on UDP + IPv4 fields */ 79 #define VENETF_RSSHASH_UDPIPV6 0x200000 /* Hash on UDP + IPv6 fields */ 80 #define VENETF_GENEVE 0x400000 /* GENEVE offload */ 81 82 #define VENET_INTR_TYPE_MIN 0 /* Timer specs min interrupt spacing */ 83 #define VENET_INTR_TYPE_IDLE 1 /* Timer specs idle time before irq */ 84 85 #define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */ 86 #define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */ 87 #define VENET_INTR_MODE_INTX 2 /* Try INTx only */ 88 89 #endif /* _VNIC_ENIC_H_ */ 90