xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c (revision 2a8c33eaff5adddac3ef2c5cb48ee67ef6d5d6dc)
1 /*	$NetBSD: intel_uncore.c,v 1.20 2021/12/19 12:32:15 riastradh Exp $	*/
2 
3 /*
4  * Copyright © 2013 Intel Corporation
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: intel_uncore.c,v 1.20 2021/12/19 12:32:15 riastradh Exp $");
28 
29 #include <linux/pm_runtime.h>
30 #include <asm/iosf_mbi.h>
31 
32 #ifdef __NetBSD__
33 #include <dev/pci/agp_i810var.h>
34 #endif
35 
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "i915_vgpu.h"
39 #include "intel_pm.h"
40 
41 #define FORCEWAKE_ACK_TIMEOUT_MS 50
42 #define GT_FIFO_TIMEOUT_MS	 10
43 
44 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
45 
46 void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug * mmio_debug)47 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
48 {
49 	spin_lock_init(&mmio_debug->lock);
50 	mmio_debug->unclaimed_mmio_check = 1;
51 }
52 
53 void
intel_uncore_mmio_debug_fini_early(struct intel_uncore_mmio_debug * mmio_debug)54 intel_uncore_mmio_debug_fini_early(struct intel_uncore_mmio_debug *mmio_debug)
55 {
56 	spin_lock_destroy(&mmio_debug->lock);
57 }
58 
mmio_debug_suspend(struct intel_uncore_mmio_debug * mmio_debug)59 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
60 {
61 	lockdep_assert_held(&mmio_debug->lock);
62 
63 	/* Save and disable mmio debugging for the user bypass */
64 	if (!mmio_debug->suspend_count++) {
65 		mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
66 		mmio_debug->unclaimed_mmio_check = 0;
67 	}
68 }
69 
mmio_debug_resume(struct intel_uncore_mmio_debug * mmio_debug)70 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
71 {
72 	lockdep_assert_held(&mmio_debug->lock);
73 
74 	if (!--mmio_debug->suspend_count)
75 		mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
76 }
77 
78 static const char * const forcewake_domain_names[] = {
79 	"render",
80 	"blitter",
81 	"media",
82 	"vdbox0",
83 	"vdbox1",
84 	"vdbox2",
85 	"vdbox3",
86 	"vebox0",
87 	"vebox1",
88 };
89 
90 const char *
intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)91 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
92 {
93 	BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
94 
95 	if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
96 		return forcewake_domain_names[id];
97 
98 	WARN_ON(id);
99 
100 	return "unknown";
101 }
102 
103 #ifdef __NetBSD__
104 static inline u32
fw_ack(const struct intel_uncore_forcewake_domain * d)105 fw_ack(const struct intel_uncore_forcewake_domain *d)
106 {
107 	return bus_space_read_4(d->uncore->regs_bst, d->uncore->regs_bsh,
108 	    d->reg_ack);
109 }
110 static inline void
fw_set(const struct intel_uncore_forcewake_domain * d,u32 val)111 fw_set(const struct intel_uncore_forcewake_domain *d, u32 val)
112 {
113 	bus_space_write_4(d->uncore->regs_bst, d->uncore->regs_bsh, d->reg_set,
114 	    _MASKED_BIT_ENABLE(val));
115 }
116 static inline void
fw_clear(const struct intel_uncore_forcewake_domain * d,u32 val)117 fw_clear(const struct intel_uncore_forcewake_domain *d, u32 val)
118 {
119 	bus_space_write_4(d->uncore->regs_bst, d->uncore->regs_bsh, d->reg_set,
120 	    _MASKED_BIT_DISABLE(val));
121 }
122 #else
123 #define fw_ack(d) readl((d)->reg_ack)
124 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
125 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
126 #endif
127 
128 static inline void
fw_domain_reset(const struct intel_uncore_forcewake_domain * d)129 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
130 {
131 	/*
132 	 * We don't really know if the powerwell for the forcewake domain we are
133 	 * trying to reset here does exist at this point (engines could be fused
134 	 * off in ICL+), so no waiting for acks
135 	 */
136 	/* WaRsClearFWBitsAtReset:bdw,skl */
137 	fw_clear(d, 0xffff);
138 }
139 
140 static inline void
fw_domain_arm_timer(struct intel_uncore_forcewake_domain * d)141 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
142 {
143 	GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
144 	d->uncore->fw_domains_timer |= d->mask;
145 	d->wake_count++;
146 	hrtimer_start_range_ns(&d->timer,
147 			       NSEC_PER_MSEC,
148 			       NSEC_PER_MSEC,
149 			       HRTIMER_MODE_REL);
150 }
151 
152 static inline int
__wait_for_ack(const struct intel_uncore_forcewake_domain * d,const u32 ack,const u32 value)153 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
154 	       const u32 ack,
155 	       const u32 value)
156 {
157 	return wait_for_atomic((fw_ack(d) & ack) == value,
158 			       FORCEWAKE_ACK_TIMEOUT_MS);
159 }
160 
161 static inline int
wait_ack_clear(const struct intel_uncore_forcewake_domain * d,const u32 ack)162 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
163 	       const u32 ack)
164 {
165 	return __wait_for_ack(d, ack, 0);
166 }
167 
168 static inline int
wait_ack_set(const struct intel_uncore_forcewake_domain * d,const u32 ack)169 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
170 	     const u32 ack)
171 {
172 	return __wait_for_ack(d, ack, ack);
173 }
174 
175 static inline void
fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain * d)176 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
177 {
178 	if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
179 		DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
180 			  intel_uncore_forcewake_domain_to_str(d->id));
181 		add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
182 	}
183 }
184 
185 enum ack_type {
186 	ACK_CLEAR = 0,
187 	ACK_SET
188 };
189 
190 static int
fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain * d,const enum ack_type type)191 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
192 				 const enum ack_type type)
193 {
194 	const u32 ack_bit = FORCEWAKE_KERNEL;
195 	const u32 value = type == ACK_SET ? ack_bit : 0;
196 	unsigned int pass;
197 	bool ack_detected;
198 
199 	/*
200 	 * There is a possibility of driver's wake request colliding
201 	 * with hardware's own wake requests and that can cause
202 	 * hardware to not deliver the driver's ack message.
203 	 *
204 	 * Use a fallback bit toggle to kick the gpu state machine
205 	 * in the hope that the original ack will be delivered along with
206 	 * the fallback ack.
207 	 *
208 	 * This workaround is described in HSDES #1604254524 and it's known as:
209 	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
210 	 * although the name is a bit misleading.
211 	 */
212 
213 	pass = 1;
214 	do {
215 		wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
216 
217 		fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
218 		/* Give gt some time to relax before the polling frenzy */
219 		udelay(10 * pass);
220 		wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
221 
222 		ack_detected = (fw_ack(d) & ack_bit) == value;
223 
224 		fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
225 	} while (!ack_detected && pass++ < 10);
226 
227 	DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
228 			 intel_uncore_forcewake_domain_to_str(d->id),
229 			 type == ACK_SET ? "set" : "clear",
230 			 fw_ack(d),
231 			 pass);
232 
233 	return ack_detected ? 0 : -ETIMEDOUT;
234 }
235 
236 static inline void
fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain * d)237 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
238 {
239 	if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
240 		return;
241 
242 	if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
243 		fw_domain_wait_ack_clear(d);
244 }
245 
246 static inline void
fw_domain_get(const struct intel_uncore_forcewake_domain * d)247 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
248 {
249 	fw_set(d, FORCEWAKE_KERNEL);
250 }
251 
252 static inline void
fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain * d)253 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
254 {
255 	if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
256 		DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
257 			  intel_uncore_forcewake_domain_to_str(d->id));
258 		add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
259 	}
260 }
261 
262 static inline void
fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain * d)263 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
264 {
265 	if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
266 		return;
267 
268 	if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
269 		fw_domain_wait_ack_set(d);
270 }
271 
272 static inline void
fw_domain_put(const struct intel_uncore_forcewake_domain * d)273 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
274 {
275 	fw_clear(d, FORCEWAKE_KERNEL);
276 }
277 
278 static void
fw_domains_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)279 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
280 {
281 	struct intel_uncore_forcewake_domain *d;
282 	unsigned int tmp;
283 
284 	GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
285 
286 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
287 		fw_domain_wait_ack_clear(d);
288 		fw_domain_get(d);
289 	}
290 
291 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
292 		fw_domain_wait_ack_set(d);
293 
294 	uncore->fw_domains_active |= fw_domains;
295 }
296 
297 static void
fw_domains_get_with_fallback(struct intel_uncore * uncore,enum forcewake_domains fw_domains)298 fw_domains_get_with_fallback(struct intel_uncore *uncore,
299 			     enum forcewake_domains fw_domains)
300 {
301 	struct intel_uncore_forcewake_domain *d;
302 	unsigned int tmp;
303 
304 	GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
305 
306 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
307 		fw_domain_wait_ack_clear_fallback(d);
308 		fw_domain_get(d);
309 	}
310 
311 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
312 		fw_domain_wait_ack_set_fallback(d);
313 
314 	uncore->fw_domains_active |= fw_domains;
315 }
316 
317 static void
fw_domains_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains)318 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
319 {
320 	struct intel_uncore_forcewake_domain *d;
321 	unsigned int tmp;
322 
323 	GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
324 
325 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
326 		fw_domain_put(d);
327 
328 	uncore->fw_domains_active &= ~fw_domains;
329 }
330 
331 static void
fw_domains_reset(struct intel_uncore * uncore,enum forcewake_domains fw_domains)332 fw_domains_reset(struct intel_uncore *uncore,
333 		 enum forcewake_domains fw_domains)
334 {
335 	struct intel_uncore_forcewake_domain *d;
336 	unsigned int tmp;
337 
338 	if (!fw_domains)
339 		return;
340 
341 	GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
342 
343 	for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
344 		fw_domain_reset(d);
345 }
346 
gt_thread_status(struct intel_uncore * uncore)347 static inline u32 gt_thread_status(struct intel_uncore *uncore)
348 {
349 	u32 val;
350 
351 	val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
352 	val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
353 
354 	return val;
355 }
356 
__gen6_gt_wait_for_thread_c0(struct intel_uncore * uncore)357 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
358 {
359 	/*
360 	 * w/a for a sporadic read returning 0 by waiting for the GT
361 	 * thread to wake up.
362 	 */
363 	WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
364 		  "GT thread status wait timed out\n");
365 }
366 
fw_domains_get_with_thread_status(struct intel_uncore * uncore,enum forcewake_domains fw_domains)367 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
368 					      enum forcewake_domains fw_domains)
369 {
370 	fw_domains_get(uncore, fw_domains);
371 
372 	/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
373 	__gen6_gt_wait_for_thread_c0(uncore);
374 }
375 
fifo_free_entries(struct intel_uncore * uncore)376 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
377 {
378 	u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
379 
380 	return count & GT_FIFO_FREE_ENTRIES_MASK;
381 }
382 
__gen6_gt_wait_for_fifo(struct intel_uncore * uncore)383 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
384 {
385 	u32 n;
386 
387 	/* On VLV, FIFO will be shared by both SW and HW.
388 	 * So, we need to read the FREE_ENTRIES everytime */
389 	if (IS_VALLEYVIEW(uncore->i915))
390 		n = fifo_free_entries(uncore);
391 	else
392 		n = uncore->fifo_count;
393 
394 	if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
395 		if (wait_for_atomic((n = fifo_free_entries(uncore)) >
396 				    GT_FIFO_NUM_RESERVED_ENTRIES,
397 				    GT_FIFO_TIMEOUT_MS)) {
398 			drm_dbg(&uncore->i915->drm,
399 				"GT_FIFO timeout, entries: %u\n", n);
400 			return;
401 		}
402 	}
403 
404 	uncore->fifo_count = n - 1;
405 }
406 
407 static enum hrtimer_restart
intel_uncore_fw_release_timer(struct hrtimer * timer)408 intel_uncore_fw_release_timer(struct hrtimer *timer)
409 {
410 	struct intel_uncore_forcewake_domain *domain =
411 	       container_of(timer, struct intel_uncore_forcewake_domain, timer);
412 	struct intel_uncore *uncore = domain->uncore;
413 	unsigned long irqflags;
414 
415 	assert_rpm_device_not_suspended(uncore->rpm);
416 
417 	if (xchg(&domain->active, false))
418 		return HRTIMER_RESTART;
419 
420 	spin_lock_irqsave(&uncore->lock, irqflags);
421 
422 	uncore->fw_domains_timer &= ~domain->mask;
423 
424 	GEM_BUG_ON(!domain->wake_count);
425 	if (--domain->wake_count == 0)
426 		uncore->funcs.force_wake_put(uncore, domain->mask);
427 
428 	spin_unlock_irqrestore(&uncore->lock, irqflags);
429 
430 	return HRTIMER_NORESTART;
431 }
432 
433 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
434 static unsigned int
intel_uncore_forcewake_reset(struct intel_uncore * uncore)435 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
436 {
437 	unsigned long irqflags;
438 	struct intel_uncore_forcewake_domain *domain;
439 	int retry_count = 100;
440 	enum forcewake_domains fw, active_domains;
441 
442 	iosf_mbi_assert_punit_acquired();
443 
444 	/* Hold uncore.lock across reset to prevent any register access
445 	 * with forcewake not set correctly. Wait until all pending
446 	 * timers are run before holding.
447 	 */
448 	while (1) {
449 		unsigned int tmp;
450 
451 		active_domains = 0;
452 
453 		for_each_fw_domain(domain, uncore, tmp) {
454 			smp_store_mb(domain->active, false);
455 			if (hrtimer_cancel(&domain->timer) == 0)
456 				continue;
457 
458 			intel_uncore_fw_release_timer(&domain->timer);
459 		}
460 
461 		spin_lock_irqsave(&uncore->lock, irqflags);
462 
463 		for_each_fw_domain(domain, uncore, tmp) {
464 			if (hrtimer_active(&domain->timer))
465 				active_domains |= domain->mask;
466 		}
467 
468 		if (active_domains == 0)
469 			break;
470 
471 		if (--retry_count == 0) {
472 			drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
473 			break;
474 		}
475 
476 		spin_unlock_irqrestore(&uncore->lock, irqflags);
477 		cond_resched();
478 	}
479 
480 	WARN_ON(active_domains);
481 
482 	fw = uncore->fw_domains_active;
483 	if (fw)
484 		uncore->funcs.force_wake_put(uncore, fw);
485 
486 	fw_domains_reset(uncore, uncore->fw_domains);
487 	assert_forcewakes_inactive(uncore);
488 
489 	spin_unlock_irqrestore(&uncore->lock, irqflags);
490 
491 	return fw; /* track the lost user forcewake domains */
492 }
493 
494 static bool
fpga_check_for_unclaimed_mmio(struct intel_uncore * uncore)495 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
496 {
497 	u32 dbg;
498 
499 	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
500 	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
501 		return false;
502 
503 	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
504 
505 	return true;
506 }
507 
508 static bool
vlv_check_for_unclaimed_mmio(struct intel_uncore * uncore)509 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
510 {
511 	u32 cer;
512 
513 	cer = __raw_uncore_read32(uncore, CLAIM_ER);
514 	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
515 		return false;
516 
517 	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
518 
519 	return true;
520 }
521 
522 static bool
gen6_check_for_fifo_debug(struct intel_uncore * uncore)523 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
524 {
525 	u32 fifodbg;
526 
527 	fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
528 
529 	if (unlikely(fifodbg)) {
530 		drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
531 		__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
532 	}
533 
534 	return fifodbg;
535 }
536 
537 static bool
check_for_unclaimed_mmio(struct intel_uncore * uncore)538 check_for_unclaimed_mmio(struct intel_uncore *uncore)
539 {
540 	bool ret = false;
541 
542 	lockdep_assert_held(&uncore->debug->lock);
543 
544 	if (uncore->debug->suspend_count)
545 		return false;
546 
547 	if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
548 		ret |= fpga_check_for_unclaimed_mmio(uncore);
549 
550 	if (intel_uncore_has_dbg_unclaimed(uncore))
551 		ret |= vlv_check_for_unclaimed_mmio(uncore);
552 
553 	if (intel_uncore_has_fifo(uncore))
554 		ret |= gen6_check_for_fifo_debug(uncore);
555 
556 	return ret;
557 }
558 
forcewake_early_sanitize(struct intel_uncore * uncore,unsigned int restore_forcewake)559 static void forcewake_early_sanitize(struct intel_uncore *uncore,
560 				     unsigned int restore_forcewake)
561 {
562 	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
563 
564 	/* WaDisableShadowRegForCpd:chv */
565 	if (IS_CHERRYVIEW(uncore->i915)) {
566 		__raw_uncore_write32(uncore, GTFIFOCTL,
567 				     __raw_uncore_read32(uncore, GTFIFOCTL) |
568 				     GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
569 				     GT_FIFO_CTL_RC6_POLICY_STALL);
570 	}
571 
572 	iosf_mbi_punit_acquire();
573 	intel_uncore_forcewake_reset(uncore);
574 	if (restore_forcewake) {
575 		spin_lock_irq(&uncore->lock);
576 		uncore->funcs.force_wake_get(uncore, restore_forcewake);
577 
578 		if (intel_uncore_has_fifo(uncore))
579 			uncore->fifo_count = fifo_free_entries(uncore);
580 		spin_unlock_irq(&uncore->lock);
581 	}
582 	iosf_mbi_punit_release();
583 }
584 
intel_uncore_suspend(struct intel_uncore * uncore)585 void intel_uncore_suspend(struct intel_uncore *uncore)
586 {
587 	if (!intel_uncore_has_forcewake(uncore))
588 		return;
589 
590 	iosf_mbi_punit_acquire();
591 	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
592 		&uncore->pmic_bus_access_nb);
593 	uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
594 	iosf_mbi_punit_release();
595 }
596 
intel_uncore_resume_early(struct intel_uncore * uncore)597 void intel_uncore_resume_early(struct intel_uncore *uncore)
598 {
599 	unsigned int restore_forcewake;
600 
601 	if (intel_uncore_unclaimed_mmio(uncore))
602 		drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
603 
604 	if (!intel_uncore_has_forcewake(uncore))
605 		return;
606 
607 	restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
608 	forcewake_early_sanitize(uncore, restore_forcewake);
609 
610 	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
611 }
612 
intel_uncore_runtime_resume(struct intel_uncore * uncore)613 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
614 {
615 	if (!intel_uncore_has_forcewake(uncore))
616 		return;
617 
618 	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
619 }
620 
__intel_uncore_forcewake_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)621 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
622 					 enum forcewake_domains fw_domains)
623 {
624 	struct intel_uncore_forcewake_domain *domain;
625 	unsigned int tmp;
626 
627 	fw_domains &= uncore->fw_domains;
628 
629 	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
630 		if (domain->wake_count++) {
631 			fw_domains &= ~domain->mask;
632 			domain->active = true;
633 		}
634 	}
635 
636 	if (fw_domains)
637 		uncore->funcs.force_wake_get(uncore, fw_domains);
638 }
639 
640 /**
641  * intel_uncore_forcewake_get - grab forcewake domain references
642  * @uncore: the intel_uncore structure
643  * @fw_domains: forcewake domains to get reference on
644  *
645  * This function can be used get GT's forcewake domain references.
646  * Normal register access will handle the forcewake domains automatically.
647  * However if some sequence requires the GT to not power down a particular
648  * forcewake domains this function should be called at the beginning of the
649  * sequence. And subsequently the reference should be dropped by symmetric
650  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
651  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
652  */
intel_uncore_forcewake_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)653 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
654 				enum forcewake_domains fw_domains)
655 {
656 	unsigned long irqflags;
657 
658 	if (!uncore->funcs.force_wake_get)
659 		return;
660 
661 	assert_rpm_wakelock_held(uncore->rpm);
662 
663 	spin_lock_irqsave(&uncore->lock, irqflags);
664 	__intel_uncore_forcewake_get(uncore, fw_domains);
665 	spin_unlock_irqrestore(&uncore->lock, irqflags);
666 }
667 
668 /**
669  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
670  * @uncore: the intel_uncore structure
671  *
672  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
673  * the GT powerwell and in the process disable our debugging for the
674  * duration of userspace's bypass.
675  */
intel_uncore_forcewake_user_get(struct intel_uncore * uncore)676 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
677 {
678 	spin_lock_irq(&uncore->lock);
679 	if (!uncore->user_forcewake_count++) {
680 		intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
681 		spin_lock(&uncore->debug->lock);
682 		mmio_debug_suspend(uncore->debug);
683 		spin_unlock(&uncore->debug->lock);
684 	}
685 	spin_unlock_irq(&uncore->lock);
686 }
687 
688 /**
689  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
690  * @uncore: the intel_uncore structure
691  *
692  * This function complements intel_uncore_forcewake_user_get() and releases
693  * the GT powerwell taken on behalf of the userspace bypass.
694  */
intel_uncore_forcewake_user_put(struct intel_uncore * uncore)695 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
696 {
697 	spin_lock_irq(&uncore->lock);
698 	if (!--uncore->user_forcewake_count) {
699 		spin_lock(&uncore->debug->lock);
700 		mmio_debug_resume(uncore->debug);
701 
702 		if (check_for_unclaimed_mmio(uncore))
703 			dev_info(uncore->i915->drm.dev,
704 				 "Invalid mmio detected during user access\n");
705 		spin_unlock(&uncore->debug->lock);
706 
707 		intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
708 	}
709 	spin_unlock_irq(&uncore->lock);
710 }
711 
712 /**
713  * intel_uncore_forcewake_get__locked - grab forcewake domain references
714  * @uncore: the intel_uncore structure
715  * @fw_domains: forcewake domains to get reference on
716  *
717  * See intel_uncore_forcewake_get(). This variant places the onus
718  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
719  */
intel_uncore_forcewake_get__locked(struct intel_uncore * uncore,enum forcewake_domains fw_domains)720 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
721 					enum forcewake_domains fw_domains)
722 {
723 	lockdep_assert_held(&uncore->lock);
724 
725 	if (!uncore->funcs.force_wake_get)
726 		return;
727 
728 	__intel_uncore_forcewake_get(uncore, fw_domains);
729 }
730 
__intel_uncore_forcewake_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains)731 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
732 					 enum forcewake_domains fw_domains)
733 {
734 	struct intel_uncore_forcewake_domain *domain;
735 	unsigned int tmp;
736 
737 	fw_domains &= uncore->fw_domains;
738 
739 	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
740 		GEM_BUG_ON(!domain->wake_count);
741 
742 		if (--domain->wake_count) {
743 			domain->active = true;
744 			continue;
745 		}
746 
747 		fw_domain_arm_timer(domain);
748 	}
749 }
750 
751 /**
752  * intel_uncore_forcewake_put - release a forcewake domain reference
753  * @uncore: the intel_uncore structure
754  * @fw_domains: forcewake domains to put references
755  *
756  * This function drops the device-level forcewakes for specified
757  * domains obtained by intel_uncore_forcewake_get().
758  */
intel_uncore_forcewake_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains)759 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
760 				enum forcewake_domains fw_domains)
761 {
762 	unsigned long irqflags;
763 
764 	if (!uncore->funcs.force_wake_put)
765 		return;
766 
767 	spin_lock_irqsave(&uncore->lock, irqflags);
768 	__intel_uncore_forcewake_put(uncore, fw_domains);
769 	spin_unlock_irqrestore(&uncore->lock, irqflags);
770 }
771 
772 /**
773  * intel_uncore_forcewake_put__locked - grab forcewake domain references
774  * @uncore: the intel_uncore structure
775  * @fw_domains: forcewake domains to get reference on
776  *
777  * See intel_uncore_forcewake_put(). This variant places the onus
778  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
779  */
intel_uncore_forcewake_put__locked(struct intel_uncore * uncore,enum forcewake_domains fw_domains)780 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
781 					enum forcewake_domains fw_domains)
782 {
783 	lockdep_assert_held(&uncore->lock);
784 
785 	if (!uncore->funcs.force_wake_put)
786 		return;
787 
788 	__intel_uncore_forcewake_put(uncore, fw_domains);
789 }
790 
assert_forcewakes_inactive(struct intel_uncore * uncore)791 void assert_forcewakes_inactive(struct intel_uncore *uncore)
792 {
793 	if (!uncore->funcs.force_wake_get)
794 		return;
795 
796 	WARN(uncore->fw_domains_active,
797 	     "Expected all fw_domains to be inactive, but %08x are still on\n",
798 	     uncore->fw_domains_active);
799 }
800 
assert_forcewakes_active(struct intel_uncore * uncore,enum forcewake_domains fw_domains)801 void assert_forcewakes_active(struct intel_uncore *uncore,
802 			      enum forcewake_domains fw_domains)
803 {
804 	struct intel_uncore_forcewake_domain *domain;
805 	unsigned int tmp;
806 
807 	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
808 		return;
809 
810 	if (!uncore->funcs.force_wake_get)
811 		return;
812 
813 	spin_lock_irq(&uncore->lock);
814 
815 	assert_rpm_wakelock_held(uncore->rpm);
816 
817 	fw_domains &= uncore->fw_domains;
818 	WARN(fw_domains & ~uncore->fw_domains_active,
819 	     "Expected %08x fw_domains to be active, but %08x are off\n",
820 	     fw_domains, fw_domains & ~uncore->fw_domains_active);
821 
822 	/*
823 	 * Check that the caller has an explicit wakeref and we don't mistake
824 	 * it for the auto wakeref.
825 	 */
826 	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
827 		unsigned int actual = READ_ONCE(domain->wake_count);
828 		unsigned int expect = 1;
829 
830 		if (uncore->fw_domains_timer & domain->mask)
831 			expect++; /* pending automatic release */
832 
833 		if (WARN(actual < expect,
834 			 "Expected domain %d to be held awake by caller, count=%d\n",
835 			 domain->id, actual))
836 			break;
837 	}
838 
839 	spin_unlock_irq(&uncore->lock);
840 }
841 
842 /* We give fast paths for the really cool registers */
843 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
844 
845 #define __gen6_reg_read_fw_domains(uncore, offset) \
846 ({ \
847 	enum forcewake_domains __fwd; \
848 	if (NEEDS_FORCE_WAKE(offset)) \
849 		__fwd = FORCEWAKE_RENDER; \
850 	else \
851 		__fwd = 0; \
852 	__fwd; \
853 })
854 
fw_range_cmp(u32 offset,const struct intel_forcewake_range * entry)855 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
856 {
857 	if (offset < entry->start)
858 		return -1;
859 	else if (offset > entry->end)
860 		return 1;
861 	else
862 		return 0;
863 }
864 
865 /* Copied and "macroized" from lib/bsearch.c */
866 #define BSEARCH(key, base, num, cmp) ({                                 \
867 	unsigned int start__ = 0, end__ = (num);                        \
868 	typeof(base) result__ = NULL;                                   \
869 	while (start__ < end__) {                                       \
870 		unsigned int mid__ = start__ + (end__ - start__) / 2;   \
871 		int ret__ = (cmp)((key), (base) + mid__);               \
872 		if (ret__ < 0) {                                        \
873 			end__ = mid__;                                  \
874 		} else if (ret__ > 0) {                                 \
875 			start__ = mid__ + 1;                            \
876 		} else {                                                \
877 			result__ = (base) + mid__;                      \
878 			break;                                          \
879 		}                                                       \
880 	}                                                               \
881 	result__;                                                       \
882 })
883 
884 static enum forcewake_domains
find_fw_domain(struct intel_uncore * uncore,u32 offset)885 find_fw_domain(struct intel_uncore *uncore, u32 offset)
886 {
887 	const struct intel_forcewake_range *entry;
888 
889 	entry = BSEARCH(offset,
890 			uncore->fw_domains_table,
891 			uncore->fw_domains_table_entries,
892 			fw_range_cmp);
893 
894 	if (!entry)
895 		return 0;
896 
897 	/*
898 	 * The list of FW domains depends on the SKU in gen11+ so we
899 	 * can't determine it statically. We use FORCEWAKE_ALL and
900 	 * translate it here to the list of available domains.
901 	 */
902 	if (entry->domains == FORCEWAKE_ALL)
903 		return uncore->fw_domains;
904 
905 	WARN(entry->domains & ~uncore->fw_domains,
906 	     "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
907 	     entry->domains & ~uncore->fw_domains, offset);
908 
909 	return entry->domains;
910 }
911 
912 #define GEN_FW_RANGE(s, e, d) \
913 	{ .start = (s), .end = (e), .domains = (d) }
914 
915 #define HAS_FWTABLE(dev_priv) \
916 	(INTEL_GEN(dev_priv) >= 9 || \
917 	 IS_CHERRYVIEW(dev_priv) || \
918 	 IS_VALLEYVIEW(dev_priv))
919 
920 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
921 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
922 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
923 	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
924 	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
925 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
926 	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
927 	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
928 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
929 };
930 
931 #define __fwtable_reg_read_fw_domains(uncore, offset) \
932 ({ \
933 	enum forcewake_domains __fwd = 0; \
934 	if (NEEDS_FORCE_WAKE((offset))) \
935 		__fwd = find_fw_domain(uncore, offset); \
936 	__fwd; \
937 })
938 
939 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
940 	find_fw_domain(uncore, offset)
941 
942 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
943 	find_fw_domain(uncore, offset)
944 
945 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
946 static const i915_reg_t gen8_shadowed_regs[] = {
947 	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
948 	GEN6_RPNSWREQ,			/* 0xA008 */
949 	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
950 	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
951 	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
952 	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
953 	/* TODO: Other registers are not yet used */
954 };
955 
956 static const i915_reg_t gen11_shadowed_regs[] = {
957 	RING_TAIL(RENDER_RING_BASE),		/* 0x2000 (base) */
958 	GEN6_RPNSWREQ,				/* 0xA008 */
959 	GEN6_RC_VIDEO_FREQ,			/* 0xA00C */
960 	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */
961 	RING_TAIL(GEN11_BSD_RING_BASE),		/* 0x1C0000 (base) */
962 	RING_TAIL(GEN11_BSD2_RING_BASE),	/* 0x1C4000 (base) */
963 	RING_TAIL(GEN11_VEBOX_RING_BASE),	/* 0x1C8000 (base) */
964 	RING_TAIL(GEN11_BSD3_RING_BASE),	/* 0x1D0000 (base) */
965 	RING_TAIL(GEN11_BSD4_RING_BASE),	/* 0x1D4000 (base) */
966 	RING_TAIL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8000 (base) */
967 	/* TODO: Other registers are not yet used */
968 };
969 
970 static const i915_reg_t gen12_shadowed_regs[] = {
971 	RING_TAIL(RENDER_RING_BASE),		/* 0x2000 (base) */
972 	GEN6_RPNSWREQ,				/* 0xA008 */
973 	GEN6_RC_VIDEO_FREQ,			/* 0xA00C */
974 	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */
975 	RING_TAIL(GEN11_BSD_RING_BASE),		/* 0x1C0000 (base) */
976 	RING_TAIL(GEN11_BSD2_RING_BASE),	/* 0x1C4000 (base) */
977 	RING_TAIL(GEN11_VEBOX_RING_BASE),	/* 0x1C8000 (base) */
978 	RING_TAIL(GEN11_BSD3_RING_BASE),	/* 0x1D0000 (base) */
979 	RING_TAIL(GEN11_BSD4_RING_BASE),	/* 0x1D4000 (base) */
980 	RING_TAIL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8000 (base) */
981 	/* TODO: Other registers are not yet used */
982 };
983 
mmio_reg_cmp(u32 key,const i915_reg_t * reg)984 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
985 {
986 	u32 offset = i915_mmio_reg_offset(*reg);
987 
988 	if (key < offset)
989 		return -1;
990 	else if (key > offset)
991 		return 1;
992 	else
993 		return 0;
994 }
995 
996 #define __is_genX_shadowed(x) \
997 static bool is_gen##x##_shadowed(u32 offset) \
998 { \
999 	const i915_reg_t *regs = gen##x##_shadowed_regs; \
1000 	return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
1001 		       mmio_reg_cmp); \
1002 }
1003 
1004 __is_genX_shadowed(8)
1005 __is_genX_shadowed(11)
1006 __is_genX_shadowed(12)
1007 
1008 static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore * uncore,i915_reg_t reg)1009 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1010 {
1011 	return FORCEWAKE_RENDER;
1012 }
1013 
1014 #define __gen8_reg_write_fw_domains(uncore, offset) \
1015 ({ \
1016 	enum forcewake_domains __fwd; \
1017 	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
1018 		__fwd = FORCEWAKE_RENDER; \
1019 	else \
1020 		__fwd = 0; \
1021 	__fwd; \
1022 })
1023 
1024 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1025 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1026 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1027 	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1028 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1029 	GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1030 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1031 	GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1032 	GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1033 	GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1034 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1035 	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1036 	GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1037 	GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1038 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1039 	GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1040 	GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1041 	GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1042 };
1043 
1044 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1045 ({ \
1046 	enum forcewake_domains __fwd = 0; \
1047 	if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
1048 		__fwd = find_fw_domain(uncore, offset); \
1049 	__fwd; \
1050 })
1051 
1052 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
1053 ({ \
1054 	enum forcewake_domains __fwd = 0; \
1055 	const u32 __offset = (offset); \
1056 	if (!is_gen11_shadowed(__offset)) \
1057 		__fwd = find_fw_domain(uncore, __offset); \
1058 	__fwd; \
1059 })
1060 
1061 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
1062 ({ \
1063 	enum forcewake_domains __fwd = 0; \
1064 	const u32 __offset = (offset); \
1065 	if (!is_gen12_shadowed(__offset)) \
1066 		__fwd = find_fw_domain(uncore, __offset); \
1067 	__fwd; \
1068 })
1069 
1070 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1071 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1072 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1073 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1074 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1075 	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1076 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1077 	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1078 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1079 	GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1080 	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1081 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1082 	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1083 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1084 	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1085 	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1086 	GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1087 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1088 	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1089 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1090 	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1091 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1092 	GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1093 	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1094 	GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1095 	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1096 	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1097 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1098 	GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1099 	GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1100 	GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1101 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1102 	GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1103 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1104 };
1105 
1106 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1107 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1108 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1109 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1110 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1111 	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1112 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1113 	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1114 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1115 	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1116 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1117 	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1118 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1119 	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1120 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1121 	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1122 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1123 	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1124 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1125 	GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
1126 	GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1127 	GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
1128 	GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1129 	GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
1130 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1131 	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1132 	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1133 	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1134 	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1135 	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1136 	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1137 	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1138 	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1139 	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1140 };
1141 
1142 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1143 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1144 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1145 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1146 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1147 	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1148 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1149 	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1150 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1151 	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1152 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1153 	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1154 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1155 	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1156 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1157 	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1158 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1159 	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1160 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1161 	GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1162 	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1163 	GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
1164 	GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
1165 	GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
1166 	GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
1167 	GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
1168 	GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
1169 	GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
1170 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1171 	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1172 	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1173 	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1174 	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1175 	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1176 	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1177 	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1178 	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1179 	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1180 };
1181 
1182 static void
ilk_dummy_write(struct intel_uncore * uncore)1183 ilk_dummy_write(struct intel_uncore *uncore)
1184 {
1185 	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1186 	 * the chip from rc6 before touching it for real. MI_MODE is masked,
1187 	 * hence harmless to write 0 into. */
1188 	__raw_uncore_write32(uncore, MI_MODE, 0);
1189 }
1190 
1191 static void
__unclaimed_reg_debug(struct intel_uncore * uncore,const i915_reg_t reg,const bool read,const bool before)1192 __unclaimed_reg_debug(struct intel_uncore *uncore,
1193 		      const i915_reg_t reg,
1194 		      const bool read,
1195 		      const bool before)
1196 {
1197 	if (WARN(check_for_unclaimed_mmio(uncore) && !before,
1198 		 "Unclaimed %s register 0x%x\n",
1199 		 read ? "read from" : "write to",
1200 		 i915_mmio_reg_offset(reg)))
1201 		/* Only report the first N failures */
1202 		i915_modparams.mmio_debug--;
1203 }
1204 
1205 static inline void
unclaimed_reg_debug(struct intel_uncore * uncore,const i915_reg_t reg,const bool read,const bool before)1206 unclaimed_reg_debug(struct intel_uncore *uncore,
1207 		    const i915_reg_t reg,
1208 		    const bool read,
1209 		    const bool before)
1210 {
1211 	if (likely(!i915_modparams.mmio_debug))
1212 		return;
1213 
1214 	/* interrupts are disabled and re-enabled around uncore->lock usage */
1215 	lockdep_assert_held(&uncore->lock);
1216 
1217 	if (before)
1218 		spin_lock(&uncore->debug->lock);
1219 
1220 	__unclaimed_reg_debug(uncore, reg, read, before);
1221 
1222 	if (!before)
1223 		spin_unlock(&uncore->debug->lock);
1224 }
1225 
1226 #define GEN2_READ_HEADER(x) \
1227 	u##x val = 0; \
1228 	assert_rpm_wakelock_held(uncore->rpm);
1229 
1230 #define GEN2_READ_FOOTER \
1231 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1232 	return val
1233 
1234 #define __gen2_read(x) \
1235 static u##x \
1236 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1237 	GEN2_READ_HEADER(x); \
1238 	val = __raw_uncore_read##x(uncore, reg); \
1239 	GEN2_READ_FOOTER; \
1240 }
1241 
1242 #define __gen5_read(x) \
1243 static u##x \
1244 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1245 	GEN2_READ_HEADER(x); \
1246 	ilk_dummy_write(uncore); \
1247 	val = __raw_uncore_read##x(uncore, reg); \
1248 	GEN2_READ_FOOTER; \
1249 }
1250 
1251 __gen5_read(8)
1252 __gen5_read(16)
1253 __gen5_read(32)
1254 __gen5_read(64)
1255 __gen2_read(8)
1256 __gen2_read(16)
1257 __gen2_read(32)
1258 __gen2_read(64)
1259 
1260 #undef __gen5_read
1261 #undef __gen2_read
1262 
1263 #undef GEN2_READ_FOOTER
1264 #undef GEN2_READ_HEADER
1265 
1266 #define GEN6_READ_HEADER(x) \
1267 	u32 offset = i915_mmio_reg_offset(reg); \
1268 	unsigned long irqflags; \
1269 	u##x val = 0; \
1270 	assert_rpm_wakelock_held(uncore->rpm); \
1271 	spin_lock_irqsave(&uncore->lock, irqflags); \
1272 	unclaimed_reg_debug(uncore, reg, true, true)
1273 
1274 #define GEN6_READ_FOOTER \
1275 	unclaimed_reg_debug(uncore, reg, true, false); \
1276 	spin_unlock_irqrestore(&uncore->lock, irqflags); \
1277 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1278 	return val
1279 
___force_wake_auto(struct intel_uncore * uncore,enum forcewake_domains fw_domains)1280 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1281 					enum forcewake_domains fw_domains)
1282 {
1283 	struct intel_uncore_forcewake_domain *domain;
1284 	unsigned int tmp;
1285 
1286 	GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1287 
1288 	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1289 		fw_domain_arm_timer(domain);
1290 
1291 	uncore->funcs.force_wake_get(uncore, fw_domains);
1292 }
1293 
__force_wake_auto(struct intel_uncore * uncore,enum forcewake_domains fw_domains)1294 static inline void __force_wake_auto(struct intel_uncore *uncore,
1295 				     enum forcewake_domains fw_domains)
1296 {
1297 	GEM_BUG_ON(!fw_domains);
1298 
1299 	/* Turn on all requested but inactive supported forcewake domains. */
1300 	fw_domains &= uncore->fw_domains;
1301 	fw_domains &= ~uncore->fw_domains_active;
1302 
1303 	if (fw_domains)
1304 		___force_wake_auto(uncore, fw_domains);
1305 }
1306 
1307 #define __gen_read(func, x) \
1308 static u##x \
1309 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1310 	enum forcewake_domains fw_engine; \
1311 	GEN6_READ_HEADER(x); \
1312 	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1313 	if (fw_engine) \
1314 		__force_wake_auto(uncore, fw_engine); \
1315 	val = __raw_uncore_read##x(uncore, reg); \
1316 	GEN6_READ_FOOTER; \
1317 }
1318 
1319 #define __gen_reg_read_funcs(func) \
1320 static enum forcewake_domains \
1321 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1322 	return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1323 } \
1324 \
1325 __gen_read(func, 8) \
1326 __gen_read(func, 16) \
1327 __gen_read(func, 32) \
1328 __gen_read(func, 64)
1329 
1330 __gen_reg_read_funcs(gen12_fwtable);
1331 __gen_reg_read_funcs(gen11_fwtable);
1332 __gen_reg_read_funcs(fwtable);
1333 __gen_reg_read_funcs(gen6);
1334 
1335 #undef __gen_reg_read_funcs
1336 #undef GEN6_READ_FOOTER
1337 #undef GEN6_READ_HEADER
1338 
1339 #define GEN2_WRITE_HEADER \
1340 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1341 	assert_rpm_wakelock_held(uncore->rpm); \
1342 
1343 #define GEN2_WRITE_FOOTER
1344 
1345 #define __gen2_write(x) \
1346 static void \
1347 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1348 	GEN2_WRITE_HEADER; \
1349 	__raw_uncore_write##x(uncore, reg, val); \
1350 	GEN2_WRITE_FOOTER; \
1351 }
1352 
1353 #define __gen5_write(x) \
1354 static void \
1355 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1356 	GEN2_WRITE_HEADER; \
1357 	ilk_dummy_write(uncore); \
1358 	__raw_uncore_write##x(uncore, reg, val); \
1359 	GEN2_WRITE_FOOTER; \
1360 }
1361 
1362 __gen5_write(8)
1363 __gen5_write(16)
1364 __gen5_write(32)
1365 __gen2_write(8)
1366 __gen2_write(16)
1367 __gen2_write(32)
1368 
1369 #undef __gen5_write
1370 #undef __gen2_write
1371 
1372 #undef GEN2_WRITE_FOOTER
1373 #undef GEN2_WRITE_HEADER
1374 
1375 #define GEN6_WRITE_HEADER \
1376 	u32 offset = i915_mmio_reg_offset(reg); \
1377 	unsigned long irqflags; \
1378 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1379 	assert_rpm_wakelock_held(uncore->rpm); \
1380 	spin_lock_irqsave(&uncore->lock, irqflags); \
1381 	unclaimed_reg_debug(uncore, reg, false, true)
1382 
1383 #define GEN6_WRITE_FOOTER \
1384 	unclaimed_reg_debug(uncore, reg, false, false); \
1385 	spin_unlock_irqrestore(&uncore->lock, irqflags)
1386 
1387 #define __gen6_write(x) \
1388 static void \
1389 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1390 	GEN6_WRITE_HEADER; \
1391 	if (NEEDS_FORCE_WAKE(offset)) \
1392 		__gen6_gt_wait_for_fifo(uncore); \
1393 	__raw_uncore_write##x(uncore, reg, val); \
1394 	GEN6_WRITE_FOOTER; \
1395 }
1396 __gen6_write(8)
1397 __gen6_write(16)
1398 __gen6_write(32)
1399 
1400 #define __gen_write(func, x) \
1401 static void \
1402 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1403 	enum forcewake_domains fw_engine; \
1404 	GEN6_WRITE_HEADER; \
1405 	fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1406 	if (fw_engine) \
1407 		__force_wake_auto(uncore, fw_engine); \
1408 	__raw_uncore_write##x(uncore, reg, val); \
1409 	GEN6_WRITE_FOOTER; \
1410 }
1411 
1412 #define __gen_reg_write_funcs(func) \
1413 static enum forcewake_domains \
1414 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1415 	return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1416 } \
1417 \
1418 __gen_write(func, 8) \
1419 __gen_write(func, 16) \
1420 __gen_write(func, 32)
1421 
1422 __gen_reg_write_funcs(gen12_fwtable);
1423 __gen_reg_write_funcs(gen11_fwtable);
1424 __gen_reg_write_funcs(fwtable);
1425 __gen_reg_write_funcs(gen8);
1426 
1427 #undef __gen_reg_write_funcs
1428 #undef GEN6_WRITE_FOOTER
1429 #undef GEN6_WRITE_HEADER
1430 
1431 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1432 do { \
1433 	(uncore)->funcs.mmio_writeb = x##_write8; \
1434 	(uncore)->funcs.mmio_writew = x##_write16; \
1435 	(uncore)->funcs.mmio_writel = x##_write32; \
1436 } while (0)
1437 
1438 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1439 do { \
1440 	(uncore)->funcs.mmio_readb = x##_read8; \
1441 	(uncore)->funcs.mmio_readw = x##_read16; \
1442 	(uncore)->funcs.mmio_readl = x##_read32; \
1443 	(uncore)->funcs.mmio_readq = x##_read64; \
1444 } while (0)
1445 
1446 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1447 do { \
1448 	ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1449 	(uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1450 } while (0)
1451 
1452 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1453 do { \
1454 	ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1455 	(uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1456 } while (0)
1457 
__fw_domain_init(struct intel_uncore * uncore,enum forcewake_domain_id domain_id,i915_reg_t reg_set,i915_reg_t reg_ack)1458 static int __fw_domain_init(struct intel_uncore *uncore,
1459 			    enum forcewake_domain_id domain_id,
1460 			    i915_reg_t reg_set,
1461 			    i915_reg_t reg_ack)
1462 {
1463 	struct intel_uncore_forcewake_domain *d;
1464 
1465 	GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1466 	GEM_BUG_ON(uncore->fw_domain[domain_id]);
1467 
1468 	if (i915_inject_probe_failure(uncore->i915))
1469 		return -ENOMEM;
1470 
1471 	d = kzalloc(sizeof(*d), GFP_KERNEL);
1472 	if (!d)
1473 		return -ENOMEM;
1474 
1475 	WARN_ON(!i915_mmio_reg_valid(reg_set));
1476 	WARN_ON(!i915_mmio_reg_valid(reg_ack));
1477 
1478 	d->uncore = uncore;
1479 	d->wake_count = 0;
1480 #ifdef __NetBSD__
1481 	d->reg_set = i915_mmio_reg_offset(reg_set);
1482 	d->reg_ack = i915_mmio_reg_offset(reg_ack);
1483 #else
1484 	d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1485 	d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1486 #endif
1487 
1488 	d->id = domain_id;
1489 
1490 	BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1491 	BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1492 	BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1493 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1494 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1495 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1496 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1497 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1498 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1499 
1500 	d->mask = BIT(domain_id);
1501 
1502 	hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1503 	d->timer.function = intel_uncore_fw_release_timer;
1504 
1505 	uncore->fw_domains |= BIT(domain_id);
1506 
1507 	fw_domain_reset(d);
1508 
1509 	uncore->fw_domain[domain_id] = d;
1510 
1511 	return 0;
1512 }
1513 
fw_domain_fini(struct intel_uncore * uncore,enum forcewake_domain_id domain_id)1514 static void fw_domain_fini(struct intel_uncore *uncore,
1515 			   enum forcewake_domain_id domain_id)
1516 {
1517 	struct intel_uncore_forcewake_domain *d;
1518 
1519 	GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1520 
1521 	d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1522 	if (!d)
1523 		return;
1524 
1525 	uncore->fw_domains &= ~BIT(domain_id);
1526 	WARN_ON(d->wake_count);
1527 	WARN_ON(hrtimer_cancel(&d->timer));
1528 	kfree(d);
1529 }
1530 
intel_uncore_fw_domains_fini(struct intel_uncore * uncore)1531 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1532 {
1533 	struct intel_uncore_forcewake_domain *d;
1534 	int tmp;
1535 
1536 	for_each_fw_domain(d, uncore, tmp)
1537 		fw_domain_fini(uncore, d->id);
1538 }
1539 
intel_uncore_fw_domains_init(struct intel_uncore * uncore)1540 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1541 {
1542 	struct drm_i915_private *i915 = uncore->i915;
1543 	int ret = 0;
1544 
1545 	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1546 
1547 #define fw_domain_init(uncore__, id__, set__, ack__) \
1548 	(ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1549 
1550 	if (INTEL_GEN(i915) >= 11) {
1551 		int i;
1552 
1553 		uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1554 		uncore->funcs.force_wake_put = fw_domains_put;
1555 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1556 			       FORCEWAKE_RENDER_GEN9,
1557 			       FORCEWAKE_ACK_RENDER_GEN9);
1558 		fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1559 			       FORCEWAKE_BLITTER_GEN9,
1560 			       FORCEWAKE_ACK_BLITTER_GEN9);
1561 
1562 		for (i = 0; i < I915_MAX_VCS; i++) {
1563 			if (!HAS_ENGINE(i915, _VCS(i)))
1564 				continue;
1565 
1566 			fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1567 				       FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1568 				       FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1569 		}
1570 		for (i = 0; i < I915_MAX_VECS; i++) {
1571 			if (!HAS_ENGINE(i915, _VECS(i)))
1572 				continue;
1573 
1574 			fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1575 				       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1576 				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1577 		}
1578 	} else if (IS_GEN_RANGE(i915, 9, 10)) {
1579 		uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1580 		uncore->funcs.force_wake_put = fw_domains_put;
1581 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1582 			       FORCEWAKE_RENDER_GEN9,
1583 			       FORCEWAKE_ACK_RENDER_GEN9);
1584 		fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1585 			       FORCEWAKE_BLITTER_GEN9,
1586 			       FORCEWAKE_ACK_BLITTER_GEN9);
1587 		fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1588 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1589 	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1590 		uncore->funcs.force_wake_get = fw_domains_get;
1591 		uncore->funcs.force_wake_put = fw_domains_put;
1592 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1593 			       FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1594 		fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1595 			       FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1596 	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1597 		uncore->funcs.force_wake_get =
1598 			fw_domains_get_with_thread_status;
1599 		uncore->funcs.force_wake_put = fw_domains_put;
1600 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1601 			       FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1602 	} else if (IS_IVYBRIDGE(i915)) {
1603 		u32 ecobus;
1604 
1605 		/* IVB configs may use multi-threaded forcewake */
1606 
1607 		/* A small trick here - if the bios hasn't configured
1608 		 * MT forcewake, and if the device is in RC6, then
1609 		 * force_wake_mt_get will not wake the device and the
1610 		 * ECOBUS read will return zero. Which will be
1611 		 * (correctly) interpreted by the test below as MT
1612 		 * forcewake being disabled.
1613 		 */
1614 		uncore->funcs.force_wake_get =
1615 			fw_domains_get_with_thread_status;
1616 		uncore->funcs.force_wake_put = fw_domains_put;
1617 
1618 		/* We need to init first for ECOBUS access and then
1619 		 * determine later if we want to reinit, in case of MT access is
1620 		 * not working. In this stage we don't know which flavour this
1621 		 * ivb is, so it is better to reset also the gen6 fw registers
1622 		 * before the ecobus check.
1623 		 */
1624 
1625 		__raw_uncore_write32(uncore, FORCEWAKE, 0);
1626 		__raw_posting_read(uncore, ECOBUS);
1627 
1628 		ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1629 				       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1630 		if (ret)
1631 			goto out;
1632 
1633 		spin_lock_irq(&uncore->lock);
1634 		fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1635 		ecobus = __raw_uncore_read32(uncore, ECOBUS);
1636 		fw_domains_put(uncore, FORCEWAKE_RENDER);
1637 		spin_unlock_irq(&uncore->lock);
1638 
1639 		if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1640 			drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1641 			drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1642 			fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1643 			fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1644 				       FORCEWAKE, FORCEWAKE_ACK);
1645 		}
1646 	} else if (IS_GEN(i915, 6)) {
1647 		uncore->funcs.force_wake_get =
1648 			fw_domains_get_with_thread_status;
1649 		uncore->funcs.force_wake_put = fw_domains_put;
1650 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1651 			       FORCEWAKE, FORCEWAKE_ACK);
1652 	}
1653 
1654 #undef fw_domain_init
1655 
1656 	/* All future platforms are expected to require complex power gating */
1657 	WARN_ON(!ret && uncore->fw_domains == 0);
1658 
1659 out:
1660 	if (ret)
1661 		intel_uncore_fw_domains_fini(uncore);
1662 
1663 	return ret;
1664 }
1665 
1666 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1667 { \
1668 	(uncore)->fw_domains_table = \
1669 			(const struct intel_forcewake_range *)(d); \
1670 	(uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1671 }
1672 
i915_pmic_bus_access_notifier(struct notifier_block * nb,unsigned long action,void * data)1673 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1674 					 unsigned long action, void *data)
1675 {
1676 	struct intel_uncore *uncore = container_of(nb,
1677 			struct intel_uncore, pmic_bus_access_nb);
1678 
1679 	switch (action) {
1680 	case MBI_PMIC_BUS_ACCESS_BEGIN:
1681 		/*
1682 		 * forcewake all now to make sure that we don't need to do a
1683 		 * forcewake later which on systems where this notifier gets
1684 		 * called requires the punit to access to the shared pmic i2c
1685 		 * bus, which will be busy after this notification, leading to:
1686 		 * "render: timed out waiting for forcewake ack request."
1687 		 * errors.
1688 		 *
1689 		 * The notifier is unregistered during intel_runtime_suspend(),
1690 		 * so it's ok to access the HW here without holding a RPM
1691 		 * wake reference -> disable wakeref asserts for the time of
1692 		 * the access.
1693 		 */
1694 		disable_rpm_wakeref_asserts(uncore->rpm);
1695 		intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1696 		enable_rpm_wakeref_asserts(uncore->rpm);
1697 		break;
1698 	case MBI_PMIC_BUS_ACCESS_END:
1699 		intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1700 		break;
1701 	}
1702 
1703 	return NOTIFY_OK;
1704 }
1705 
uncore_mmio_setup(struct intel_uncore * uncore)1706 static int uncore_mmio_setup(struct intel_uncore *uncore)
1707 {
1708 	struct drm_i915_private *i915 = uncore->i915;
1709 	struct pci_dev *pdev = i915->drm.pdev;
1710 	int mmio_bar;
1711 	int mmio_size;
1712 
1713 	mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1714 	/*
1715 	 * Before gen4, the registers and the GTT are behind different BARs.
1716 	 * However, from gen4 onwards, the registers and the GTT are shared
1717 	 * in the same BAR, so we want to restrict this ioremap from
1718 	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1719 	 * the register BAR remains the same size for all the earlier
1720 	 * generations up to Ironlake.
1721 	 */
1722 	if (INTEL_GEN(i915) < 5)
1723 		mmio_size = 512 * 1024;
1724 	else
1725 		mmio_size = 2 * 1024 * 1024;
1726 	uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1727 #ifdef __NetBSD__
1728 	if (uncore->regs) {
1729 		KASSERT(pdev->pd_resources[mmio_bar].mapped);
1730 		uncore->regs_bst = pdev->pd_resources[mmio_bar].bst;
1731 		uncore->regs_bsh = pdev->pd_resources[mmio_bar].bsh;
1732 	} else if (agp_i810_borrow(pdev->pd_resources[mmio_bar].addr,
1733 		mmio_size, &uncore->regs_bsh)) {
1734 		KASSERT(!pdev->pd_resources[mmio_bar].mapped);
1735 		uncore->regs_bst = pdev->pd_pa.pa_memt;
1736 		uncore->regs = bus_space_vaddr(pdev->pd_pa.pa_memt,
1737 		    uncore->regs_bsh);
1738 	}
1739 #endif
1740 	if (uncore->regs == NULL) {
1741 		drm_err(&i915->drm, "failed to map registers\n");
1742 		return -EIO;
1743 	}
1744 
1745 	return 0;
1746 }
1747 
uncore_mmio_cleanup(struct intel_uncore * uncore)1748 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1749 {
1750 	struct pci_dev *pdev = uncore->i915->drm.pdev;
1751 
1752 	pci_iounmap(pdev, uncore->regs);
1753 }
1754 
intel_uncore_init_early(struct intel_uncore * uncore,struct drm_i915_private * i915)1755 void intel_uncore_init_early(struct intel_uncore *uncore,
1756 			     struct drm_i915_private *i915)
1757 {
1758 	spin_lock_init(&uncore->lock);
1759 	uncore->i915 = i915;
1760 	uncore->rpm = &i915->runtime_pm;
1761 	uncore->debug = &i915->mmio_debug;
1762 }
1763 
intel_uncore_fini_early(struct intel_uncore * uncore,struct drm_i915_private * i915)1764 void intel_uncore_fini_early(struct intel_uncore *uncore,
1765 			     struct drm_i915_private *i915)
1766 {
1767 	spin_lock_init(&uncore->lock);
1768 }
1769 
uncore_raw_init(struct intel_uncore * uncore)1770 static void uncore_raw_init(struct intel_uncore *uncore)
1771 {
1772 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
1773 
1774 	if (IS_GEN(uncore->i915, 5)) {
1775 		ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
1776 		ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
1777 	} else {
1778 		ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
1779 		ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
1780 	}
1781 }
1782 
uncore_forcewake_init(struct intel_uncore * uncore)1783 static int uncore_forcewake_init(struct intel_uncore *uncore)
1784 {
1785 	struct drm_i915_private *i915 = uncore->i915;
1786 	int ret;
1787 
1788 	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1789 
1790 	ret = intel_uncore_fw_domains_init(uncore);
1791 	if (ret)
1792 		return ret;
1793 	forcewake_early_sanitize(uncore, 0);
1794 
1795 	if (IS_GEN_RANGE(i915, 6, 7)) {
1796 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1797 
1798 		if (IS_VALLEYVIEW(i915)) {
1799 			ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1800 			ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1801 		} else {
1802 			ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1803 		}
1804 	} else if (IS_GEN(i915, 8)) {
1805 		if (IS_CHERRYVIEW(i915)) {
1806 			ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1807 			ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1808 			ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1809 		} else {
1810 			ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1811 			ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1812 		}
1813 	} else if (IS_GEN_RANGE(i915, 9, 10)) {
1814 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1815 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1816 		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1817 	} else if (IS_GEN(i915, 11)) {
1818 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1819 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1820 		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1821 	} else {
1822 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
1823 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
1824 		ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
1825 	}
1826 
1827 	uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
1828 	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1829 
1830 	return 0;
1831 }
1832 
intel_uncore_init_mmio(struct intel_uncore * uncore)1833 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1834 {
1835 	struct drm_i915_private *i915 = uncore->i915;
1836 	int ret;
1837 
1838 	ret = uncore_mmio_setup(uncore);
1839 	if (ret)
1840 		return ret;
1841 
1842 	if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1843 		uncore->flags |= UNCORE_HAS_FORCEWAKE;
1844 
1845 	if (!intel_uncore_has_forcewake(uncore)) {
1846 		uncore_raw_init(uncore);
1847 	} else {
1848 		ret = uncore_forcewake_init(uncore);
1849 		if (ret)
1850 			goto out_mmio_cleanup;
1851 	}
1852 
1853 	/* make sure fw funcs are set if and only if we have fw*/
1854 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
1855 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
1856 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
1857 	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
1858 
1859 	if (HAS_FPGA_DBG_UNCLAIMED(i915))
1860 		uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1861 
1862 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1863 		uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1864 
1865 	if (IS_GEN_RANGE(i915, 6, 7))
1866 		uncore->flags |= UNCORE_HAS_FIFO;
1867 
1868 	/* clear out unclaimed reg detection bit */
1869 	if (intel_uncore_unclaimed_mmio(uncore))
1870 		drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
1871 
1872 	return 0;
1873 
1874 out_mmio_cleanup:
1875 	uncore_mmio_cleanup(uncore);
1876 
1877 	return ret;
1878 }
1879 
1880 /*
1881  * We might have detected that some engines are fused off after we initialized
1882  * the forcewake domains. Prune them, to make sure they only reference existing
1883  * engines.
1884  */
intel_uncore_prune_mmio_domains(struct intel_uncore * uncore)1885 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
1886 {
1887 	struct drm_i915_private *i915 = uncore->i915;
1888 	enum forcewake_domains fw_domains = uncore->fw_domains;
1889 	enum forcewake_domain_id domain_id;
1890 	int i;
1891 
1892 	if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
1893 		return;
1894 
1895 	for (i = 0; i < I915_MAX_VCS; i++) {
1896 		domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1897 
1898 		if (HAS_ENGINE(i915, _VCS(i)))
1899 			continue;
1900 
1901 		if (fw_domains & BIT(domain_id))
1902 			fw_domain_fini(uncore, domain_id);
1903 	}
1904 
1905 	for (i = 0; i < I915_MAX_VECS; i++) {
1906 		domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1907 
1908 		if (HAS_ENGINE(i915, _VECS(i)))
1909 			continue;
1910 
1911 		if (fw_domains & BIT(domain_id))
1912 			fw_domain_fini(uncore, domain_id);
1913 	}
1914 }
1915 
intel_uncore_fini_mmio(struct intel_uncore * uncore)1916 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1917 {
1918 	if (intel_uncore_has_forcewake(uncore)) {
1919 		iosf_mbi_punit_acquire();
1920 		iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1921 			&uncore->pmic_bus_access_nb);
1922 		intel_uncore_forcewake_reset(uncore);
1923 		intel_uncore_fw_domains_fini(uncore);
1924 		iosf_mbi_punit_release();
1925 	}
1926 
1927 	uncore_mmio_cleanup(uncore);
1928 }
1929 
1930 static const struct reg_whitelist {
1931 	i915_reg_t offset_ldw;
1932 	i915_reg_t offset_udw;
1933 	u16 gen_mask;
1934 	u8 size;
1935 } reg_read_whitelist[] = { {
1936 	.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1937 	.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1938 	.gen_mask = INTEL_GEN_MASK(4, 12),
1939 	.size = 8
1940 } };
1941 
i915_reg_read_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1942 int i915_reg_read_ioctl(struct drm_device *dev,
1943 			void *data, struct drm_file *file)
1944 {
1945 	struct drm_i915_private *i915 = to_i915(dev);
1946 	struct intel_uncore *uncore = &i915->uncore;
1947 	struct drm_i915_reg_read *reg = data;
1948 	struct reg_whitelist const *entry;
1949 	intel_wakeref_t wakeref;
1950 	unsigned int flags;
1951 	int remain;
1952 	int ret = 0;
1953 
1954 	entry = reg_read_whitelist;
1955 	remain = ARRAY_SIZE(reg_read_whitelist);
1956 	while (remain) {
1957 		u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1958 
1959 		GEM_BUG_ON(!is_power_of_2(entry->size));
1960 		GEM_BUG_ON(entry->size > 8);
1961 		GEM_BUG_ON(entry_offset & (entry->size - 1));
1962 
1963 		if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
1964 		    entry_offset == (reg->offset & -entry->size))
1965 			break;
1966 		entry++;
1967 		remain--;
1968 	}
1969 
1970 	if (!remain)
1971 		return -EINVAL;
1972 
1973 	flags = reg->offset & (entry->size - 1);
1974 
1975 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
1976 		if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1977 			reg->val = intel_uncore_read64_2x32(uncore,
1978 							    entry->offset_ldw,
1979 							    entry->offset_udw);
1980 		else if (entry->size == 8 && flags == 0)
1981 			reg->val = intel_uncore_read64(uncore,
1982 						       entry->offset_ldw);
1983 		else if (entry->size == 4 && flags == 0)
1984 			reg->val = intel_uncore_read(uncore, entry->offset_ldw);
1985 		else if (entry->size == 2 && flags == 0)
1986 			reg->val = intel_uncore_read16(uncore,
1987 						       entry->offset_ldw);
1988 		else if (entry->size == 1 && flags == 0)
1989 			reg->val = intel_uncore_read8(uncore,
1990 						      entry->offset_ldw);
1991 		else
1992 			ret = -EINVAL;
1993 	}
1994 
1995 	return ret;
1996 }
1997 
1998 /**
1999  * __intel_wait_for_register_fw - wait until register matches expected state
2000  * @uncore: the struct intel_uncore
2001  * @reg: the register to read
2002  * @mask: mask to apply to register value
2003  * @value: expected value
2004  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2005  * @slow_timeout_ms: slow timeout in millisecond
2006  * @out_value: optional placeholder to hold registry value
2007  *
2008  * This routine waits until the target register @reg contains the expected
2009  * @value after applying the @mask, i.e. it waits until ::
2010  *
2011  *     (I915_READ_FW(reg) & mask) == value
2012  *
2013  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2014  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2015  * must be not larger than 20,0000 microseconds.
2016  *
2017  * Note that this routine assumes the caller holds forcewake asserted, it is
2018  * not suitable for very long waits. See intel_wait_for_register() if you
2019  * wish to wait without holding forcewake for the duration (i.e. you expect
2020  * the wait to be slow).
2021  *
2022  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2023  */
__intel_wait_for_register_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us,unsigned int slow_timeout_ms,u32 * out_value)2024 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2025 				 i915_reg_t reg,
2026 				 u32 mask,
2027 				 u32 value,
2028 				 unsigned int fast_timeout_us,
2029 				 unsigned int slow_timeout_ms,
2030 				 u32 *out_value)
2031 {
2032 	u32 uninitialized_var(reg_value);
2033 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2034 	int ret;
2035 
2036 	/* Catch any overuse of this function */
2037 	might_sleep_if(slow_timeout_ms);
2038 	GEM_BUG_ON(fast_timeout_us > 20000);
2039 
2040 	ret = -ETIMEDOUT;
2041 	if (fast_timeout_us && fast_timeout_us <= 20000)
2042 		ret = _wait_for_atomic(done, fast_timeout_us, 0);
2043 	if (ret && slow_timeout_ms)
2044 		ret = wait_for(done, slow_timeout_ms);
2045 
2046 	if (out_value)
2047 		*out_value = reg_value;
2048 
2049 	return ret;
2050 #undef done
2051 }
2052 
2053 /**
2054  * __intel_wait_for_register - wait until register matches expected state
2055  * @uncore: the struct intel_uncore
2056  * @reg: the register to read
2057  * @mask: mask to apply to register value
2058  * @value: expected value
2059  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2060  * @slow_timeout_ms: slow timeout in millisecond
2061  * @out_value: optional placeholder to hold registry value
2062  *
2063  * This routine waits until the target register @reg contains the expected
2064  * @value after applying the @mask, i.e. it waits until ::
2065  *
2066  *     (I915_READ(reg) & mask) == value
2067  *
2068  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2069  *
2070  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2071  */
__intel_wait_for_register(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us,unsigned int slow_timeout_ms,u32 * out_value)2072 int __intel_wait_for_register(struct intel_uncore *uncore,
2073 			      i915_reg_t reg,
2074 			      u32 mask,
2075 			      u32 value,
2076 			      unsigned int fast_timeout_us,
2077 			      unsigned int slow_timeout_ms,
2078 			      u32 *out_value)
2079 {
2080 	unsigned fw =
2081 		intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2082 	u32 reg_value;
2083 	int ret;
2084 
2085 	might_sleep_if(slow_timeout_ms);
2086 
2087 	spin_lock_irq(&uncore->lock);
2088 	intel_uncore_forcewake_get__locked(uncore, fw);
2089 
2090 	ret = __intel_wait_for_register_fw(uncore,
2091 					   reg, mask, value,
2092 					   fast_timeout_us, 0, &reg_value);
2093 
2094 	intel_uncore_forcewake_put__locked(uncore, fw);
2095 	spin_unlock_irq(&uncore->lock);
2096 
2097 	if (ret && slow_timeout_ms)
2098 		ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2099 								       reg),
2100 				 (reg_value & mask) == value,
2101 				 slow_timeout_ms * 1000, 10, 1000);
2102 
2103 	/* just trace the final value */
2104 	trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2105 
2106 	if (out_value)
2107 		*out_value = reg_value;
2108 
2109 	return ret;
2110 }
2111 
intel_uncore_unclaimed_mmio(struct intel_uncore * uncore)2112 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2113 {
2114 	bool ret;
2115 
2116 	spin_lock_irq(&uncore->debug->lock);
2117 	ret = check_for_unclaimed_mmio(uncore);
2118 	spin_unlock_irq(&uncore->debug->lock);
2119 
2120 	return ret;
2121 }
2122 
2123 bool
intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore * uncore)2124 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2125 {
2126 	bool ret = false;
2127 
2128 	spin_lock_irq(&uncore->debug->lock);
2129 
2130 	if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2131 		goto out;
2132 
2133 	if (unlikely(check_for_unclaimed_mmio(uncore))) {
2134 		if (!i915_modparams.mmio_debug) {
2135 			drm_dbg(&uncore->i915->drm,
2136 				"Unclaimed register detected, "
2137 				"enabling oneshot unclaimed register reporting. "
2138 				"Please use i915.mmio_debug=N for more information.\n");
2139 			i915_modparams.mmio_debug++;
2140 		}
2141 		uncore->debug->unclaimed_mmio_check--;
2142 		ret = true;
2143 	}
2144 
2145 out:
2146 	spin_unlock_irq(&uncore->debug->lock);
2147 
2148 	return ret;
2149 }
2150 
2151 /**
2152  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2153  * 				    a register
2154  * @uncore: pointer to struct intel_uncore
2155  * @reg: register in question
2156  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2157  *
2158  * Returns a set of forcewake domains required to be taken with for example
2159  * intel_uncore_forcewake_get for the specified register to be accessible in the
2160  * specified mode (read, write or read/write) with raw mmio accessors.
2161  *
2162  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2163  * callers to do FIFO management on their own or risk losing writes.
2164  */
2165 enum forcewake_domains
intel_uncore_forcewake_for_reg(struct intel_uncore * uncore,i915_reg_t reg,unsigned int op)2166 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2167 			       i915_reg_t reg, unsigned int op)
2168 {
2169 	enum forcewake_domains fw_domains = 0;
2170 
2171 	WARN_ON(!op);
2172 
2173 	if (!intel_uncore_has_forcewake(uncore))
2174 		return 0;
2175 
2176 	if (op & FW_REG_READ)
2177 		fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2178 
2179 	if (op & FW_REG_WRITE)
2180 		fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2181 
2182 	WARN_ON(fw_domains & ~uncore->fw_domains);
2183 
2184 	return fw_domains;
2185 }
2186 
2187 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2188 #include "selftests/mock_uncore.c"
2189 #include "selftests/intel_uncore.c"
2190 #endif
2191