xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/intel_gmbus.c (revision 2e4b9c494f00e69f213474fcb4b5613654d58f4f)
1 /*	$NetBSD: intel_gmbus.c,v 1.7 2022/05/22 21:18:12 riastradh Exp $	*/
2 
3 /*
4  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
5  * Copyright © 2006-2008,2010 Intel Corporation
6  *   Jesse Barnes <jesse.barnes@intel.com>
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *	Eric Anholt <eric@anholt.net>
29  *	Chris Wilson <chris@chris-wilson.co.uk>
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: intel_gmbus.c,v 1.7 2022/05/22 21:18:12 riastradh Exp $");
34 
35 #include <linux/export.h>
36 #include <linux/i2c-algo-bit.h>
37 #include <linux/i2c.h>
38 
39 #include <drm/drm_hdcp.h>
40 #include <drm/i915_drm.h>
41 
42 #include "i915_drv.h"
43 #include "intel_display_types.h"
44 #include "intel_gmbus.h"
45 
46 #include <linux/nbsd-namespace.h>
47 
48 struct gmbus_pin {
49 	const char *name;
50 	enum i915_gpio gpio;
51 };
52 
53 /* Map gmbus pin pairs to names and registers. */
54 static const struct gmbus_pin gmbus_pins[] = {
55 	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
56 	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
57 	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
58 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
59 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
60 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
61 };
62 
63 static const struct gmbus_pin gmbus_pins_bdw[] = {
64 	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
65 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
66 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
67 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
68 };
69 
70 static const struct gmbus_pin gmbus_pins_skl[] = {
71 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
72 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
73 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
74 };
75 
76 static const struct gmbus_pin gmbus_pins_bxt[] = {
77 	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
78 	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
79 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
80 };
81 
82 static const struct gmbus_pin gmbus_pins_cnp[] = {
83 	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
84 	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
85 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
86 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
87 };
88 
89 static const struct gmbus_pin gmbus_pins_icp[] = {
90 	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
91 	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
92 	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
93 	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
94 	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
95 	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
96 	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
97 	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
98 	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
99 };
100 
101 /* pin is expected to be valid */
get_gmbus_pin(struct drm_i915_private * dev_priv,unsigned int pin)102 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
103 					     unsigned int pin)
104 {
105 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
106 		return &gmbus_pins_icp[pin];
107 	else if (HAS_PCH_CNP(dev_priv))
108 		return &gmbus_pins_cnp[pin];
109 	else if (IS_GEN9_LP(dev_priv))
110 		return &gmbus_pins_bxt[pin];
111 	else if (IS_GEN9_BC(dev_priv))
112 		return &gmbus_pins_skl[pin];
113 	else if (IS_BROADWELL(dev_priv))
114 		return &gmbus_pins_bdw[pin];
115 	else
116 		return &gmbus_pins[pin];
117 }
118 
intel_gmbus_is_valid_pin(struct drm_i915_private * dev_priv,unsigned int pin)119 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
120 			      unsigned int pin)
121 {
122 	unsigned int size;
123 
124 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
125 		size = ARRAY_SIZE(gmbus_pins_icp);
126 	else if (HAS_PCH_CNP(dev_priv))
127 		size = ARRAY_SIZE(gmbus_pins_cnp);
128 	else if (IS_GEN9_LP(dev_priv))
129 		size = ARRAY_SIZE(gmbus_pins_bxt);
130 	else if (IS_GEN9_BC(dev_priv))
131 		size = ARRAY_SIZE(gmbus_pins_skl);
132 	else if (IS_BROADWELL(dev_priv))
133 		size = ARRAY_SIZE(gmbus_pins_bdw);
134 	else
135 		size = ARRAY_SIZE(gmbus_pins);
136 
137 	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
138 }
139 
140 /* Intel GPIO access functions */
141 
142 #define I2C_RISEFALL_TIME 10
143 
144 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)145 to_intel_gmbus(struct i2c_adapter *i2c)
146 {
147 	return container_of(i2c, struct intel_gmbus, adapter);
148 }
149 
150 void
intel_gmbus_reset(struct drm_i915_private * dev_priv)151 intel_gmbus_reset(struct drm_i915_private *dev_priv)
152 {
153 	I915_WRITE(GMBUS0, 0);
154 	I915_WRITE(GMBUS4, 0);
155 }
156 
pnv_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)157 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
158 				   bool enable)
159 {
160 	u32 val;
161 
162 	/* When using bit bashing for I2C, this bit needs to be set to 1 */
163 	val = I915_READ(DSPCLK_GATE_D);
164 	if (!enable)
165 		val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
166 	else
167 		val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
168 	I915_WRITE(DSPCLK_GATE_D, val);
169 }
170 
pch_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)171 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
172 				   bool enable)
173 {
174 	u32 val;
175 
176 	val = I915_READ(SOUTH_DSPCLK_GATE_D);
177 	if (!enable)
178 		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
179 	else
180 		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
181 	I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
182 }
183 
bxt_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)184 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
185 				   bool enable)
186 {
187 	u32 val;
188 
189 	val = I915_READ(GEN9_CLKGATE_DIS_4);
190 	if (!enable)
191 		val |= BXT_GMBUS_GATING_DIS;
192 	else
193 		val &= ~BXT_GMBUS_GATING_DIS;
194 	I915_WRITE(GEN9_CLKGATE_DIS_4, val);
195 }
196 
get_reserved(struct intel_gmbus * bus)197 static u32 get_reserved(struct intel_gmbus *bus)
198 {
199 	struct drm_i915_private *i915 = bus->dev_priv;
200 	struct intel_uncore *uncore = &i915->uncore;
201 	u32 reserved = 0;
202 
203 	/* On most chips, these bits must be preserved in software. */
204 	if (!IS_I830(i915) && !IS_I845G(i915))
205 		reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
206 			   (GPIO_DATA_PULLUP_DISABLE |
207 			    GPIO_CLOCK_PULLUP_DISABLE);
208 
209 	return reserved;
210 }
211 
get_clock(void * data)212 static int get_clock(void *data)
213 {
214 	struct intel_gmbus *bus = data;
215 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
216 	u32 reserved = get_reserved(bus);
217 
218 	intel_uncore_write_notrace(uncore,
219 				   bus->gpio_reg,
220 				   reserved | GPIO_CLOCK_DIR_MASK);
221 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
222 
223 	return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
224 		GPIO_CLOCK_VAL_IN) != 0;
225 }
226 
get_data(void * data)227 static int get_data(void *data)
228 {
229 	struct intel_gmbus *bus = data;
230 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
231 	u32 reserved = get_reserved(bus);
232 
233 	intel_uncore_write_notrace(uncore,
234 				   bus->gpio_reg,
235 				   reserved | GPIO_DATA_DIR_MASK);
236 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
237 
238 	return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
239 		GPIO_DATA_VAL_IN) != 0;
240 }
241 
set_clock(void * data,int state_high)242 static void set_clock(void *data, int state_high)
243 {
244 	struct intel_gmbus *bus = data;
245 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
246 	u32 reserved = get_reserved(bus);
247 	u32 clock_bits;
248 
249 	if (state_high)
250 		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
251 	else
252 		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
253 			     GPIO_CLOCK_VAL_MASK;
254 
255 	intel_uncore_write_notrace(uncore,
256 				   bus->gpio_reg,
257 				   reserved | clock_bits);
258 	intel_uncore_posting_read(uncore, bus->gpio_reg);
259 }
260 
set_data(void * data,int state_high)261 static void set_data(void *data, int state_high)
262 {
263 	struct intel_gmbus *bus = data;
264 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
265 	u32 reserved = get_reserved(bus);
266 	u32 data_bits;
267 
268 	if (state_high)
269 		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
270 	else
271 		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
272 			GPIO_DATA_VAL_MASK;
273 
274 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
275 	intel_uncore_posting_read(uncore, bus->gpio_reg);
276 }
277 
278 static int
intel_gpio_pre_xfer(struct i2c_adapter * adapter)279 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
280 {
281 	struct intel_gmbus *bus = container_of(adapter,
282 					       struct intel_gmbus,
283 					       adapter);
284 	struct drm_i915_private *dev_priv = bus->dev_priv;
285 
286 	intel_gmbus_reset(dev_priv);
287 
288 	if (IS_PINEVIEW(dev_priv))
289 		pnv_gmbus_clock_gating(dev_priv, false);
290 
291 	set_data(bus, 1);
292 	set_clock(bus, 1);
293 	udelay(I2C_RISEFALL_TIME);
294 	return 0;
295 }
296 
297 static void
intel_gpio_post_xfer(struct i2c_adapter * adapter)298 intel_gpio_post_xfer(struct i2c_adapter *adapter)
299 {
300 	struct intel_gmbus *bus = container_of(adapter,
301 					       struct intel_gmbus,
302 					       adapter);
303 	struct drm_i915_private *dev_priv = bus->dev_priv;
304 
305 	set_data(bus, 1);
306 	set_clock(bus, 1);
307 
308 	if (IS_PINEVIEW(dev_priv))
309 		pnv_gmbus_clock_gating(dev_priv, true);
310 }
311 
312 static void
intel_gpio_setup(struct intel_gmbus * bus,unsigned int pin)313 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
314 {
315 	struct drm_i915_private *dev_priv = bus->dev_priv;
316 	struct i2c_algo_bit_data *algo;
317 
318 	algo = &bus->bit_algo;
319 
320 	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
321 	bus->adapter.algo_data = algo;
322 	algo->setsda = set_data;
323 	algo->setscl = set_clock;
324 	algo->getsda = get_data;
325 	algo->getscl = get_clock;
326 	algo->pre_xfer = intel_gpio_pre_xfer;
327 	algo->post_xfer = intel_gpio_post_xfer;
328 	algo->udelay = I2C_RISEFALL_TIME;
329 	algo->timeout = usecs_to_jiffies(2200);
330 	algo->data = bus;
331 }
332 
gmbus_wait(struct drm_i915_private * dev_priv,u32 status,u32 irq_en)333 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
334 {
335 	u32 gmbus2;
336 	int ret;
337 
338 	/* Important: The hw handles only the first bit, so set only one! Since
339 	 * we also need to check for NAKs besides the hw ready/idle signal, we
340 	 * need to wake up periodically and check that ourselves.
341 	 */
342 	if (!HAS_GMBUS_IRQ(dev_priv))
343 		irq_en = 0;
344 #ifdef __NetBSD__
345 	if (cold)
346 		irq_en = 0;
347 #endif
348 
349 	spin_lock(&dev_priv->gmbus_wait_lock);
350 	I915_WRITE_FW(GMBUS4, irq_en);
351 
352 	status |= GMBUS_SATOER;
353 	if (!irq_en) {
354 		unsigned timeout = 50*1000;
355 
356 		ret = 0;
357 		while (((gmbus2 = intel_uncore_read_fw(&dev_priv->uncore,
358 				GMBUS2)) & status) == 0) {
359 			if (--timeout == 0) {
360 				ret = -ETIMEDOUT;
361 				break;
362 			}
363 			udelay(1);
364 		}
365 	} else {
366 		DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
367 		    &dev_priv->gmbus_wait_queue,
368 		    &dev_priv->gmbus_wait_lock,
369 		    msecs_to_jiffies_timeout(50),
370 		    (((gmbus2 = intel_uncore_read_fw(&dev_priv->uncore,
371 				GMBUS2))
372 			    & status)
373 			!= 0));
374 		/*
375 		 * After DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL, ret<0 on
376 		 * error (-ERESTARTSYS, interrupt), ret=0 on timeout,
377 		 * ret>0 on success (time remaining).
378 		 *
379 		 * We want ret=-ETIMEDOUT on timeout and ret=0 on
380 		 * success.
381 		 */
382 		if (ret < 0) {
383 			/* error */
384 		} else if (ret == 0) {
385 			ret = -ETIMEDOUT;
386 		} else {
387 			ret = 0;
388 		}
389 	}
390 
391 	I915_WRITE_FW(GMBUS4, 0);
392 	spin_unlock(&dev_priv->gmbus_wait_lock);
393 
394 	if (gmbus2 & GMBUS_SATOER)
395 		return -ENXIO;
396 
397 	return ret;
398 }
399 
400 static int
gmbus_wait_idle(struct drm_i915_private * dev_priv)401 gmbus_wait_idle(struct drm_i915_private *dev_priv)
402 {
403 	u32 irq_enable;
404 	int ret;
405 
406 	/* Important: The hw handles only the first bit, so set only one! */
407 	irq_enable = 0;
408 	if (HAS_GMBUS_IRQ(dev_priv))
409 		irq_enable = GMBUS_IDLE_EN;
410 #ifdef __NetBSD__
411 	if (cold)
412 		irq_enable = 0;
413 #endif
414 
415 	spin_lock(&dev_priv->gmbus_wait_lock);
416 	I915_WRITE_FW(GMBUS4, irq_enable);
417 
418 	if (!irq_enable) {
419 		unsigned timeout = 10*1000;
420 
421 		ret = 0;
422 		while (intel_uncore_read_fw(&dev_priv->uncore, GMBUS2)
423 		    & GMBUS_ACTIVE) {
424 			if (--timeout == 0) {
425 				ret = -ETIMEDOUT;
426 				break;
427 			}
428 			udelay(1);
429 		}
430 	} else {
431 		DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
432 		    &dev_priv->gmbus_wait_queue,
433 		    &dev_priv->gmbus_wait_lock,
434 		    msecs_to_jiffies_timeout(10),
435 		    ((intel_uncore_read_fw(&dev_priv->uncore, GMBUS2)
436 			    & GMBUS_ACTIVE)
437 			== 0));
438 		/*
439 		 * After DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL, ret<0 on
440 		 * error (-ERESTARTSYS, interrupt), ret=0 on timeout,
441 		 * ret>0 on success (time remaining).
442 		 *
443 		 * We want ret=-ETIMEDOUT on timeout and ret=0 on
444 		 * success.
445 		 */
446 		if (ret < 0) {
447 			/* error */
448 		} else if (ret == 0) {
449 			ret = -ETIMEDOUT;
450 		} else {
451 			ret = 0;
452 		}
453 	}
454 
455 	I915_WRITE_FW(GMBUS4, 0);
456 	spin_unlock(&dev_priv->gmbus_wait_lock);
457 
458 	return ret;
459 }
460 
461 static inline
gmbus_max_xfer_size(struct drm_i915_private * dev_priv)462 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
463 {
464 	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
465 	       GMBUS_BYTE_COUNT_MAX;
466 }
467 
468 static int
gmbus_xfer_read_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus0_reg,u32 gmbus1_index)469 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
470 		      unsigned short addr, u8 *buf, unsigned int len,
471 		      u32 gmbus0_reg, u32 gmbus1_index)
472 {
473 	unsigned int size = len;
474 	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
475 	bool extra_byte_added = false;
476 
477 	if (burst_read) {
478 		/*
479 		 * As per HW Spec, for 512Bytes need to read extra Byte and
480 		 * Ignore the extra byte read.
481 		 */
482 		if (len == 512) {
483 			extra_byte_added = true;
484 			len++;
485 		}
486 		size = len % 256 + 256;
487 		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
488 	}
489 
490 	I915_WRITE_FW(GMBUS1,
491 		      gmbus1_index |
492 		      GMBUS_CYCLE_WAIT |
493 		      (size << GMBUS_BYTE_COUNT_SHIFT) |
494 		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
495 		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
496 	while (len) {
497 		int ret;
498 		u32 val, loop = 0;
499 
500 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
501 		if (ret)
502 			return ret;
503 
504 		val = I915_READ_FW(GMBUS3);
505 		do {
506 			if (extra_byte_added && len == 1)
507 				break;
508 
509 			*buf++ = val & 0xff;
510 			val >>= 8;
511 		} while (--len && ++loop < 4);
512 
513 		if (burst_read && len == size - 4)
514 			/* Reset the override bit */
515 			I915_WRITE_FW(GMBUS0, gmbus0_reg);
516 	}
517 
518 	return 0;
519 }
520 
521 /*
522  * HW spec says that 512Bytes in Burst read need special treatment.
523  * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
524  * an I2C slave, which supports such a lengthy burst read too for experiments.
525  *
526  * So until things get clarified on HW support, to avoid the burst read length
527  * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
528  */
529 #define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
530 
531 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus0_reg,u32 gmbus1_index)532 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
533 		u32 gmbus0_reg, u32 gmbus1_index)
534 {
535 	u8 *buf = msg->buf;
536 	unsigned int rx_size = msg->len;
537 	unsigned int len;
538 	int ret;
539 
540 	do {
541 		if (HAS_GMBUS_BURST_READ(dev_priv))
542 			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
543 		else
544 			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
545 
546 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
547 					    gmbus0_reg, gmbus1_index);
548 		if (ret)
549 			return ret;
550 
551 		rx_size -= len;
552 		buf += len;
553 	} while (rx_size != 0);
554 
555 	return 0;
556 }
557 
558 static int
gmbus_xfer_write_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus1_index)559 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
560 		       unsigned short addr, u8 *buf, unsigned int len,
561 		       u32 gmbus1_index)
562 {
563 	unsigned int chunk_size = len;
564 	u32 val, loop;
565 
566 	val = loop = 0;
567 	while (len && loop < 4) {
568 		val |= *buf++ << (8 * loop++);
569 		len -= 1;
570 	}
571 
572 	I915_WRITE_FW(GMBUS3, val);
573 	I915_WRITE_FW(GMBUS1,
574 		      gmbus1_index | GMBUS_CYCLE_WAIT |
575 		      (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
576 		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
577 		      GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
578 	while (len) {
579 		int ret;
580 
581 		val = loop = 0;
582 		do {
583 			val |= *buf++ << (8 * loop);
584 		} while (--len && ++loop < 4);
585 
586 		I915_WRITE_FW(GMBUS3, val);
587 
588 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
589 		if (ret)
590 			return ret;
591 	}
592 
593 	return 0;
594 }
595 
596 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus1_index)597 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
598 		 u32 gmbus1_index)
599 {
600 	u8 *buf = msg->buf;
601 	unsigned int tx_size = msg->len;
602 	unsigned int len;
603 	int ret;
604 
605 	do {
606 		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
607 
608 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
609 					     gmbus1_index);
610 		if (ret)
611 			return ret;
612 
613 		buf += len;
614 		tx_size -= len;
615 	} while (tx_size != 0);
616 
617 	return 0;
618 }
619 
620 /*
621  * The gmbus controller can combine a 1 or 2 byte write with another read/write
622  * that immediately follows it by using an "INDEX" cycle.
623  */
624 static bool
gmbus_is_index_xfer(struct i2c_msg * msgs,int i,int num)625 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
626 {
627 	return (i + 1 < num &&
628 		msgs[i].addr == msgs[i + 1].addr &&
629 		!(msgs[i].flags & I2C_M_RD) &&
630 		(msgs[i].len == 1 || msgs[i].len == 2) &&
631 		msgs[i + 1].len > 0);
632 }
633 
634 static int
gmbus_index_xfer(struct drm_i915_private * dev_priv,struct i2c_msg * msgs,u32 gmbus0_reg)635 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
636 		 u32 gmbus0_reg)
637 {
638 	u32 gmbus1_index = 0;
639 	u32 gmbus5 = 0;
640 	int ret;
641 
642 	if (msgs[0].len == 2)
643 		gmbus5 = GMBUS_2BYTE_INDEX_EN |
644 			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
645 	if (msgs[0].len == 1)
646 		gmbus1_index = GMBUS_CYCLE_INDEX |
647 			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
648 
649 	/* GMBUS5 holds 16-bit index */
650 	if (gmbus5)
651 		I915_WRITE_FW(GMBUS5, gmbus5);
652 
653 	if (msgs[1].flags & I2C_M_RD)
654 		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
655 				      gmbus1_index);
656 	else
657 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
658 
659 	/* Clear GMBUS5 after each index transfer */
660 	if (gmbus5)
661 		I915_WRITE_FW(GMBUS5, 0);
662 
663 	return ret;
664 }
665 
666 static int
do_gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,u32 gmbus0_source)667 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
668 	      u32 gmbus0_source)
669 {
670 	struct intel_gmbus *bus = container_of(adapter,
671 					       struct intel_gmbus,
672 					       adapter);
673 	struct drm_i915_private *dev_priv = bus->dev_priv;
674 	int i = 0, inc, try = 0;
675 	int ret = 0;
676 
677 	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
678 	if (IS_GEN9_LP(dev_priv))
679 		bxt_gmbus_clock_gating(dev_priv, false);
680 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
681 		pch_gmbus_clock_gating(dev_priv, false);
682 
683 retry:
684 	I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
685 
686 	for (; i < num; i += inc) {
687 		inc = 1;
688 		if (gmbus_is_index_xfer(msgs, i, num)) {
689 			ret = gmbus_index_xfer(dev_priv, &msgs[i],
690 					       gmbus0_source | bus->reg0);
691 			inc = 2; /* an index transmission is two msgs */
692 		} else if (msgs[i].flags & I2C_M_RD) {
693 			ret = gmbus_xfer_read(dev_priv, &msgs[i],
694 					      gmbus0_source | bus->reg0, 0);
695 		} else {
696 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
697 		}
698 
699 		if (!ret)
700 			ret = gmbus_wait(dev_priv,
701 					 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
702 		if (ret == -ETIMEDOUT)
703 			goto timeout;
704 		else if (ret)
705 			goto clear_err;
706 	}
707 
708 	/* Generate a STOP condition on the bus. Note that gmbus can't generata
709 	 * a STOP on the very first cycle. To simplify the code we
710 	 * unconditionally generate the STOP condition with an additional gmbus
711 	 * cycle. */
712 	I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
713 
714 	/* Mark the GMBUS interface as disabled after waiting for idle.
715 	 * We will re-enable it at the start of the next xfer,
716 	 * till then let it sleep.
717 	 */
718 	if (gmbus_wait_idle(dev_priv)) {
719 		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
720 			 adapter->name);
721 		ret = -ETIMEDOUT;
722 	}
723 	I915_WRITE_FW(GMBUS0, 0);
724 	ret = ret ?: i;
725 	goto out;
726 
727 clear_err:
728 	/*
729 	 * Wait for bus to IDLE before clearing NAK.
730 	 * If we clear the NAK while bus is still active, then it will stay
731 	 * active and the next transaction may fail.
732 	 *
733 	 * If no ACK is received during the address phase of a transaction, the
734 	 * adapter must report -ENXIO. It is not clear what to return if no ACK
735 	 * is received at other times. But we have to be careful to not return
736 	 * spurious -ENXIO because that will prevent i2c and drm edid functions
737 	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
738 	 * timing out seems to happen when there _is_ a ddc chip present, but
739 	 * it's slow responding and only answers on the 2nd retry.
740 	 */
741 	ret = -ENXIO;
742 	if (gmbus_wait_idle(dev_priv)) {
743 		DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
744 			      adapter->name);
745 		ret = -ETIMEDOUT;
746 	}
747 
748 	/* Toggle the Software Clear Interrupt bit. This has the effect
749 	 * of resetting the GMBUS controller and so clearing the
750 	 * BUS_ERROR raised by the slave's NAK.
751 	 */
752 	I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
753 	I915_WRITE_FW(GMBUS1, 0);
754 	I915_WRITE_FW(GMBUS0, 0);
755 
756 	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
757 			 adapter->name, msgs[i].addr,
758 			 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
759 
760 	/*
761 	 * Passive adapters sometimes NAK the first probe. Retry the first
762 	 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
763 	 * has retries internally. See also the retry loop in
764 	 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
765 	 */
766 	if (ret == -ENXIO && i == 0 && try++ == 0) {
767 		DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
768 			      adapter->name);
769 		goto retry;
770 	}
771 
772 	goto out;
773 
774 timeout:
775 	DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
776 		      bus->adapter.name, bus->reg0 & 0xff);
777 	I915_WRITE_FW(GMBUS0, 0);
778 
779 	/*
780 	 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
781 	 * instead. Use EAGAIN to have i2c core retry.
782 	 */
783 	ret = -EAGAIN;
784 
785 out:
786 	/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
787 	if (IS_GEN9_LP(dev_priv))
788 		bxt_gmbus_clock_gating(dev_priv, true);
789 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
790 		pch_gmbus_clock_gating(dev_priv, true);
791 
792 	return ret;
793 }
794 
795 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)796 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
797 {
798 	struct intel_gmbus *bus =
799 		container_of(adapter, struct intel_gmbus, adapter);
800 	struct drm_i915_private *dev_priv = bus->dev_priv;
801 	intel_wakeref_t wakeref;
802 	int ret;
803 
804 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
805 
806 	if (bus->force_bit) {
807 		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
808 		if (ret < 0)
809 			bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
810 	} else {
811 		ret = do_gmbus_xfer(adapter, msgs, num, 0);
812 		if (ret == -EAGAIN)
813 			bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
814 	}
815 
816 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
817 
818 	return ret;
819 }
820 
intel_gmbus_output_aksv(struct i2c_adapter * adapter)821 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
822 {
823 	struct intel_gmbus *bus =
824 		container_of(adapter, struct intel_gmbus, adapter);
825 	struct drm_i915_private *dev_priv = bus->dev_priv;
826 	u8 cmd = DRM_HDCP_DDC_AKSV;
827 	u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
828 	struct i2c_msg msgs[] = {
829 		{
830 			.addr = DRM_HDCP_DDC_ADDR,
831 			.flags = 0,
832 			.len = sizeof(cmd),
833 			.buf = &cmd,
834 		},
835 		{
836 			.addr = DRM_HDCP_DDC_ADDR,
837 			.flags = 0,
838 			.len = sizeof(buf),
839 			.buf = buf,
840 		}
841 	};
842 	intel_wakeref_t wakeref;
843 	int ret;
844 
845 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
846 	mutex_lock(&dev_priv->gmbus_mutex);
847 
848 	/*
849 	 * In order to output Aksv to the receiver, use an indexed write to
850 	 * pass the i2c command, and tell GMBUS to use the HW-provided value
851 	 * instead of sourcing GMBUS3 for the data.
852 	 */
853 	ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
854 
855 	mutex_unlock(&dev_priv->gmbus_mutex);
856 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
857 
858 	return ret;
859 }
860 
gmbus_func(struct i2c_adapter * adapter)861 static u32 gmbus_func(struct i2c_adapter *adapter)
862 {
863 	return i2c_bit_algo.functionality(adapter) &
864 		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
865 		/* I2C_FUNC_10BIT_ADDR | */
866 		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
867 		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
868 }
869 
870 static const struct i2c_algorithm gmbus_algorithm = {
871 	.master_xfer	= gmbus_xfer,
872 	.functionality	= gmbus_func
873 };
874 
gmbus_lock_bus(struct i2c_adapter * adapter,unsigned int flags)875 static void gmbus_lock_bus(struct i2c_adapter *adapter,
876 			   unsigned int flags)
877 {
878 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
879 	struct drm_i915_private *dev_priv = bus->dev_priv;
880 
881 	mutex_lock(&dev_priv->gmbus_mutex);
882 }
883 
gmbus_trylock_bus(struct i2c_adapter * adapter,unsigned int flags)884 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
885 			     unsigned int flags)
886 {
887 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
888 	struct drm_i915_private *dev_priv = bus->dev_priv;
889 
890 	return mutex_trylock(&dev_priv->gmbus_mutex);
891 }
892 
gmbus_unlock_bus(struct i2c_adapter * adapter,unsigned int flags)893 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
894 			     unsigned int flags)
895 {
896 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
897 	struct drm_i915_private *dev_priv = bus->dev_priv;
898 
899 	mutex_unlock(&dev_priv->gmbus_mutex);
900 }
901 
902 static const struct i2c_lock_operations gmbus_lock_ops = {
903 	.lock_bus =    gmbus_lock_bus,
904 	.trylock_bus = gmbus_trylock_bus,
905 	.unlock_bus =  gmbus_unlock_bus,
906 };
907 
908 /**
909  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
910  * @dev_priv: i915 device private
911  */
intel_gmbus_setup(struct drm_i915_private * dev_priv)912 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
913 {
914 	struct intel_gmbus *bus;
915 	unsigned int pin;
916 	int ret;
917 
918 	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
919 		return 0;
920 
921 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
922 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
923 	else if (!HAS_GMCH(dev_priv))
924 		/*
925 		 * Broxton uses the same PCH offsets for South Display Engine,
926 		 * even though it doesn't have a PCH.
927 		 */
928 		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
929 
930 	mutex_init(&dev_priv->gmbus_mutex);
931 
932 	spin_lock_init(&dev_priv->gmbus_wait_lock);
933 	DRM_INIT_WAITQUEUE(&dev_priv->gmbus_wait_queue, "i915i2c");
934 
935 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
936 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
937 			continue;
938 
939 		bus = &dev_priv->gmbus[pin];
940 
941 		bus->adapter.owner = THIS_MODULE;
942 		bus->adapter.class = I2C_CLASS_DDC;
943 		snprintf(bus->adapter.name,
944 			 sizeof(bus->adapter.name),
945 			 "i915 gmbus %s",
946 			 get_gmbus_pin(dev_priv, pin)->name);
947 
948 		bus->adapter.dev.parent = dev_priv->drm.dev;
949 		bus->dev_priv = dev_priv;
950 
951 		bus->adapter.algo = &gmbus_algorithm;
952 		bus->adapter.lock_ops = &gmbus_lock_ops;
953 
954 		/*
955 		 * We wish to retry with bit banging
956 		 * after a timed out GMBUS attempt.
957 		 */
958 		bus->adapter.retries = 1;
959 
960 		/* By default use a conservative clock rate */
961 		bus->reg0 = pin | GMBUS_RATE_100KHZ;
962 
963 		/* gmbus seems to be broken on i830 */
964 		if (IS_I830(dev_priv))
965 			bus->force_bit = 1;
966 
967 		intel_gpio_setup(bus, pin);
968 
969 		ret = i2c_add_adapter(&bus->adapter);
970 		if (ret)
971 			goto err;
972 	}
973 
974 	intel_gmbus_reset(dev_priv);
975 
976 	return 0;
977 
978 err:
979 	while (pin--) {
980 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
981 			continue;
982 
983 		bus = &dev_priv->gmbus[pin];
984 		i2c_del_adapter(&bus->adapter);
985 	}
986 	return ret;
987 }
988 
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned int pin)989 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
990 					    unsigned int pin)
991 {
992 	if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
993 		return NULL;
994 
995 	return &dev_priv->gmbus[pin].adapter;
996 }
997 
intel_gmbus_set_speed(struct i2c_adapter * adapter,int speed)998 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
999 {
1000 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
1001 
1002 	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
1003 }
1004 
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)1005 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
1006 {
1007 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
1008 	struct drm_i915_private *dev_priv = bus->dev_priv;
1009 
1010 	mutex_lock(&dev_priv->gmbus_mutex);
1011 
1012 	bus->force_bit += force_bit ? 1 : -1;
1013 	DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
1014 		      force_bit ? "en" : "dis", adapter->name,
1015 		      bus->force_bit);
1016 
1017 	mutex_unlock(&dev_priv->gmbus_mutex);
1018 }
1019 
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)1020 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1021 {
1022 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
1023 
1024 	return bus->force_bit;
1025 }
1026 
intel_gmbus_teardown(struct drm_i915_private * dev_priv)1027 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
1028 {
1029 	struct intel_gmbus *bus;
1030 	unsigned int pin;
1031 
1032 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
1033 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
1034 			continue;
1035 
1036 		bus = &dev_priv->gmbus[pin];
1037 		i2c_del_adapter(&bus->adapter);
1038 	}
1039 
1040 	DRM_DESTROY_WAITQUEUE(&dev_priv->gmbus_wait_queue);
1041 	spin_lock_destroy(&dev_priv->gmbus_wait_lock);
1042 	mutex_destroy(&dev_priv->gmbus_mutex);
1043 }
1044