1 /* $NetBSD: intel_dp_link_training.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */
2
3 /*
4 * Copyright © 2008-2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: intel_dp_link_training.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
28
29 #include "intel_display_types.h"
30 #include "intel_dp.h"
31 #include "intel_dp_link_training.h"
32
33 static void
intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])34 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
35 {
36
37 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
38 link_status[0], link_status[1], link_status[2],
39 link_status[3], link_status[4], link_status[5]);
40 }
41
42 static void
intel_get_adjust_train(struct intel_dp * intel_dp,const u8 link_status[DP_LINK_STATUS_SIZE])43 intel_get_adjust_train(struct intel_dp *intel_dp,
44 const u8 link_status[DP_LINK_STATUS_SIZE])
45 {
46 u8 v = 0;
47 u8 p = 0;
48 int lane;
49 u8 voltage_max;
50 u8 preemph_max;
51
52 for (lane = 0; lane < intel_dp->lane_count; lane++) {
53 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
54 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
55
56 if (this_v > v)
57 v = this_v;
58 if (this_p > p)
59 p = this_p;
60 }
61
62 voltage_max = intel_dp_voltage_max(intel_dp);
63 if (v >= voltage_max)
64 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
65
66 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
67 if (p >= preemph_max)
68 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
69
70 for (lane = 0; lane < 4; lane++)
71 intel_dp->train_set[lane] = v | p;
72 }
73
74 static bool
intel_dp_set_link_train(struct intel_dp * intel_dp,u8 dp_train_pat)75 intel_dp_set_link_train(struct intel_dp *intel_dp,
76 u8 dp_train_pat)
77 {
78 u8 buf[sizeof(intel_dp->train_set) + 1];
79 int ret, len;
80
81 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
82
83 buf[0] = dp_train_pat;
84 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
85 DP_TRAINING_PATTERN_DISABLE) {
86 /* don't write DP_TRAINING_LANEx_SET on disable */
87 len = 1;
88 } else {
89 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
90 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
91 len = intel_dp->lane_count + 1;
92 }
93
94 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
95 buf, len);
96
97 return ret == len;
98 }
99
100 static bool
intel_dp_reset_link_train(struct intel_dp * intel_dp,u8 dp_train_pat)101 intel_dp_reset_link_train(struct intel_dp *intel_dp,
102 u8 dp_train_pat)
103 {
104 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
105 intel_dp_set_signal_levels(intel_dp);
106 return intel_dp_set_link_train(intel_dp, dp_train_pat);
107 }
108
109 static bool
intel_dp_update_link_train(struct intel_dp * intel_dp)110 intel_dp_update_link_train(struct intel_dp *intel_dp)
111 {
112 int ret;
113
114 intel_dp_set_signal_levels(intel_dp);
115
116 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
117 intel_dp->train_set, intel_dp->lane_count);
118
119 return ret == intel_dp->lane_count;
120 }
121
intel_dp_link_max_vswing_reached(struct intel_dp * intel_dp)122 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
123 {
124 int lane;
125
126 for (lane = 0; lane < intel_dp->lane_count; lane++)
127 if ((intel_dp->train_set[lane] &
128 DP_TRAIN_MAX_SWING_REACHED) == 0)
129 return false;
130
131 return true;
132 }
133
134 /* Enable corresponding port and start training pattern 1 */
135 static bool
intel_dp_link_training_clock_recovery(struct intel_dp * intel_dp)136 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
137 {
138 u8 voltage;
139 int voltage_tries, cr_tries, max_cr_tries;
140 bool max_vswing_reached = false;
141 u8 link_config[2];
142 u8 link_bw, rate_select;
143
144 if (intel_dp->prepare_link_retrain)
145 intel_dp->prepare_link_retrain(intel_dp);
146
147 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
148 &link_bw, &rate_select);
149
150 if (link_bw)
151 DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
152 else
153 DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
154
155 /* Write the link configuration data */
156 link_config[0] = link_bw;
157 link_config[1] = intel_dp->lane_count;
158 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
159 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
160 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
161
162 /* eDP 1.4 rate select method. */
163 if (!link_bw)
164 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
165 &rate_select, 1);
166
167 link_config[0] = 0;
168 link_config[1] = DP_SET_ANSI_8B10B;
169 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
170
171 intel_dp->DP |= DP_PORT_EN;
172
173 /* clock recovery */
174 if (!intel_dp_reset_link_train(intel_dp,
175 DP_TRAINING_PATTERN_1 |
176 DP_LINK_SCRAMBLING_DISABLE)) {
177 DRM_ERROR("failed to enable link training\n");
178 return false;
179 }
180
181 /*
182 * The DP 1.4 spec defines the max clock recovery retries value
183 * as 10 but for pre-DP 1.4 devices we set a very tolerant
184 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
185 * x 5 identical voltage retries). Since the previous specs didn't
186 * define a limit and created the possibility of an infinite loop
187 * we want to prevent any sync from triggering that corner case.
188 */
189 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
190 max_cr_tries = 10;
191 else
192 max_cr_tries = 80;
193
194 voltage_tries = 1;
195 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
196 u8 link_status[DP_LINK_STATUS_SIZE];
197
198 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
199
200 if (!intel_dp_get_link_status(intel_dp, link_status)) {
201 DRM_ERROR("failed to get link status\n");
202 return false;
203 }
204
205 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
206 DRM_DEBUG_KMS("clock recovery OK\n");
207 return true;
208 }
209
210 if (voltage_tries == 5) {
211 DRM_DEBUG_KMS("Same voltage tried 5 times\n");
212 return false;
213 }
214
215 if (max_vswing_reached) {
216 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
217 return false;
218 }
219
220 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
221
222 /* Update training set as requested by target */
223 intel_get_adjust_train(intel_dp, link_status);
224 if (!intel_dp_update_link_train(intel_dp)) {
225 DRM_ERROR("failed to update link training\n");
226 return false;
227 }
228
229 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
230 voltage)
231 ++voltage_tries;
232 else
233 voltage_tries = 1;
234
235 if (intel_dp_link_max_vswing_reached(intel_dp))
236 max_vswing_reached = true;
237
238 }
239 DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries);
240 return false;
241 }
242
243 /*
244 * Pick training pattern for channel equalization. Training pattern 4 for HBR3
245 * or for 1.4 devices that support it, training Pattern 3 for HBR2
246 * or 1.2 devices that support it, Training Pattern 2 otherwise.
247 */
intel_dp_training_pattern(struct intel_dp * intel_dp)248 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
249 {
250 bool source_tps3, sink_tps3, source_tps4, sink_tps4;
251
252 /*
253 * Intel platforms that support HBR3 also support TPS4. It is mandatory
254 * for all downstream devices that support HBR3. There are no known eDP
255 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
256 * specification.
257 */
258 source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
259 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
260 if (source_tps4 && sink_tps4) {
261 return DP_TRAINING_PATTERN_4;
262 } else if (intel_dp->link_rate == 810000) {
263 if (!source_tps4)
264 DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
265 if (!sink_tps4)
266 DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
267 }
268 /*
269 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
270 * also mandatory for downstream devices that support HBR2. However, not
271 * all sinks follow the spec.
272 */
273 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
274 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
275 if (source_tps3 && sink_tps3) {
276 return DP_TRAINING_PATTERN_3;
277 } else if (intel_dp->link_rate >= 540000) {
278 if (!source_tps3)
279 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
280 if (!sink_tps3)
281 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
282 }
283
284 return DP_TRAINING_PATTERN_2;
285 }
286
287 static bool
intel_dp_link_training_channel_equalization(struct intel_dp * intel_dp)288 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
289 {
290 int tries;
291 u32 training_pattern;
292 u8 link_status[DP_LINK_STATUS_SIZE];
293 bool channel_eq = false;
294
295 training_pattern = intel_dp_training_pattern(intel_dp);
296 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
297 if (training_pattern != DP_TRAINING_PATTERN_4)
298 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
299
300 /* channel equalization */
301 if (!intel_dp_set_link_train(intel_dp,
302 training_pattern)) {
303 DRM_ERROR("failed to start channel equalization\n");
304 return false;
305 }
306
307 for (tries = 0; tries < 5; tries++) {
308
309 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
310 if (!intel_dp_get_link_status(intel_dp, link_status)) {
311 DRM_ERROR("failed to get link status\n");
312 break;
313 }
314
315 /* Make sure clock is still ok */
316 if (!drm_dp_clock_recovery_ok(link_status,
317 intel_dp->lane_count)) {
318 intel_dp_dump_link_status(link_status);
319 DRM_DEBUG_KMS("Clock recovery check failed, cannot "
320 "continue channel equalization\n");
321 break;
322 }
323
324 if (drm_dp_channel_eq_ok(link_status,
325 intel_dp->lane_count)) {
326 channel_eq = true;
327 DRM_DEBUG_KMS("Channel EQ done. DP Training "
328 "successful\n");
329 break;
330 }
331
332 /* Update training set as requested by target */
333 intel_get_adjust_train(intel_dp, link_status);
334 if (!intel_dp_update_link_train(intel_dp)) {
335 DRM_ERROR("failed to update link training\n");
336 break;
337 }
338 }
339
340 /* Try 5 times, else fail and try at lower BW */
341 if (tries == 5) {
342 intel_dp_dump_link_status(link_status);
343 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
344 }
345
346 intel_dp_set_idle_link_train(intel_dp);
347
348 return channel_eq;
349
350 }
351
intel_dp_stop_link_train(struct intel_dp * intel_dp)352 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
353 {
354 intel_dp->link_trained = true;
355
356 intel_dp_set_link_train(intel_dp,
357 DP_TRAINING_PATTERN_DISABLE);
358 }
359
360 void
intel_dp_start_link_train(struct intel_dp * intel_dp)361 intel_dp_start_link_train(struct intel_dp *intel_dp)
362 {
363 struct intel_connector *intel_connector = intel_dp->attached_connector;
364
365 if (!intel_dp_link_training_clock_recovery(intel_dp))
366 goto failure_handling;
367 if (!intel_dp_link_training_channel_equalization(intel_dp))
368 goto failure_handling;
369
370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
371 intel_connector->base.base.id,
372 intel_connector->base.name,
373 intel_dp->link_rate, intel_dp->lane_count);
374 return;
375
376 failure_handling:
377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
378 intel_connector->base.base.id,
379 intel_connector->base.name,
380 intel_dp->link_rate, intel_dp->lane_count);
381 if (!intel_dp_get_link_train_fallback_values(intel_dp,
382 intel_dp->link_rate,
383 intel_dp->lane_count))
384 /* Schedule a Hotplug Uevent to userspace to start modeset */
385 schedule_work(&intel_connector->modeset_retry_work);
386 return;
387 }
388