1//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp 2// Description: LMU illegal address exceptions 3// Illegal core MMR: addr[19:16] != 0 4// Illegal core MMR: Illegal peripheral 5// Illegal core MMR: Illegal addr in peripheral 6# mach: bfin 7# sim: --environment operating 8 9#include "test.h" 10.include "testutils.inc" 11start 12 13include(selfcheck.inc) 14include(std.inc) 15include(mmrs.inc) 16 17#ifndef SR_BASE 18#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs 19#endif 20#ifndef A_SRAM_BASE 21#define A_SRAM_BASE SR_BASE 22#endif 23#ifndef B_SRAM_BASE 24#define B_SRAM_BASE SR_BASE + 0x100000 25#endif 26#ifndef I_SRAM_BASE 27#define I_SRAM_BASE SR_BASE + 0x200000 28#endif 29#ifndef SCRATCH_SRAM_BASE 30#define SCRATCH_SRAM_BASE SR_BASE + 0x300000 31#endif 32 33#ifndef A_SRAM_SIZE 34#define A_SRAM_SIZE 0x4000 35#endif 36#ifndef B_SRAM_SIZE 37#define B_SRAM_SIZE 0x4000 38#endif 39#ifndef I_SRAM_SIZE 40#define I_SRAM_SIZE 0x4000 41#endif 42#ifndef SCRATCH_SRAM_SIZE 43#define SCRATCH_SRAM_SIZE 0x1000 44#endif 45 46CHECK_INIT(p5, 0xE0000000); 47 48 // setup interrupt controller with exception handler address 49 WR_MMR_LABEL(EVT3, handler, p0, r1); 50 WR_MMR_LABEL(EVT15, int15, p0, r1); 51 WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); 52 WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); 53 54 // Set up CPLB 55 56 WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable 57 WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); 58 59 WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable 60 WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); 61 62 WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable 63 WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); 64 65 WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0); 66 67 CSYNC; 68 69 // Write fault addr MMR to known state 70 WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); 71 NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC 72 73 // go to user mode. and enable exceptions 74 LD32_LABEL(r0, User); 75 RETI = R0; 76 77 // But first raise interrupt 15 so we will run in supervisor mode. 78 RAISE 15; 79 NOP; 80 RTI; 81 82 // Nops to work around ICache bug 83 NOP;NOP;NOP;NOP;NOP; 84 NOP;NOP;NOP;NOP;NOP; 85 86int15: 87 NOP;NOP;NOP;NOP;NOP; 88 89 //------------------------------------------------------- 90 // First do stores 91 //------------------------------------------------------- 92 // 93 94 // illegal core MMR: addr[19] !=0 95 96 97 LD32(p1, 0xFFE80000); 98 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 99 LD32(r1, 0xDEADBEEF); 100 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 101 102X01: [ P1 ] = R1; // Exception should occur here 103 104 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 105 CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address 106 CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) 107 108 //------------------------------------------------------- 109 110 // illegal core MMR: addr[18] !=0 111 112 113 LD32(p1, 0xFFE40000); 114 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 115 LD32(r1, 0xDEADBEEF); 116 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 117 118X02: [ P1 ] = R1; // Exception should occur here 119 120 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 121 CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address 122 CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) 123 124 //------------------------------------------------------- 125 126 // illegal core MMR: addr[17] !=0 127 128 129 LD32(p1, 0xFFE20000); 130 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 131 LD32(r1, 0xDEADBEEF); 132 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 133 134X03: [ P1 ] = R1; // Exception should occur here 135 136 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 137 CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address 138 CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) 139 140 //------------------------------------------------------- 141 142 // illegal core MMR: addr[16] !=0 143 144 145 LD32(p1, 0xFFE10000); 146 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 147 LD32(r1, 0xDEADBEEF); 148 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 149 150X04: [ P1 ] = R1; // Exception should occur here 151 152 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 153 CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address 154 CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) 155 156 //------------------------------------------------------- 157 158 // illegal core MMR: illegal periperal (addr[15:12] > 8) 159 160 161 LD32(p1, 0xFFE09000); 162 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 163 LD32(r1, 0xDEADBEEF); 164 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 165 166X10: [ P1 ] = R1; // Exception should occur here 167 168 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 169 CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address 170 CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!) 171 172 //------------------------------------------------------- 173 174 // illegal core MMR: illegal addr in peripheral 00 175 176 177 LD32(p1, 0xFFE00408); 178 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 179 LD32(r1, 0xDEADBEEF); 180 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 181 182X20: [ P1 ] = R1; // Exception should occur here 183 184 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 185 CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address 186 CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!) 187 188 //------------------------------------------------------- 189 190 // illegal core MMR: illegal addr in peripheral 01 191 192 193 LD32(p1, 0xFFE01408); 194 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 195 LD32(r1, 0xDEADBEEF); 196 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 197 198X21: [ P1 ] = R1; // Exception should occur here 199 200 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 201 CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address 202 CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!) 203 204 //------------------------------------------------------- 205 206 // illegal core MMR: illegal addr in peripheral 02 207 208 209 LD32(p1, 0xFFE02114); 210 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 211 LD32(r1, 0xDEADBEEF); 212 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 213 214X22: [ P1 ] = R1; // Exception should occur here 215 216 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 217 CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address 218 CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!) 219 220 //------------------------------------------------------- 221 222 // illegal core MMR: illegal addr in peripheral 03 223 224 225 LD32(p1, 0xFFE03010); 226 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 227 LD32(r1, 0xDEADBEEF); 228 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 229 230X23: [ P1 ] = R1; // Exception should occur here 231 232 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 233 CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address 234 CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!) 235 236 //------------------------------------------------------- 237 238 // illegal core MMR: illegal addr in peripheral 04 239 240 241 LD32(p1, 0xFFE04008); 242 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 243 LD32(r1, 0xDEADBEEF); 244 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 245 246X24: [ P1 ] = R1; // Exception should occur here 247 248 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 249 CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address 250 CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!) 251 252 //------------------------------------------------------- 253 254 // illegal core MMR: illegal addr in peripheral 05 255 256 257 LD32(p1, 0xFFE05010); 258 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 259 LD32(r1, 0xDEADBEEF); 260 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 261 262X25: [ P1 ] = R1; // Exception should occur here 263 264 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 265 CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address 266 CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!) 267 268 //------------------------------------------------------- 269 270 // illegal core MMR: illegal addr in peripheral 06 271 272 273 LD32(p1, 0xFFE06104); 274 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 275 LD32(r1, 0xDEADBEEF); 276 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 277 278X26: [ P1 ] = R1; // Exception should occur here 279 280 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 281 CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address 282 CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!) 283 284 //------------------------------------------------------- 285 286 // illegal core MMR: illegal addr in peripheral 07 287 288 289 LD32(p1, 0xFFE07204); 290 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 291 LD32(r1, 0xDEADBEEF); 292 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 293 294X27: [ P1 ] = R1; // Exception should occur here 295 296 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 297 CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address 298 CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!) 299 300 //------------------------------------------------------- 301 302 // illegal core MMR: illegal addr in peripheral 08 303 304 305 LD32(p1, 0xFFE08108); 306 LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) 307 LD32(r1, 0xDEADBEEF); 308 R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 309 310X28: [ P1 ] = R1; // Exception should occur here 311 312 CHECKREG(r5,0x2e); // supv and EXCPT_PROT 313 CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address 314 CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!) 315 316 //------------------------------------------------------- 317User: 318 dbg_pass; 319 320 321 //------------------------------------------------------- 322handler: 323 R5 = SEQSTAT; // Get exception cause 324 325 // read and check fail addr (addr_which_causes_exception) 326 // should not be set for alignment exception 327 RD_MMR(DCPLB_FAULT_ADDR, p0, r6); 328 329 R7 = RETX; // get address of excepting instruction 330 331 // align the offending address 332 P1 = P2; 333 334 RTX; 335 // Nops to work around ICache bug 336 NOP;NOP;NOP;NOP;NOP; 337 NOP;NOP;NOP;NOP;NOP; 338