1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2022 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43 typedef struct instr_info instr_info;
44
45 static void dofloat (instr_info *, int);
46 static void OP_ST (instr_info *, int, int);
47 static void OP_STi (instr_info *, int, int);
48 static int putop (instr_info *, const char *, int);
49 static void oappend_with_style (instr_info *, const char *,
50 enum disassembler_style);
51 static void oappend (instr_info *, const char *);
52 static void append_seg (instr_info *);
53 static void OP_indirE (instr_info *, int, int);
54 static void OP_E_memory (instr_info *, int, int);
55 static void OP_E (instr_info *, int, int);
56 static void OP_G (instr_info *, int, int);
57 static bfd_vma get64 (instr_info *);
58 static bfd_signed_vma get32 (instr_info *);
59 static bfd_signed_vma get32s (instr_info *);
60 static int get16 (instr_info *);
61 static void set_op (instr_info *, bfd_vma, bool);
62 static void OP_Skip_MODRM (instr_info *, int, int);
63 static void OP_REG (instr_info *, int, int);
64 static void OP_IMREG (instr_info *, int, int);
65 static void OP_I (instr_info *, int, int);
66 static void OP_I64 (instr_info *, int, int);
67 static void OP_sI (instr_info *, int, int);
68 static void OP_J (instr_info *, int, int);
69 static void OP_SEG (instr_info *, int, int);
70 static void OP_DIR (instr_info *, int, int);
71 static void OP_OFF (instr_info *, int, int);
72 static void OP_OFF64 (instr_info *, int, int);
73 static void ptr_reg (instr_info *, int, int);
74 static void OP_ESreg (instr_info *, int, int);
75 static void OP_DSreg (instr_info *, int, int);
76 static void OP_C (instr_info *, int, int);
77 static void OP_D (instr_info *, int, int);
78 static void OP_T (instr_info *, int, int);
79 static void OP_MMX (instr_info *, int, int);
80 static void OP_XMM (instr_info *, int, int);
81 static void OP_EM (instr_info *, int, int);
82 static void OP_EX (instr_info *, int, int);
83 static void OP_EMC (instr_info *, int,int);
84 static void OP_MXC (instr_info *, int,int);
85 static void OP_MS (instr_info *, int, int);
86 static void OP_XS (instr_info *, int, int);
87 static void OP_M (instr_info *, int, int);
88 static void OP_VEX (instr_info *, int, int);
89 static void OP_VexR (instr_info *, int, int);
90 static void OP_VexW (instr_info *, int, int);
91 static void OP_Rounding (instr_info *, int, int);
92 static void OP_REG_VexI4 (instr_info *, int, int);
93 static void OP_VexI4 (instr_info *, int, int);
94 static void PCLMUL_Fixup (instr_info *, int, int);
95 static void VPCMP_Fixup (instr_info *, int, int);
96 static void VPCOM_Fixup (instr_info *, int, int);
97 static void OP_0f07 (instr_info *, int, int);
98 static void OP_Monitor (instr_info *, int, int);
99 static void OP_Mwait (instr_info *, int, int);
100 static void NOP_Fixup (instr_info *, int, int);
101 static void OP_3DNowSuffix (instr_info *, int, int);
102 static void CMP_Fixup (instr_info *, int, int);
103 static void BadOp (instr_info *);
104 static void REP_Fixup (instr_info *, int, int);
105 static void SEP_Fixup (instr_info *, int, int);
106 static void BND_Fixup (instr_info *, int, int);
107 static void NOTRACK_Fixup (instr_info *, int, int);
108 static void HLE_Fixup1 (instr_info *, int, int);
109 static void HLE_Fixup2 (instr_info *, int, int);
110 static void HLE_Fixup3 (instr_info *, int, int);
111 static void CMPXCHG8B_Fixup (instr_info *, int, int);
112 static void XMM_Fixup (instr_info *, int, int);
113 static void FXSAVE_Fixup (instr_info *, int, int);
114
115 static void MOVSXD_Fixup (instr_info *, int, int);
116 static void DistinctDest_Fixup (instr_info *, int, int);
117
118 /* This character is used to encode style information within the output
119 buffers. See oappend_insert_style for more details. */
120 #define STYLE_MARKER_CHAR '\002'
121
122 struct dis_private {
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 bfd_vma insn_start;
127 int orig_sizeflag;
128 OPCODES_SIGJMP_BUF bailout;
129 };
130
131 enum address_mode
132 {
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136 };
137
138 enum x86_64_isa
139 {
140 amd64 = 1,
141 intel64
142 };
143
144 struct instr_info
145 {
146 enum address_mode address_mode;
147
148 /* Flags for the prefixes for the current instruction. See below. */
149 int prefixes;
150
151 /* REX prefix the current instruction. See below. */
152 unsigned char rex;
153 /* Bits of REX we've already used. */
154 unsigned char rex_used;
155
156 bool need_modrm;
157 bool need_vex;
158 bool has_sib;
159
160 /* Flags for ins->prefixes which we somehow handled when printing the
161 current instruction. */
162 int used_prefixes;
163
164 /* Flags for EVEX bits which we somehow handled when printing the
165 current instruction. */
166 int evex_used;
167
168 char obuf[100];
169 char *obufp;
170 char *mnemonicendp;
171 unsigned char *start_codep;
172 unsigned char *insn_codep;
173 unsigned char *codep;
174 unsigned char *end_codep;
175 signed char last_lock_prefix;
176 signed char last_repz_prefix;
177 signed char last_repnz_prefix;
178 signed char last_data_prefix;
179 signed char last_addr_prefix;
180 signed char last_rex_prefix;
181 signed char last_seg_prefix;
182 signed char fwait_prefix;
183 /* The active segment register prefix. */
184 unsigned char active_seg_prefix;
185
186 #define MAX_CODE_LENGTH 15
187 /* We can up to 14 ins->prefixes since the maximum instruction length is
188 15bytes. */
189 unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
190 disassemble_info *info;
191
192 struct
193 {
194 int mod;
195 int reg;
196 int rm;
197 }
198 modrm;
199
200 struct
201 {
202 int scale;
203 int index;
204 int base;
205 }
206 sib;
207
208 struct
209 {
210 int register_specifier;
211 int length;
212 int prefix;
213 int mask_register_specifier;
214 int ll;
215 bool w;
216 bool evex;
217 bool r;
218 bool v;
219 bool zeroing;
220 bool b;
221 bool no_broadcast;
222 }
223 vex;
224
225 /* Remember if the current op is a jump instruction. */
226 bool op_is_jump;
227
228 bool two_source_ops;
229
230 unsigned char op_ad;
231 signed char op_index[MAX_OPERANDS];
232 bool op_riprel[MAX_OPERANDS];
233 char *op_out[MAX_OPERANDS];
234 bfd_vma op_address[MAX_OPERANDS];
235 bfd_vma start_pc;
236
237 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
238 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
239 * section of the "Virtual 8086 Mode" chapter.)
240 * 'pc' should be the address of this instruction, it will
241 * be used to print the target address if this is a relative jump or call
242 * The function returns the length of this instruction in bytes.
243 */
244 char intel_syntax;
245 bool intel_mnemonic;
246 char open_char;
247 char close_char;
248 char separator_char;
249 char scale_char;
250
251 enum x86_64_isa isa64;
252 };
253
254 /* Mark parts used in the REX prefix. When we are testing for
255 empty prefix (for 8bit register REX extension), just mask it
256 out. Otherwise test for REX bit is excuse for existence of REX
257 only in case value is nonzero. */
258 #define USED_REX(value) \
259 { \
260 if (value) \
261 { \
262 if ((ins->rex & value)) \
263 ins->rex_used |= (value) | REX_OPCODE; \
264 } \
265 else \
266 ins->rex_used |= REX_OPCODE; \
267 }
268
269
270 #define EVEX_b_used 1
271 #define EVEX_len_used 2
272
273 /* Flags stored in PREFIXES. */
274 #define PREFIX_REPZ 1
275 #define PREFIX_REPNZ 2
276 #define PREFIX_CS 4
277 #define PREFIX_SS 8
278 #define PREFIX_DS 0x10
279 #define PREFIX_ES 0x20
280 #define PREFIX_FS 0x40
281 #define PREFIX_GS 0x80
282 #define PREFIX_LOCK 0x100
283 #define PREFIX_DATA 0x200
284 #define PREFIX_ADDR 0x400
285 #define PREFIX_FWAIT 0x800
286
287 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
288 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
289 on error. */
290 #define FETCH_DATA(info, addr) \
291 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
292 ? 1 : fetch_data ((info), (addr)))
293
294 static int
fetch_data(struct disassemble_info * info,bfd_byte * addr)295 fetch_data (struct disassemble_info *info, bfd_byte *addr)
296 {
297 int status;
298 struct dis_private *priv = (struct dis_private *) info->private_data;
299 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
300
301 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
302 status = (*info->read_memory_func) (start,
303 priv->max_fetched,
304 addr - priv->max_fetched,
305 info);
306 else
307 status = -1;
308 if (status != 0)
309 {
310 /* If we did manage to read at least one byte, then
311 print_insn_i386 will do something sensible. Otherwise, print
312 an error. We do that here because this is where we know
313 STATUS. */
314 if (priv->max_fetched == priv->the_buffer)
315 (*info->memory_error_func) (status, start, info);
316 OPCODES_SIGLONGJMP (priv->bailout, 1);
317 }
318 else
319 priv->max_fetched = addr;
320 return 1;
321 }
322
323 /* Possible values for prefix requirement. */
324 #define PREFIX_IGNORED_SHIFT 16
325 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
326 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
327 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
328 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
329 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
330
331 /* Opcode prefixes. */
332 #define PREFIX_OPCODE (PREFIX_REPZ \
333 | PREFIX_REPNZ \
334 | PREFIX_DATA)
335
336 /* Prefixes ignored. */
337 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
338 | PREFIX_IGNORED_REPNZ \
339 | PREFIX_IGNORED_DATA)
340
341 #define XX { NULL, 0 }
342 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
343
344 #define Eb { OP_E, b_mode }
345 #define Ebnd { OP_E, bnd_mode }
346 #define EbS { OP_E, b_swap_mode }
347 #define EbndS { OP_E, bnd_swap_mode }
348 #define Ev { OP_E, v_mode }
349 #define Eva { OP_E, va_mode }
350 #define Ev_bnd { OP_E, v_bnd_mode }
351 #define EvS { OP_E, v_swap_mode }
352 #define Ed { OP_E, d_mode }
353 #define Edq { OP_E, dq_mode }
354 #define Edb { OP_E, db_mode }
355 #define Edw { OP_E, dw_mode }
356 #define Eq { OP_E, q_mode }
357 #define indirEv { OP_indirE, indir_v_mode }
358 #define indirEp { OP_indirE, f_mode }
359 #define stackEv { OP_E, stack_v_mode }
360 #define Em { OP_E, m_mode }
361 #define Ew { OP_E, w_mode }
362 #define M { OP_M, 0 } /* lea, lgdt, etc. */
363 #define Ma { OP_M, a_mode }
364 #define Mb { OP_M, b_mode }
365 #define Md { OP_M, d_mode }
366 #define Mo { OP_M, o_mode }
367 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
368 #define Mq { OP_M, q_mode }
369 #define Mv { OP_M, v_mode }
370 #define Mv_bnd { OP_M, v_bndmk_mode }
371 #define Mx { OP_M, x_mode }
372 #define Mxmm { OP_M, xmm_mode }
373 #define Gb { OP_G, b_mode }
374 #define Gbnd { OP_G, bnd_mode }
375 #define Gv { OP_G, v_mode }
376 #define Gd { OP_G, d_mode }
377 #define Gdq { OP_G, dq_mode }
378 #define Gm { OP_G, m_mode }
379 #define Gva { OP_G, va_mode }
380 #define Gw { OP_G, w_mode }
381 #define Ib { OP_I, b_mode }
382 #define sIb { OP_sI, b_mode } /* sign extened byte */
383 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
384 #define Iv { OP_I, v_mode }
385 #define sIv { OP_sI, v_mode }
386 #define Iv64 { OP_I64, v_mode }
387 #define Id { OP_I, d_mode }
388 #define Iw { OP_I, w_mode }
389 #define I1 { OP_I, const_1_mode }
390 #define Jb { OP_J, b_mode }
391 #define Jv { OP_J, v_mode }
392 #define Jdqw { OP_J, dqw_mode }
393 #define Cm { OP_C, m_mode }
394 #define Dm { OP_D, m_mode }
395 #define Td { OP_T, d_mode }
396 #define Skip_MODRM { OP_Skip_MODRM, 0 }
397
398 #define RMeAX { OP_REG, eAX_reg }
399 #define RMeBX { OP_REG, eBX_reg }
400 #define RMeCX { OP_REG, eCX_reg }
401 #define RMeDX { OP_REG, eDX_reg }
402 #define RMeSP { OP_REG, eSP_reg }
403 #define RMeBP { OP_REG, eBP_reg }
404 #define RMeSI { OP_REG, eSI_reg }
405 #define RMeDI { OP_REG, eDI_reg }
406 #define RMrAX { OP_REG, rAX_reg }
407 #define RMrBX { OP_REG, rBX_reg }
408 #define RMrCX { OP_REG, rCX_reg }
409 #define RMrDX { OP_REG, rDX_reg }
410 #define RMrSP { OP_REG, rSP_reg }
411 #define RMrBP { OP_REG, rBP_reg }
412 #define RMrSI { OP_REG, rSI_reg }
413 #define RMrDI { OP_REG, rDI_reg }
414 #define RMAL { OP_REG, al_reg }
415 #define RMCL { OP_REG, cl_reg }
416 #define RMDL { OP_REG, dl_reg }
417 #define RMBL { OP_REG, bl_reg }
418 #define RMAH { OP_REG, ah_reg }
419 #define RMCH { OP_REG, ch_reg }
420 #define RMDH { OP_REG, dh_reg }
421 #define RMBH { OP_REG, bh_reg }
422 #define RMAX { OP_REG, ax_reg }
423 #define RMDX { OP_REG, dx_reg }
424
425 #define eAX { OP_IMREG, eAX_reg }
426 #define AL { OP_IMREG, al_reg }
427 #define CL { OP_IMREG, cl_reg }
428 #define zAX { OP_IMREG, z_mode_ax_reg }
429 #define indirDX { OP_IMREG, indir_dx_reg }
430
431 #define Sw { OP_SEG, w_mode }
432 #define Sv { OP_SEG, v_mode }
433 #define Ap { OP_DIR, 0 }
434 #define Ob { OP_OFF64, b_mode }
435 #define Ov { OP_OFF64, v_mode }
436 #define Xb { OP_DSreg, eSI_reg }
437 #define Xv { OP_DSreg, eSI_reg }
438 #define Xz { OP_DSreg, eSI_reg }
439 #define Yb { OP_ESreg, eDI_reg }
440 #define Yv { OP_ESreg, eDI_reg }
441 #define DSBX { OP_DSreg, eBX_reg }
442
443 #define es { OP_REG, es_reg }
444 #define ss { OP_REG, ss_reg }
445 #define cs { OP_REG, cs_reg }
446 #define ds { OP_REG, ds_reg }
447 #define fs { OP_REG, fs_reg }
448 #define gs { OP_REG, gs_reg }
449
450 #define MX { OP_MMX, 0 }
451 #define XM { OP_XMM, 0 }
452 #define XMScalar { OP_XMM, scalar_mode }
453 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
454 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
455 #define XMM { OP_XMM, xmm_mode }
456 #define TMM { OP_XMM, tmm_mode }
457 #define XMxmmq { OP_XMM, xmmq_mode }
458 #define EM { OP_EM, v_mode }
459 #define EMS { OP_EM, v_swap_mode }
460 #define EMd { OP_EM, d_mode }
461 #define EMx { OP_EM, x_mode }
462 #define EXbwUnit { OP_EX, bw_unit_mode }
463 #define EXb { OP_EX, b_mode }
464 #define EXw { OP_EX, w_mode }
465 #define EXd { OP_EX, d_mode }
466 #define EXdS { OP_EX, d_swap_mode }
467 #define EXwS { OP_EX, w_swap_mode }
468 #define EXq { OP_EX, q_mode }
469 #define EXqS { OP_EX, q_swap_mode }
470 #define EXdq { OP_EX, dq_mode }
471 #define EXx { OP_EX, x_mode }
472 #define EXxh { OP_EX, xh_mode }
473 #define EXxS { OP_EX, x_swap_mode }
474 #define EXxmm { OP_EX, xmm_mode }
475 #define EXymm { OP_EX, ymm_mode }
476 #define EXtmm { OP_EX, tmm_mode }
477 #define EXxmmq { OP_EX, xmmq_mode }
478 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
479 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
480 #define EXxmmdw { OP_EX, xmmdw_mode }
481 #define EXxmmqd { OP_EX, xmmqd_mode }
482 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
483 #define EXymmq { OP_EX, ymmq_mode }
484 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
485 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
486 #define MS { OP_MS, v_mode }
487 #define XS { OP_XS, v_mode }
488 #define EMCq { OP_EMC, q_mode }
489 #define MXC { OP_MXC, 0 }
490 #define OPSUF { OP_3DNowSuffix, 0 }
491 #define SEP { SEP_Fixup, 0 }
492 #define CMP { CMP_Fixup, 0 }
493 #define XMM0 { XMM_Fixup, 0 }
494 #define FXSAVE { FXSAVE_Fixup, 0 }
495
496 #define Vex { OP_VEX, x_mode }
497 #define VexW { OP_VexW, x_mode }
498 #define VexScalar { OP_VEX, scalar_mode }
499 #define VexScalarR { OP_VexR, scalar_mode }
500 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
501 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
502 #define VexGdq { OP_VEX, dq_mode }
503 #define VexTmm { OP_VEX, tmm_mode }
504 #define XMVexI4 { OP_REG_VexI4, x_mode }
505 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
506 #define VexI4 { OP_VexI4, 0 }
507 #define PCLMUL { PCLMUL_Fixup, 0 }
508 #define VPCMP { VPCMP_Fixup, 0 }
509 #define VPCOM { VPCOM_Fixup, 0 }
510
511 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
512 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
513 #define EXxEVexS { OP_Rounding, evex_sae_mode }
514
515 #define MaskG { OP_G, mask_mode }
516 #define MaskE { OP_E, mask_mode }
517 #define MaskBDE { OP_E, mask_bd_mode }
518 #define MaskVex { OP_VEX, mask_mode }
519
520 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
521 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
522
523 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
524
525 /* Used handle "rep" prefix for string instructions. */
526 #define Xbr { REP_Fixup, eSI_reg }
527 #define Xvr { REP_Fixup, eSI_reg }
528 #define Ybr { REP_Fixup, eDI_reg }
529 #define Yvr { REP_Fixup, eDI_reg }
530 #define Yzr { REP_Fixup, eDI_reg }
531 #define indirDXr { REP_Fixup, indir_dx_reg }
532 #define ALr { REP_Fixup, al_reg }
533 #define eAXr { REP_Fixup, eAX_reg }
534
535 /* Used handle HLE prefix for lockable instructions. */
536 #define Ebh1 { HLE_Fixup1, b_mode }
537 #define Evh1 { HLE_Fixup1, v_mode }
538 #define Ebh2 { HLE_Fixup2, b_mode }
539 #define Evh2 { HLE_Fixup2, v_mode }
540 #define Ebh3 { HLE_Fixup3, b_mode }
541 #define Evh3 { HLE_Fixup3, v_mode }
542
543 #define BND { BND_Fixup, 0 }
544 #define NOTRACK { NOTRACK_Fixup, 0 }
545
546 #define cond_jump_flag { NULL, cond_jump_mode }
547 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
548
549 /* bits in sizeflag */
550 #define SUFFIX_ALWAYS 4
551 #define AFLAG 2
552 #define DFLAG 1
553
554 enum
555 {
556 /* byte operand */
557 b_mode = 1,
558 /* byte operand with operand swapped */
559 b_swap_mode,
560 /* byte operand, sign extend like 'T' suffix */
561 b_T_mode,
562 /* operand size depends on prefixes */
563 v_mode,
564 /* operand size depends on prefixes with operand swapped */
565 v_swap_mode,
566 /* operand size depends on address prefix */
567 va_mode,
568 /* word operand */
569 w_mode,
570 /* double word operand */
571 d_mode,
572 /* word operand with operand swapped */
573 w_swap_mode,
574 /* double word operand with operand swapped */
575 d_swap_mode,
576 /* quad word operand */
577 q_mode,
578 /* quad word operand with operand swapped */
579 q_swap_mode,
580 /* ten-byte operand */
581 t_mode,
582 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
583 broadcast enabled. */
584 x_mode,
585 /* Similar to x_mode, but with different EVEX mem shifts. */
586 evex_x_gscat_mode,
587 /* Similar to x_mode, but with yet different EVEX mem shifts. */
588 bw_unit_mode,
589 /* Similar to x_mode, but with disabled broadcast. */
590 evex_x_nobcst_mode,
591 /* Similar to x_mode, but with operands swapped and disabled broadcast
592 in EVEX. */
593 x_swap_mode,
594 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
595 broadcast of 16bit enabled. */
596 xh_mode,
597 /* 16-byte XMM operand */
598 xmm_mode,
599 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
600 memory operand (depending on vector length). Broadcast isn't
601 allowed. */
602 xmmq_mode,
603 /* Same as xmmq_mode, but broadcast is allowed. */
604 evex_half_bcst_xmmq_mode,
605 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
606 memory operand (depending on vector length). 16bit broadcast. */
607 evex_half_bcst_xmmqh_mode,
608 /* 16-byte XMM, word, double word or quad word operand. */
609 xmmdw_mode,
610 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
611 xmmqd_mode,
612 /* 16-byte XMM, double word, quad word operand or xmm word operand.
613 16bit broadcast. */
614 evex_half_bcst_xmmqdh_mode,
615 /* 32-byte YMM operand */
616 ymm_mode,
617 /* quad word, ymmword or zmmword memory operand. */
618 ymmq_mode,
619 /* TMM operand */
620 tmm_mode,
621 /* d_mode in 32bit, q_mode in 64bit mode. */
622 m_mode,
623 /* pair of v_mode operands */
624 a_mode,
625 cond_jump_mode,
626 loop_jcxz_mode,
627 movsxd_mode,
628 v_bnd_mode,
629 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
630 v_bndmk_mode,
631 /* operand size depends on REX.W / VEX.W. */
632 dq_mode,
633 /* Displacements like v_mode without considering Intel64 ISA. */
634 dqw_mode,
635 /* bounds operand */
636 bnd_mode,
637 /* bounds operand with operand swapped */
638 bnd_swap_mode,
639 /* 4- or 6-byte pointer operand */
640 f_mode,
641 const_1_mode,
642 /* v_mode for indirect branch opcodes. */
643 indir_v_mode,
644 /* v_mode for stack-related opcodes. */
645 stack_v_mode,
646 /* non-quad operand size depends on prefixes */
647 z_mode,
648 /* 16-byte operand */
649 o_mode,
650 /* registers like d_mode, memory like b_mode. */
651 db_mode,
652 /* registers like d_mode, memory like w_mode. */
653 dw_mode,
654
655 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
656 vex_vsib_d_w_dq_mode,
657 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
658 vex_vsib_q_w_dq_mode,
659 /* mandatory non-vector SIB. */
660 vex_sibmem_mode,
661
662 /* scalar, ignore vector length. */
663 scalar_mode,
664
665 /* Static rounding. */
666 evex_rounding_mode,
667 /* Static rounding, 64-bit mode only. */
668 evex_rounding_64_mode,
669 /* Supress all exceptions. */
670 evex_sae_mode,
671
672 /* Mask register operand. */
673 mask_mode,
674 /* Mask register operand. */
675 mask_bd_mode,
676
677 es_reg,
678 cs_reg,
679 ss_reg,
680 ds_reg,
681 fs_reg,
682 gs_reg,
683
684 eAX_reg,
685 eCX_reg,
686 eDX_reg,
687 eBX_reg,
688 eSP_reg,
689 eBP_reg,
690 eSI_reg,
691 eDI_reg,
692
693 al_reg,
694 cl_reg,
695 dl_reg,
696 bl_reg,
697 ah_reg,
698 ch_reg,
699 dh_reg,
700 bh_reg,
701
702 ax_reg,
703 cx_reg,
704 dx_reg,
705 bx_reg,
706 sp_reg,
707 bp_reg,
708 si_reg,
709 di_reg,
710
711 rAX_reg,
712 rCX_reg,
713 rDX_reg,
714 rBX_reg,
715 rSP_reg,
716 rBP_reg,
717 rSI_reg,
718 rDI_reg,
719
720 z_mode_ax_reg,
721 indir_dx_reg
722 };
723
724 enum
725 {
726 FLOATCODE = 1,
727 USE_REG_TABLE,
728 USE_MOD_TABLE,
729 USE_RM_TABLE,
730 USE_PREFIX_TABLE,
731 USE_X86_64_TABLE,
732 USE_3BYTE_TABLE,
733 USE_XOP_8F_TABLE,
734 USE_VEX_C4_TABLE,
735 USE_VEX_C5_TABLE,
736 USE_VEX_LEN_TABLE,
737 USE_VEX_W_TABLE,
738 USE_EVEX_TABLE,
739 USE_EVEX_LEN_TABLE
740 };
741
742 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
743
744 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
745 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
746 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
747 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
748 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
749 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
750 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
751 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
752 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
753 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
754 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
755 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
756 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
757 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
758 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
759 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
760
761 enum
762 {
763 REG_80 = 0,
764 REG_81,
765 REG_83,
766 REG_8F,
767 REG_C0,
768 REG_C1,
769 REG_C6,
770 REG_C7,
771 REG_D0,
772 REG_D1,
773 REG_D2,
774 REG_D3,
775 REG_F6,
776 REG_F7,
777 REG_FE,
778 REG_FF,
779 REG_0F00,
780 REG_0F01,
781 REG_0F0D,
782 REG_0F18,
783 REG_0F1C_P_0_MOD_0,
784 REG_0F1E_P_1_MOD_3,
785 REG_0F38D8_PREFIX_1,
786 REG_0F3A0F_PREFIX_1_MOD_3,
787 REG_0F71_MOD_0,
788 REG_0F72_MOD_0,
789 REG_0F73_MOD_0,
790 REG_0FA6,
791 REG_0FA7,
792 REG_0FAE,
793 REG_0FBA,
794 REG_0FC7,
795 REG_VEX_0F71_M_0,
796 REG_VEX_0F72_M_0,
797 REG_VEX_0F73_M_0,
798 REG_VEX_0FAE,
799 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
800 REG_VEX_0F38F3_L_0,
801
802 REG_XOP_09_01_L_0,
803 REG_XOP_09_02_L_0,
804 REG_XOP_09_12_M_1_L_0,
805 REG_XOP_0A_12_L_0,
806
807 REG_EVEX_0F71,
808 REG_EVEX_0F72,
809 REG_EVEX_0F73,
810 REG_EVEX_0F38C6_M_0_L_2,
811 REG_EVEX_0F38C7_M_0_L_2
812 };
813
814 enum
815 {
816 MOD_62_32BIT = 0,
817 MOD_8D,
818 MOD_C4_32BIT,
819 MOD_C5_32BIT,
820 MOD_C6_REG_7,
821 MOD_C7_REG_7,
822 MOD_FF_REG_3,
823 MOD_FF_REG_5,
824 MOD_0F01_REG_0,
825 MOD_0F01_REG_1,
826 MOD_0F01_REG_2,
827 MOD_0F01_REG_3,
828 MOD_0F01_REG_5,
829 MOD_0F01_REG_7,
830 MOD_0F12_PREFIX_0,
831 MOD_0F12_PREFIX_2,
832 MOD_0F13,
833 MOD_0F16_PREFIX_0,
834 MOD_0F16_PREFIX_2,
835 MOD_0F17,
836 MOD_0F18_REG_0,
837 MOD_0F18_REG_1,
838 MOD_0F18_REG_2,
839 MOD_0F18_REG_3,
840 MOD_0F1A_PREFIX_0,
841 MOD_0F1B_PREFIX_0,
842 MOD_0F1B_PREFIX_1,
843 MOD_0F1C_PREFIX_0,
844 MOD_0F1E_PREFIX_1,
845 MOD_0F2B_PREFIX_0,
846 MOD_0F2B_PREFIX_1,
847 MOD_0F2B_PREFIX_2,
848 MOD_0F2B_PREFIX_3,
849 MOD_0F50,
850 MOD_0F71,
851 MOD_0F72,
852 MOD_0F73,
853 MOD_0FAE_REG_0,
854 MOD_0FAE_REG_1,
855 MOD_0FAE_REG_2,
856 MOD_0FAE_REG_3,
857 MOD_0FAE_REG_4,
858 MOD_0FAE_REG_5,
859 MOD_0FAE_REG_6,
860 MOD_0FAE_REG_7,
861 MOD_0FB2,
862 MOD_0FB4,
863 MOD_0FB5,
864 MOD_0FC3,
865 MOD_0FC7_REG_3,
866 MOD_0FC7_REG_4,
867 MOD_0FC7_REG_5,
868 MOD_0FC7_REG_6,
869 MOD_0FC7_REG_7,
870 MOD_0FD7,
871 MOD_0FE7_PREFIX_2,
872 MOD_0FF0_PREFIX_3,
873 MOD_0F382A,
874 MOD_0F38DC_PREFIX_1,
875 MOD_0F38DD_PREFIX_1,
876 MOD_0F38DE_PREFIX_1,
877 MOD_0F38DF_PREFIX_1,
878 MOD_0F38F5,
879 MOD_0F38F6_PREFIX_0,
880 MOD_0F38F8_PREFIX_1,
881 MOD_0F38F8_PREFIX_2,
882 MOD_0F38F8_PREFIX_3,
883 MOD_0F38F9,
884 MOD_0F38FA_PREFIX_1,
885 MOD_0F38FB_PREFIX_1,
886 MOD_0F3A0F_PREFIX_1,
887
888 MOD_VEX_0F12_PREFIX_0,
889 MOD_VEX_0F12_PREFIX_2,
890 MOD_VEX_0F13,
891 MOD_VEX_0F16_PREFIX_0,
892 MOD_VEX_0F16_PREFIX_2,
893 MOD_VEX_0F17,
894 MOD_VEX_0F2B,
895 MOD_VEX_0F41_L_1,
896 MOD_VEX_0F42_L_1,
897 MOD_VEX_0F44_L_0,
898 MOD_VEX_0F45_L_1,
899 MOD_VEX_0F46_L_1,
900 MOD_VEX_0F47_L_1,
901 MOD_VEX_0F4A_L_1,
902 MOD_VEX_0F4B_L_1,
903 MOD_VEX_0F50,
904 MOD_VEX_0F71,
905 MOD_VEX_0F72,
906 MOD_VEX_0F73,
907 MOD_VEX_0F91_L_0,
908 MOD_VEX_0F92_L_0,
909 MOD_VEX_0F93_L_0,
910 MOD_VEX_0F98_L_0,
911 MOD_VEX_0F99_L_0,
912 MOD_VEX_0FAE_REG_2,
913 MOD_VEX_0FAE_REG_3,
914 MOD_VEX_0FD7,
915 MOD_VEX_0FE7,
916 MOD_VEX_0FF0_PREFIX_3,
917 MOD_VEX_0F381A,
918 MOD_VEX_0F382A,
919 MOD_VEX_0F382C,
920 MOD_VEX_0F382D,
921 MOD_VEX_0F382E,
922 MOD_VEX_0F382F,
923 MOD_VEX_0F3849_X86_64_P_0_W_0,
924 MOD_VEX_0F3849_X86_64_P_2_W_0,
925 MOD_VEX_0F3849_X86_64_P_3_W_0,
926 MOD_VEX_0F384B_X86_64_P_1_W_0,
927 MOD_VEX_0F384B_X86_64_P_2_W_0,
928 MOD_VEX_0F384B_X86_64_P_3_W_0,
929 MOD_VEX_0F385A,
930 MOD_VEX_0F385C_X86_64_P_1_W_0,
931 MOD_VEX_0F385E_X86_64_P_0_W_0,
932 MOD_VEX_0F385E_X86_64_P_1_W_0,
933 MOD_VEX_0F385E_X86_64_P_2_W_0,
934 MOD_VEX_0F385E_X86_64_P_3_W_0,
935 MOD_VEX_0F388C,
936 MOD_VEX_0F388E,
937 MOD_VEX_0F3A30_L_0,
938 MOD_VEX_0F3A31_L_0,
939 MOD_VEX_0F3A32_L_0,
940 MOD_VEX_0F3A33_L_0,
941
942 MOD_XOP_09_12,
943
944 MOD_EVEX_0F381A,
945 MOD_EVEX_0F381B,
946 MOD_EVEX_0F3828_P_1,
947 MOD_EVEX_0F382A_P_1_W_1,
948 MOD_EVEX_0F3838_P_1,
949 MOD_EVEX_0F383A_P_1_W_0,
950 MOD_EVEX_0F385A,
951 MOD_EVEX_0F385B,
952 MOD_EVEX_0F387A_W_0,
953 MOD_EVEX_0F387B_W_0,
954 MOD_EVEX_0F387C,
955 MOD_EVEX_0F38C6,
956 MOD_EVEX_0F38C7,
957 };
958
959 enum
960 {
961 RM_C6_REG_7 = 0,
962 RM_C7_REG_7,
963 RM_0F01_REG_0,
964 RM_0F01_REG_1,
965 RM_0F01_REG_2,
966 RM_0F01_REG_3,
967 RM_0F01_REG_5_MOD_3,
968 RM_0F01_REG_7_MOD_3,
969 RM_0F1E_P_1_MOD_3_REG_7,
970 RM_0FAE_REG_6_MOD_3_P_0,
971 RM_0FAE_REG_7_MOD_3,
972 RM_0F3A0F_P_1_MOD_3_REG_0,
973
974 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
975 };
976
977 enum
978 {
979 PREFIX_90 = 0,
980 PREFIX_0F01_REG_1_RM_4,
981 PREFIX_0F01_REG_1_RM_5,
982 PREFIX_0F01_REG_1_RM_6,
983 PREFIX_0F01_REG_1_RM_7,
984 PREFIX_0F01_REG_3_RM_1,
985 PREFIX_0F01_REG_5_MOD_0,
986 PREFIX_0F01_REG_5_MOD_3_RM_0,
987 PREFIX_0F01_REG_5_MOD_3_RM_1,
988 PREFIX_0F01_REG_5_MOD_3_RM_2,
989 PREFIX_0F01_REG_5_MOD_3_RM_4,
990 PREFIX_0F01_REG_5_MOD_3_RM_5,
991 PREFIX_0F01_REG_5_MOD_3_RM_6,
992 PREFIX_0F01_REG_5_MOD_3_RM_7,
993 PREFIX_0F01_REG_7_MOD_3_RM_2,
994 PREFIX_0F01_REG_7_MOD_3_RM_6,
995 PREFIX_0F01_REG_7_MOD_3_RM_7,
996 PREFIX_0F09,
997 PREFIX_0F10,
998 PREFIX_0F11,
999 PREFIX_0F12,
1000 PREFIX_0F16,
1001 PREFIX_0F1A,
1002 PREFIX_0F1B,
1003 PREFIX_0F1C,
1004 PREFIX_0F1E,
1005 PREFIX_0F2A,
1006 PREFIX_0F2B,
1007 PREFIX_0F2C,
1008 PREFIX_0F2D,
1009 PREFIX_0F2E,
1010 PREFIX_0F2F,
1011 PREFIX_0F51,
1012 PREFIX_0F52,
1013 PREFIX_0F53,
1014 PREFIX_0F58,
1015 PREFIX_0F59,
1016 PREFIX_0F5A,
1017 PREFIX_0F5B,
1018 PREFIX_0F5C,
1019 PREFIX_0F5D,
1020 PREFIX_0F5E,
1021 PREFIX_0F5F,
1022 PREFIX_0F60,
1023 PREFIX_0F61,
1024 PREFIX_0F62,
1025 PREFIX_0F6F,
1026 PREFIX_0F70,
1027 PREFIX_0F78,
1028 PREFIX_0F79,
1029 PREFIX_0F7C,
1030 PREFIX_0F7D,
1031 PREFIX_0F7E,
1032 PREFIX_0F7F,
1033 PREFIX_0FAE_REG_0_MOD_3,
1034 PREFIX_0FAE_REG_1_MOD_3,
1035 PREFIX_0FAE_REG_2_MOD_3,
1036 PREFIX_0FAE_REG_3_MOD_3,
1037 PREFIX_0FAE_REG_4_MOD_0,
1038 PREFIX_0FAE_REG_4_MOD_3,
1039 PREFIX_0FAE_REG_5_MOD_3,
1040 PREFIX_0FAE_REG_6_MOD_0,
1041 PREFIX_0FAE_REG_6_MOD_3,
1042 PREFIX_0FAE_REG_7_MOD_0,
1043 PREFIX_0FB8,
1044 PREFIX_0FBC,
1045 PREFIX_0FBD,
1046 PREFIX_0FC2,
1047 PREFIX_0FC7_REG_6_MOD_0,
1048 PREFIX_0FC7_REG_6_MOD_3,
1049 PREFIX_0FC7_REG_7_MOD_3,
1050 PREFIX_0FD0,
1051 PREFIX_0FD6,
1052 PREFIX_0FE6,
1053 PREFIX_0FE7,
1054 PREFIX_0FF0,
1055 PREFIX_0FF7,
1056 PREFIX_0F38D8,
1057 PREFIX_0F38DC,
1058 PREFIX_0F38DD,
1059 PREFIX_0F38DE,
1060 PREFIX_0F38DF,
1061 PREFIX_0F38F0,
1062 PREFIX_0F38F1,
1063 PREFIX_0F38F6,
1064 PREFIX_0F38F8,
1065 PREFIX_0F38FA,
1066 PREFIX_0F38FB,
1067 PREFIX_0F3A0F,
1068 PREFIX_VEX_0F10,
1069 PREFIX_VEX_0F11,
1070 PREFIX_VEX_0F12,
1071 PREFIX_VEX_0F16,
1072 PREFIX_VEX_0F2A,
1073 PREFIX_VEX_0F2C,
1074 PREFIX_VEX_0F2D,
1075 PREFIX_VEX_0F2E,
1076 PREFIX_VEX_0F2F,
1077 PREFIX_VEX_0F41_L_1_M_1_W_0,
1078 PREFIX_VEX_0F41_L_1_M_1_W_1,
1079 PREFIX_VEX_0F42_L_1_M_1_W_0,
1080 PREFIX_VEX_0F42_L_1_M_1_W_1,
1081 PREFIX_VEX_0F44_L_0_M_1_W_0,
1082 PREFIX_VEX_0F44_L_0_M_1_W_1,
1083 PREFIX_VEX_0F45_L_1_M_1_W_0,
1084 PREFIX_VEX_0F45_L_1_M_1_W_1,
1085 PREFIX_VEX_0F46_L_1_M_1_W_0,
1086 PREFIX_VEX_0F46_L_1_M_1_W_1,
1087 PREFIX_VEX_0F47_L_1_M_1_W_0,
1088 PREFIX_VEX_0F47_L_1_M_1_W_1,
1089 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1090 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1091 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1092 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1093 PREFIX_VEX_0F51,
1094 PREFIX_VEX_0F52,
1095 PREFIX_VEX_0F53,
1096 PREFIX_VEX_0F58,
1097 PREFIX_VEX_0F59,
1098 PREFIX_VEX_0F5A,
1099 PREFIX_VEX_0F5B,
1100 PREFIX_VEX_0F5C,
1101 PREFIX_VEX_0F5D,
1102 PREFIX_VEX_0F5E,
1103 PREFIX_VEX_0F5F,
1104 PREFIX_VEX_0F6F,
1105 PREFIX_VEX_0F70,
1106 PREFIX_VEX_0F7C,
1107 PREFIX_VEX_0F7D,
1108 PREFIX_VEX_0F7E,
1109 PREFIX_VEX_0F7F,
1110 PREFIX_VEX_0F90_L_0_W_0,
1111 PREFIX_VEX_0F90_L_0_W_1,
1112 PREFIX_VEX_0F91_L_0_M_0_W_0,
1113 PREFIX_VEX_0F91_L_0_M_0_W_1,
1114 PREFIX_VEX_0F92_L_0_M_1_W_0,
1115 PREFIX_VEX_0F92_L_0_M_1_W_1,
1116 PREFIX_VEX_0F93_L_0_M_1_W_0,
1117 PREFIX_VEX_0F93_L_0_M_1_W_1,
1118 PREFIX_VEX_0F98_L_0_M_1_W_0,
1119 PREFIX_VEX_0F98_L_0_M_1_W_1,
1120 PREFIX_VEX_0F99_L_0_M_1_W_0,
1121 PREFIX_VEX_0F99_L_0_M_1_W_1,
1122 PREFIX_VEX_0FC2,
1123 PREFIX_VEX_0FD0,
1124 PREFIX_VEX_0FE6,
1125 PREFIX_VEX_0FF0,
1126 PREFIX_VEX_0F3849_X86_64,
1127 PREFIX_VEX_0F384B_X86_64,
1128 PREFIX_VEX_0F385C_X86_64,
1129 PREFIX_VEX_0F385E_X86_64,
1130 PREFIX_VEX_0F38F5_L_0,
1131 PREFIX_VEX_0F38F6_L_0,
1132 PREFIX_VEX_0F38F7_L_0,
1133 PREFIX_VEX_0F3AF0_L_0,
1134
1135 PREFIX_EVEX_0F5B,
1136 PREFIX_EVEX_0F6F,
1137 PREFIX_EVEX_0F70,
1138 PREFIX_EVEX_0F78,
1139 PREFIX_EVEX_0F79,
1140 PREFIX_EVEX_0F7A,
1141 PREFIX_EVEX_0F7B,
1142 PREFIX_EVEX_0F7E,
1143 PREFIX_EVEX_0F7F,
1144 PREFIX_EVEX_0FC2,
1145 PREFIX_EVEX_0FE6,
1146 PREFIX_EVEX_0F3810,
1147 PREFIX_EVEX_0F3811,
1148 PREFIX_EVEX_0F3812,
1149 PREFIX_EVEX_0F3813,
1150 PREFIX_EVEX_0F3814,
1151 PREFIX_EVEX_0F3815,
1152 PREFIX_EVEX_0F3820,
1153 PREFIX_EVEX_0F3821,
1154 PREFIX_EVEX_0F3822,
1155 PREFIX_EVEX_0F3823,
1156 PREFIX_EVEX_0F3824,
1157 PREFIX_EVEX_0F3825,
1158 PREFIX_EVEX_0F3826,
1159 PREFIX_EVEX_0F3827,
1160 PREFIX_EVEX_0F3828,
1161 PREFIX_EVEX_0F3829,
1162 PREFIX_EVEX_0F382A,
1163 PREFIX_EVEX_0F3830,
1164 PREFIX_EVEX_0F3831,
1165 PREFIX_EVEX_0F3832,
1166 PREFIX_EVEX_0F3833,
1167 PREFIX_EVEX_0F3834,
1168 PREFIX_EVEX_0F3835,
1169 PREFIX_EVEX_0F3838,
1170 PREFIX_EVEX_0F3839,
1171 PREFIX_EVEX_0F383A,
1172 PREFIX_EVEX_0F3852,
1173 PREFIX_EVEX_0F3853,
1174 PREFIX_EVEX_0F3868,
1175 PREFIX_EVEX_0F3872,
1176 PREFIX_EVEX_0F389A,
1177 PREFIX_EVEX_0F389B,
1178 PREFIX_EVEX_0F38AA,
1179 PREFIX_EVEX_0F38AB,
1180
1181 PREFIX_EVEX_0F3A08,
1182 PREFIX_EVEX_0F3A0A,
1183 PREFIX_EVEX_0F3A26,
1184 PREFIX_EVEX_0F3A27,
1185 PREFIX_EVEX_0F3A56,
1186 PREFIX_EVEX_0F3A57,
1187 PREFIX_EVEX_0F3A66,
1188 PREFIX_EVEX_0F3A67,
1189 PREFIX_EVEX_0F3AC2,
1190
1191 PREFIX_EVEX_MAP5_10,
1192 PREFIX_EVEX_MAP5_11,
1193 PREFIX_EVEX_MAP5_1D,
1194 PREFIX_EVEX_MAP5_2A,
1195 PREFIX_EVEX_MAP5_2C,
1196 PREFIX_EVEX_MAP5_2D,
1197 PREFIX_EVEX_MAP5_2E,
1198 PREFIX_EVEX_MAP5_2F,
1199 PREFIX_EVEX_MAP5_51,
1200 PREFIX_EVEX_MAP5_58,
1201 PREFIX_EVEX_MAP5_59,
1202 PREFIX_EVEX_MAP5_5A,
1203 PREFIX_EVEX_MAP5_5B,
1204 PREFIX_EVEX_MAP5_5C,
1205 PREFIX_EVEX_MAP5_5D,
1206 PREFIX_EVEX_MAP5_5E,
1207 PREFIX_EVEX_MAP5_5F,
1208 PREFIX_EVEX_MAP5_78,
1209 PREFIX_EVEX_MAP5_79,
1210 PREFIX_EVEX_MAP5_7A,
1211 PREFIX_EVEX_MAP5_7B,
1212 PREFIX_EVEX_MAP5_7C,
1213 PREFIX_EVEX_MAP5_7D,
1214
1215 PREFIX_EVEX_MAP6_13,
1216 PREFIX_EVEX_MAP6_56,
1217 PREFIX_EVEX_MAP6_57,
1218 PREFIX_EVEX_MAP6_D6,
1219 PREFIX_EVEX_MAP6_D7,
1220 };
1221
1222 enum
1223 {
1224 X86_64_06 = 0,
1225 X86_64_07,
1226 X86_64_0E,
1227 X86_64_16,
1228 X86_64_17,
1229 X86_64_1E,
1230 X86_64_1F,
1231 X86_64_27,
1232 X86_64_2F,
1233 X86_64_37,
1234 X86_64_3F,
1235 X86_64_60,
1236 X86_64_61,
1237 X86_64_62,
1238 X86_64_63,
1239 X86_64_6D,
1240 X86_64_6F,
1241 X86_64_82,
1242 X86_64_9A,
1243 X86_64_C2,
1244 X86_64_C3,
1245 X86_64_C4,
1246 X86_64_C5,
1247 X86_64_CE,
1248 X86_64_D4,
1249 X86_64_D5,
1250 X86_64_E8,
1251 X86_64_E9,
1252 X86_64_EA,
1253 X86_64_0F01_REG_0,
1254 X86_64_0F01_REG_1,
1255 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1256 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1257 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1258 X86_64_0F01_REG_2,
1259 X86_64_0F01_REG_3,
1260 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1261 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1262 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1263 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1264 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1265 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1266 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1267 X86_64_0F24,
1268 X86_64_0F26,
1269 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1270
1271 X86_64_VEX_0F3849,
1272 X86_64_VEX_0F384B,
1273 X86_64_VEX_0F385C,
1274 X86_64_VEX_0F385E
1275 };
1276
1277 enum
1278 {
1279 THREE_BYTE_0F38 = 0,
1280 THREE_BYTE_0F3A
1281 };
1282
1283 enum
1284 {
1285 XOP_08 = 0,
1286 XOP_09,
1287 XOP_0A
1288 };
1289
1290 enum
1291 {
1292 VEX_0F = 0,
1293 VEX_0F38,
1294 VEX_0F3A
1295 };
1296
1297 enum
1298 {
1299 EVEX_0F = 0,
1300 EVEX_0F38,
1301 EVEX_0F3A,
1302 EVEX_MAP5,
1303 EVEX_MAP6,
1304 };
1305
1306 enum
1307 {
1308 VEX_LEN_0F12_P_0_M_0 = 0,
1309 VEX_LEN_0F12_P_0_M_1,
1310 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1311 VEX_LEN_0F13_M_0,
1312 VEX_LEN_0F16_P_0_M_0,
1313 VEX_LEN_0F16_P_0_M_1,
1314 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1315 VEX_LEN_0F17_M_0,
1316 VEX_LEN_0F41,
1317 VEX_LEN_0F42,
1318 VEX_LEN_0F44,
1319 VEX_LEN_0F45,
1320 VEX_LEN_0F46,
1321 VEX_LEN_0F47,
1322 VEX_LEN_0F4A,
1323 VEX_LEN_0F4B,
1324 VEX_LEN_0F6E,
1325 VEX_LEN_0F77,
1326 VEX_LEN_0F7E_P_1,
1327 VEX_LEN_0F7E_P_2,
1328 VEX_LEN_0F90,
1329 VEX_LEN_0F91,
1330 VEX_LEN_0F92,
1331 VEX_LEN_0F93,
1332 VEX_LEN_0F98,
1333 VEX_LEN_0F99,
1334 VEX_LEN_0FAE_R_2_M_0,
1335 VEX_LEN_0FAE_R_3_M_0,
1336 VEX_LEN_0FC4,
1337 VEX_LEN_0FC5,
1338 VEX_LEN_0FD6,
1339 VEX_LEN_0FF7,
1340 VEX_LEN_0F3816,
1341 VEX_LEN_0F3819,
1342 VEX_LEN_0F381A_M_0,
1343 VEX_LEN_0F3836,
1344 VEX_LEN_0F3841,
1345 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1346 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1347 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1348 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1349 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1350 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1351 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1352 VEX_LEN_0F385A_M_0,
1353 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1354 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1355 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1356 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1357 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1358 VEX_LEN_0F38DB,
1359 VEX_LEN_0F38F2,
1360 VEX_LEN_0F38F3,
1361 VEX_LEN_0F38F5,
1362 VEX_LEN_0F38F6,
1363 VEX_LEN_0F38F7,
1364 VEX_LEN_0F3A00,
1365 VEX_LEN_0F3A01,
1366 VEX_LEN_0F3A06,
1367 VEX_LEN_0F3A14,
1368 VEX_LEN_0F3A15,
1369 VEX_LEN_0F3A16,
1370 VEX_LEN_0F3A17,
1371 VEX_LEN_0F3A18,
1372 VEX_LEN_0F3A19,
1373 VEX_LEN_0F3A20,
1374 VEX_LEN_0F3A21,
1375 VEX_LEN_0F3A22,
1376 VEX_LEN_0F3A30,
1377 VEX_LEN_0F3A31,
1378 VEX_LEN_0F3A32,
1379 VEX_LEN_0F3A33,
1380 VEX_LEN_0F3A38,
1381 VEX_LEN_0F3A39,
1382 VEX_LEN_0F3A41,
1383 VEX_LEN_0F3A46,
1384 VEX_LEN_0F3A60,
1385 VEX_LEN_0F3A61,
1386 VEX_LEN_0F3A62,
1387 VEX_LEN_0F3A63,
1388 VEX_LEN_0F3ADF,
1389 VEX_LEN_0F3AF0,
1390 VEX_LEN_0FXOP_08_85,
1391 VEX_LEN_0FXOP_08_86,
1392 VEX_LEN_0FXOP_08_87,
1393 VEX_LEN_0FXOP_08_8E,
1394 VEX_LEN_0FXOP_08_8F,
1395 VEX_LEN_0FXOP_08_95,
1396 VEX_LEN_0FXOP_08_96,
1397 VEX_LEN_0FXOP_08_97,
1398 VEX_LEN_0FXOP_08_9E,
1399 VEX_LEN_0FXOP_08_9F,
1400 VEX_LEN_0FXOP_08_A3,
1401 VEX_LEN_0FXOP_08_A6,
1402 VEX_LEN_0FXOP_08_B6,
1403 VEX_LEN_0FXOP_08_C0,
1404 VEX_LEN_0FXOP_08_C1,
1405 VEX_LEN_0FXOP_08_C2,
1406 VEX_LEN_0FXOP_08_C3,
1407 VEX_LEN_0FXOP_08_CC,
1408 VEX_LEN_0FXOP_08_CD,
1409 VEX_LEN_0FXOP_08_CE,
1410 VEX_LEN_0FXOP_08_CF,
1411 VEX_LEN_0FXOP_08_EC,
1412 VEX_LEN_0FXOP_08_ED,
1413 VEX_LEN_0FXOP_08_EE,
1414 VEX_LEN_0FXOP_08_EF,
1415 VEX_LEN_0FXOP_09_01,
1416 VEX_LEN_0FXOP_09_02,
1417 VEX_LEN_0FXOP_09_12_M_1,
1418 VEX_LEN_0FXOP_09_82_W_0,
1419 VEX_LEN_0FXOP_09_83_W_0,
1420 VEX_LEN_0FXOP_09_90,
1421 VEX_LEN_0FXOP_09_91,
1422 VEX_LEN_0FXOP_09_92,
1423 VEX_LEN_0FXOP_09_93,
1424 VEX_LEN_0FXOP_09_94,
1425 VEX_LEN_0FXOP_09_95,
1426 VEX_LEN_0FXOP_09_96,
1427 VEX_LEN_0FXOP_09_97,
1428 VEX_LEN_0FXOP_09_98,
1429 VEX_LEN_0FXOP_09_99,
1430 VEX_LEN_0FXOP_09_9A,
1431 VEX_LEN_0FXOP_09_9B,
1432 VEX_LEN_0FXOP_09_C1,
1433 VEX_LEN_0FXOP_09_C2,
1434 VEX_LEN_0FXOP_09_C3,
1435 VEX_LEN_0FXOP_09_C6,
1436 VEX_LEN_0FXOP_09_C7,
1437 VEX_LEN_0FXOP_09_CB,
1438 VEX_LEN_0FXOP_09_D1,
1439 VEX_LEN_0FXOP_09_D2,
1440 VEX_LEN_0FXOP_09_D3,
1441 VEX_LEN_0FXOP_09_D6,
1442 VEX_LEN_0FXOP_09_D7,
1443 VEX_LEN_0FXOP_09_DB,
1444 VEX_LEN_0FXOP_09_E1,
1445 VEX_LEN_0FXOP_09_E2,
1446 VEX_LEN_0FXOP_09_E3,
1447 VEX_LEN_0FXOP_0A_12,
1448 };
1449
1450 enum
1451 {
1452 EVEX_LEN_0F3816 = 0,
1453 EVEX_LEN_0F3819,
1454 EVEX_LEN_0F381A_M_0,
1455 EVEX_LEN_0F381B_M_0,
1456 EVEX_LEN_0F3836,
1457 EVEX_LEN_0F385A_M_0,
1458 EVEX_LEN_0F385B_M_0,
1459 EVEX_LEN_0F38C6_M_0,
1460 EVEX_LEN_0F38C7_M_0,
1461 EVEX_LEN_0F3A00,
1462 EVEX_LEN_0F3A01,
1463 EVEX_LEN_0F3A18,
1464 EVEX_LEN_0F3A19,
1465 EVEX_LEN_0F3A1A,
1466 EVEX_LEN_0F3A1B,
1467 EVEX_LEN_0F3A23,
1468 EVEX_LEN_0F3A38,
1469 EVEX_LEN_0F3A39,
1470 EVEX_LEN_0F3A3A,
1471 EVEX_LEN_0F3A3B,
1472 EVEX_LEN_0F3A43
1473 };
1474
1475 enum
1476 {
1477 VEX_W_0F41_L_1_M_1 = 0,
1478 VEX_W_0F42_L_1_M_1,
1479 VEX_W_0F44_L_0_M_1,
1480 VEX_W_0F45_L_1_M_1,
1481 VEX_W_0F46_L_1_M_1,
1482 VEX_W_0F47_L_1_M_1,
1483 VEX_W_0F4A_L_1_M_1,
1484 VEX_W_0F4B_L_1_M_1,
1485 VEX_W_0F90_L_0,
1486 VEX_W_0F91_L_0_M_0,
1487 VEX_W_0F92_L_0_M_1,
1488 VEX_W_0F93_L_0_M_1,
1489 VEX_W_0F98_L_0_M_1,
1490 VEX_W_0F99_L_0_M_1,
1491 VEX_W_0F380C,
1492 VEX_W_0F380D,
1493 VEX_W_0F380E,
1494 VEX_W_0F380F,
1495 VEX_W_0F3813,
1496 VEX_W_0F3816_L_1,
1497 VEX_W_0F3818,
1498 VEX_W_0F3819_L_1,
1499 VEX_W_0F381A_M_0_L_1,
1500 VEX_W_0F382C_M_0,
1501 VEX_W_0F382D_M_0,
1502 VEX_W_0F382E_M_0,
1503 VEX_W_0F382F_M_0,
1504 VEX_W_0F3836,
1505 VEX_W_0F3846,
1506 VEX_W_0F3849_X86_64_P_0,
1507 VEX_W_0F3849_X86_64_P_2,
1508 VEX_W_0F3849_X86_64_P_3,
1509 VEX_W_0F384B_X86_64_P_1,
1510 VEX_W_0F384B_X86_64_P_2,
1511 VEX_W_0F384B_X86_64_P_3,
1512 VEX_W_0F3850,
1513 VEX_W_0F3851,
1514 VEX_W_0F3852,
1515 VEX_W_0F3853,
1516 VEX_W_0F3858,
1517 VEX_W_0F3859,
1518 VEX_W_0F385A_M_0_L_0,
1519 VEX_W_0F385C_X86_64_P_1,
1520 VEX_W_0F385E_X86_64_P_0,
1521 VEX_W_0F385E_X86_64_P_1,
1522 VEX_W_0F385E_X86_64_P_2,
1523 VEX_W_0F385E_X86_64_P_3,
1524 VEX_W_0F3878,
1525 VEX_W_0F3879,
1526 VEX_W_0F38CF,
1527 VEX_W_0F3A00_L_1,
1528 VEX_W_0F3A01_L_1,
1529 VEX_W_0F3A02,
1530 VEX_W_0F3A04,
1531 VEX_W_0F3A05,
1532 VEX_W_0F3A06_L_1,
1533 VEX_W_0F3A18_L_1,
1534 VEX_W_0F3A19_L_1,
1535 VEX_W_0F3A1D,
1536 VEX_W_0F3A38_L_1,
1537 VEX_W_0F3A39_L_1,
1538 VEX_W_0F3A46_L_1,
1539 VEX_W_0F3A4A,
1540 VEX_W_0F3A4B,
1541 VEX_W_0F3A4C,
1542 VEX_W_0F3ACE,
1543 VEX_W_0F3ACF,
1544
1545 VEX_W_0FXOP_08_85_L_0,
1546 VEX_W_0FXOP_08_86_L_0,
1547 VEX_W_0FXOP_08_87_L_0,
1548 VEX_W_0FXOP_08_8E_L_0,
1549 VEX_W_0FXOP_08_8F_L_0,
1550 VEX_W_0FXOP_08_95_L_0,
1551 VEX_W_0FXOP_08_96_L_0,
1552 VEX_W_0FXOP_08_97_L_0,
1553 VEX_W_0FXOP_08_9E_L_0,
1554 VEX_W_0FXOP_08_9F_L_0,
1555 VEX_W_0FXOP_08_A6_L_0,
1556 VEX_W_0FXOP_08_B6_L_0,
1557 VEX_W_0FXOP_08_C0_L_0,
1558 VEX_W_0FXOP_08_C1_L_0,
1559 VEX_W_0FXOP_08_C2_L_0,
1560 VEX_W_0FXOP_08_C3_L_0,
1561 VEX_W_0FXOP_08_CC_L_0,
1562 VEX_W_0FXOP_08_CD_L_0,
1563 VEX_W_0FXOP_08_CE_L_0,
1564 VEX_W_0FXOP_08_CF_L_0,
1565 VEX_W_0FXOP_08_EC_L_0,
1566 VEX_W_0FXOP_08_ED_L_0,
1567 VEX_W_0FXOP_08_EE_L_0,
1568 VEX_W_0FXOP_08_EF_L_0,
1569
1570 VEX_W_0FXOP_09_80,
1571 VEX_W_0FXOP_09_81,
1572 VEX_W_0FXOP_09_82,
1573 VEX_W_0FXOP_09_83,
1574 VEX_W_0FXOP_09_C1_L_0,
1575 VEX_W_0FXOP_09_C2_L_0,
1576 VEX_W_0FXOP_09_C3_L_0,
1577 VEX_W_0FXOP_09_C6_L_0,
1578 VEX_W_0FXOP_09_C7_L_0,
1579 VEX_W_0FXOP_09_CB_L_0,
1580 VEX_W_0FXOP_09_D1_L_0,
1581 VEX_W_0FXOP_09_D2_L_0,
1582 VEX_W_0FXOP_09_D3_L_0,
1583 VEX_W_0FXOP_09_D6_L_0,
1584 VEX_W_0FXOP_09_D7_L_0,
1585 VEX_W_0FXOP_09_DB_L_0,
1586 VEX_W_0FXOP_09_E1_L_0,
1587 VEX_W_0FXOP_09_E2_L_0,
1588 VEX_W_0FXOP_09_E3_L_0,
1589
1590 EVEX_W_0F5B_P_0,
1591 EVEX_W_0F62,
1592 EVEX_W_0F66,
1593 EVEX_W_0F6A,
1594 EVEX_W_0F6B,
1595 EVEX_W_0F6C,
1596 EVEX_W_0F6D,
1597 EVEX_W_0F6F_P_1,
1598 EVEX_W_0F6F_P_2,
1599 EVEX_W_0F6F_P_3,
1600 EVEX_W_0F70_P_2,
1601 EVEX_W_0F72_R_2,
1602 EVEX_W_0F72_R_6,
1603 EVEX_W_0F73_R_2,
1604 EVEX_W_0F73_R_6,
1605 EVEX_W_0F76,
1606 EVEX_W_0F78_P_0,
1607 EVEX_W_0F78_P_2,
1608 EVEX_W_0F79_P_0,
1609 EVEX_W_0F79_P_2,
1610 EVEX_W_0F7A_P_1,
1611 EVEX_W_0F7A_P_2,
1612 EVEX_W_0F7A_P_3,
1613 EVEX_W_0F7B_P_2,
1614 EVEX_W_0F7E_P_1,
1615 EVEX_W_0F7F_P_1,
1616 EVEX_W_0F7F_P_2,
1617 EVEX_W_0F7F_P_3,
1618 EVEX_W_0FD2,
1619 EVEX_W_0FD3,
1620 EVEX_W_0FD4,
1621 EVEX_W_0FD6,
1622 EVEX_W_0FE6_P_1,
1623 EVEX_W_0FE7,
1624 EVEX_W_0FF2,
1625 EVEX_W_0FF3,
1626 EVEX_W_0FF4,
1627 EVEX_W_0FFA,
1628 EVEX_W_0FFB,
1629 EVEX_W_0FFE,
1630
1631 EVEX_W_0F3810_P_1,
1632 EVEX_W_0F3810_P_2,
1633 EVEX_W_0F3811_P_1,
1634 EVEX_W_0F3811_P_2,
1635 EVEX_W_0F3812_P_1,
1636 EVEX_W_0F3812_P_2,
1637 EVEX_W_0F3813_P_1,
1638 EVEX_W_0F3814_P_1,
1639 EVEX_W_0F3815_P_1,
1640 EVEX_W_0F3819_L_n,
1641 EVEX_W_0F381A_M_0_L_n,
1642 EVEX_W_0F381B_M_0_L_2,
1643 EVEX_W_0F381E,
1644 EVEX_W_0F381F,
1645 EVEX_W_0F3820_P_1,
1646 EVEX_W_0F3821_P_1,
1647 EVEX_W_0F3822_P_1,
1648 EVEX_W_0F3823_P_1,
1649 EVEX_W_0F3824_P_1,
1650 EVEX_W_0F3825_P_1,
1651 EVEX_W_0F3825_P_2,
1652 EVEX_W_0F3828_P_2,
1653 EVEX_W_0F3829_P_2,
1654 EVEX_W_0F382A_P_1,
1655 EVEX_W_0F382A_P_2,
1656 EVEX_W_0F382B,
1657 EVEX_W_0F3830_P_1,
1658 EVEX_W_0F3831_P_1,
1659 EVEX_W_0F3832_P_1,
1660 EVEX_W_0F3833_P_1,
1661 EVEX_W_0F3834_P_1,
1662 EVEX_W_0F3835_P_1,
1663 EVEX_W_0F3835_P_2,
1664 EVEX_W_0F3837,
1665 EVEX_W_0F383A_P_1,
1666 EVEX_W_0F3859,
1667 EVEX_W_0F385A_M_0_L_n,
1668 EVEX_W_0F385B_M_0_L_2,
1669 EVEX_W_0F3870,
1670 EVEX_W_0F3872_P_2,
1671 EVEX_W_0F387A,
1672 EVEX_W_0F387B,
1673 EVEX_W_0F3883,
1674
1675 EVEX_W_0F3A18_L_n,
1676 EVEX_W_0F3A19_L_n,
1677 EVEX_W_0F3A1A_L_2,
1678 EVEX_W_0F3A1B_L_2,
1679 EVEX_W_0F3A21,
1680 EVEX_W_0F3A23_L_n,
1681 EVEX_W_0F3A38_L_n,
1682 EVEX_W_0F3A39_L_n,
1683 EVEX_W_0F3A3A_L_2,
1684 EVEX_W_0F3A3B_L_2,
1685 EVEX_W_0F3A42,
1686 EVEX_W_0F3A43_L_n,
1687 EVEX_W_0F3A70,
1688 EVEX_W_0F3A72,
1689
1690 EVEX_W_MAP5_5B_P_0,
1691 EVEX_W_MAP5_7A_P_3,
1692 };
1693
1694 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1695
1696 struct dis386 {
1697 const char *name;
1698 struct
1699 {
1700 op_rtn rtn;
1701 int bytemode;
1702 } op[MAX_OPERANDS];
1703 unsigned int prefix_requirement;
1704 };
1705
1706 /* Upper case letters in the instruction names here are macros.
1707 'A' => print 'b' if no register operands or suffix_always is true
1708 'B' => print 'b' if suffix_always is true
1709 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1710 size prefix
1711 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1712 suffix_always is true
1713 'E' => print 'e' if 32-bit form of jcxz
1714 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1715 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1716 'H' => print ",pt" or ",pn" branch hint
1717 'I' unused.
1718 'J' unused.
1719 'K' => print 'd' or 'q' if rex prefix is present.
1720 'L' unused.
1721 'M' => print 'r' if intel_mnemonic is false.
1722 'N' => print 'n' if instruction has no wait "prefix"
1723 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1724 'P' => behave as 'T' except with register operand outside of suffix_always
1725 mode
1726 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1727 is true
1728 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1729 'S' => print 'w', 'l' or 'q' if suffix_always is true
1730 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1731 prefix or if suffix_always is true.
1732 'U' unused.
1733 'V' unused.
1734 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1735 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1736 'Y' unused.
1737 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1738 '!' => change condition from true to false or from false to true.
1739 '%' => add 1 upper case letter to the macro.
1740 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1741 prefix or suffix_always is true (lcall/ljmp).
1742 '@' => in 64bit mode for Intel64 ISA or if instruction
1743 has no operand sizing prefix, print 'q' if suffix_always is true or
1744 nothing otherwise; behave as 'P' in all other cases
1745
1746 2 upper case letter macros:
1747 "XY" => print 'x' or 'y' if suffix_always is true or no register
1748 operands and no broadcast.
1749 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1750 register operands and no broadcast.
1751 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1752 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1753 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1754 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1755 "XV" => print "{vex3}" pseudo prefix
1756 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1757 being false, or no operand at all in 64bit mode, or if suffix_always
1758 is true.
1759 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1760 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1761 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1762 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1763 "BW" => print 'b' or 'w' depending on the VEX.W bit
1764 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1765 an operand size prefix, or suffix_always is true. print
1766 'q' if rex prefix is present.
1767
1768 Many of the above letters print nothing in Intel mode. See "putop"
1769 for the details.
1770
1771 Braces '{' and '}', and vertical bars '|', indicate alternative
1772 mnemonic strings for AT&T and Intel. */
1773
1774 static const struct dis386 dis386[] = {
1775 /* 00 */
1776 { "addB", { Ebh1, Gb }, 0 },
1777 { "addS", { Evh1, Gv }, 0 },
1778 { "addB", { Gb, EbS }, 0 },
1779 { "addS", { Gv, EvS }, 0 },
1780 { "addB", { AL, Ib }, 0 },
1781 { "addS", { eAX, Iv }, 0 },
1782 { X86_64_TABLE (X86_64_06) },
1783 { X86_64_TABLE (X86_64_07) },
1784 /* 08 */
1785 { "orB", { Ebh1, Gb }, 0 },
1786 { "orS", { Evh1, Gv }, 0 },
1787 { "orB", { Gb, EbS }, 0 },
1788 { "orS", { Gv, EvS }, 0 },
1789 { "orB", { AL, Ib }, 0 },
1790 { "orS", { eAX, Iv }, 0 },
1791 { X86_64_TABLE (X86_64_0E) },
1792 { Bad_Opcode }, /* 0x0f extended opcode escape */
1793 /* 10 */
1794 { "adcB", { Ebh1, Gb }, 0 },
1795 { "adcS", { Evh1, Gv }, 0 },
1796 { "adcB", { Gb, EbS }, 0 },
1797 { "adcS", { Gv, EvS }, 0 },
1798 { "adcB", { AL, Ib }, 0 },
1799 { "adcS", { eAX, Iv }, 0 },
1800 { X86_64_TABLE (X86_64_16) },
1801 { X86_64_TABLE (X86_64_17) },
1802 /* 18 */
1803 { "sbbB", { Ebh1, Gb }, 0 },
1804 { "sbbS", { Evh1, Gv }, 0 },
1805 { "sbbB", { Gb, EbS }, 0 },
1806 { "sbbS", { Gv, EvS }, 0 },
1807 { "sbbB", { AL, Ib }, 0 },
1808 { "sbbS", { eAX, Iv }, 0 },
1809 { X86_64_TABLE (X86_64_1E) },
1810 { X86_64_TABLE (X86_64_1F) },
1811 /* 20 */
1812 { "andB", { Ebh1, Gb }, 0 },
1813 { "andS", { Evh1, Gv }, 0 },
1814 { "andB", { Gb, EbS }, 0 },
1815 { "andS", { Gv, EvS }, 0 },
1816 { "andB", { AL, Ib }, 0 },
1817 { "andS", { eAX, Iv }, 0 },
1818 { Bad_Opcode }, /* SEG ES prefix */
1819 { X86_64_TABLE (X86_64_27) },
1820 /* 28 */
1821 { "subB", { Ebh1, Gb }, 0 },
1822 { "subS", { Evh1, Gv }, 0 },
1823 { "subB", { Gb, EbS }, 0 },
1824 { "subS", { Gv, EvS }, 0 },
1825 { "subB", { AL, Ib }, 0 },
1826 { "subS", { eAX, Iv }, 0 },
1827 { Bad_Opcode }, /* SEG CS prefix */
1828 { X86_64_TABLE (X86_64_2F) },
1829 /* 30 */
1830 { "xorB", { Ebh1, Gb }, 0 },
1831 { "xorS", { Evh1, Gv }, 0 },
1832 { "xorB", { Gb, EbS }, 0 },
1833 { "xorS", { Gv, EvS }, 0 },
1834 { "xorB", { AL, Ib }, 0 },
1835 { "xorS", { eAX, Iv }, 0 },
1836 { Bad_Opcode }, /* SEG SS prefix */
1837 { X86_64_TABLE (X86_64_37) },
1838 /* 38 */
1839 { "cmpB", { Eb, Gb }, 0 },
1840 { "cmpS", { Ev, Gv }, 0 },
1841 { "cmpB", { Gb, EbS }, 0 },
1842 { "cmpS", { Gv, EvS }, 0 },
1843 { "cmpB", { AL, Ib }, 0 },
1844 { "cmpS", { eAX, Iv }, 0 },
1845 { Bad_Opcode }, /* SEG DS prefix */
1846 { X86_64_TABLE (X86_64_3F) },
1847 /* 40 */
1848 { "inc{S|}", { RMeAX }, 0 },
1849 { "inc{S|}", { RMeCX }, 0 },
1850 { "inc{S|}", { RMeDX }, 0 },
1851 { "inc{S|}", { RMeBX }, 0 },
1852 { "inc{S|}", { RMeSP }, 0 },
1853 { "inc{S|}", { RMeBP }, 0 },
1854 { "inc{S|}", { RMeSI }, 0 },
1855 { "inc{S|}", { RMeDI }, 0 },
1856 /* 48 */
1857 { "dec{S|}", { RMeAX }, 0 },
1858 { "dec{S|}", { RMeCX }, 0 },
1859 { "dec{S|}", { RMeDX }, 0 },
1860 { "dec{S|}", { RMeBX }, 0 },
1861 { "dec{S|}", { RMeSP }, 0 },
1862 { "dec{S|}", { RMeBP }, 0 },
1863 { "dec{S|}", { RMeSI }, 0 },
1864 { "dec{S|}", { RMeDI }, 0 },
1865 /* 50 */
1866 { "push{!P|}", { RMrAX }, 0 },
1867 { "push{!P|}", { RMrCX }, 0 },
1868 { "push{!P|}", { RMrDX }, 0 },
1869 { "push{!P|}", { RMrBX }, 0 },
1870 { "push{!P|}", { RMrSP }, 0 },
1871 { "push{!P|}", { RMrBP }, 0 },
1872 { "push{!P|}", { RMrSI }, 0 },
1873 { "push{!P|}", { RMrDI }, 0 },
1874 /* 58 */
1875 { "pop{!P|}", { RMrAX }, 0 },
1876 { "pop{!P|}", { RMrCX }, 0 },
1877 { "pop{!P|}", { RMrDX }, 0 },
1878 { "pop{!P|}", { RMrBX }, 0 },
1879 { "pop{!P|}", { RMrSP }, 0 },
1880 { "pop{!P|}", { RMrBP }, 0 },
1881 { "pop{!P|}", { RMrSI }, 0 },
1882 { "pop{!P|}", { RMrDI }, 0 },
1883 /* 60 */
1884 { X86_64_TABLE (X86_64_60) },
1885 { X86_64_TABLE (X86_64_61) },
1886 { X86_64_TABLE (X86_64_62) },
1887 { X86_64_TABLE (X86_64_63) },
1888 { Bad_Opcode }, /* seg fs */
1889 { Bad_Opcode }, /* seg gs */
1890 { Bad_Opcode }, /* op size prefix */
1891 { Bad_Opcode }, /* adr size prefix */
1892 /* 68 */
1893 { "pushP", { sIv }, 0 },
1894 { "imulS", { Gv, Ev, Iv }, 0 },
1895 { "pushP", { sIbT }, 0 },
1896 { "imulS", { Gv, Ev, sIb }, 0 },
1897 { "ins{b|}", { Ybr, indirDX }, 0 },
1898 { X86_64_TABLE (X86_64_6D) },
1899 { "outs{b|}", { indirDXr, Xb }, 0 },
1900 { X86_64_TABLE (X86_64_6F) },
1901 /* 70 */
1902 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1903 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1904 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1905 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1906 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1907 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1908 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1909 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1910 /* 78 */
1911 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1912 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1913 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1914 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1915 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1916 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1917 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1918 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1919 /* 80 */
1920 { REG_TABLE (REG_80) },
1921 { REG_TABLE (REG_81) },
1922 { X86_64_TABLE (X86_64_82) },
1923 { REG_TABLE (REG_83) },
1924 { "testB", { Eb, Gb }, 0 },
1925 { "testS", { Ev, Gv }, 0 },
1926 { "xchgB", { Ebh2, Gb }, 0 },
1927 { "xchgS", { Evh2, Gv }, 0 },
1928 /* 88 */
1929 { "movB", { Ebh3, Gb }, 0 },
1930 { "movS", { Evh3, Gv }, 0 },
1931 { "movB", { Gb, EbS }, 0 },
1932 { "movS", { Gv, EvS }, 0 },
1933 { "movD", { Sv, Sw }, 0 },
1934 { MOD_TABLE (MOD_8D) },
1935 { "movD", { Sw, Sv }, 0 },
1936 { REG_TABLE (REG_8F) },
1937 /* 90 */
1938 { PREFIX_TABLE (PREFIX_90) },
1939 { "xchgS", { RMeCX, eAX }, 0 },
1940 { "xchgS", { RMeDX, eAX }, 0 },
1941 { "xchgS", { RMeBX, eAX }, 0 },
1942 { "xchgS", { RMeSP, eAX }, 0 },
1943 { "xchgS", { RMeBP, eAX }, 0 },
1944 { "xchgS", { RMeSI, eAX }, 0 },
1945 { "xchgS", { RMeDI, eAX }, 0 },
1946 /* 98 */
1947 { "cW{t|}R", { XX }, 0 },
1948 { "cR{t|}O", { XX }, 0 },
1949 { X86_64_TABLE (X86_64_9A) },
1950 { Bad_Opcode }, /* fwait */
1951 { "pushfP", { XX }, 0 },
1952 { "popfP", { XX }, 0 },
1953 { "sahf", { XX }, 0 },
1954 { "lahf", { XX }, 0 },
1955 /* a0 */
1956 { "mov%LB", { AL, Ob }, 0 },
1957 { "mov%LS", { eAX, Ov }, 0 },
1958 { "mov%LB", { Ob, AL }, 0 },
1959 { "mov%LS", { Ov, eAX }, 0 },
1960 { "movs{b|}", { Ybr, Xb }, 0 },
1961 { "movs{R|}", { Yvr, Xv }, 0 },
1962 { "cmps{b|}", { Xb, Yb }, 0 },
1963 { "cmps{R|}", { Xv, Yv }, 0 },
1964 /* a8 */
1965 { "testB", { AL, Ib }, 0 },
1966 { "testS", { eAX, Iv }, 0 },
1967 { "stosB", { Ybr, AL }, 0 },
1968 { "stosS", { Yvr, eAX }, 0 },
1969 { "lodsB", { ALr, Xb }, 0 },
1970 { "lodsS", { eAXr, Xv }, 0 },
1971 { "scasB", { AL, Yb }, 0 },
1972 { "scasS", { eAX, Yv }, 0 },
1973 /* b0 */
1974 { "movB", { RMAL, Ib }, 0 },
1975 { "movB", { RMCL, Ib }, 0 },
1976 { "movB", { RMDL, Ib }, 0 },
1977 { "movB", { RMBL, Ib }, 0 },
1978 { "movB", { RMAH, Ib }, 0 },
1979 { "movB", { RMCH, Ib }, 0 },
1980 { "movB", { RMDH, Ib }, 0 },
1981 { "movB", { RMBH, Ib }, 0 },
1982 /* b8 */
1983 { "mov%LV", { RMeAX, Iv64 }, 0 },
1984 { "mov%LV", { RMeCX, Iv64 }, 0 },
1985 { "mov%LV", { RMeDX, Iv64 }, 0 },
1986 { "mov%LV", { RMeBX, Iv64 }, 0 },
1987 { "mov%LV", { RMeSP, Iv64 }, 0 },
1988 { "mov%LV", { RMeBP, Iv64 }, 0 },
1989 { "mov%LV", { RMeSI, Iv64 }, 0 },
1990 { "mov%LV", { RMeDI, Iv64 }, 0 },
1991 /* c0 */
1992 { REG_TABLE (REG_C0) },
1993 { REG_TABLE (REG_C1) },
1994 { X86_64_TABLE (X86_64_C2) },
1995 { X86_64_TABLE (X86_64_C3) },
1996 { X86_64_TABLE (X86_64_C4) },
1997 { X86_64_TABLE (X86_64_C5) },
1998 { REG_TABLE (REG_C6) },
1999 { REG_TABLE (REG_C7) },
2000 /* c8 */
2001 { "enterP", { Iw, Ib }, 0 },
2002 { "leaveP", { XX }, 0 },
2003 { "{l|}ret{|f}%LP", { Iw }, 0 },
2004 { "{l|}ret{|f}%LP", { XX }, 0 },
2005 { "int3", { XX }, 0 },
2006 { "int", { Ib }, 0 },
2007 { X86_64_TABLE (X86_64_CE) },
2008 { "iret%LP", { XX }, 0 },
2009 /* d0 */
2010 { REG_TABLE (REG_D0) },
2011 { REG_TABLE (REG_D1) },
2012 { REG_TABLE (REG_D2) },
2013 { REG_TABLE (REG_D3) },
2014 { X86_64_TABLE (X86_64_D4) },
2015 { X86_64_TABLE (X86_64_D5) },
2016 { Bad_Opcode },
2017 { "xlat", { DSBX }, 0 },
2018 /* d8 */
2019 { FLOAT },
2020 { FLOAT },
2021 { FLOAT },
2022 { FLOAT },
2023 { FLOAT },
2024 { FLOAT },
2025 { FLOAT },
2026 { FLOAT },
2027 /* e0 */
2028 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2029 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2030 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2031 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2032 { "inB", { AL, Ib }, 0 },
2033 { "inG", { zAX, Ib }, 0 },
2034 { "outB", { Ib, AL }, 0 },
2035 { "outG", { Ib, zAX }, 0 },
2036 /* e8 */
2037 { X86_64_TABLE (X86_64_E8) },
2038 { X86_64_TABLE (X86_64_E9) },
2039 { X86_64_TABLE (X86_64_EA) },
2040 { "jmp", { Jb, BND }, 0 },
2041 { "inB", { AL, indirDX }, 0 },
2042 { "inG", { zAX, indirDX }, 0 },
2043 { "outB", { indirDX, AL }, 0 },
2044 { "outG", { indirDX, zAX }, 0 },
2045 /* f0 */
2046 { Bad_Opcode }, /* lock prefix */
2047 { "int1", { XX }, 0 },
2048 { Bad_Opcode }, /* repne */
2049 { Bad_Opcode }, /* repz */
2050 { "hlt", { XX }, 0 },
2051 { "cmc", { XX }, 0 },
2052 { REG_TABLE (REG_F6) },
2053 { REG_TABLE (REG_F7) },
2054 /* f8 */
2055 { "clc", { XX }, 0 },
2056 { "stc", { XX }, 0 },
2057 { "cli", { XX }, 0 },
2058 { "sti", { XX }, 0 },
2059 { "cld", { XX }, 0 },
2060 { "std", { XX }, 0 },
2061 { REG_TABLE (REG_FE) },
2062 { REG_TABLE (REG_FF) },
2063 };
2064
2065 static const struct dis386 dis386_twobyte[] = {
2066 /* 00 */
2067 { REG_TABLE (REG_0F00 ) },
2068 { REG_TABLE (REG_0F01 ) },
2069 { "larS", { Gv, Ew }, 0 },
2070 { "lslS", { Gv, Ew }, 0 },
2071 { Bad_Opcode },
2072 { "syscall", { XX }, 0 },
2073 { "clts", { XX }, 0 },
2074 { "sysret%LQ", { XX }, 0 },
2075 /* 08 */
2076 { "invd", { XX }, 0 },
2077 { PREFIX_TABLE (PREFIX_0F09) },
2078 { Bad_Opcode },
2079 { "ud2", { XX }, 0 },
2080 { Bad_Opcode },
2081 { REG_TABLE (REG_0F0D) },
2082 { "femms", { XX }, 0 },
2083 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2084 /* 10 */
2085 { PREFIX_TABLE (PREFIX_0F10) },
2086 { PREFIX_TABLE (PREFIX_0F11) },
2087 { PREFIX_TABLE (PREFIX_0F12) },
2088 { MOD_TABLE (MOD_0F13) },
2089 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2090 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2091 { PREFIX_TABLE (PREFIX_0F16) },
2092 { MOD_TABLE (MOD_0F17) },
2093 /* 18 */
2094 { REG_TABLE (REG_0F18) },
2095 { "nopQ", { Ev }, 0 },
2096 { PREFIX_TABLE (PREFIX_0F1A) },
2097 { PREFIX_TABLE (PREFIX_0F1B) },
2098 { PREFIX_TABLE (PREFIX_0F1C) },
2099 { "nopQ", { Ev }, 0 },
2100 { PREFIX_TABLE (PREFIX_0F1E) },
2101 { "nopQ", { Ev }, 0 },
2102 /* 20 */
2103 { "movZ", { Em, Cm }, 0 },
2104 { "movZ", { Em, Dm }, 0 },
2105 { "movZ", { Cm, Em }, 0 },
2106 { "movZ", { Dm, Em }, 0 },
2107 { X86_64_TABLE (X86_64_0F24) },
2108 { Bad_Opcode },
2109 { X86_64_TABLE (X86_64_0F26) },
2110 { Bad_Opcode },
2111 /* 28 */
2112 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2113 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2114 { PREFIX_TABLE (PREFIX_0F2A) },
2115 { PREFIX_TABLE (PREFIX_0F2B) },
2116 { PREFIX_TABLE (PREFIX_0F2C) },
2117 { PREFIX_TABLE (PREFIX_0F2D) },
2118 { PREFIX_TABLE (PREFIX_0F2E) },
2119 { PREFIX_TABLE (PREFIX_0F2F) },
2120 /* 30 */
2121 { "wrmsr", { XX }, 0 },
2122 { "rdtsc", { XX }, 0 },
2123 { "rdmsr", { XX }, 0 },
2124 { "rdpmc", { XX }, 0 },
2125 { "sysenter", { SEP }, 0 },
2126 { "sysexit%LQ", { SEP }, 0 },
2127 { Bad_Opcode },
2128 { "getsec", { XX }, 0 },
2129 /* 38 */
2130 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2131 { Bad_Opcode },
2132 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2133 { Bad_Opcode },
2134 { Bad_Opcode },
2135 { Bad_Opcode },
2136 { Bad_Opcode },
2137 { Bad_Opcode },
2138 /* 40 */
2139 { "cmovoS", { Gv, Ev }, 0 },
2140 { "cmovnoS", { Gv, Ev }, 0 },
2141 { "cmovbS", { Gv, Ev }, 0 },
2142 { "cmovaeS", { Gv, Ev }, 0 },
2143 { "cmoveS", { Gv, Ev }, 0 },
2144 { "cmovneS", { Gv, Ev }, 0 },
2145 { "cmovbeS", { Gv, Ev }, 0 },
2146 { "cmovaS", { Gv, Ev }, 0 },
2147 /* 48 */
2148 { "cmovsS", { Gv, Ev }, 0 },
2149 { "cmovnsS", { Gv, Ev }, 0 },
2150 { "cmovpS", { Gv, Ev }, 0 },
2151 { "cmovnpS", { Gv, Ev }, 0 },
2152 { "cmovlS", { Gv, Ev }, 0 },
2153 { "cmovgeS", { Gv, Ev }, 0 },
2154 { "cmovleS", { Gv, Ev }, 0 },
2155 { "cmovgS", { Gv, Ev }, 0 },
2156 /* 50 */
2157 { MOD_TABLE (MOD_0F50) },
2158 { PREFIX_TABLE (PREFIX_0F51) },
2159 { PREFIX_TABLE (PREFIX_0F52) },
2160 { PREFIX_TABLE (PREFIX_0F53) },
2161 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2162 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2163 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2164 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2165 /* 58 */
2166 { PREFIX_TABLE (PREFIX_0F58) },
2167 { PREFIX_TABLE (PREFIX_0F59) },
2168 { PREFIX_TABLE (PREFIX_0F5A) },
2169 { PREFIX_TABLE (PREFIX_0F5B) },
2170 { PREFIX_TABLE (PREFIX_0F5C) },
2171 { PREFIX_TABLE (PREFIX_0F5D) },
2172 { PREFIX_TABLE (PREFIX_0F5E) },
2173 { PREFIX_TABLE (PREFIX_0F5F) },
2174 /* 60 */
2175 { PREFIX_TABLE (PREFIX_0F60) },
2176 { PREFIX_TABLE (PREFIX_0F61) },
2177 { PREFIX_TABLE (PREFIX_0F62) },
2178 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2179 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2180 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2181 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2182 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2183 /* 68 */
2184 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2185 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2186 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2187 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2188 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2189 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2190 { "movK", { MX, Edq }, PREFIX_OPCODE },
2191 { PREFIX_TABLE (PREFIX_0F6F) },
2192 /* 70 */
2193 { PREFIX_TABLE (PREFIX_0F70) },
2194 { MOD_TABLE (MOD_0F71) },
2195 { MOD_TABLE (MOD_0F72) },
2196 { MOD_TABLE (MOD_0F73) },
2197 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2198 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2199 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2200 { "emms", { XX }, PREFIX_OPCODE },
2201 /* 78 */
2202 { PREFIX_TABLE (PREFIX_0F78) },
2203 { PREFIX_TABLE (PREFIX_0F79) },
2204 { Bad_Opcode },
2205 { Bad_Opcode },
2206 { PREFIX_TABLE (PREFIX_0F7C) },
2207 { PREFIX_TABLE (PREFIX_0F7D) },
2208 { PREFIX_TABLE (PREFIX_0F7E) },
2209 { PREFIX_TABLE (PREFIX_0F7F) },
2210 /* 80 */
2211 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2212 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2213 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2214 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2215 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2216 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2217 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2218 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2219 /* 88 */
2220 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2221 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2222 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2223 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2224 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2225 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2226 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2227 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2228 /* 90 */
2229 { "seto", { Eb }, 0 },
2230 { "setno", { Eb }, 0 },
2231 { "setb", { Eb }, 0 },
2232 { "setae", { Eb }, 0 },
2233 { "sete", { Eb }, 0 },
2234 { "setne", { Eb }, 0 },
2235 { "setbe", { Eb }, 0 },
2236 { "seta", { Eb }, 0 },
2237 /* 98 */
2238 { "sets", { Eb }, 0 },
2239 { "setns", { Eb }, 0 },
2240 { "setp", { Eb }, 0 },
2241 { "setnp", { Eb }, 0 },
2242 { "setl", { Eb }, 0 },
2243 { "setge", { Eb }, 0 },
2244 { "setle", { Eb }, 0 },
2245 { "setg", { Eb }, 0 },
2246 /* a0 */
2247 { "pushP", { fs }, 0 },
2248 { "popP", { fs }, 0 },
2249 { "cpuid", { XX }, 0 },
2250 { "btS", { Ev, Gv }, 0 },
2251 { "shldS", { Ev, Gv, Ib }, 0 },
2252 { "shldS", { Ev, Gv, CL }, 0 },
2253 { REG_TABLE (REG_0FA6) },
2254 { REG_TABLE (REG_0FA7) },
2255 /* a8 */
2256 { "pushP", { gs }, 0 },
2257 { "popP", { gs }, 0 },
2258 { "rsm", { XX }, 0 },
2259 { "btsS", { Evh1, Gv }, 0 },
2260 { "shrdS", { Ev, Gv, Ib }, 0 },
2261 { "shrdS", { Ev, Gv, CL }, 0 },
2262 { REG_TABLE (REG_0FAE) },
2263 { "imulS", { Gv, Ev }, 0 },
2264 /* b0 */
2265 { "cmpxchgB", { Ebh1, Gb }, 0 },
2266 { "cmpxchgS", { Evh1, Gv }, 0 },
2267 { MOD_TABLE (MOD_0FB2) },
2268 { "btrS", { Evh1, Gv }, 0 },
2269 { MOD_TABLE (MOD_0FB4) },
2270 { MOD_TABLE (MOD_0FB5) },
2271 { "movz{bR|x}", { Gv, Eb }, 0 },
2272 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2273 /* b8 */
2274 { PREFIX_TABLE (PREFIX_0FB8) },
2275 { "ud1S", { Gv, Ev }, 0 },
2276 { REG_TABLE (REG_0FBA) },
2277 { "btcS", { Evh1, Gv }, 0 },
2278 { PREFIX_TABLE (PREFIX_0FBC) },
2279 { PREFIX_TABLE (PREFIX_0FBD) },
2280 { "movs{bR|x}", { Gv, Eb }, 0 },
2281 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2282 /* c0 */
2283 { "xaddB", { Ebh1, Gb }, 0 },
2284 { "xaddS", { Evh1, Gv }, 0 },
2285 { PREFIX_TABLE (PREFIX_0FC2) },
2286 { MOD_TABLE (MOD_0FC3) },
2287 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2288 { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
2289 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2290 { REG_TABLE (REG_0FC7) },
2291 /* c8 */
2292 { "bswap", { RMeAX }, 0 },
2293 { "bswap", { RMeCX }, 0 },
2294 { "bswap", { RMeDX }, 0 },
2295 { "bswap", { RMeBX }, 0 },
2296 { "bswap", { RMeSP }, 0 },
2297 { "bswap", { RMeBP }, 0 },
2298 { "bswap", { RMeSI }, 0 },
2299 { "bswap", { RMeDI }, 0 },
2300 /* d0 */
2301 { PREFIX_TABLE (PREFIX_0FD0) },
2302 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2303 { "psrld", { MX, EM }, PREFIX_OPCODE },
2304 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2305 { "paddq", { MX, EM }, PREFIX_OPCODE },
2306 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2307 { PREFIX_TABLE (PREFIX_0FD6) },
2308 { MOD_TABLE (MOD_0FD7) },
2309 /* d8 */
2310 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2311 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2312 { "pminub", { MX, EM }, PREFIX_OPCODE },
2313 { "pand", { MX, EM }, PREFIX_OPCODE },
2314 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2315 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2316 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2317 { "pandn", { MX, EM }, PREFIX_OPCODE },
2318 /* e0 */
2319 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2320 { "psraw", { MX, EM }, PREFIX_OPCODE },
2321 { "psrad", { MX, EM }, PREFIX_OPCODE },
2322 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2323 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2324 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2325 { PREFIX_TABLE (PREFIX_0FE6) },
2326 { PREFIX_TABLE (PREFIX_0FE7) },
2327 /* e8 */
2328 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2329 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2330 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2331 { "por", { MX, EM }, PREFIX_OPCODE },
2332 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2333 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2334 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2335 { "pxor", { MX, EM }, PREFIX_OPCODE },
2336 /* f0 */
2337 { PREFIX_TABLE (PREFIX_0FF0) },
2338 { "psllw", { MX, EM }, PREFIX_OPCODE },
2339 { "pslld", { MX, EM }, PREFIX_OPCODE },
2340 { "psllq", { MX, EM }, PREFIX_OPCODE },
2341 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2342 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2343 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2344 { PREFIX_TABLE (PREFIX_0FF7) },
2345 /* f8 */
2346 { "psubb", { MX, EM }, PREFIX_OPCODE },
2347 { "psubw", { MX, EM }, PREFIX_OPCODE },
2348 { "psubd", { MX, EM }, PREFIX_OPCODE },
2349 { "psubq", { MX, EM }, PREFIX_OPCODE },
2350 { "paddb", { MX, EM }, PREFIX_OPCODE },
2351 { "paddw", { MX, EM }, PREFIX_OPCODE },
2352 { "paddd", { MX, EM }, PREFIX_OPCODE },
2353 { "ud0S", { Gv, Ev }, 0 },
2354 };
2355
2356 static const bool onebyte_has_modrm[256] = {
2357 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2358 /* ------------------------------- */
2359 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2360 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2361 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2362 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2363 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2364 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2365 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2366 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2367 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2368 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2369 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2370 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2371 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2372 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2373 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2374 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2375 /* ------------------------------- */
2376 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2377 };
2378
2379 static const bool twobyte_has_modrm[256] = {
2380 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2381 /* ------------------------------- */
2382 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2383 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2384 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2385 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2386 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2387 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2388 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2389 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2390 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2391 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2392 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2393 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2394 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2395 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2396 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2397 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2398 /* ------------------------------- */
2399 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2400 };
2401
2402
2403 struct op
2404 {
2405 const char *name;
2406 unsigned int len;
2407 };
2408
2409 /* If we are accessing mod/rm/reg without need_modrm set, then the
2410 values are stale. Hitting this abort likely indicates that you
2411 need to update onebyte_has_modrm or twobyte_has_modrm. */
2412 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2413
2414 static const char *const intel_index16[] = {
2415 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2416 };
2417
2418 static const char *const att_names64[] = {
2419 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2420 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2421 };
2422 static const char *const att_names32[] = {
2423 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2424 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2425 };
2426 static const char *const att_names16[] = {
2427 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2428 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2429 };
2430 static const char *const att_names8[] = {
2431 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2432 };
2433 static const char *const att_names8rex[] = {
2434 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2435 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2436 };
2437 static const char *const att_names_seg[] = {
2438 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2439 };
2440 static const char att_index64[] = "%riz";
2441 static const char att_index32[] = "%eiz";
2442 static const char *const att_index16[] = {
2443 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2444 };
2445
2446 static const char *const att_names_mm[] = {
2447 "%mm0", "%mm1", "%mm2", "%mm3",
2448 "%mm4", "%mm5", "%mm6", "%mm7"
2449 };
2450
2451 static const char *const att_names_bnd[] = {
2452 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2453 };
2454
2455 static const char *const att_names_xmm[] = {
2456 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2457 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2458 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2459 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2460 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2461 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2462 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2463 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2464 };
2465
2466 static const char *const att_names_ymm[] = {
2467 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2468 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2469 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2470 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2471 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2472 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2473 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2474 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2475 };
2476
2477 static const char *const att_names_zmm[] = {
2478 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2479 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2480 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2481 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2482 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2483 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2484 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2485 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2486 };
2487
2488 static const char *const att_names_tmm[] = {
2489 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2490 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2491 };
2492
2493 static const char *const att_names_mask[] = {
2494 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2495 };
2496
2497 static const char *const names_rounding[] =
2498 {
2499 "{rn-",
2500 "{rd-",
2501 "{ru-",
2502 "{rz-"
2503 };
2504
2505 static const struct dis386 reg_table[][8] = {
2506 /* REG_80 */
2507 {
2508 { "addA", { Ebh1, Ib }, 0 },
2509 { "orA", { Ebh1, Ib }, 0 },
2510 { "adcA", { Ebh1, Ib }, 0 },
2511 { "sbbA", { Ebh1, Ib }, 0 },
2512 { "andA", { Ebh1, Ib }, 0 },
2513 { "subA", { Ebh1, Ib }, 0 },
2514 { "xorA", { Ebh1, Ib }, 0 },
2515 { "cmpA", { Eb, Ib }, 0 },
2516 },
2517 /* REG_81 */
2518 {
2519 { "addQ", { Evh1, Iv }, 0 },
2520 { "orQ", { Evh1, Iv }, 0 },
2521 { "adcQ", { Evh1, Iv }, 0 },
2522 { "sbbQ", { Evh1, Iv }, 0 },
2523 { "andQ", { Evh1, Iv }, 0 },
2524 { "subQ", { Evh1, Iv }, 0 },
2525 { "xorQ", { Evh1, Iv }, 0 },
2526 { "cmpQ", { Ev, Iv }, 0 },
2527 },
2528 /* REG_83 */
2529 {
2530 { "addQ", { Evh1, sIb }, 0 },
2531 { "orQ", { Evh1, sIb }, 0 },
2532 { "adcQ", { Evh1, sIb }, 0 },
2533 { "sbbQ", { Evh1, sIb }, 0 },
2534 { "andQ", { Evh1, sIb }, 0 },
2535 { "subQ", { Evh1, sIb }, 0 },
2536 { "xorQ", { Evh1, sIb }, 0 },
2537 { "cmpQ", { Ev, sIb }, 0 },
2538 },
2539 /* REG_8F */
2540 {
2541 { "pop{P|}", { stackEv }, 0 },
2542 { XOP_8F_TABLE (XOP_09) },
2543 { Bad_Opcode },
2544 { Bad_Opcode },
2545 { Bad_Opcode },
2546 { XOP_8F_TABLE (XOP_09) },
2547 },
2548 /* REG_C0 */
2549 {
2550 { "rolA", { Eb, Ib }, 0 },
2551 { "rorA", { Eb, Ib }, 0 },
2552 { "rclA", { Eb, Ib }, 0 },
2553 { "rcrA", { Eb, Ib }, 0 },
2554 { "shlA", { Eb, Ib }, 0 },
2555 { "shrA", { Eb, Ib }, 0 },
2556 { "shlA", { Eb, Ib }, 0 },
2557 { "sarA", { Eb, Ib }, 0 },
2558 },
2559 /* REG_C1 */
2560 {
2561 { "rolQ", { Ev, Ib }, 0 },
2562 { "rorQ", { Ev, Ib }, 0 },
2563 { "rclQ", { Ev, Ib }, 0 },
2564 { "rcrQ", { Ev, Ib }, 0 },
2565 { "shlQ", { Ev, Ib }, 0 },
2566 { "shrQ", { Ev, Ib }, 0 },
2567 { "shlQ", { Ev, Ib }, 0 },
2568 { "sarQ", { Ev, Ib }, 0 },
2569 },
2570 /* REG_C6 */
2571 {
2572 { "movA", { Ebh3, Ib }, 0 },
2573 { Bad_Opcode },
2574 { Bad_Opcode },
2575 { Bad_Opcode },
2576 { Bad_Opcode },
2577 { Bad_Opcode },
2578 { Bad_Opcode },
2579 { MOD_TABLE (MOD_C6_REG_7) },
2580 },
2581 /* REG_C7 */
2582 {
2583 { "movQ", { Evh3, Iv }, 0 },
2584 { Bad_Opcode },
2585 { Bad_Opcode },
2586 { Bad_Opcode },
2587 { Bad_Opcode },
2588 { Bad_Opcode },
2589 { Bad_Opcode },
2590 { MOD_TABLE (MOD_C7_REG_7) },
2591 },
2592 /* REG_D0 */
2593 {
2594 { "rolA", { Eb, I1 }, 0 },
2595 { "rorA", { Eb, I1 }, 0 },
2596 { "rclA", { Eb, I1 }, 0 },
2597 { "rcrA", { Eb, I1 }, 0 },
2598 { "shlA", { Eb, I1 }, 0 },
2599 { "shrA", { Eb, I1 }, 0 },
2600 { "shlA", { Eb, I1 }, 0 },
2601 { "sarA", { Eb, I1 }, 0 },
2602 },
2603 /* REG_D1 */
2604 {
2605 { "rolQ", { Ev, I1 }, 0 },
2606 { "rorQ", { Ev, I1 }, 0 },
2607 { "rclQ", { Ev, I1 }, 0 },
2608 { "rcrQ", { Ev, I1 }, 0 },
2609 { "shlQ", { Ev, I1 }, 0 },
2610 { "shrQ", { Ev, I1 }, 0 },
2611 { "shlQ", { Ev, I1 }, 0 },
2612 { "sarQ", { Ev, I1 }, 0 },
2613 },
2614 /* REG_D2 */
2615 {
2616 { "rolA", { Eb, CL }, 0 },
2617 { "rorA", { Eb, CL }, 0 },
2618 { "rclA", { Eb, CL }, 0 },
2619 { "rcrA", { Eb, CL }, 0 },
2620 { "shlA", { Eb, CL }, 0 },
2621 { "shrA", { Eb, CL }, 0 },
2622 { "shlA", { Eb, CL }, 0 },
2623 { "sarA", { Eb, CL }, 0 },
2624 },
2625 /* REG_D3 */
2626 {
2627 { "rolQ", { Ev, CL }, 0 },
2628 { "rorQ", { Ev, CL }, 0 },
2629 { "rclQ", { Ev, CL }, 0 },
2630 { "rcrQ", { Ev, CL }, 0 },
2631 { "shlQ", { Ev, CL }, 0 },
2632 { "shrQ", { Ev, CL }, 0 },
2633 { "shlQ", { Ev, CL }, 0 },
2634 { "sarQ", { Ev, CL }, 0 },
2635 },
2636 /* REG_F6 */
2637 {
2638 { "testA", { Eb, Ib }, 0 },
2639 { "testA", { Eb, Ib }, 0 },
2640 { "notA", { Ebh1 }, 0 },
2641 { "negA", { Ebh1 }, 0 },
2642 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2643 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2644 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2645 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2646 },
2647 /* REG_F7 */
2648 {
2649 { "testQ", { Ev, Iv }, 0 },
2650 { "testQ", { Ev, Iv }, 0 },
2651 { "notQ", { Evh1 }, 0 },
2652 { "negQ", { Evh1 }, 0 },
2653 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2654 { "imulQ", { Ev }, 0 },
2655 { "divQ", { Ev }, 0 },
2656 { "idivQ", { Ev }, 0 },
2657 },
2658 /* REG_FE */
2659 {
2660 { "incA", { Ebh1 }, 0 },
2661 { "decA", { Ebh1 }, 0 },
2662 },
2663 /* REG_FF */
2664 {
2665 { "incQ", { Evh1 }, 0 },
2666 { "decQ", { Evh1 }, 0 },
2667 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2668 { MOD_TABLE (MOD_FF_REG_3) },
2669 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2670 { MOD_TABLE (MOD_FF_REG_5) },
2671 { "push{P|}", { stackEv }, 0 },
2672 { Bad_Opcode },
2673 },
2674 /* REG_0F00 */
2675 {
2676 { "sldtD", { Sv }, 0 },
2677 { "strD", { Sv }, 0 },
2678 { "lldt", { Ew }, 0 },
2679 { "ltr", { Ew }, 0 },
2680 { "verr", { Ew }, 0 },
2681 { "verw", { Ew }, 0 },
2682 { Bad_Opcode },
2683 { Bad_Opcode },
2684 },
2685 /* REG_0F01 */
2686 {
2687 { MOD_TABLE (MOD_0F01_REG_0) },
2688 { MOD_TABLE (MOD_0F01_REG_1) },
2689 { MOD_TABLE (MOD_0F01_REG_2) },
2690 { MOD_TABLE (MOD_0F01_REG_3) },
2691 { "smswD", { Sv }, 0 },
2692 { MOD_TABLE (MOD_0F01_REG_5) },
2693 { "lmsw", { Ew }, 0 },
2694 { MOD_TABLE (MOD_0F01_REG_7) },
2695 },
2696 /* REG_0F0D */
2697 {
2698 { "prefetch", { Mb }, 0 },
2699 { "prefetchw", { Mb }, 0 },
2700 { "prefetchwt1", { Mb }, 0 },
2701 { "prefetch", { Mb }, 0 },
2702 { "prefetch", { Mb }, 0 },
2703 { "prefetch", { Mb }, 0 },
2704 { "prefetch", { Mb }, 0 },
2705 { "prefetch", { Mb }, 0 },
2706 },
2707 /* REG_0F18 */
2708 {
2709 { MOD_TABLE (MOD_0F18_REG_0) },
2710 { MOD_TABLE (MOD_0F18_REG_1) },
2711 { MOD_TABLE (MOD_0F18_REG_2) },
2712 { MOD_TABLE (MOD_0F18_REG_3) },
2713 { "nopQ", { Ev }, 0 },
2714 { "nopQ", { Ev }, 0 },
2715 { "nopQ", { Ev }, 0 },
2716 { "nopQ", { Ev }, 0 },
2717 },
2718 /* REG_0F1C_P_0_MOD_0 */
2719 {
2720 { "cldemote", { Mb }, 0 },
2721 { "nopQ", { Ev }, 0 },
2722 { "nopQ", { Ev }, 0 },
2723 { "nopQ", { Ev }, 0 },
2724 { "nopQ", { Ev }, 0 },
2725 { "nopQ", { Ev }, 0 },
2726 { "nopQ", { Ev }, 0 },
2727 { "nopQ", { Ev }, 0 },
2728 },
2729 /* REG_0F1E_P_1_MOD_3 */
2730 {
2731 { "nopQ", { Ev }, PREFIX_IGNORED },
2732 { "rdsspK", { Edq }, 0 },
2733 { "nopQ", { Ev }, PREFIX_IGNORED },
2734 { "nopQ", { Ev }, PREFIX_IGNORED },
2735 { "nopQ", { Ev }, PREFIX_IGNORED },
2736 { "nopQ", { Ev }, PREFIX_IGNORED },
2737 { "nopQ", { Ev }, PREFIX_IGNORED },
2738 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2739 },
2740 /* REG_0F38D8_PREFIX_1 */
2741 {
2742 { "aesencwide128kl", { M }, 0 },
2743 { "aesdecwide128kl", { M }, 0 },
2744 { "aesencwide256kl", { M }, 0 },
2745 { "aesdecwide256kl", { M }, 0 },
2746 },
2747 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2748 {
2749 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2750 },
2751 /* REG_0F71_MOD_0 */
2752 {
2753 { Bad_Opcode },
2754 { Bad_Opcode },
2755 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2756 { Bad_Opcode },
2757 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2758 { Bad_Opcode },
2759 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2760 },
2761 /* REG_0F72_MOD_0 */
2762 {
2763 { Bad_Opcode },
2764 { Bad_Opcode },
2765 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2766 { Bad_Opcode },
2767 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2768 { Bad_Opcode },
2769 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2770 },
2771 /* REG_0F73_MOD_0 */
2772 {
2773 { Bad_Opcode },
2774 { Bad_Opcode },
2775 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2776 { "psrldq", { XS, Ib }, PREFIX_DATA },
2777 { Bad_Opcode },
2778 { Bad_Opcode },
2779 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2780 { "pslldq", { XS, Ib }, PREFIX_DATA },
2781 },
2782 /* REG_0FA6 */
2783 {
2784 { "montmul", { { OP_0f07, 0 } }, 0 },
2785 { "xsha1", { { OP_0f07, 0 } }, 0 },
2786 { "xsha256", { { OP_0f07, 0 } }, 0 },
2787 },
2788 /* REG_0FA7 */
2789 {
2790 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2791 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2792 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2793 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2794 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2795 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2796 },
2797 /* REG_0FAE */
2798 {
2799 { MOD_TABLE (MOD_0FAE_REG_0) },
2800 { MOD_TABLE (MOD_0FAE_REG_1) },
2801 { MOD_TABLE (MOD_0FAE_REG_2) },
2802 { MOD_TABLE (MOD_0FAE_REG_3) },
2803 { MOD_TABLE (MOD_0FAE_REG_4) },
2804 { MOD_TABLE (MOD_0FAE_REG_5) },
2805 { MOD_TABLE (MOD_0FAE_REG_6) },
2806 { MOD_TABLE (MOD_0FAE_REG_7) },
2807 },
2808 /* REG_0FBA */
2809 {
2810 { Bad_Opcode },
2811 { Bad_Opcode },
2812 { Bad_Opcode },
2813 { Bad_Opcode },
2814 { "btQ", { Ev, Ib }, 0 },
2815 { "btsQ", { Evh1, Ib }, 0 },
2816 { "btrQ", { Evh1, Ib }, 0 },
2817 { "btcQ", { Evh1, Ib }, 0 },
2818 },
2819 /* REG_0FC7 */
2820 {
2821 { Bad_Opcode },
2822 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2823 { Bad_Opcode },
2824 { MOD_TABLE (MOD_0FC7_REG_3) },
2825 { MOD_TABLE (MOD_0FC7_REG_4) },
2826 { MOD_TABLE (MOD_0FC7_REG_5) },
2827 { MOD_TABLE (MOD_0FC7_REG_6) },
2828 { MOD_TABLE (MOD_0FC7_REG_7) },
2829 },
2830 /* REG_VEX_0F71_M_0 */
2831 {
2832 { Bad_Opcode },
2833 { Bad_Opcode },
2834 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2835 { Bad_Opcode },
2836 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2837 { Bad_Opcode },
2838 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2839 },
2840 /* REG_VEX_0F72_M_0 */
2841 {
2842 { Bad_Opcode },
2843 { Bad_Opcode },
2844 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2845 { Bad_Opcode },
2846 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2847 { Bad_Opcode },
2848 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2849 },
2850 /* REG_VEX_0F73_M_0 */
2851 {
2852 { Bad_Opcode },
2853 { Bad_Opcode },
2854 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2855 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2856 { Bad_Opcode },
2857 { Bad_Opcode },
2858 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2859 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2860 },
2861 /* REG_VEX_0FAE */
2862 {
2863 { Bad_Opcode },
2864 { Bad_Opcode },
2865 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2866 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2867 },
2868 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2869 {
2870 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2871 },
2872 /* REG_VEX_0F38F3_L_0 */
2873 {
2874 { Bad_Opcode },
2875 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2876 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2877 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2878 },
2879 /* REG_XOP_09_01_L_0 */
2880 {
2881 { Bad_Opcode },
2882 { "blcfill", { VexGdq, Edq }, 0 },
2883 { "blsfill", { VexGdq, Edq }, 0 },
2884 { "blcs", { VexGdq, Edq }, 0 },
2885 { "tzmsk", { VexGdq, Edq }, 0 },
2886 { "blcic", { VexGdq, Edq }, 0 },
2887 { "blsic", { VexGdq, Edq }, 0 },
2888 { "t1mskc", { VexGdq, Edq }, 0 },
2889 },
2890 /* REG_XOP_09_02_L_0 */
2891 {
2892 { Bad_Opcode },
2893 { "blcmsk", { VexGdq, Edq }, 0 },
2894 { Bad_Opcode },
2895 { Bad_Opcode },
2896 { Bad_Opcode },
2897 { Bad_Opcode },
2898 { "blci", { VexGdq, Edq }, 0 },
2899 },
2900 /* REG_XOP_09_12_M_1_L_0 */
2901 {
2902 { "llwpcb", { Edq }, 0 },
2903 { "slwpcb", { Edq }, 0 },
2904 },
2905 /* REG_XOP_0A_12_L_0 */
2906 {
2907 { "lwpins", { VexGdq, Ed, Id }, 0 },
2908 { "lwpval", { VexGdq, Ed, Id }, 0 },
2909 },
2910
2911 #include "i386-dis-evex-reg.h"
2912 };
2913
2914 static const struct dis386 prefix_table[][4] = {
2915 /* PREFIX_90 */
2916 {
2917 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2918 { "pause", { XX }, 0 },
2919 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2920 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2921 },
2922
2923 /* PREFIX_0F01_REG_1_RM_4 */
2924 {
2925 { Bad_Opcode },
2926 { Bad_Opcode },
2927 { "tdcall", { Skip_MODRM }, 0 },
2928 { Bad_Opcode },
2929 },
2930
2931 /* PREFIX_0F01_REG_1_RM_5 */
2932 {
2933 { Bad_Opcode },
2934 { Bad_Opcode },
2935 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2936 { Bad_Opcode },
2937 },
2938
2939 /* PREFIX_0F01_REG_1_RM_6 */
2940 {
2941 { Bad_Opcode },
2942 { Bad_Opcode },
2943 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2944 { Bad_Opcode },
2945 },
2946
2947 /* PREFIX_0F01_REG_1_RM_7 */
2948 {
2949 { "encls", { Skip_MODRM }, 0 },
2950 { Bad_Opcode },
2951 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
2952 { Bad_Opcode },
2953 },
2954
2955 /* PREFIX_0F01_REG_3_RM_1 */
2956 {
2957 { "vmmcall", { Skip_MODRM }, 0 },
2958 { "vmgexit", { Skip_MODRM }, 0 },
2959 { Bad_Opcode },
2960 { "vmgexit", { Skip_MODRM }, 0 },
2961 },
2962
2963 /* PREFIX_0F01_REG_5_MOD_0 */
2964 {
2965 { Bad_Opcode },
2966 { "rstorssp", { Mq }, PREFIX_OPCODE },
2967 },
2968
2969 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
2970 {
2971 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
2972 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
2973 { Bad_Opcode },
2974 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
2975 },
2976
2977 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
2978 {
2979 { Bad_Opcode },
2980 { Bad_Opcode },
2981 { Bad_Opcode },
2982 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
2983 },
2984
2985 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
2986 {
2987 { Bad_Opcode },
2988 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
2989 },
2990
2991 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
2992 {
2993 { Bad_Opcode },
2994 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
2995 },
2996
2997 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
2998 {
2999 { Bad_Opcode },
3000 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3001 },
3002
3003 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3004 {
3005 { "rdpkru", { Skip_MODRM }, 0 },
3006 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3007 },
3008
3009 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3010 {
3011 { "wrpkru", { Skip_MODRM }, 0 },
3012 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3013 },
3014
3015 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3016 {
3017 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3018 { "mcommit", { Skip_MODRM }, 0 },
3019 },
3020
3021 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3022 {
3023 { "invlpgb", { Skip_MODRM }, 0 },
3024 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3025 { Bad_Opcode },
3026 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3027 },
3028
3029 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3030 {
3031 { "tlbsync", { Skip_MODRM }, 0 },
3032 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3033 { Bad_Opcode },
3034 { "pvalidate", { Skip_MODRM }, 0 },
3035 },
3036
3037 /* PREFIX_0F09 */
3038 {
3039 { "wbinvd", { XX }, 0 },
3040 { "wbnoinvd", { XX }, 0 },
3041 },
3042
3043 /* PREFIX_0F10 */
3044 {
3045 { "movups", { XM, EXx }, PREFIX_OPCODE },
3046 { "movss", { XM, EXd }, PREFIX_OPCODE },
3047 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3048 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3049 },
3050
3051 /* PREFIX_0F11 */
3052 {
3053 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3054 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3055 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3056 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3057 },
3058
3059 /* PREFIX_0F12 */
3060 {
3061 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3062 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3063 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3064 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3065 },
3066
3067 /* PREFIX_0F16 */
3068 {
3069 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3070 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3071 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3072 },
3073
3074 /* PREFIX_0F1A */
3075 {
3076 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3077 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3078 { "bndmov", { Gbnd, Ebnd }, 0 },
3079 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3080 },
3081
3082 /* PREFIX_0F1B */
3083 {
3084 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3085 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3086 { "bndmov", { EbndS, Gbnd }, 0 },
3087 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3088 },
3089
3090 /* PREFIX_0F1C */
3091 {
3092 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3093 { "nopQ", { Ev }, PREFIX_IGNORED },
3094 { "nopQ", { Ev }, 0 },
3095 { "nopQ", { Ev }, PREFIX_IGNORED },
3096 },
3097
3098 /* PREFIX_0F1E */
3099 {
3100 { "nopQ", { Ev }, 0 },
3101 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3102 { "nopQ", { Ev }, 0 },
3103 { NULL, { XX }, PREFIX_IGNORED },
3104 },
3105
3106 /* PREFIX_0F2A */
3107 {
3108 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3109 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3110 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3111 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3112 },
3113
3114 /* PREFIX_0F2B */
3115 {
3116 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3117 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3118 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3119 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3120 },
3121
3122 /* PREFIX_0F2C */
3123 {
3124 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3125 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3126 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3127 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3128 },
3129
3130 /* PREFIX_0F2D */
3131 {
3132 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3133 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3134 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3135 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3136 },
3137
3138 /* PREFIX_0F2E */
3139 {
3140 { "ucomiss",{ XM, EXd }, 0 },
3141 { Bad_Opcode },
3142 { "ucomisd",{ XM, EXq }, 0 },
3143 },
3144
3145 /* PREFIX_0F2F */
3146 {
3147 { "comiss", { XM, EXd }, 0 },
3148 { Bad_Opcode },
3149 { "comisd", { XM, EXq }, 0 },
3150 },
3151
3152 /* PREFIX_0F51 */
3153 {
3154 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3155 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3156 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3157 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3158 },
3159
3160 /* PREFIX_0F52 */
3161 {
3162 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3163 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3164 },
3165
3166 /* PREFIX_0F53 */
3167 {
3168 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3169 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3170 },
3171
3172 /* PREFIX_0F58 */
3173 {
3174 { "addps", { XM, EXx }, PREFIX_OPCODE },
3175 { "addss", { XM, EXd }, PREFIX_OPCODE },
3176 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3177 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3178 },
3179
3180 /* PREFIX_0F59 */
3181 {
3182 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3183 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3184 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3185 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3186 },
3187
3188 /* PREFIX_0F5A */
3189 {
3190 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3191 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3192 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3193 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3194 },
3195
3196 /* PREFIX_0F5B */
3197 {
3198 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3199 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3200 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3201 },
3202
3203 /* PREFIX_0F5C */
3204 {
3205 { "subps", { XM, EXx }, PREFIX_OPCODE },
3206 { "subss", { XM, EXd }, PREFIX_OPCODE },
3207 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3208 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3209 },
3210
3211 /* PREFIX_0F5D */
3212 {
3213 { "minps", { XM, EXx }, PREFIX_OPCODE },
3214 { "minss", { XM, EXd }, PREFIX_OPCODE },
3215 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3216 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3217 },
3218
3219 /* PREFIX_0F5E */
3220 {
3221 { "divps", { XM, EXx }, PREFIX_OPCODE },
3222 { "divss", { XM, EXd }, PREFIX_OPCODE },
3223 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3224 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3225 },
3226
3227 /* PREFIX_0F5F */
3228 {
3229 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3230 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3231 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3232 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3233 },
3234
3235 /* PREFIX_0F60 */
3236 {
3237 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3238 { Bad_Opcode },
3239 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3240 },
3241
3242 /* PREFIX_0F61 */
3243 {
3244 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3245 { Bad_Opcode },
3246 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3247 },
3248
3249 /* PREFIX_0F62 */
3250 {
3251 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3252 { Bad_Opcode },
3253 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3254 },
3255
3256 /* PREFIX_0F6F */
3257 {
3258 { "movq", { MX, EM }, PREFIX_OPCODE },
3259 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3260 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3261 },
3262
3263 /* PREFIX_0F70 */
3264 {
3265 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3266 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3267 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3268 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3269 },
3270
3271 /* PREFIX_0F78 */
3272 {
3273 {"vmread", { Em, Gm }, 0 },
3274 { Bad_Opcode },
3275 {"extrq", { XS, Ib, Ib }, 0 },
3276 {"insertq", { XM, XS, Ib, Ib }, 0 },
3277 },
3278
3279 /* PREFIX_0F79 */
3280 {
3281 {"vmwrite", { Gm, Em }, 0 },
3282 { Bad_Opcode },
3283 {"extrq", { XM, XS }, 0 },
3284 {"insertq", { XM, XS }, 0 },
3285 },
3286
3287 /* PREFIX_0F7C */
3288 {
3289 { Bad_Opcode },
3290 { Bad_Opcode },
3291 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3292 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3293 },
3294
3295 /* PREFIX_0F7D */
3296 {
3297 { Bad_Opcode },
3298 { Bad_Opcode },
3299 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3300 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3301 },
3302
3303 /* PREFIX_0F7E */
3304 {
3305 { "movK", { Edq, MX }, PREFIX_OPCODE },
3306 { "movq", { XM, EXq }, PREFIX_OPCODE },
3307 { "movK", { Edq, XM }, PREFIX_OPCODE },
3308 },
3309
3310 /* PREFIX_0F7F */
3311 {
3312 { "movq", { EMS, MX }, PREFIX_OPCODE },
3313 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3314 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3315 },
3316
3317 /* PREFIX_0FAE_REG_0_MOD_3 */
3318 {
3319 { Bad_Opcode },
3320 { "rdfsbase", { Ev }, 0 },
3321 },
3322
3323 /* PREFIX_0FAE_REG_1_MOD_3 */
3324 {
3325 { Bad_Opcode },
3326 { "rdgsbase", { Ev }, 0 },
3327 },
3328
3329 /* PREFIX_0FAE_REG_2_MOD_3 */
3330 {
3331 { Bad_Opcode },
3332 { "wrfsbase", { Ev }, 0 },
3333 },
3334
3335 /* PREFIX_0FAE_REG_3_MOD_3 */
3336 {
3337 { Bad_Opcode },
3338 { "wrgsbase", { Ev }, 0 },
3339 },
3340
3341 /* PREFIX_0FAE_REG_4_MOD_0 */
3342 {
3343 { "xsave", { FXSAVE }, 0 },
3344 { "ptwrite{%LQ|}", { Edq }, 0 },
3345 },
3346
3347 /* PREFIX_0FAE_REG_4_MOD_3 */
3348 {
3349 { Bad_Opcode },
3350 { "ptwrite{%LQ|}", { Edq }, 0 },
3351 },
3352
3353 /* PREFIX_0FAE_REG_5_MOD_3 */
3354 {
3355 { "lfence", { Skip_MODRM }, 0 },
3356 { "incsspK", { Edq }, PREFIX_OPCODE },
3357 },
3358
3359 /* PREFIX_0FAE_REG_6_MOD_0 */
3360 {
3361 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3362 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3363 { "clwb", { Mb }, PREFIX_OPCODE },
3364 },
3365
3366 /* PREFIX_0FAE_REG_6_MOD_3 */
3367 {
3368 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3369 { "umonitor", { Eva }, PREFIX_OPCODE },
3370 { "tpause", { Edq }, PREFIX_OPCODE },
3371 { "umwait", { Edq }, PREFIX_OPCODE },
3372 },
3373
3374 /* PREFIX_0FAE_REG_7_MOD_0 */
3375 {
3376 { "clflush", { Mb }, 0 },
3377 { Bad_Opcode },
3378 { "clflushopt", { Mb }, 0 },
3379 },
3380
3381 /* PREFIX_0FB8 */
3382 {
3383 { Bad_Opcode },
3384 { "popcntS", { Gv, Ev }, 0 },
3385 },
3386
3387 /* PREFIX_0FBC */
3388 {
3389 { "bsfS", { Gv, Ev }, 0 },
3390 { "tzcntS", { Gv, Ev }, 0 },
3391 { "bsfS", { Gv, Ev }, 0 },
3392 },
3393
3394 /* PREFIX_0FBD */
3395 {
3396 { "bsrS", { Gv, Ev }, 0 },
3397 { "lzcntS", { Gv, Ev }, 0 },
3398 { "bsrS", { Gv, Ev }, 0 },
3399 },
3400
3401 /* PREFIX_0FC2 */
3402 {
3403 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3404 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3405 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3406 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3407 },
3408
3409 /* PREFIX_0FC7_REG_6_MOD_0 */
3410 {
3411 { "vmptrld",{ Mq }, 0 },
3412 { "vmxon", { Mq }, 0 },
3413 { "vmclear",{ Mq }, 0 },
3414 },
3415
3416 /* PREFIX_0FC7_REG_6_MOD_3 */
3417 {
3418 { "rdrand", { Ev }, 0 },
3419 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3420 { "rdrand", { Ev }, 0 }
3421 },
3422
3423 /* PREFIX_0FC7_REG_7_MOD_3 */
3424 {
3425 { "rdseed", { Ev }, 0 },
3426 { "rdpid", { Em }, 0 },
3427 { "rdseed", { Ev }, 0 },
3428 },
3429
3430 /* PREFIX_0FD0 */
3431 {
3432 { Bad_Opcode },
3433 { Bad_Opcode },
3434 { "addsubpd", { XM, EXx }, 0 },
3435 { "addsubps", { XM, EXx }, 0 },
3436 },
3437
3438 /* PREFIX_0FD6 */
3439 {
3440 { Bad_Opcode },
3441 { "movq2dq",{ XM, MS }, 0 },
3442 { "movq", { EXqS, XM }, 0 },
3443 { "movdq2q",{ MX, XS }, 0 },
3444 },
3445
3446 /* PREFIX_0FE6 */
3447 {
3448 { Bad_Opcode },
3449 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3450 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3451 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3452 },
3453
3454 /* PREFIX_0FE7 */
3455 {
3456 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3457 { Bad_Opcode },
3458 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3459 },
3460
3461 /* PREFIX_0FF0 */
3462 {
3463 { Bad_Opcode },
3464 { Bad_Opcode },
3465 { Bad_Opcode },
3466 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3467 },
3468
3469 /* PREFIX_0FF7 */
3470 {
3471 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3472 { Bad_Opcode },
3473 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3474 },
3475
3476 /* PREFIX_0F38D8 */
3477 {
3478 { Bad_Opcode },
3479 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3480 },
3481
3482 /* PREFIX_0F38DC */
3483 {
3484 { Bad_Opcode },
3485 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3486 { "aesenc", { XM, EXx }, 0 },
3487 },
3488
3489 /* PREFIX_0F38DD */
3490 {
3491 { Bad_Opcode },
3492 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3493 { "aesenclast", { XM, EXx }, 0 },
3494 },
3495
3496 /* PREFIX_0F38DE */
3497 {
3498 { Bad_Opcode },
3499 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3500 { "aesdec", { XM, EXx }, 0 },
3501 },
3502
3503 /* PREFIX_0F38DF */
3504 {
3505 { Bad_Opcode },
3506 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3507 { "aesdeclast", { XM, EXx }, 0 },
3508 },
3509
3510 /* PREFIX_0F38F0 */
3511 {
3512 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3513 { Bad_Opcode },
3514 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3515 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3516 },
3517
3518 /* PREFIX_0F38F1 */
3519 {
3520 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3521 { Bad_Opcode },
3522 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3523 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3524 },
3525
3526 /* PREFIX_0F38F6 */
3527 {
3528 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3529 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3530 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3531 { Bad_Opcode },
3532 },
3533
3534 /* PREFIX_0F38F8 */
3535 {
3536 { Bad_Opcode },
3537 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3538 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3539 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3540 },
3541 /* PREFIX_0F38FA */
3542 {
3543 { Bad_Opcode },
3544 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3545 },
3546
3547 /* PREFIX_0F38FB */
3548 {
3549 { Bad_Opcode },
3550 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3551 },
3552
3553 /* PREFIX_0F3A0F */
3554 {
3555 { Bad_Opcode },
3556 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3557 },
3558
3559 /* PREFIX_VEX_0F10 */
3560 {
3561 { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3562 { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3563 { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3564 { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3565 },
3566
3567 /* PREFIX_VEX_0F11 */
3568 {
3569 { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3570 { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3571 { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3572 { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3573 },
3574
3575 /* PREFIX_VEX_0F12 */
3576 {
3577 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3578 { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3579 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3580 { "vmov%XDdup", { XM, EXymmq }, 0 },
3581 },
3582
3583 /* PREFIX_VEX_0F16 */
3584 {
3585 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3586 { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3587 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3588 },
3589
3590 /* PREFIX_VEX_0F2A */
3591 {
3592 { Bad_Opcode },
3593 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3594 { Bad_Opcode },
3595 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3596 },
3597
3598 /* PREFIX_VEX_0F2C */
3599 {
3600 { Bad_Opcode },
3601 { "vcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3602 { Bad_Opcode },
3603 { "vcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3604 },
3605
3606 /* PREFIX_VEX_0F2D */
3607 {
3608 { Bad_Opcode },
3609 { "vcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3610 { Bad_Opcode },
3611 { "vcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3612 },
3613
3614 /* PREFIX_VEX_0F2E */
3615 {
3616 { "vucomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3617 { Bad_Opcode },
3618 { "vucomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3619 },
3620
3621 /* PREFIX_VEX_0F2F */
3622 {
3623 { "vcomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3624 { Bad_Opcode },
3625 { "vcomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3626 },
3627
3628 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3629 {
3630 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3631 { Bad_Opcode },
3632 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3633 },
3634
3635 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3636 {
3637 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3638 { Bad_Opcode },
3639 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3640 },
3641
3642 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3643 {
3644 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3645 { Bad_Opcode },
3646 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3647 },
3648
3649 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3650 {
3651 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3652 { Bad_Opcode },
3653 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3654 },
3655
3656 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3657 {
3658 { "knotw", { MaskG, MaskE }, 0 },
3659 { Bad_Opcode },
3660 { "knotb", { MaskG, MaskE }, 0 },
3661 },
3662
3663 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3664 {
3665 { "knotq", { MaskG, MaskE }, 0 },
3666 { Bad_Opcode },
3667 { "knotd", { MaskG, MaskE }, 0 },
3668 },
3669
3670 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3671 {
3672 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3673 { Bad_Opcode },
3674 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3675 },
3676
3677 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3678 {
3679 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3680 { Bad_Opcode },
3681 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3682 },
3683
3684 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3685 {
3686 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3687 { Bad_Opcode },
3688 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3689 },
3690
3691 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3692 {
3693 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3694 { Bad_Opcode },
3695 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3696 },
3697
3698 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3699 {
3700 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3701 { Bad_Opcode },
3702 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3703 },
3704
3705 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3706 {
3707 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3708 { Bad_Opcode },
3709 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3710 },
3711
3712 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3713 {
3714 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3715 { Bad_Opcode },
3716 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3717 },
3718
3719 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3720 {
3721 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3722 { Bad_Opcode },
3723 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3724 },
3725
3726 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3727 {
3728 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3729 { Bad_Opcode },
3730 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3731 },
3732
3733 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3734 {
3735 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3736 },
3737
3738 /* PREFIX_VEX_0F51 */
3739 {
3740 { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3741 { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3742 { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3743 { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3744 },
3745
3746 /* PREFIX_VEX_0F52 */
3747 {
3748 { "vrsqrtps", { XM, EXx }, 0 },
3749 { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3750 },
3751
3752 /* PREFIX_VEX_0F53 */
3753 {
3754 { "vrcpps", { XM, EXx }, 0 },
3755 { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3756 },
3757
3758 /* PREFIX_VEX_0F58 */
3759 {
3760 { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3761 { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3762 { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3763 { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3764 },
3765
3766 /* PREFIX_VEX_0F59 */
3767 {
3768 { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3769 { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3770 { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3771 { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F5A */
3775 {
3776 { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3777 { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3778 { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3779 { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3780 },
3781
3782 /* PREFIX_VEX_0F5B */
3783 {
3784 { "vcvtdq2ps", { XM, EXx }, 0 },
3785 { "vcvttps2dq", { XM, EXx }, 0 },
3786 { "vcvtps2dq", { XM, EXx }, 0 },
3787 },
3788
3789 /* PREFIX_VEX_0F5C */
3790 {
3791 { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3792 { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3793 { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3794 { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3795 },
3796
3797 /* PREFIX_VEX_0F5D */
3798 {
3799 { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3800 { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3801 { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3802 { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3803 },
3804
3805 /* PREFIX_VEX_0F5E */
3806 {
3807 { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3808 { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3809 { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3810 { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3811 },
3812
3813 /* PREFIX_VEX_0F5F */
3814 {
3815 { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3816 { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3817 { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3818 { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3819 },
3820
3821 /* PREFIX_VEX_0F6F */
3822 {
3823 { Bad_Opcode },
3824 { "vmovdqu", { XM, EXx }, 0 },
3825 { "vmovdqa", { XM, EXx }, 0 },
3826 },
3827
3828 /* PREFIX_VEX_0F70 */
3829 {
3830 { Bad_Opcode },
3831 { "vpshufhw", { XM, EXx, Ib }, 0 },
3832 { "vpshufd", { XM, EXx, Ib }, 0 },
3833 { "vpshuflw", { XM, EXx, Ib }, 0 },
3834 },
3835
3836 /* PREFIX_VEX_0F7C */
3837 {
3838 { Bad_Opcode },
3839 { Bad_Opcode },
3840 { "vhaddpd", { XM, Vex, EXx }, 0 },
3841 { "vhaddps", { XM, Vex, EXx }, 0 },
3842 },
3843
3844 /* PREFIX_VEX_0F7D */
3845 {
3846 { Bad_Opcode },
3847 { Bad_Opcode },
3848 { "vhsubpd", { XM, Vex, EXx }, 0 },
3849 { "vhsubps", { XM, Vex, EXx }, 0 },
3850 },
3851
3852 /* PREFIX_VEX_0F7E */
3853 {
3854 { Bad_Opcode },
3855 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3856 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3857 },
3858
3859 /* PREFIX_VEX_0F7F */
3860 {
3861 { Bad_Opcode },
3862 { "vmovdqu", { EXxS, XM }, 0 },
3863 { "vmovdqa", { EXxS, XM }, 0 },
3864 },
3865
3866 /* PREFIX_VEX_0F90_L_0_W_0 */
3867 {
3868 { "kmovw", { MaskG, MaskE }, 0 },
3869 { Bad_Opcode },
3870 { "kmovb", { MaskG, MaskBDE }, 0 },
3871 },
3872
3873 /* PREFIX_VEX_0F90_L_0_W_1 */
3874 {
3875 { "kmovq", { MaskG, MaskE }, 0 },
3876 { Bad_Opcode },
3877 { "kmovd", { MaskG, MaskBDE }, 0 },
3878 },
3879
3880 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3881 {
3882 { "kmovw", { Ew, MaskG }, 0 },
3883 { Bad_Opcode },
3884 { "kmovb", { Eb, MaskG }, 0 },
3885 },
3886
3887 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3888 {
3889 { "kmovq", { Eq, MaskG }, 0 },
3890 { Bad_Opcode },
3891 { "kmovd", { Ed, MaskG }, 0 },
3892 },
3893
3894 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3895 {
3896 { "kmovw", { MaskG, Edq }, 0 },
3897 { Bad_Opcode },
3898 { "kmovb", { MaskG, Edq }, 0 },
3899 { "kmovd", { MaskG, Edq }, 0 },
3900 },
3901
3902 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3903 {
3904 { Bad_Opcode },
3905 { Bad_Opcode },
3906 { Bad_Opcode },
3907 { "kmovK", { MaskG, Edq }, 0 },
3908 },
3909
3910 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3911 {
3912 { "kmovw", { Gdq, MaskE }, 0 },
3913 { Bad_Opcode },
3914 { "kmovb", { Gdq, MaskE }, 0 },
3915 { "kmovd", { Gdq, MaskE }, 0 },
3916 },
3917
3918 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3919 {
3920 { Bad_Opcode },
3921 { Bad_Opcode },
3922 { Bad_Opcode },
3923 { "kmovK", { Gdq, MaskE }, 0 },
3924 },
3925
3926 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3927 {
3928 { "kortestw", { MaskG, MaskE }, 0 },
3929 { Bad_Opcode },
3930 { "kortestb", { MaskG, MaskE }, 0 },
3931 },
3932
3933 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3934 {
3935 { "kortestq", { MaskG, MaskE }, 0 },
3936 { Bad_Opcode },
3937 { "kortestd", { MaskG, MaskE }, 0 },
3938 },
3939
3940 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3941 {
3942 { "ktestw", { MaskG, MaskE }, 0 },
3943 { Bad_Opcode },
3944 { "ktestb", { MaskG, MaskE }, 0 },
3945 },
3946
3947 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3948 {
3949 { "ktestq", { MaskG, MaskE }, 0 },
3950 { Bad_Opcode },
3951 { "ktestd", { MaskG, MaskE }, 0 },
3952 },
3953
3954 /* PREFIX_VEX_0FC2 */
3955 {
3956 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3957 { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3958 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3959 { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3960 },
3961
3962 /* PREFIX_VEX_0FD0 */
3963 {
3964 { Bad_Opcode },
3965 { Bad_Opcode },
3966 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3967 { "vaddsubps", { XM, Vex, EXx }, 0 },
3968 },
3969
3970 /* PREFIX_VEX_0FE6 */
3971 {
3972 { Bad_Opcode },
3973 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3974 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3975 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3976 },
3977
3978 /* PREFIX_VEX_0FF0 */
3979 {
3980 { Bad_Opcode },
3981 { Bad_Opcode },
3982 { Bad_Opcode },
3983 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3984 },
3985
3986 /* PREFIX_VEX_0F3849_X86_64 */
3987 {
3988 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3989 { Bad_Opcode },
3990 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3991 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3992 },
3993
3994 /* PREFIX_VEX_0F384B_X86_64 */
3995 {
3996 { Bad_Opcode },
3997 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3998 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3999 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4000 },
4001
4002 /* PREFIX_VEX_0F385C_X86_64 */
4003 {
4004 { Bad_Opcode },
4005 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4006 { Bad_Opcode },
4007 },
4008
4009 /* PREFIX_VEX_0F385E_X86_64 */
4010 {
4011 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4012 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4013 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4014 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4015 },
4016
4017 /* PREFIX_VEX_0F38F5_L_0 */
4018 {
4019 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4020 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4021 { Bad_Opcode },
4022 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4023 },
4024
4025 /* PREFIX_VEX_0F38F6_L_0 */
4026 {
4027 { Bad_Opcode },
4028 { Bad_Opcode },
4029 { Bad_Opcode },
4030 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4031 },
4032
4033 /* PREFIX_VEX_0F38F7_L_0 */
4034 {
4035 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4036 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4037 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4038 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4039 },
4040
4041 /* PREFIX_VEX_0F3AF0_L_0 */
4042 {
4043 { Bad_Opcode },
4044 { Bad_Opcode },
4045 { Bad_Opcode },
4046 { "rorxS", { Gdq, Edq, Ib }, 0 },
4047 },
4048
4049 #include "i386-dis-evex-prefix.h"
4050 };
4051
4052 static const struct dis386 x86_64_table[][2] = {
4053 /* X86_64_06 */
4054 {
4055 { "pushP", { es }, 0 },
4056 },
4057
4058 /* X86_64_07 */
4059 {
4060 { "popP", { es }, 0 },
4061 },
4062
4063 /* X86_64_0E */
4064 {
4065 { "pushP", { cs }, 0 },
4066 },
4067
4068 /* X86_64_16 */
4069 {
4070 { "pushP", { ss }, 0 },
4071 },
4072
4073 /* X86_64_17 */
4074 {
4075 { "popP", { ss }, 0 },
4076 },
4077
4078 /* X86_64_1E */
4079 {
4080 { "pushP", { ds }, 0 },
4081 },
4082
4083 /* X86_64_1F */
4084 {
4085 { "popP", { ds }, 0 },
4086 },
4087
4088 /* X86_64_27 */
4089 {
4090 { "daa", { XX }, 0 },
4091 },
4092
4093 /* X86_64_2F */
4094 {
4095 { "das", { XX }, 0 },
4096 },
4097
4098 /* X86_64_37 */
4099 {
4100 { "aaa", { XX }, 0 },
4101 },
4102
4103 /* X86_64_3F */
4104 {
4105 { "aas", { XX }, 0 },
4106 },
4107
4108 /* X86_64_60 */
4109 {
4110 { "pushaP", { XX }, 0 },
4111 },
4112
4113 /* X86_64_61 */
4114 {
4115 { "popaP", { XX }, 0 },
4116 },
4117
4118 /* X86_64_62 */
4119 {
4120 { MOD_TABLE (MOD_62_32BIT) },
4121 { EVEX_TABLE (EVEX_0F) },
4122 },
4123
4124 /* X86_64_63 */
4125 {
4126 { "arpl", { Ew, Gw }, 0 },
4127 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4128 },
4129
4130 /* X86_64_6D */
4131 {
4132 { "ins{R|}", { Yzr, indirDX }, 0 },
4133 { "ins{G|}", { Yzr, indirDX }, 0 },
4134 },
4135
4136 /* X86_64_6F */
4137 {
4138 { "outs{R|}", { indirDXr, Xz }, 0 },
4139 { "outs{G|}", { indirDXr, Xz }, 0 },
4140 },
4141
4142 /* X86_64_82 */
4143 {
4144 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4145 { REG_TABLE (REG_80) },
4146 },
4147
4148 /* X86_64_9A */
4149 {
4150 { "{l|}call{P|}", { Ap }, 0 },
4151 },
4152
4153 /* X86_64_C2 */
4154 {
4155 { "retP", { Iw, BND }, 0 },
4156 { "ret@", { Iw, BND }, 0 },
4157 },
4158
4159 /* X86_64_C3 */
4160 {
4161 { "retP", { BND }, 0 },
4162 { "ret@", { BND }, 0 },
4163 },
4164
4165 /* X86_64_C4 */
4166 {
4167 { MOD_TABLE (MOD_C4_32BIT) },
4168 { VEX_C4_TABLE (VEX_0F) },
4169 },
4170
4171 /* X86_64_C5 */
4172 {
4173 { MOD_TABLE (MOD_C5_32BIT) },
4174 { VEX_C5_TABLE (VEX_0F) },
4175 },
4176
4177 /* X86_64_CE */
4178 {
4179 { "into", { XX }, 0 },
4180 },
4181
4182 /* X86_64_D4 */
4183 {
4184 { "aam", { Ib }, 0 },
4185 },
4186
4187 /* X86_64_D5 */
4188 {
4189 { "aad", { Ib }, 0 },
4190 },
4191
4192 /* X86_64_E8 */
4193 {
4194 { "callP", { Jv, BND }, 0 },
4195 { "call@", { Jv, BND }, 0 }
4196 },
4197
4198 /* X86_64_E9 */
4199 {
4200 { "jmpP", { Jv, BND }, 0 },
4201 { "jmp@", { Jv, BND }, 0 }
4202 },
4203
4204 /* X86_64_EA */
4205 {
4206 { "{l|}jmp{P|}", { Ap }, 0 },
4207 },
4208
4209 /* X86_64_0F01_REG_0 */
4210 {
4211 { "sgdt{Q|Q}", { M }, 0 },
4212 { "sgdt", { M }, 0 },
4213 },
4214
4215 /* X86_64_0F01_REG_1 */
4216 {
4217 { "sidt{Q|Q}", { M }, 0 },
4218 { "sidt", { M }, 0 },
4219 },
4220
4221 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4222 {
4223 { Bad_Opcode },
4224 { "seamret", { Skip_MODRM }, 0 },
4225 },
4226
4227 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4228 {
4229 { Bad_Opcode },
4230 { "seamops", { Skip_MODRM }, 0 },
4231 },
4232
4233 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4234 {
4235 { Bad_Opcode },
4236 { "seamcall", { Skip_MODRM }, 0 },
4237 },
4238
4239 /* X86_64_0F01_REG_2 */
4240 {
4241 { "lgdt{Q|Q}", { M }, 0 },
4242 { "lgdt", { M }, 0 },
4243 },
4244
4245 /* X86_64_0F01_REG_3 */
4246 {
4247 { "lidt{Q|Q}", { M }, 0 },
4248 { "lidt", { M }, 0 },
4249 },
4250
4251 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4252 {
4253 { Bad_Opcode },
4254 { "uiret", { Skip_MODRM }, 0 },
4255 },
4256
4257 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4258 {
4259 { Bad_Opcode },
4260 { "testui", { Skip_MODRM }, 0 },
4261 },
4262
4263 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4264 {
4265 { Bad_Opcode },
4266 { "clui", { Skip_MODRM }, 0 },
4267 },
4268
4269 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4270 {
4271 { Bad_Opcode },
4272 { "stui", { Skip_MODRM }, 0 },
4273 },
4274
4275 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4276 {
4277 { Bad_Opcode },
4278 { "rmpadjust", { Skip_MODRM }, 0 },
4279 },
4280
4281 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4282 {
4283 { Bad_Opcode },
4284 { "rmpupdate", { Skip_MODRM }, 0 },
4285 },
4286
4287 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4288 {
4289 { Bad_Opcode },
4290 { "psmash", { Skip_MODRM }, 0 },
4291 },
4292
4293 {
4294 /* X86_64_0F24 */
4295 { "movZ", { Em, Td }, 0 },
4296 },
4297
4298 {
4299 /* X86_64_0F26 */
4300 { "movZ", { Td, Em }, 0 },
4301 },
4302
4303 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4304 {
4305 { Bad_Opcode },
4306 { "senduipi", { Eq }, 0 },
4307 },
4308
4309 /* X86_64_VEX_0F3849 */
4310 {
4311 { Bad_Opcode },
4312 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4313 },
4314
4315 /* X86_64_VEX_0F384B */
4316 {
4317 { Bad_Opcode },
4318 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4319 },
4320
4321 /* X86_64_VEX_0F385C */
4322 {
4323 { Bad_Opcode },
4324 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4325 },
4326
4327 /* X86_64_VEX_0F385E */
4328 {
4329 { Bad_Opcode },
4330 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4331 },
4332 };
4333
4334 static const struct dis386 three_byte_table[][256] = {
4335
4336 /* THREE_BYTE_0F38 */
4337 {
4338 /* 00 */
4339 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4340 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4341 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4342 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4343 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4344 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4345 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4346 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4347 /* 08 */
4348 { "psignb", { MX, EM }, PREFIX_OPCODE },
4349 { "psignw", { MX, EM }, PREFIX_OPCODE },
4350 { "psignd", { MX, EM }, PREFIX_OPCODE },
4351 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4352 { Bad_Opcode },
4353 { Bad_Opcode },
4354 { Bad_Opcode },
4355 { Bad_Opcode },
4356 /* 10 */
4357 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4358 { Bad_Opcode },
4359 { Bad_Opcode },
4360 { Bad_Opcode },
4361 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4362 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4363 { Bad_Opcode },
4364 { "ptest", { XM, EXx }, PREFIX_DATA },
4365 /* 18 */
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 { Bad_Opcode },
4369 { Bad_Opcode },
4370 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4371 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4372 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4373 { Bad_Opcode },
4374 /* 20 */
4375 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4376 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4377 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4378 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4379 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4380 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4381 { Bad_Opcode },
4382 { Bad_Opcode },
4383 /* 28 */
4384 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4385 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4386 { MOD_TABLE (MOD_0F382A) },
4387 { "packusdw", { XM, EXx }, PREFIX_DATA },
4388 { Bad_Opcode },
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 { Bad_Opcode },
4392 /* 30 */
4393 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4394 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4395 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4396 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4397 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4398 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4399 { Bad_Opcode },
4400 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4401 /* 38 */
4402 { "pminsb", { XM, EXx }, PREFIX_DATA },
4403 { "pminsd", { XM, EXx }, PREFIX_DATA },
4404 { "pminuw", { XM, EXx }, PREFIX_DATA },
4405 { "pminud", { XM, EXx }, PREFIX_DATA },
4406 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4407 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4408 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4409 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4410 /* 40 */
4411 { "pmulld", { XM, EXx }, PREFIX_DATA },
4412 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4413 { Bad_Opcode },
4414 { Bad_Opcode },
4415 { Bad_Opcode },
4416 { Bad_Opcode },
4417 { Bad_Opcode },
4418 { Bad_Opcode },
4419 /* 48 */
4420 { Bad_Opcode },
4421 { Bad_Opcode },
4422 { Bad_Opcode },
4423 { Bad_Opcode },
4424 { Bad_Opcode },
4425 { Bad_Opcode },
4426 { Bad_Opcode },
4427 { Bad_Opcode },
4428 /* 50 */
4429 { Bad_Opcode },
4430 { Bad_Opcode },
4431 { Bad_Opcode },
4432 { Bad_Opcode },
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { Bad_Opcode },
4436 { Bad_Opcode },
4437 /* 58 */
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 { Bad_Opcode },
4443 { Bad_Opcode },
4444 { Bad_Opcode },
4445 { Bad_Opcode },
4446 /* 60 */
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 /* 68 */
4456 { Bad_Opcode },
4457 { Bad_Opcode },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { Bad_Opcode },
4464 /* 70 */
4465 { Bad_Opcode },
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 /* 78 */
4474 { Bad_Opcode },
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 /* 80 */
4483 { "invept", { Gm, Mo }, PREFIX_DATA },
4484 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4485 { "invpcid", { Gm, M }, PREFIX_DATA },
4486 { Bad_Opcode },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 /* 88 */
4492 { Bad_Opcode },
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { Bad_Opcode },
4500 /* 90 */
4501 { Bad_Opcode },
4502 { Bad_Opcode },
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 /* 98 */
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 /* a0 */
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 /* a8 */
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 /* b0 */
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 /* b8 */
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 /* c0 */
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 /* c8 */
4564 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4565 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4566 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4567 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4568 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4569 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4570 { Bad_Opcode },
4571 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4572 /* d0 */
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 /* d8 */
4582 { PREFIX_TABLE (PREFIX_0F38D8) },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 { "aesimc", { XM, EXx }, PREFIX_DATA },
4586 { PREFIX_TABLE (PREFIX_0F38DC) },
4587 { PREFIX_TABLE (PREFIX_0F38DD) },
4588 { PREFIX_TABLE (PREFIX_0F38DE) },
4589 { PREFIX_TABLE (PREFIX_0F38DF) },
4590 /* e0 */
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 /* e8 */
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 /* f0 */
4609 { PREFIX_TABLE (PREFIX_0F38F0) },
4610 { PREFIX_TABLE (PREFIX_0F38F1) },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { MOD_TABLE (MOD_0F38F5) },
4615 { PREFIX_TABLE (PREFIX_0F38F6) },
4616 { Bad_Opcode },
4617 /* f8 */
4618 { PREFIX_TABLE (PREFIX_0F38F8) },
4619 { MOD_TABLE (MOD_0F38F9) },
4620 { PREFIX_TABLE (PREFIX_0F38FA) },
4621 { PREFIX_TABLE (PREFIX_0F38FB) },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 },
4627 /* THREE_BYTE_0F3A */
4628 {
4629 /* 00 */
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 /* 08 */
4639 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4640 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4641 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4642 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4643 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4644 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4645 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4646 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4647 /* 10 */
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4653 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4654 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4655 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4656 /* 18 */
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 /* 20 */
4666 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4667 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4668 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 /* 28 */
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 /* 30 */
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 /* 38 */
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 /* 40 */
4702 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4703 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4704 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4705 { Bad_Opcode },
4706 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 /* 48 */
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 /* 50 */
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 /* 58 */
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 /* 60 */
4738 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4739 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4740 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4741 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 /* 68 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 /* 70 */
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 /* 78 */
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 /* 80 */
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 /* 88 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* 90 */
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* 98 */
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* a0 */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* a8 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* b0 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* b8 */
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 /* c0 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* c8 */
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4860 { Bad_Opcode },
4861 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4862 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4863 /* d0 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* d8 */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4881 /* e0 */
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 /* e8 */
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 /* f0 */
4900 { PREFIX_TABLE (PREFIX_0F3A0F) },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 /* f8 */
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 },
4918 };
4919
4920 static const struct dis386 xop_table[][256] = {
4921 /* XOP_08 */
4922 {
4923 /* 00 */
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 /* 08 */
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 /* 10 */
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 /* 18 */
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 /* 20 */
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 /* 28 */
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 /* 30 */
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 /* 38 */
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 /* 40 */
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 /* 48 */
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 /* 50 */
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 /* 58 */
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 /* 60 */
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 /* 68 */
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 /* 70 */
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 /* 78 */
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 /* 80 */
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5074 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5075 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5076 /* 88 */
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5084 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5085 /* 90 */
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5092 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5093 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5094 /* 98 */
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5102 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5103 /* a0 */
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5107 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5111 { Bad_Opcode },
5112 /* a8 */
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 /* b0 */
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5129 { Bad_Opcode },
5130 /* b8 */
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 /* c0 */
5140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5141 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5142 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5143 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 /* c8 */
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5154 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5155 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5156 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5157 /* d0 */
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 /* d8 */
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 /* e0 */
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 /* e8 */
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5190 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5191 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5193 /* f0 */
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 /* f8 */
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 },
5212 /* XOP_09 */
5213 {
5214 /* 00 */
5215 { Bad_Opcode },
5216 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5217 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 /* 08 */
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 /* 10 */
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { MOD_TABLE (MOD_XOP_09_12) },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 /* 18 */
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 /* 20 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* 28 */
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* 30 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 /* 38 */
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 /* 40 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* 48 */
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 /* 50 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 /* 58 */
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* 60 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* 68 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* 70 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 /* 78 */
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 /* 80 */
5359 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5360 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5361 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5362 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 /* 88 */
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 /* 90 */
5377 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5378 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5379 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5380 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5381 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5382 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5383 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5384 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5385 /* 98 */
5386 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5387 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5388 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5389 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 /* a0 */
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 /* a8 */
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 /* b0 */
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 /* b8 */
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 /* c0 */
5431 { Bad_Opcode },
5432 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5433 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5434 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5439 /* c8 */
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 /* d0 */
5449 { Bad_Opcode },
5450 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5451 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5452 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5456 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5457 /* d8 */
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 /* e0 */
5467 { Bad_Opcode },
5468 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5469 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5470 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 /* e8 */
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 /* f0 */
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 /* f8 */
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 },
5503 /* XOP_0A */
5504 {
5505 /* 00 */
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 /* 08 */
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 /* 10 */
5524 { "bextrS", { Gdq, Edq, Id }, 0 },
5525 { Bad_Opcode },
5526 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* 18 */
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 /* 20 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* 28 */
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* 30 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* 38 */
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 /* 40 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* 48 */
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* 50 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* 58 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 60 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 68 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 70 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 78 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 80 */
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 /* 88 */
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 90 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 98 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* a0 */
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* a8 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* b0 */
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 /* b8 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* c0 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* c8 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* d0 */
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* d8 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* e0 */
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 /* e8 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 /* f0 */
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 /* f8 */
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 },
5794 };
5795
5796 static const struct dis386 vex_table[][256] = {
5797 /* VEX_0F */
5798 {
5799 /* 00 */
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 /* 08 */
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 /* 10 */
5818 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5820 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5821 { MOD_TABLE (MOD_VEX_0F13) },
5822 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5823 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5824 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5825 { MOD_TABLE (MOD_VEX_0F17) },
5826 /* 18 */
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 /* 20 */
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 /* 28 */
5845 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5846 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5847 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5848 { MOD_TABLE (MOD_VEX_0F2B) },
5849 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5850 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5851 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5852 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5853 /* 30 */
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 /* 38 */
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 /* 40 */
5872 { Bad_Opcode },
5873 { VEX_LEN_TABLE (VEX_LEN_0F41) },
5874 { VEX_LEN_TABLE (VEX_LEN_0F42) },
5875 { Bad_Opcode },
5876 { VEX_LEN_TABLE (VEX_LEN_0F44) },
5877 { VEX_LEN_TABLE (VEX_LEN_0F45) },
5878 { VEX_LEN_TABLE (VEX_LEN_0F46) },
5879 { VEX_LEN_TABLE (VEX_LEN_0F47) },
5880 /* 48 */
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5884 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 /* 50 */
5890 { MOD_TABLE (MOD_VEX_0F50) },
5891 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5892 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5893 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5894 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5895 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5896 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5897 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5898 /* 58 */
5899 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5900 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5901 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5902 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5903 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5904 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5905 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5906 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5907 /* 60 */
5908 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5909 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5910 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5911 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5912 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5913 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5914 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5915 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5916 /* 68 */
5917 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5918 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5919 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5920 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5921 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5922 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5923 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5924 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5925 /* 70 */
5926 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5927 { MOD_TABLE (MOD_VEX_0F71) },
5928 { MOD_TABLE (MOD_VEX_0F72) },
5929 { MOD_TABLE (MOD_VEX_0F73) },
5930 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5931 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5932 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5933 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5934 /* 78 */
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5940 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5941 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5942 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5943 /* 80 */
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 /* 88 */
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 /* 90 */
5962 { VEX_LEN_TABLE (VEX_LEN_0F90) },
5963 { VEX_LEN_TABLE (VEX_LEN_0F91) },
5964 { VEX_LEN_TABLE (VEX_LEN_0F92) },
5965 { VEX_LEN_TABLE (VEX_LEN_0F93) },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 /* 98 */
5971 { VEX_LEN_TABLE (VEX_LEN_0F98) },
5972 { VEX_LEN_TABLE (VEX_LEN_0F99) },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 /* a0 */
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 /* a8 */
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { Bad_Opcode },
5995 { REG_TABLE (REG_VEX_0FAE) },
5996 { Bad_Opcode },
5997 /* b0 */
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 /* b8 */
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 /* c0 */
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6019 { Bad_Opcode },
6020 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6021 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6022 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6023 { Bad_Opcode },
6024 /* c8 */
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 /* d0 */
6034 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6035 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6036 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6037 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6038 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6039 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6040 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6041 { MOD_TABLE (MOD_VEX_0FD7) },
6042 /* d8 */
6043 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6044 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6045 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6046 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6047 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6048 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6049 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6050 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6051 /* e0 */
6052 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6053 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6054 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6055 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6056 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6057 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6058 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6059 { MOD_TABLE (MOD_VEX_0FE7) },
6060 /* e8 */
6061 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6062 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6063 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6064 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6065 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6066 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6067 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6068 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6069 /* f0 */
6070 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6071 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6072 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6073 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6074 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6075 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6076 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6077 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6078 /* f8 */
6079 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6080 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6081 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6082 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6083 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6084 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6085 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6086 { Bad_Opcode },
6087 },
6088 /* VEX_0F38 */
6089 {
6090 /* 00 */
6091 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6092 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6093 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6094 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6095 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6096 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6097 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6098 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6099 /* 08 */
6100 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6101 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6102 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6103 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6104 { VEX_W_TABLE (VEX_W_0F380C) },
6105 { VEX_W_TABLE (VEX_W_0F380D) },
6106 { VEX_W_TABLE (VEX_W_0F380E) },
6107 { VEX_W_TABLE (VEX_W_0F380F) },
6108 /* 10 */
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { VEX_W_TABLE (VEX_W_0F3813) },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6116 { "vptest", { XM, EXx }, PREFIX_DATA },
6117 /* 18 */
6118 { VEX_W_TABLE (VEX_W_0F3818) },
6119 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6120 { MOD_TABLE (MOD_VEX_0F381A) },
6121 { Bad_Opcode },
6122 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6123 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6124 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6125 { Bad_Opcode },
6126 /* 20 */
6127 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6128 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6129 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6130 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6131 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6132 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 /* 28 */
6136 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6137 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6138 { MOD_TABLE (MOD_VEX_0F382A) },
6139 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6140 { MOD_TABLE (MOD_VEX_0F382C) },
6141 { MOD_TABLE (MOD_VEX_0F382D) },
6142 { MOD_TABLE (MOD_VEX_0F382E) },
6143 { MOD_TABLE (MOD_VEX_0F382F) },
6144 /* 30 */
6145 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6146 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6147 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6148 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6149 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6150 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6151 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6152 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6153 /* 38 */
6154 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6155 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6156 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6157 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6159 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6161 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6162 /* 40 */
6163 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6164 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6169 { VEX_W_TABLE (VEX_W_0F3846) },
6170 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6171 /* 48 */
6172 { Bad_Opcode },
6173 { X86_64_TABLE (X86_64_VEX_0F3849) },
6174 { Bad_Opcode },
6175 { X86_64_TABLE (X86_64_VEX_0F384B) },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 /* 50 */
6181 { VEX_W_TABLE (VEX_W_0F3850) },
6182 { VEX_W_TABLE (VEX_W_0F3851) },
6183 { VEX_W_TABLE (VEX_W_0F3852) },
6184 { VEX_W_TABLE (VEX_W_0F3853) },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 /* 58 */
6190 { VEX_W_TABLE (VEX_W_0F3858) },
6191 { VEX_W_TABLE (VEX_W_0F3859) },
6192 { MOD_TABLE (MOD_VEX_0F385A) },
6193 { Bad_Opcode },
6194 { X86_64_TABLE (X86_64_VEX_0F385C) },
6195 { Bad_Opcode },
6196 { X86_64_TABLE (X86_64_VEX_0F385E) },
6197 { Bad_Opcode },
6198 /* 60 */
6199 { Bad_Opcode },
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 /* 68 */
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 { Bad_Opcode },
6216 /* 70 */
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { Bad_Opcode },
6225 /* 78 */
6226 { VEX_W_TABLE (VEX_W_0F3878) },
6227 { VEX_W_TABLE (VEX_W_0F3879) },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 /* 80 */
6235 { Bad_Opcode },
6236 { Bad_Opcode },
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 /* 88 */
6244 { Bad_Opcode },
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { Bad_Opcode },
6248 { MOD_TABLE (MOD_VEX_0F388C) },
6249 { Bad_Opcode },
6250 { MOD_TABLE (MOD_VEX_0F388E) },
6251 { Bad_Opcode },
6252 /* 90 */
6253 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6254 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6255 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6256 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6260 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6261 /* 98 */
6262 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6263 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6264 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6265 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6266 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6267 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6268 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6269 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6270 /* a0 */
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6278 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6279 /* a8 */
6280 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6281 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6282 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6283 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6284 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6285 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6286 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6287 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6288 /* b0 */
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6296 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6297 /* b8 */
6298 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6299 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6300 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6301 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6302 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6303 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6304 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6305 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6306 /* c0 */
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 /* c8 */
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { VEX_W_TABLE (VEX_W_0F38CF) },
6324 /* d0 */
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 /* d8 */
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6338 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6339 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6340 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6341 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6342 /* e0 */
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 { Bad_Opcode },
6350 { Bad_Opcode },
6351 /* e8 */
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 /* f0 */
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6364 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6365 { Bad_Opcode },
6366 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6367 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6368 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6369 /* f8 */
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 },
6379 /* VEX_0F3A */
6380 {
6381 /* 00 */
6382 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6384 { VEX_W_TABLE (VEX_W_0F3A02) },
6385 { Bad_Opcode },
6386 { VEX_W_TABLE (VEX_W_0F3A04) },
6387 { VEX_W_TABLE (VEX_W_0F3A05) },
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6389 { Bad_Opcode },
6390 /* 08 */
6391 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6392 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6393 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6394 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6395 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6396 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6397 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6398 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6399 /* 10 */
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6405 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6406 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6407 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6408 /* 18 */
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6410 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { VEX_W_TABLE (VEX_W_0F3A1D) },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 /* 20 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6420 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 /* 28 */
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 /* 30 */
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 /* 38 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 /* 40 */
6454 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6455 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6456 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6457 { Bad_Opcode },
6458 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6459 { Bad_Opcode },
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6461 { Bad_Opcode },
6462 /* 48 */
6463 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6464 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6465 { VEX_W_TABLE (VEX_W_0F3A4A) },
6466 { VEX_W_TABLE (VEX_W_0F3A4B) },
6467 { VEX_W_TABLE (VEX_W_0F3A4C) },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 /* 50 */
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 /* 58 */
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6486 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6487 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6488 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6489 /* 60 */
6490 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 /* 68 */
6499 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6500 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6501 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6502 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6503 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6504 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6505 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6506 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6507 /* 70 */
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 /* 78 */
6517 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6518 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6519 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6520 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6521 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6522 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6523 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6524 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6525 /* 80 */
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 /* 88 */
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 /* 90 */
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 /* 98 */
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 /* a0 */
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 /* a8 */
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 /* b0 */
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 /* b8 */
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 /* c0 */
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 /* c8 */
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { VEX_W_TABLE (VEX_W_0F3ACE) },
6614 { VEX_W_TABLE (VEX_W_0F3ACF) },
6615 /* d0 */
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 /* d8 */
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6633 /* e0 */
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 /* e8 */
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 /* f0 */
6652 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 /* f8 */
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 },
6670 };
6671
6672 #include "i386-dis-evex.h"
6673
6674 static const struct dis386 vex_len_table[][2] = {
6675 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6676 {
6677 { "vmovlpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6678 },
6679
6680 /* VEX_LEN_0F12_P_0_M_1 */
6681 {
6682 { "vmovhlp%XS", { XM, Vex, EXq }, 0 },
6683 },
6684
6685 /* VEX_LEN_0F13_M_0 */
6686 {
6687 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6688 },
6689
6690 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6691 {
6692 { "vmovhpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6693 },
6694
6695 /* VEX_LEN_0F16_P_0_M_1 */
6696 {
6697 { "vmovlhp%XS", { XM, Vex, EXq }, 0 },
6698 },
6699
6700 /* VEX_LEN_0F17_M_0 */
6701 {
6702 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6703 },
6704
6705 /* VEX_LEN_0F41 */
6706 {
6707 { Bad_Opcode },
6708 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6709 },
6710
6711 /* VEX_LEN_0F42 */
6712 {
6713 { Bad_Opcode },
6714 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6715 },
6716
6717 /* VEX_LEN_0F44 */
6718 {
6719 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6720 },
6721
6722 /* VEX_LEN_0F45 */
6723 {
6724 { Bad_Opcode },
6725 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6726 },
6727
6728 /* VEX_LEN_0F46 */
6729 {
6730 { Bad_Opcode },
6731 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6732 },
6733
6734 /* VEX_LEN_0F47 */
6735 {
6736 { Bad_Opcode },
6737 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6738 },
6739
6740 /* VEX_LEN_0F4A */
6741 {
6742 { Bad_Opcode },
6743 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6744 },
6745
6746 /* VEX_LEN_0F4B */
6747 {
6748 { Bad_Opcode },
6749 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6750 },
6751
6752 /* VEX_LEN_0F6E */
6753 {
6754 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6755 },
6756
6757 /* VEX_LEN_0F77 */
6758 {
6759 { "vzeroupper", { XX }, 0 },
6760 { "vzeroall", { XX }, 0 },
6761 },
6762
6763 /* VEX_LEN_0F7E_P_1 */
6764 {
6765 { "vmovq", { XMScalar, EXq }, 0 },
6766 },
6767
6768 /* VEX_LEN_0F7E_P_2 */
6769 {
6770 { "vmovK", { Edq, XMScalar }, 0 },
6771 },
6772
6773 /* VEX_LEN_0F90 */
6774 {
6775 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6776 },
6777
6778 /* VEX_LEN_0F91 */
6779 {
6780 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6781 },
6782
6783 /* VEX_LEN_0F92 */
6784 {
6785 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6786 },
6787
6788 /* VEX_LEN_0F93 */
6789 {
6790 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6791 },
6792
6793 /* VEX_LEN_0F98 */
6794 {
6795 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6796 },
6797
6798 /* VEX_LEN_0F99 */
6799 {
6800 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6801 },
6802
6803 /* VEX_LEN_0FAE_R_2_M_0 */
6804 {
6805 { "vldmxcsr", { Md }, 0 },
6806 },
6807
6808 /* VEX_LEN_0FAE_R_3_M_0 */
6809 {
6810 { "vstmxcsr", { Md }, 0 },
6811 },
6812
6813 /* VEX_LEN_0FC4 */
6814 {
6815 { "vpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
6816 },
6817
6818 /* VEX_LEN_0FC5 */
6819 {
6820 { "vpextrw", { Gd, XS, Ib }, PREFIX_DATA },
6821 },
6822
6823 /* VEX_LEN_0FD6 */
6824 {
6825 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6826 },
6827
6828 /* VEX_LEN_0FF7 */
6829 {
6830 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6831 },
6832
6833 /* VEX_LEN_0F3816 */
6834 {
6835 { Bad_Opcode },
6836 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6837 },
6838
6839 /* VEX_LEN_0F3819 */
6840 {
6841 { Bad_Opcode },
6842 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6843 },
6844
6845 /* VEX_LEN_0F381A_M_0 */
6846 {
6847 { Bad_Opcode },
6848 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6849 },
6850
6851 /* VEX_LEN_0F3836 */
6852 {
6853 { Bad_Opcode },
6854 { VEX_W_TABLE (VEX_W_0F3836) },
6855 },
6856
6857 /* VEX_LEN_0F3841 */
6858 {
6859 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6860 },
6861
6862 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6863 {
6864 { "ldtilecfg", { M }, 0 },
6865 },
6866
6867 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6868 {
6869 { "tilerelease", { Skip_MODRM }, 0 },
6870 },
6871
6872 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6873 {
6874 { "sttilecfg", { M }, 0 },
6875 },
6876
6877 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6878 {
6879 { "tilezero", { TMM, Skip_MODRM }, 0 },
6880 },
6881
6882 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6883 {
6884 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6885 },
6886 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6887 {
6888 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6889 },
6890
6891 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6892 {
6893 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6894 },
6895
6896 /* VEX_LEN_0F385A_M_0 */
6897 {
6898 { Bad_Opcode },
6899 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6900 },
6901
6902 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6903 {
6904 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6905 },
6906
6907 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6908 {
6909 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6910 },
6911
6912 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6913 {
6914 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6915 },
6916
6917 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6918 {
6919 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6920 },
6921
6922 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6923 {
6924 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6925 },
6926
6927 /* VEX_LEN_0F38DB */
6928 {
6929 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6930 },
6931
6932 /* VEX_LEN_0F38F2 */
6933 {
6934 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6935 },
6936
6937 /* VEX_LEN_0F38F3 */
6938 {
6939 { REG_TABLE(REG_VEX_0F38F3_L_0) },
6940 },
6941
6942 /* VEX_LEN_0F38F5 */
6943 {
6944 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
6945 },
6946
6947 /* VEX_LEN_0F38F6 */
6948 {
6949 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
6950 },
6951
6952 /* VEX_LEN_0F38F7 */
6953 {
6954 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
6955 },
6956
6957 /* VEX_LEN_0F3A00 */
6958 {
6959 { Bad_Opcode },
6960 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6961 },
6962
6963 /* VEX_LEN_0F3A01 */
6964 {
6965 { Bad_Opcode },
6966 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6967 },
6968
6969 /* VEX_LEN_0F3A06 */
6970 {
6971 { Bad_Opcode },
6972 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6973 },
6974
6975 /* VEX_LEN_0F3A14 */
6976 {
6977 { "vpextrb", { Edb, XM, Ib }, PREFIX_DATA },
6978 },
6979
6980 /* VEX_LEN_0F3A15 */
6981 {
6982 { "vpextrw", { Edw, XM, Ib }, PREFIX_DATA },
6983 },
6984
6985 /* VEX_LEN_0F3A16 */
6986 {
6987 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
6988 },
6989
6990 /* VEX_LEN_0F3A17 */
6991 {
6992 { "vextractps", { Ed, XM, Ib }, PREFIX_DATA },
6993 },
6994
6995 /* VEX_LEN_0F3A18 */
6996 {
6997 { Bad_Opcode },
6998 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6999 },
7000
7001 /* VEX_LEN_0F3A19 */
7002 {
7003 { Bad_Opcode },
7004 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7005 },
7006
7007 /* VEX_LEN_0F3A20 */
7008 {
7009 { "vpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7010 },
7011
7012 /* VEX_LEN_0F3A21 */
7013 {
7014 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7015 },
7016
7017 /* VEX_LEN_0F3A22 */
7018 {
7019 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7020 },
7021
7022 /* VEX_LEN_0F3A30 */
7023 {
7024 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7025 },
7026
7027 /* VEX_LEN_0F3A31 */
7028 {
7029 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7030 },
7031
7032 /* VEX_LEN_0F3A32 */
7033 {
7034 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7035 },
7036
7037 /* VEX_LEN_0F3A33 */
7038 {
7039 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7040 },
7041
7042 /* VEX_LEN_0F3A38 */
7043 {
7044 { Bad_Opcode },
7045 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7046 },
7047
7048 /* VEX_LEN_0F3A39 */
7049 {
7050 { Bad_Opcode },
7051 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7052 },
7053
7054 /* VEX_LEN_0F3A41 */
7055 {
7056 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7057 },
7058
7059 /* VEX_LEN_0F3A46 */
7060 {
7061 { Bad_Opcode },
7062 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7063 },
7064
7065 /* VEX_LEN_0F3A60 */
7066 {
7067 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7068 },
7069
7070 /* VEX_LEN_0F3A61 */
7071 {
7072 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7073 },
7074
7075 /* VEX_LEN_0F3A62 */
7076 {
7077 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7078 },
7079
7080 /* VEX_LEN_0F3A63 */
7081 {
7082 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7083 },
7084
7085 /* VEX_LEN_0F3ADF */
7086 {
7087 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7088 },
7089
7090 /* VEX_LEN_0F3AF0 */
7091 {
7092 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7093 },
7094
7095 /* VEX_LEN_0FXOP_08_85 */
7096 {
7097 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7098 },
7099
7100 /* VEX_LEN_0FXOP_08_86 */
7101 {
7102 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7103 },
7104
7105 /* VEX_LEN_0FXOP_08_87 */
7106 {
7107 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7108 },
7109
7110 /* VEX_LEN_0FXOP_08_8E */
7111 {
7112 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7113 },
7114
7115 /* VEX_LEN_0FXOP_08_8F */
7116 {
7117 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7118 },
7119
7120 /* VEX_LEN_0FXOP_08_95 */
7121 {
7122 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7123 },
7124
7125 /* VEX_LEN_0FXOP_08_96 */
7126 {
7127 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7128 },
7129
7130 /* VEX_LEN_0FXOP_08_97 */
7131 {
7132 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7133 },
7134
7135 /* VEX_LEN_0FXOP_08_9E */
7136 {
7137 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7138 },
7139
7140 /* VEX_LEN_0FXOP_08_9F */
7141 {
7142 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7143 },
7144
7145 /* VEX_LEN_0FXOP_08_A3 */
7146 {
7147 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7148 },
7149
7150 /* VEX_LEN_0FXOP_08_A6 */
7151 {
7152 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7153 },
7154
7155 /* VEX_LEN_0FXOP_08_B6 */
7156 {
7157 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7158 },
7159
7160 /* VEX_LEN_0FXOP_08_C0 */
7161 {
7162 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7163 },
7164
7165 /* VEX_LEN_0FXOP_08_C1 */
7166 {
7167 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7168 },
7169
7170 /* VEX_LEN_0FXOP_08_C2 */
7171 {
7172 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7173 },
7174
7175 /* VEX_LEN_0FXOP_08_C3 */
7176 {
7177 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7178 },
7179
7180 /* VEX_LEN_0FXOP_08_CC */
7181 {
7182 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7183 },
7184
7185 /* VEX_LEN_0FXOP_08_CD */
7186 {
7187 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7188 },
7189
7190 /* VEX_LEN_0FXOP_08_CE */
7191 {
7192 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7193 },
7194
7195 /* VEX_LEN_0FXOP_08_CF */
7196 {
7197 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7198 },
7199
7200 /* VEX_LEN_0FXOP_08_EC */
7201 {
7202 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7203 },
7204
7205 /* VEX_LEN_0FXOP_08_ED */
7206 {
7207 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7208 },
7209
7210 /* VEX_LEN_0FXOP_08_EE */
7211 {
7212 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7213 },
7214
7215 /* VEX_LEN_0FXOP_08_EF */
7216 {
7217 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7218 },
7219
7220 /* VEX_LEN_0FXOP_09_01 */
7221 {
7222 { REG_TABLE (REG_XOP_09_01_L_0) },
7223 },
7224
7225 /* VEX_LEN_0FXOP_09_02 */
7226 {
7227 { REG_TABLE (REG_XOP_09_02_L_0) },
7228 },
7229
7230 /* VEX_LEN_0FXOP_09_12_M_1 */
7231 {
7232 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7233 },
7234
7235 /* VEX_LEN_0FXOP_09_82_W_0 */
7236 {
7237 { "vfrczss", { XM, EXd }, 0 },
7238 },
7239
7240 /* VEX_LEN_0FXOP_09_83_W_0 */
7241 {
7242 { "vfrczsd", { XM, EXq }, 0 },
7243 },
7244
7245 /* VEX_LEN_0FXOP_09_90 */
7246 {
7247 { "vprotb", { XM, EXx, VexW }, 0 },
7248 },
7249
7250 /* VEX_LEN_0FXOP_09_91 */
7251 {
7252 { "vprotw", { XM, EXx, VexW }, 0 },
7253 },
7254
7255 /* VEX_LEN_0FXOP_09_92 */
7256 {
7257 { "vprotd", { XM, EXx, VexW }, 0 },
7258 },
7259
7260 /* VEX_LEN_0FXOP_09_93 */
7261 {
7262 { "vprotq", { XM, EXx, VexW }, 0 },
7263 },
7264
7265 /* VEX_LEN_0FXOP_09_94 */
7266 {
7267 { "vpshlb", { XM, EXx, VexW }, 0 },
7268 },
7269
7270 /* VEX_LEN_0FXOP_09_95 */
7271 {
7272 { "vpshlw", { XM, EXx, VexW }, 0 },
7273 },
7274
7275 /* VEX_LEN_0FXOP_09_96 */
7276 {
7277 { "vpshld", { XM, EXx, VexW }, 0 },
7278 },
7279
7280 /* VEX_LEN_0FXOP_09_97 */
7281 {
7282 { "vpshlq", { XM, EXx, VexW }, 0 },
7283 },
7284
7285 /* VEX_LEN_0FXOP_09_98 */
7286 {
7287 { "vpshab", { XM, EXx, VexW }, 0 },
7288 },
7289
7290 /* VEX_LEN_0FXOP_09_99 */
7291 {
7292 { "vpshaw", { XM, EXx, VexW }, 0 },
7293 },
7294
7295 /* VEX_LEN_0FXOP_09_9A */
7296 {
7297 { "vpshad", { XM, EXx, VexW }, 0 },
7298 },
7299
7300 /* VEX_LEN_0FXOP_09_9B */
7301 {
7302 { "vpshaq", { XM, EXx, VexW }, 0 },
7303 },
7304
7305 /* VEX_LEN_0FXOP_09_C1 */
7306 {
7307 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7308 },
7309
7310 /* VEX_LEN_0FXOP_09_C2 */
7311 {
7312 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7313 },
7314
7315 /* VEX_LEN_0FXOP_09_C3 */
7316 {
7317 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7318 },
7319
7320 /* VEX_LEN_0FXOP_09_C6 */
7321 {
7322 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7323 },
7324
7325 /* VEX_LEN_0FXOP_09_C7 */
7326 {
7327 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7328 },
7329
7330 /* VEX_LEN_0FXOP_09_CB */
7331 {
7332 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7333 },
7334
7335 /* VEX_LEN_0FXOP_09_D1 */
7336 {
7337 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7338 },
7339
7340 /* VEX_LEN_0FXOP_09_D2 */
7341 {
7342 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7343 },
7344
7345 /* VEX_LEN_0FXOP_09_D3 */
7346 {
7347 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7348 },
7349
7350 /* VEX_LEN_0FXOP_09_D6 */
7351 {
7352 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7353 },
7354
7355 /* VEX_LEN_0FXOP_09_D7 */
7356 {
7357 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7358 },
7359
7360 /* VEX_LEN_0FXOP_09_DB */
7361 {
7362 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7363 },
7364
7365 /* VEX_LEN_0FXOP_09_E1 */
7366 {
7367 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7368 },
7369
7370 /* VEX_LEN_0FXOP_09_E2 */
7371 {
7372 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7373 },
7374
7375 /* VEX_LEN_0FXOP_09_E3 */
7376 {
7377 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7378 },
7379
7380 /* VEX_LEN_0FXOP_0A_12 */
7381 {
7382 { REG_TABLE (REG_XOP_0A_12_L_0) },
7383 },
7384 };
7385
7386 #include "i386-dis-evex-len.h"
7387
7388 static const struct dis386 vex_w_table[][2] = {
7389 {
7390 /* VEX_W_0F41_L_1_M_1 */
7391 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7392 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7393 },
7394 {
7395 /* VEX_W_0F42_L_1_M_1 */
7396 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7397 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7398 },
7399 {
7400 /* VEX_W_0F44_L_0_M_1 */
7401 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7402 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7403 },
7404 {
7405 /* VEX_W_0F45_L_1_M_1 */
7406 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7407 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7408 },
7409 {
7410 /* VEX_W_0F46_L_1_M_1 */
7411 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7412 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7413 },
7414 {
7415 /* VEX_W_0F47_L_1_M_1 */
7416 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7417 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7418 },
7419 {
7420 /* VEX_W_0F4A_L_1_M_1 */
7421 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7422 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7423 },
7424 {
7425 /* VEX_W_0F4B_L_1_M_1 */
7426 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7427 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7428 },
7429 {
7430 /* VEX_W_0F90_L_0 */
7431 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7432 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7433 },
7434 {
7435 /* VEX_W_0F91_L_0_M_0 */
7436 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7437 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7438 },
7439 {
7440 /* VEX_W_0F92_L_0_M_1 */
7441 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7442 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7443 },
7444 {
7445 /* VEX_W_0F93_L_0_M_1 */
7446 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7447 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7448 },
7449 {
7450 /* VEX_W_0F98_L_0_M_1 */
7451 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7452 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7453 },
7454 {
7455 /* VEX_W_0F99_L_0_M_1 */
7456 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7457 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7458 },
7459 {
7460 /* VEX_W_0F380C */
7461 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7462 },
7463 {
7464 /* VEX_W_0F380D */
7465 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7466 },
7467 {
7468 /* VEX_W_0F380E */
7469 { "vtestps", { XM, EXx }, PREFIX_DATA },
7470 },
7471 {
7472 /* VEX_W_0F380F */
7473 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7474 },
7475 {
7476 /* VEX_W_0F3813 */
7477 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7478 },
7479 {
7480 /* VEX_W_0F3816_L_1 */
7481 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7482 },
7483 {
7484 /* VEX_W_0F3818 */
7485 { "vbroadcastss", { XM, EXd }, PREFIX_DATA },
7486 },
7487 {
7488 /* VEX_W_0F3819_L_1 */
7489 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7490 },
7491 {
7492 /* VEX_W_0F381A_M_0_L_1 */
7493 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7494 },
7495 {
7496 /* VEX_W_0F382C_M_0 */
7497 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7498 },
7499 {
7500 /* VEX_W_0F382D_M_0 */
7501 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7502 },
7503 {
7504 /* VEX_W_0F382E_M_0 */
7505 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7506 },
7507 {
7508 /* VEX_W_0F382F_M_0 */
7509 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7510 },
7511 {
7512 /* VEX_W_0F3836 */
7513 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7514 },
7515 {
7516 /* VEX_W_0F3846 */
7517 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7518 },
7519 {
7520 /* VEX_W_0F3849_X86_64_P_0 */
7521 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7522 },
7523 {
7524 /* VEX_W_0F3849_X86_64_P_2 */
7525 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7526 },
7527 {
7528 /* VEX_W_0F3849_X86_64_P_3 */
7529 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7530 },
7531 {
7532 /* VEX_W_0F384B_X86_64_P_1 */
7533 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7534 },
7535 {
7536 /* VEX_W_0F384B_X86_64_P_2 */
7537 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7538 },
7539 {
7540 /* VEX_W_0F384B_X86_64_P_3 */
7541 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7542 },
7543 {
7544 /* VEX_W_0F3850 */
7545 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7546 },
7547 {
7548 /* VEX_W_0F3851 */
7549 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7550 },
7551 {
7552 /* VEX_W_0F3852 */
7553 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7554 },
7555 {
7556 /* VEX_W_0F3853 */
7557 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7558 },
7559 {
7560 /* VEX_W_0F3858 */
7561 { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7562 },
7563 {
7564 /* VEX_W_0F3859 */
7565 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7566 },
7567 {
7568 /* VEX_W_0F385A_M_0_L_0 */
7569 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7570 },
7571 {
7572 /* VEX_W_0F385C_X86_64_P_1 */
7573 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7574 },
7575 {
7576 /* VEX_W_0F385E_X86_64_P_0 */
7577 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7578 },
7579 {
7580 /* VEX_W_0F385E_X86_64_P_1 */
7581 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7582 },
7583 {
7584 /* VEX_W_0F385E_X86_64_P_2 */
7585 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7586 },
7587 {
7588 /* VEX_W_0F385E_X86_64_P_3 */
7589 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7590 },
7591 {
7592 /* VEX_W_0F3878 */
7593 { "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
7594 },
7595 {
7596 /* VEX_W_0F3879 */
7597 { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
7598 },
7599 {
7600 /* VEX_W_0F38CF */
7601 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7602 },
7603 {
7604 /* VEX_W_0F3A00_L_1 */
7605 { Bad_Opcode },
7606 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7607 },
7608 {
7609 /* VEX_W_0F3A01_L_1 */
7610 { Bad_Opcode },
7611 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7612 },
7613 {
7614 /* VEX_W_0F3A02 */
7615 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7616 },
7617 {
7618 /* VEX_W_0F3A04 */
7619 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7620 },
7621 {
7622 /* VEX_W_0F3A05 */
7623 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7624 },
7625 {
7626 /* VEX_W_0F3A06_L_1 */
7627 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7628 },
7629 {
7630 /* VEX_W_0F3A18_L_1 */
7631 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7632 },
7633 {
7634 /* VEX_W_0F3A19_L_1 */
7635 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7636 },
7637 {
7638 /* VEX_W_0F3A1D */
7639 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7640 },
7641 {
7642 /* VEX_W_0F3A38_L_1 */
7643 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7644 },
7645 {
7646 /* VEX_W_0F3A39_L_1 */
7647 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7648 },
7649 {
7650 /* VEX_W_0F3A46_L_1 */
7651 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7652 },
7653 {
7654 /* VEX_W_0F3A4A */
7655 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7656 },
7657 {
7658 /* VEX_W_0F3A4B */
7659 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7660 },
7661 {
7662 /* VEX_W_0F3A4C */
7663 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7664 },
7665 {
7666 /* VEX_W_0F3ACE */
7667 { Bad_Opcode },
7668 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7669 },
7670 {
7671 /* VEX_W_0F3ACF */
7672 { Bad_Opcode },
7673 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7674 },
7675 /* VEX_W_0FXOP_08_85_L_0 */
7676 {
7677 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7678 },
7679 /* VEX_W_0FXOP_08_86_L_0 */
7680 {
7681 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7682 },
7683 /* VEX_W_0FXOP_08_87_L_0 */
7684 {
7685 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7686 },
7687 /* VEX_W_0FXOP_08_8E_L_0 */
7688 {
7689 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7690 },
7691 /* VEX_W_0FXOP_08_8F_L_0 */
7692 {
7693 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7694 },
7695 /* VEX_W_0FXOP_08_95_L_0 */
7696 {
7697 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7698 },
7699 /* VEX_W_0FXOP_08_96_L_0 */
7700 {
7701 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7702 },
7703 /* VEX_W_0FXOP_08_97_L_0 */
7704 {
7705 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7706 },
7707 /* VEX_W_0FXOP_08_9E_L_0 */
7708 {
7709 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7710 },
7711 /* VEX_W_0FXOP_08_9F_L_0 */
7712 {
7713 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7714 },
7715 /* VEX_W_0FXOP_08_A6_L_0 */
7716 {
7717 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7718 },
7719 /* VEX_W_0FXOP_08_B6_L_0 */
7720 {
7721 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7722 },
7723 /* VEX_W_0FXOP_08_C0_L_0 */
7724 {
7725 { "vprotb", { XM, EXx, Ib }, 0 },
7726 },
7727 /* VEX_W_0FXOP_08_C1_L_0 */
7728 {
7729 { "vprotw", { XM, EXx, Ib }, 0 },
7730 },
7731 /* VEX_W_0FXOP_08_C2_L_0 */
7732 {
7733 { "vprotd", { XM, EXx, Ib }, 0 },
7734 },
7735 /* VEX_W_0FXOP_08_C3_L_0 */
7736 {
7737 { "vprotq", { XM, EXx, Ib }, 0 },
7738 },
7739 /* VEX_W_0FXOP_08_CC_L_0 */
7740 {
7741 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7742 },
7743 /* VEX_W_0FXOP_08_CD_L_0 */
7744 {
7745 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7746 },
7747 /* VEX_W_0FXOP_08_CE_L_0 */
7748 {
7749 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7750 },
7751 /* VEX_W_0FXOP_08_CF_L_0 */
7752 {
7753 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7754 },
7755 /* VEX_W_0FXOP_08_EC_L_0 */
7756 {
7757 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7758 },
7759 /* VEX_W_0FXOP_08_ED_L_0 */
7760 {
7761 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7762 },
7763 /* VEX_W_0FXOP_08_EE_L_0 */
7764 {
7765 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7766 },
7767 /* VEX_W_0FXOP_08_EF_L_0 */
7768 {
7769 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7770 },
7771 /* VEX_W_0FXOP_09_80 */
7772 {
7773 { "vfrczps", { XM, EXx }, 0 },
7774 },
7775 /* VEX_W_0FXOP_09_81 */
7776 {
7777 { "vfrczpd", { XM, EXx }, 0 },
7778 },
7779 /* VEX_W_0FXOP_09_82 */
7780 {
7781 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7782 },
7783 /* VEX_W_0FXOP_09_83 */
7784 {
7785 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7786 },
7787 /* VEX_W_0FXOP_09_C1_L_0 */
7788 {
7789 { "vphaddbw", { XM, EXxmm }, 0 },
7790 },
7791 /* VEX_W_0FXOP_09_C2_L_0 */
7792 {
7793 { "vphaddbd", { XM, EXxmm }, 0 },
7794 },
7795 /* VEX_W_0FXOP_09_C3_L_0 */
7796 {
7797 { "vphaddbq", { XM, EXxmm }, 0 },
7798 },
7799 /* VEX_W_0FXOP_09_C6_L_0 */
7800 {
7801 { "vphaddwd", { XM, EXxmm }, 0 },
7802 },
7803 /* VEX_W_0FXOP_09_C7_L_0 */
7804 {
7805 { "vphaddwq", { XM, EXxmm }, 0 },
7806 },
7807 /* VEX_W_0FXOP_09_CB_L_0 */
7808 {
7809 { "vphadddq", { XM, EXxmm }, 0 },
7810 },
7811 /* VEX_W_0FXOP_09_D1_L_0 */
7812 {
7813 { "vphaddubw", { XM, EXxmm }, 0 },
7814 },
7815 /* VEX_W_0FXOP_09_D2_L_0 */
7816 {
7817 { "vphaddubd", { XM, EXxmm }, 0 },
7818 },
7819 /* VEX_W_0FXOP_09_D3_L_0 */
7820 {
7821 { "vphaddubq", { XM, EXxmm }, 0 },
7822 },
7823 /* VEX_W_0FXOP_09_D6_L_0 */
7824 {
7825 { "vphadduwd", { XM, EXxmm }, 0 },
7826 },
7827 /* VEX_W_0FXOP_09_D7_L_0 */
7828 {
7829 { "vphadduwq", { XM, EXxmm }, 0 },
7830 },
7831 /* VEX_W_0FXOP_09_DB_L_0 */
7832 {
7833 { "vphaddudq", { XM, EXxmm }, 0 },
7834 },
7835 /* VEX_W_0FXOP_09_E1_L_0 */
7836 {
7837 { "vphsubbw", { XM, EXxmm }, 0 },
7838 },
7839 /* VEX_W_0FXOP_09_E2_L_0 */
7840 {
7841 { "vphsubwd", { XM, EXxmm }, 0 },
7842 },
7843 /* VEX_W_0FXOP_09_E3_L_0 */
7844 {
7845 { "vphsubdq", { XM, EXxmm }, 0 },
7846 },
7847
7848 #include "i386-dis-evex-w.h"
7849 };
7850
7851 static const struct dis386 mod_table[][2] = {
7852 {
7853 /* MOD_62_32BIT */
7854 { "bound{S|}", { Gv, Ma }, 0 },
7855 { EVEX_TABLE (EVEX_0F) },
7856 },
7857 {
7858 /* MOD_8D */
7859 { "leaS", { Gv, M }, 0 },
7860 },
7861 {
7862 /* MOD_C4_32BIT */
7863 { "lesS", { Gv, Mp }, 0 },
7864 { VEX_C4_TABLE (VEX_0F) },
7865 },
7866 {
7867 /* MOD_C5_32BIT */
7868 { "ldsS", { Gv, Mp }, 0 },
7869 { VEX_C5_TABLE (VEX_0F) },
7870 },
7871 {
7872 /* MOD_C6_REG_7 */
7873 { Bad_Opcode },
7874 { RM_TABLE (RM_C6_REG_7) },
7875 },
7876 {
7877 /* MOD_C7_REG_7 */
7878 { Bad_Opcode },
7879 { RM_TABLE (RM_C7_REG_7) },
7880 },
7881 {
7882 /* MOD_FF_REG_3 */
7883 { "{l|}call^", { indirEp }, 0 },
7884 },
7885 {
7886 /* MOD_FF_REG_5 */
7887 { "{l|}jmp^", { indirEp }, 0 },
7888 },
7889 {
7890 /* MOD_0F01_REG_0 */
7891 { X86_64_TABLE (X86_64_0F01_REG_0) },
7892 { RM_TABLE (RM_0F01_REG_0) },
7893 },
7894 {
7895 /* MOD_0F01_REG_1 */
7896 { X86_64_TABLE (X86_64_0F01_REG_1) },
7897 { RM_TABLE (RM_0F01_REG_1) },
7898 },
7899 {
7900 /* MOD_0F01_REG_2 */
7901 { X86_64_TABLE (X86_64_0F01_REG_2) },
7902 { RM_TABLE (RM_0F01_REG_2) },
7903 },
7904 {
7905 /* MOD_0F01_REG_3 */
7906 { X86_64_TABLE (X86_64_0F01_REG_3) },
7907 { RM_TABLE (RM_0F01_REG_3) },
7908 },
7909 {
7910 /* MOD_0F01_REG_5 */
7911 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7912 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7913 },
7914 {
7915 /* MOD_0F01_REG_7 */
7916 { "invlpg", { Mb }, 0 },
7917 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7918 },
7919 {
7920 /* MOD_0F12_PREFIX_0 */
7921 { "movlpX", { XM, EXq }, 0 },
7922 { "movhlps", { XM, EXq }, 0 },
7923 },
7924 {
7925 /* MOD_0F12_PREFIX_2 */
7926 { "movlpX", { XM, EXq }, 0 },
7927 },
7928 {
7929 /* MOD_0F13 */
7930 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7931 },
7932 {
7933 /* MOD_0F16_PREFIX_0 */
7934 { "movhpX", { XM, EXq }, 0 },
7935 { "movlhps", { XM, EXq }, 0 },
7936 },
7937 {
7938 /* MOD_0F16_PREFIX_2 */
7939 { "movhpX", { XM, EXq }, 0 },
7940 },
7941 {
7942 /* MOD_0F17 */
7943 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7944 },
7945 {
7946 /* MOD_0F18_REG_0 */
7947 { "prefetchnta", { Mb }, 0 },
7948 { "nopQ", { Ev }, 0 },
7949 },
7950 {
7951 /* MOD_0F18_REG_1 */
7952 { "prefetcht0", { Mb }, 0 },
7953 { "nopQ", { Ev }, 0 },
7954 },
7955 {
7956 /* MOD_0F18_REG_2 */
7957 { "prefetcht1", { Mb }, 0 },
7958 { "nopQ", { Ev }, 0 },
7959 },
7960 {
7961 /* MOD_0F18_REG_3 */
7962 { "prefetcht2", { Mb }, 0 },
7963 { "nopQ", { Ev }, 0 },
7964 },
7965 {
7966 /* MOD_0F1A_PREFIX_0 */
7967 { "bndldx", { Gbnd, Mv_bnd }, 0 },
7968 { "nopQ", { Ev }, 0 },
7969 },
7970 {
7971 /* MOD_0F1B_PREFIX_0 */
7972 { "bndstx", { Mv_bnd, Gbnd }, 0 },
7973 { "nopQ", { Ev }, 0 },
7974 },
7975 {
7976 /* MOD_0F1B_PREFIX_1 */
7977 { "bndmk", { Gbnd, Mv_bnd }, 0 },
7978 { "nopQ", { Ev }, PREFIX_IGNORED },
7979 },
7980 {
7981 /* MOD_0F1C_PREFIX_0 */
7982 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7983 { "nopQ", { Ev }, 0 },
7984 },
7985 {
7986 /* MOD_0F1E_PREFIX_1 */
7987 { "nopQ", { Ev }, PREFIX_IGNORED },
7988 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7989 },
7990 {
7991 /* MOD_0F2B_PREFIX_0 */
7992 {"movntps", { Mx, XM }, PREFIX_OPCODE },
7993 },
7994 {
7995 /* MOD_0F2B_PREFIX_1 */
7996 {"movntss", { Md, XM }, PREFIX_OPCODE },
7997 },
7998 {
7999 /* MOD_0F2B_PREFIX_2 */
8000 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8001 },
8002 {
8003 /* MOD_0F2B_PREFIX_3 */
8004 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8005 },
8006 {
8007 /* MOD_0F50 */
8008 { Bad_Opcode },
8009 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8010 },
8011 {
8012 /* MOD_0F71 */
8013 { Bad_Opcode },
8014 { REG_TABLE (REG_0F71_MOD_0) },
8015 },
8016 {
8017 /* MOD_0F72 */
8018 { Bad_Opcode },
8019 { REG_TABLE (REG_0F72_MOD_0) },
8020 },
8021 {
8022 /* MOD_0F73 */
8023 { Bad_Opcode },
8024 { REG_TABLE (REG_0F73_MOD_0) },
8025 },
8026 {
8027 /* MOD_0FAE_REG_0 */
8028 { "fxsave", { FXSAVE }, 0 },
8029 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8030 },
8031 {
8032 /* MOD_0FAE_REG_1 */
8033 { "fxrstor", { FXSAVE }, 0 },
8034 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8035 },
8036 {
8037 /* MOD_0FAE_REG_2 */
8038 { "ldmxcsr", { Md }, 0 },
8039 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8040 },
8041 {
8042 /* MOD_0FAE_REG_3 */
8043 { "stmxcsr", { Md }, 0 },
8044 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8045 },
8046 {
8047 /* MOD_0FAE_REG_4 */
8048 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8049 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8050 },
8051 {
8052 /* MOD_0FAE_REG_5 */
8053 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8054 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8055 },
8056 {
8057 /* MOD_0FAE_REG_6 */
8058 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8059 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8060 },
8061 {
8062 /* MOD_0FAE_REG_7 */
8063 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8064 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8065 },
8066 {
8067 /* MOD_0FB2 */
8068 { "lssS", { Gv, Mp }, 0 },
8069 },
8070 {
8071 /* MOD_0FB4 */
8072 { "lfsS", { Gv, Mp }, 0 },
8073 },
8074 {
8075 /* MOD_0FB5 */
8076 { "lgsS", { Gv, Mp }, 0 },
8077 },
8078 {
8079 /* MOD_0FC3 */
8080 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8081 },
8082 {
8083 /* MOD_0FC7_REG_3 */
8084 { "xrstors", { FXSAVE }, 0 },
8085 },
8086 {
8087 /* MOD_0FC7_REG_4 */
8088 { "xsavec", { FXSAVE }, 0 },
8089 },
8090 {
8091 /* MOD_0FC7_REG_5 */
8092 { "xsaves", { FXSAVE }, 0 },
8093 },
8094 {
8095 /* MOD_0FC7_REG_6 */
8096 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8097 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8098 },
8099 {
8100 /* MOD_0FC7_REG_7 */
8101 { "vmptrst", { Mq }, 0 },
8102 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8103 },
8104 {
8105 /* MOD_0FD7 */
8106 { Bad_Opcode },
8107 { "pmovmskb", { Gdq, MS }, 0 },
8108 },
8109 {
8110 /* MOD_0FE7_PREFIX_2 */
8111 { "movntdq", { Mx, XM }, 0 },
8112 },
8113 {
8114 /* MOD_0FF0_PREFIX_3 */
8115 { "lddqu", { XM, M }, 0 },
8116 },
8117 {
8118 /* MOD_0F382A */
8119 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8120 },
8121 {
8122 /* MOD_0F38DC_PREFIX_1 */
8123 { "aesenc128kl", { XM, M }, 0 },
8124 { "loadiwkey", { XM, EXx }, 0 },
8125 },
8126 {
8127 /* MOD_0F38DD_PREFIX_1 */
8128 { "aesdec128kl", { XM, M }, 0 },
8129 },
8130 {
8131 /* MOD_0F38DE_PREFIX_1 */
8132 { "aesenc256kl", { XM, M }, 0 },
8133 },
8134 {
8135 /* MOD_0F38DF_PREFIX_1 */
8136 { "aesdec256kl", { XM, M }, 0 },
8137 },
8138 {
8139 /* MOD_0F38F5 */
8140 { "wrussK", { M, Gdq }, PREFIX_DATA },
8141 },
8142 {
8143 /* MOD_0F38F6_PREFIX_0 */
8144 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8145 },
8146 {
8147 /* MOD_0F38F8_PREFIX_1 */
8148 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8149 },
8150 {
8151 /* MOD_0F38F8_PREFIX_2 */
8152 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8153 },
8154 {
8155 /* MOD_0F38F8_PREFIX_3 */
8156 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8157 },
8158 {
8159 /* MOD_0F38F9 */
8160 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8161 },
8162 {
8163 /* MOD_0F38FA_PREFIX_1 */
8164 { Bad_Opcode },
8165 { "encodekey128", { Gd, Ed }, 0 },
8166 },
8167 {
8168 /* MOD_0F38FB_PREFIX_1 */
8169 { Bad_Opcode },
8170 { "encodekey256", { Gd, Ed }, 0 },
8171 },
8172 {
8173 /* MOD_0F3A0F_PREFIX_1 */
8174 { Bad_Opcode },
8175 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8176 },
8177 {
8178 /* MOD_VEX_0F12_PREFIX_0 */
8179 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8180 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8181 },
8182 {
8183 /* MOD_VEX_0F12_PREFIX_2 */
8184 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8185 },
8186 {
8187 /* MOD_VEX_0F13 */
8188 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8189 },
8190 {
8191 /* MOD_VEX_0F16_PREFIX_0 */
8192 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8193 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8194 },
8195 {
8196 /* MOD_VEX_0F16_PREFIX_2 */
8197 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8198 },
8199 {
8200 /* MOD_VEX_0F17 */
8201 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8202 },
8203 {
8204 /* MOD_VEX_0F2B */
8205 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8206 },
8207 {
8208 /* MOD_VEX_0F41_L_1 */
8209 { Bad_Opcode },
8210 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8211 },
8212 {
8213 /* MOD_VEX_0F42_L_1 */
8214 { Bad_Opcode },
8215 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8216 },
8217 {
8218 /* MOD_VEX_0F44_L_0 */
8219 { Bad_Opcode },
8220 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8221 },
8222 {
8223 /* MOD_VEX_0F45_L_1 */
8224 { Bad_Opcode },
8225 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8226 },
8227 {
8228 /* MOD_VEX_0F46_L_1 */
8229 { Bad_Opcode },
8230 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8231 },
8232 {
8233 /* MOD_VEX_0F47_L_1 */
8234 { Bad_Opcode },
8235 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8236 },
8237 {
8238 /* MOD_VEX_0F4A_L_1 */
8239 { Bad_Opcode },
8240 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8241 },
8242 {
8243 /* MOD_VEX_0F4B_L_1 */
8244 { Bad_Opcode },
8245 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8246 },
8247 {
8248 /* MOD_VEX_0F50 */
8249 { Bad_Opcode },
8250 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8251 },
8252 {
8253 /* MOD_VEX_0F71 */
8254 { Bad_Opcode },
8255 { REG_TABLE (REG_VEX_0F71_M_0) },
8256 },
8257 {
8258 /* MOD_VEX_0F72 */
8259 { Bad_Opcode },
8260 { REG_TABLE (REG_VEX_0F72_M_0) },
8261 },
8262 {
8263 /* MOD_VEX_0F73 */
8264 { Bad_Opcode },
8265 { REG_TABLE (REG_VEX_0F73_M_0) },
8266 },
8267 {
8268 /* MOD_VEX_0F91_L_0 */
8269 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8270 },
8271 {
8272 /* MOD_VEX_0F92_L_0 */
8273 { Bad_Opcode },
8274 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8275 },
8276 {
8277 /* MOD_VEX_0F93_L_0 */
8278 { Bad_Opcode },
8279 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8280 },
8281 {
8282 /* MOD_VEX_0F98_L_0 */
8283 { Bad_Opcode },
8284 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8285 },
8286 {
8287 /* MOD_VEX_0F99_L_0 */
8288 { Bad_Opcode },
8289 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8290 },
8291 {
8292 /* MOD_VEX_0FAE_REG_2 */
8293 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8294 },
8295 {
8296 /* MOD_VEX_0FAE_REG_3 */
8297 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8298 },
8299 {
8300 /* MOD_VEX_0FD7 */
8301 { Bad_Opcode },
8302 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8303 },
8304 {
8305 /* MOD_VEX_0FE7 */
8306 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8307 },
8308 {
8309 /* MOD_VEX_0FF0_PREFIX_3 */
8310 { "vlddqu", { XM, M }, 0 },
8311 },
8312 {
8313 /* MOD_VEX_0F381A */
8314 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8315 },
8316 {
8317 /* MOD_VEX_0F382A */
8318 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8319 },
8320 {
8321 /* MOD_VEX_0F382C */
8322 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8323 },
8324 {
8325 /* MOD_VEX_0F382D */
8326 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8327 },
8328 {
8329 /* MOD_VEX_0F382E */
8330 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8331 },
8332 {
8333 /* MOD_VEX_0F382F */
8334 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8335 },
8336 {
8337 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8338 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8339 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8340 },
8341 {
8342 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8343 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8344 },
8345 {
8346 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8347 { Bad_Opcode },
8348 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8349 },
8350 {
8351 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8352 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8353 },
8354 {
8355 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8356 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8357 },
8358 {
8359 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8360 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8361 },
8362 {
8363 /* MOD_VEX_0F385A */
8364 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8365 },
8366 {
8367 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8368 { Bad_Opcode },
8369 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8370 },
8371 {
8372 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8373 { Bad_Opcode },
8374 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8375 },
8376 {
8377 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8378 { Bad_Opcode },
8379 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8380 },
8381 {
8382 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8383 { Bad_Opcode },
8384 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8385 },
8386 {
8387 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8388 { Bad_Opcode },
8389 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8390 },
8391 {
8392 /* MOD_VEX_0F388C */
8393 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8394 },
8395 {
8396 /* MOD_VEX_0F388E */
8397 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8398 },
8399 {
8400 /* MOD_VEX_0F3A30_L_0 */
8401 { Bad_Opcode },
8402 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8403 },
8404 {
8405 /* MOD_VEX_0F3A31_L_0 */
8406 { Bad_Opcode },
8407 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8408 },
8409 {
8410 /* MOD_VEX_0F3A32_L_0 */
8411 { Bad_Opcode },
8412 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8413 },
8414 {
8415 /* MOD_VEX_0F3A33_L_0 */
8416 { Bad_Opcode },
8417 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8418 },
8419 {
8420 /* MOD_XOP_09_12 */
8421 { Bad_Opcode },
8422 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8423 },
8424
8425 #include "i386-dis-evex-mod.h"
8426 };
8427
8428 static const struct dis386 rm_table[][8] = {
8429 {
8430 /* RM_C6_REG_7 */
8431 { "xabort", { Skip_MODRM, Ib }, 0 },
8432 },
8433 {
8434 /* RM_C7_REG_7 */
8435 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8436 },
8437 {
8438 /* RM_0F01_REG_0 */
8439 { "enclv", { Skip_MODRM }, 0 },
8440 { "vmcall", { Skip_MODRM }, 0 },
8441 { "vmlaunch", { Skip_MODRM }, 0 },
8442 { "vmresume", { Skip_MODRM }, 0 },
8443 { "vmxoff", { Skip_MODRM }, 0 },
8444 { "pconfig", { Skip_MODRM }, 0 },
8445 },
8446 {
8447 /* RM_0F01_REG_1 */
8448 { "monitor", { { OP_Monitor, 0 } }, 0 },
8449 { "mwait", { { OP_Mwait, 0 } }, 0 },
8450 { "clac", { Skip_MODRM }, 0 },
8451 { "stac", { Skip_MODRM }, 0 },
8452 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8453 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8454 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8455 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8456 },
8457 {
8458 /* RM_0F01_REG_2 */
8459 { "xgetbv", { Skip_MODRM }, 0 },
8460 { "xsetbv", { Skip_MODRM }, 0 },
8461 { Bad_Opcode },
8462 { Bad_Opcode },
8463 { "vmfunc", { Skip_MODRM }, 0 },
8464 { "xend", { Skip_MODRM }, 0 },
8465 { "xtest", { Skip_MODRM }, 0 },
8466 { "enclu", { Skip_MODRM }, 0 },
8467 },
8468 {
8469 /* RM_0F01_REG_3 */
8470 { "vmrun", { Skip_MODRM }, 0 },
8471 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8472 { "vmload", { Skip_MODRM }, 0 },
8473 { "vmsave", { Skip_MODRM }, 0 },
8474 { "stgi", { Skip_MODRM }, 0 },
8475 { "clgi", { Skip_MODRM }, 0 },
8476 { "skinit", { Skip_MODRM }, 0 },
8477 { "invlpga", { Skip_MODRM }, 0 },
8478 },
8479 {
8480 /* RM_0F01_REG_5_MOD_3 */
8481 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8482 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8483 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8484 { Bad_Opcode },
8485 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8486 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8487 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8488 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8489 },
8490 {
8491 /* RM_0F01_REG_7_MOD_3 */
8492 { "swapgs", { Skip_MODRM }, 0 },
8493 { "rdtscp", { Skip_MODRM }, 0 },
8494 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8495 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8496 { "clzero", { Skip_MODRM }, 0 },
8497 { "rdpru", { Skip_MODRM }, 0 },
8498 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8499 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8500 },
8501 {
8502 /* RM_0F1E_P_1_MOD_3_REG_7 */
8503 { "nopQ", { Ev }, PREFIX_IGNORED },
8504 { "nopQ", { Ev }, PREFIX_IGNORED },
8505 { "endbr64", { Skip_MODRM }, 0 },
8506 { "endbr32", { Skip_MODRM }, 0 },
8507 { "nopQ", { Ev }, PREFIX_IGNORED },
8508 { "nopQ", { Ev }, PREFIX_IGNORED },
8509 { "nopQ", { Ev }, PREFIX_IGNORED },
8510 { "nopQ", { Ev }, PREFIX_IGNORED },
8511 },
8512 {
8513 /* RM_0FAE_REG_6_MOD_3 */
8514 { "mfence", { Skip_MODRM }, 0 },
8515 },
8516 {
8517 /* RM_0FAE_REG_7_MOD_3 */
8518 { "sfence", { Skip_MODRM }, 0 },
8519 },
8520 {
8521 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8522 { "hreset", { Skip_MODRM, Ib }, 0 },
8523 },
8524 {
8525 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8526 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8527 },
8528 };
8529
8530 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8531
8532 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8533 in conflict with actual prefix opcodes. */
8534 #define REP_PREFIX 0x01
8535 #define XACQUIRE_PREFIX 0x02
8536 #define XRELEASE_PREFIX 0x03
8537 #define BND_PREFIX 0x04
8538 #define NOTRACK_PREFIX 0x05
8539
8540 static int
ckprefix(instr_info * ins)8541 ckprefix (instr_info *ins)
8542 {
8543 int newrex, i, length;
8544
8545 i = 0;
8546 length = 0;
8547 /* The maximum instruction length is 15bytes. */
8548 while (length < MAX_CODE_LENGTH - 1)
8549 {
8550 FETCH_DATA (ins->info, ins->codep + 1);
8551 newrex = 0;
8552 switch (*ins->codep)
8553 {
8554 /* REX prefixes family. */
8555 case 0x40:
8556 case 0x41:
8557 case 0x42:
8558 case 0x43:
8559 case 0x44:
8560 case 0x45:
8561 case 0x46:
8562 case 0x47:
8563 case 0x48:
8564 case 0x49:
8565 case 0x4a:
8566 case 0x4b:
8567 case 0x4c:
8568 case 0x4d:
8569 case 0x4e:
8570 case 0x4f:
8571 if (ins->address_mode == mode_64bit)
8572 newrex = *ins->codep;
8573 else
8574 return 1;
8575 ins->last_rex_prefix = i;
8576 break;
8577 case 0xf3:
8578 ins->prefixes |= PREFIX_REPZ;
8579 ins->last_repz_prefix = i;
8580 break;
8581 case 0xf2:
8582 ins->prefixes |= PREFIX_REPNZ;
8583 ins->last_repnz_prefix = i;
8584 break;
8585 case 0xf0:
8586 ins->prefixes |= PREFIX_LOCK;
8587 ins->last_lock_prefix = i;
8588 break;
8589 case 0x2e:
8590 ins->prefixes |= PREFIX_CS;
8591 ins->last_seg_prefix = i;
8592 if (ins->address_mode != mode_64bit)
8593 ins->active_seg_prefix = PREFIX_CS;
8594 break;
8595 case 0x36:
8596 ins->prefixes |= PREFIX_SS;
8597 ins->last_seg_prefix = i;
8598 if (ins->address_mode != mode_64bit)
8599 ins->active_seg_prefix = PREFIX_SS;
8600 break;
8601 case 0x3e:
8602 ins->prefixes |= PREFIX_DS;
8603 ins->last_seg_prefix = i;
8604 if (ins->address_mode != mode_64bit)
8605 ins->active_seg_prefix = PREFIX_DS;
8606 break;
8607 case 0x26:
8608 ins->prefixes |= PREFIX_ES;
8609 ins->last_seg_prefix = i;
8610 if (ins->address_mode != mode_64bit)
8611 ins->active_seg_prefix = PREFIX_ES;
8612 break;
8613 case 0x64:
8614 ins->prefixes |= PREFIX_FS;
8615 ins->last_seg_prefix = i;
8616 ins->active_seg_prefix = PREFIX_FS;
8617 break;
8618 case 0x65:
8619 ins->prefixes |= PREFIX_GS;
8620 ins->last_seg_prefix = i;
8621 ins->active_seg_prefix = PREFIX_GS;
8622 break;
8623 case 0x66:
8624 ins->prefixes |= PREFIX_DATA;
8625 ins->last_data_prefix = i;
8626 break;
8627 case 0x67:
8628 ins->prefixes |= PREFIX_ADDR;
8629 ins->last_addr_prefix = i;
8630 break;
8631 case FWAIT_OPCODE:
8632 /* fwait is really an instruction. If there are prefixes
8633 before the fwait, they belong to the fwait, *not* to the
8634 following instruction. */
8635 ins->fwait_prefix = i;
8636 if (ins->prefixes || ins->rex)
8637 {
8638 ins->prefixes |= PREFIX_FWAIT;
8639 ins->codep++;
8640 /* This ensures that the previous REX prefixes are noticed
8641 as unused prefixes, as in the return case below. */
8642 ins->rex_used = ins->rex;
8643 return 1;
8644 }
8645 ins->prefixes = PREFIX_FWAIT;
8646 break;
8647 default:
8648 return 1;
8649 }
8650 /* Rex is ignored when followed by another prefix. */
8651 if (ins->rex)
8652 {
8653 ins->rex_used = ins->rex;
8654 return 1;
8655 }
8656 if (*ins->codep != FWAIT_OPCODE)
8657 ins->all_prefixes[i++] = *ins->codep;
8658 ins->rex = newrex;
8659 ins->codep++;
8660 length++;
8661 }
8662 return 0;
8663 }
8664
8665 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8666 prefix byte. */
8667
8668 static const char *
prefix_name(instr_info * ins,int pref,int sizeflag)8669 prefix_name (instr_info *ins, int pref, int sizeflag)
8670 {
8671 static const char *rexes [16] =
8672 {
8673 "rex", /* 0x40 */
8674 "rex.B", /* 0x41 */
8675 "rex.X", /* 0x42 */
8676 "rex.XB", /* 0x43 */
8677 "rex.R", /* 0x44 */
8678 "rex.RB", /* 0x45 */
8679 "rex.RX", /* 0x46 */
8680 "rex.RXB", /* 0x47 */
8681 "rex.W", /* 0x48 */
8682 "rex.WB", /* 0x49 */
8683 "rex.WX", /* 0x4a */
8684 "rex.WXB", /* 0x4b */
8685 "rex.WR", /* 0x4c */
8686 "rex.WRB", /* 0x4d */
8687 "rex.WRX", /* 0x4e */
8688 "rex.WRXB", /* 0x4f */
8689 };
8690
8691 switch (pref)
8692 {
8693 /* REX prefixes family. */
8694 case 0x40:
8695 case 0x41:
8696 case 0x42:
8697 case 0x43:
8698 case 0x44:
8699 case 0x45:
8700 case 0x46:
8701 case 0x47:
8702 case 0x48:
8703 case 0x49:
8704 case 0x4a:
8705 case 0x4b:
8706 case 0x4c:
8707 case 0x4d:
8708 case 0x4e:
8709 case 0x4f:
8710 return rexes [pref - 0x40];
8711 case 0xf3:
8712 return "repz";
8713 case 0xf2:
8714 return "repnz";
8715 case 0xf0:
8716 return "lock";
8717 case 0x2e:
8718 return "cs";
8719 case 0x36:
8720 return "ss";
8721 case 0x3e:
8722 return "ds";
8723 case 0x26:
8724 return "es";
8725 case 0x64:
8726 return "fs";
8727 case 0x65:
8728 return "gs";
8729 case 0x66:
8730 return (sizeflag & DFLAG) ? "data16" : "data32";
8731 case 0x67:
8732 if (ins->address_mode == mode_64bit)
8733 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8734 else
8735 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8736 case FWAIT_OPCODE:
8737 return "fwait";
8738 case REP_PREFIX:
8739 return "rep";
8740 case XACQUIRE_PREFIX:
8741 return "xacquire";
8742 case XRELEASE_PREFIX:
8743 return "xrelease";
8744 case BND_PREFIX:
8745 return "bnd";
8746 case NOTRACK_PREFIX:
8747 return "notrack";
8748 default:
8749 return NULL;
8750 }
8751 }
8752
8753 void
print_i386_disassembler_options(FILE * stream)8754 print_i386_disassembler_options (FILE *stream)
8755 {
8756 fprintf (stream, _("\n\
8757 The following i386/x86-64 specific disassembler options are supported for use\n\
8758 with the -M switch (multiple options should be separated by commas):\n"));
8759
8760 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8761 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8762 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8763 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8764 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8765 fprintf (stream, _(" att-mnemonic\n"
8766 " Display instruction in AT&T mnemonic\n"));
8767 fprintf (stream, _(" intel-mnemonic\n"
8768 " Display instruction in Intel mnemonic\n"));
8769 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8770 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8771 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8772 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8773 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8774 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8775 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8776 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8777 }
8778
8779 /* Bad opcode. */
8780 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8781
8782 /* Get a pointer to struct dis386 with a valid name. */
8783
8784 static const struct dis386 *
get_valid_dis386(const struct dis386 * dp,instr_info * ins)8785 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8786 {
8787 int vindex, vex_table_index;
8788
8789 if (dp->name != NULL)
8790 return dp;
8791
8792 switch (dp->op[0].bytemode)
8793 {
8794 case USE_REG_TABLE:
8795 dp = ®_table[dp->op[1].bytemode][ins->modrm.reg];
8796 break;
8797
8798 case USE_MOD_TABLE:
8799 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8800 dp = &mod_table[dp->op[1].bytemode][vindex];
8801 break;
8802
8803 case USE_RM_TABLE:
8804 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8805 break;
8806
8807 case USE_PREFIX_TABLE:
8808 if (ins->need_vex)
8809 {
8810 /* The prefix in VEX is implicit. */
8811 switch (ins->vex.prefix)
8812 {
8813 case 0:
8814 vindex = 0;
8815 break;
8816 case REPE_PREFIX_OPCODE:
8817 vindex = 1;
8818 break;
8819 case DATA_PREFIX_OPCODE:
8820 vindex = 2;
8821 break;
8822 case REPNE_PREFIX_OPCODE:
8823 vindex = 3;
8824 break;
8825 default:
8826 abort ();
8827 break;
8828 }
8829 }
8830 else
8831 {
8832 int last_prefix = -1;
8833 int prefix = 0;
8834 vindex = 0;
8835 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8836 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8837 last one wins. */
8838 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8839 {
8840 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8841 {
8842 vindex = 1;
8843 prefix = PREFIX_REPZ;
8844 last_prefix = ins->last_repz_prefix;
8845 }
8846 else
8847 {
8848 vindex = 3;
8849 prefix = PREFIX_REPNZ;
8850 last_prefix = ins->last_repnz_prefix;
8851 }
8852
8853 /* Check if prefix should be ignored. */
8854 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8855 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8856 & prefix) != 0
8857 && !prefix_table[dp->op[1].bytemode][vindex].name)
8858 vindex = 0;
8859 }
8860
8861 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8862 {
8863 vindex = 2;
8864 prefix = PREFIX_DATA;
8865 last_prefix = ins->last_data_prefix;
8866 }
8867
8868 if (vindex != 0)
8869 {
8870 ins->used_prefixes |= prefix;
8871 ins->all_prefixes[last_prefix] = 0;
8872 }
8873 }
8874 dp = &prefix_table[dp->op[1].bytemode][vindex];
8875 break;
8876
8877 case USE_X86_64_TABLE:
8878 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8879 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8880 break;
8881
8882 case USE_3BYTE_TABLE:
8883 FETCH_DATA (ins->info, ins->codep + 2);
8884 vindex = *ins->codep++;
8885 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8886 ins->end_codep = ins->codep;
8887 ins->modrm.mod = (*ins->codep >> 6) & 3;
8888 ins->modrm.reg = (*ins->codep >> 3) & 7;
8889 ins->modrm.rm = *ins->codep & 7;
8890 break;
8891
8892 case USE_VEX_LEN_TABLE:
8893 if (!ins->need_vex)
8894 abort ();
8895
8896 switch (ins->vex.length)
8897 {
8898 case 128:
8899 vindex = 0;
8900 break;
8901 case 512:
8902 /* This allows re-using in particular table entries where only
8903 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8904 if (ins->vex.evex)
8905 {
8906 case 256:
8907 vindex = 1;
8908 break;
8909 }
8910 /* Fall through. */
8911 default:
8912 abort ();
8913 break;
8914 }
8915
8916 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8917 break;
8918
8919 case USE_EVEX_LEN_TABLE:
8920 if (!ins->vex.evex)
8921 abort ();
8922
8923 switch (ins->vex.length)
8924 {
8925 case 128:
8926 vindex = 0;
8927 break;
8928 case 256:
8929 vindex = 1;
8930 break;
8931 case 512:
8932 vindex = 2;
8933 break;
8934 default:
8935 abort ();
8936 break;
8937 }
8938
8939 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8940 break;
8941
8942 case USE_XOP_8F_TABLE:
8943 FETCH_DATA (ins->info, ins->codep + 3);
8944 ins->rex = ~(*ins->codep >> 5) & 0x7;
8945
8946 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8947 switch ((*ins->codep & 0x1f))
8948 {
8949 default:
8950 dp = &bad_opcode;
8951 return dp;
8952 case 0x8:
8953 vex_table_index = XOP_08;
8954 break;
8955 case 0x9:
8956 vex_table_index = XOP_09;
8957 break;
8958 case 0xa:
8959 vex_table_index = XOP_0A;
8960 break;
8961 }
8962 ins->codep++;
8963 ins->vex.w = *ins->codep & 0x80;
8964 if (ins->vex.w && ins->address_mode == mode_64bit)
8965 ins->rex |= REX_W;
8966
8967 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8968 if (ins->address_mode != mode_64bit)
8969 {
8970 /* In 16/32-bit mode REX_B is silently ignored. */
8971 ins->rex &= ~REX_B;
8972 }
8973
8974 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8975 switch ((*ins->codep & 0x3))
8976 {
8977 case 0:
8978 break;
8979 case 1:
8980 ins->vex.prefix = DATA_PREFIX_OPCODE;
8981 break;
8982 case 2:
8983 ins->vex.prefix = REPE_PREFIX_OPCODE;
8984 break;
8985 case 3:
8986 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8987 break;
8988 }
8989 ins->need_vex = true;
8990 ins->codep++;
8991 vindex = *ins->codep++;
8992 dp = &xop_table[vex_table_index][vindex];
8993
8994 ins->end_codep = ins->codep;
8995 FETCH_DATA (ins->info, ins->codep + 1);
8996 ins->modrm.mod = (*ins->codep >> 6) & 3;
8997 ins->modrm.reg = (*ins->codep >> 3) & 7;
8998 ins->modrm.rm = *ins->codep & 7;
8999
9000 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9001 having to decode the bits for every otherwise valid encoding. */
9002 if (ins->vex.prefix)
9003 return &bad_opcode;
9004 break;
9005
9006 case USE_VEX_C4_TABLE:
9007 /* VEX prefix. */
9008 FETCH_DATA (ins->info, ins->codep + 3);
9009 ins->rex = ~(*ins->codep >> 5) & 0x7;
9010 switch ((*ins->codep & 0x1f))
9011 {
9012 default:
9013 dp = &bad_opcode;
9014 return dp;
9015 case 0x1:
9016 vex_table_index = VEX_0F;
9017 break;
9018 case 0x2:
9019 vex_table_index = VEX_0F38;
9020 break;
9021 case 0x3:
9022 vex_table_index = VEX_0F3A;
9023 break;
9024 }
9025 ins->codep++;
9026 ins->vex.w = *ins->codep & 0x80;
9027 if (ins->address_mode == mode_64bit)
9028 {
9029 if (ins->vex.w)
9030 ins->rex |= REX_W;
9031 }
9032 else
9033 {
9034 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9035 is ignored, other REX bits are 0 and the highest bit in
9036 VEX.vvvv is also ignored (but we mustn't clear it here). */
9037 ins->rex = 0;
9038 }
9039 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9040 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9041 switch ((*ins->codep & 0x3))
9042 {
9043 case 0:
9044 break;
9045 case 1:
9046 ins->vex.prefix = DATA_PREFIX_OPCODE;
9047 break;
9048 case 2:
9049 ins->vex.prefix = REPE_PREFIX_OPCODE;
9050 break;
9051 case 3:
9052 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9053 break;
9054 }
9055 ins->need_vex = true;
9056 ins->codep++;
9057 vindex = *ins->codep++;
9058 dp = &vex_table[vex_table_index][vindex];
9059 ins->end_codep = ins->codep;
9060 /* There is no MODRM byte for VEX0F 77. */
9061 if (vex_table_index != VEX_0F || vindex != 0x77)
9062 {
9063 FETCH_DATA (ins->info, ins->codep + 1);
9064 ins->modrm.mod = (*ins->codep >> 6) & 3;
9065 ins->modrm.reg = (*ins->codep >> 3) & 7;
9066 ins->modrm.rm = *ins->codep & 7;
9067 }
9068 break;
9069
9070 case USE_VEX_C5_TABLE:
9071 /* VEX prefix. */
9072 FETCH_DATA (ins->info, ins->codep + 2);
9073 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9074
9075 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9076 VEX.vvvv is 1. */
9077 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9078 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9079 switch ((*ins->codep & 0x3))
9080 {
9081 case 0:
9082 break;
9083 case 1:
9084 ins->vex.prefix = DATA_PREFIX_OPCODE;
9085 break;
9086 case 2:
9087 ins->vex.prefix = REPE_PREFIX_OPCODE;
9088 break;
9089 case 3:
9090 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9091 break;
9092 }
9093 ins->need_vex = true;
9094 ins->codep++;
9095 vindex = *ins->codep++;
9096 dp = &vex_table[dp->op[1].bytemode][vindex];
9097 ins->end_codep = ins->codep;
9098 /* There is no MODRM byte for VEX 77. */
9099 if (vindex != 0x77)
9100 {
9101 FETCH_DATA (ins->info, ins->codep + 1);
9102 ins->modrm.mod = (*ins->codep >> 6) & 3;
9103 ins->modrm.reg = (*ins->codep >> 3) & 7;
9104 ins->modrm.rm = *ins->codep & 7;
9105 }
9106 break;
9107
9108 case USE_VEX_W_TABLE:
9109 if (!ins->need_vex)
9110 abort ();
9111
9112 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9113 break;
9114
9115 case USE_EVEX_TABLE:
9116 ins->two_source_ops = false;
9117 /* EVEX prefix. */
9118 ins->vex.evex = true;
9119 FETCH_DATA (ins->info, ins->codep + 4);
9120 /* The first byte after 0x62. */
9121 ins->rex = ~(*ins->codep >> 5) & 0x7;
9122 ins->vex.r = *ins->codep & 0x10;
9123 switch ((*ins->codep & 0xf))
9124 {
9125 default:
9126 return &bad_opcode;
9127 case 0x1:
9128 vex_table_index = EVEX_0F;
9129 break;
9130 case 0x2:
9131 vex_table_index = EVEX_0F38;
9132 break;
9133 case 0x3:
9134 vex_table_index = EVEX_0F3A;
9135 break;
9136 case 0x5:
9137 vex_table_index = EVEX_MAP5;
9138 break;
9139 case 0x6:
9140 vex_table_index = EVEX_MAP6;
9141 break;
9142 }
9143
9144 /* The second byte after 0x62. */
9145 ins->codep++;
9146 ins->vex.w = *ins->codep & 0x80;
9147 if (ins->vex.w && ins->address_mode == mode_64bit)
9148 ins->rex |= REX_W;
9149
9150 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9151
9152 /* The U bit. */
9153 if (!(*ins->codep & 0x4))
9154 return &bad_opcode;
9155
9156 switch ((*ins->codep & 0x3))
9157 {
9158 case 0:
9159 break;
9160 case 1:
9161 ins->vex.prefix = DATA_PREFIX_OPCODE;
9162 break;
9163 case 2:
9164 ins->vex.prefix = REPE_PREFIX_OPCODE;
9165 break;
9166 case 3:
9167 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9168 break;
9169 }
9170
9171 /* The third byte after 0x62. */
9172 ins->codep++;
9173
9174 /* Remember the static rounding bits. */
9175 ins->vex.ll = (*ins->codep >> 5) & 3;
9176 ins->vex.b = *ins->codep & 0x10;
9177
9178 ins->vex.v = *ins->codep & 0x8;
9179 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9180 ins->vex.zeroing = *ins->codep & 0x80;
9181
9182 if (ins->address_mode != mode_64bit)
9183 {
9184 /* In 16/32-bit mode silently ignore following bits. */
9185 ins->rex &= ~REX_B;
9186 ins->vex.r = true;
9187 }
9188
9189 ins->need_vex = true;
9190 ins->codep++;
9191 vindex = *ins->codep++;
9192 dp = &evex_table[vex_table_index][vindex];
9193 ins->end_codep = ins->codep;
9194 FETCH_DATA (ins->info, ins->codep + 1);
9195 ins->modrm.mod = (*ins->codep >> 6) & 3;
9196 ins->modrm.reg = (*ins->codep >> 3) & 7;
9197 ins->modrm.rm = *ins->codep & 7;
9198
9199 /* Set vector length. */
9200 if (ins->modrm.mod == 3 && ins->vex.b)
9201 ins->vex.length = 512;
9202 else
9203 {
9204 switch (ins->vex.ll)
9205 {
9206 case 0x0:
9207 ins->vex.length = 128;
9208 break;
9209 case 0x1:
9210 ins->vex.length = 256;
9211 break;
9212 case 0x2:
9213 ins->vex.length = 512;
9214 break;
9215 default:
9216 return &bad_opcode;
9217 }
9218 }
9219 break;
9220
9221 case 0:
9222 dp = &bad_opcode;
9223 break;
9224
9225 default:
9226 abort ();
9227 }
9228
9229 if (dp->name != NULL)
9230 return dp;
9231 else
9232 return get_valid_dis386 (dp, ins);
9233 }
9234
9235 static void
get_sib(instr_info * ins,int sizeflag)9236 get_sib (instr_info *ins, int sizeflag)
9237 {
9238 /* If modrm.mod == 3, operand must be register. */
9239 if (ins->need_modrm
9240 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9241 && ins->modrm.mod != 3
9242 && ins->modrm.rm == 4)
9243 {
9244 FETCH_DATA (ins->info, ins->codep + 2);
9245 ins->sib.index = (ins->codep[1] >> 3) & 7;
9246 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9247 ins->sib.base = ins->codep[1] & 7;
9248 ins->has_sib = true;
9249 }
9250 else
9251 ins->has_sib = false;
9252 }
9253
9254 /* Like oappend (below), but S is a string starting with '%'. In
9255 Intel syntax, the '%' is elided. */
9256
9257 static void
oappend_register(instr_info * ins,const char * s)9258 oappend_register (instr_info *ins, const char *s)
9259 {
9260 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9261 }
9262
9263 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9264 STYLE is the default style to use in the fprintf_styled_func calls,
9265 however, FMT might include embedded style markers (see oappend_style),
9266 these embedded markers are not printed, but instead change the style
9267 used in the next fprintf_styled_func call.
9268
9269 Return non-zero to indicate the print call was a success. */
9270
9271 static int ATTRIBUTE_PRINTF_3
i386_dis_printf(instr_info * ins,enum disassembler_style style,const char * fmt,...)9272 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9273 const char *fmt, ...)
9274 {
9275 va_list ap;
9276 enum disassembler_style curr_style = style;
9277 char *start, *curr;
9278 char staging_area[100];
9279 int res;
9280
9281 va_start (ap, fmt);
9282 res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9283 va_end (ap);
9284
9285 if (res < 0)
9286 return res;
9287
9288 if ((size_t) res >= sizeof (staging_area))
9289 abort ();
9290
9291 start = curr = staging_area;
9292
9293 do
9294 {
9295 if (*curr == '\0'
9296 || (*curr == STYLE_MARKER_CHAR
9297 && ISXDIGIT (*(curr + 1))
9298 && *(curr + 2) == STYLE_MARKER_CHAR))
9299 {
9300 /* Output content between our START position and CURR. */
9301 int len = curr - start;
9302 int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9303 curr_style,
9304 "%.*s", len, start);
9305 if (n < 0)
9306 {
9307 res = n;
9308 break;
9309 }
9310
9311 if (*curr == '\0')
9312 break;
9313
9314 /* Skip over the initial STYLE_MARKER_CHAR. */
9315 ++curr;
9316
9317 /* Update the CURR_STYLE. As there are less than 16 styles, it
9318 is possible, that if the input is corrupted in some way, that
9319 we might set CURR_STYLE to an invalid value. Don't worry
9320 though, we check for this situation. */
9321 if (*curr >= '0' && *curr <= '9')
9322 curr_style = (enum disassembler_style) (*curr - '0');
9323 else if (*curr >= 'a' && *curr <= 'f')
9324 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9325 else
9326 curr_style = dis_style_text;
9327
9328 /* Check for an invalid style having been selected. This should
9329 never happen, but it doesn't hurt to be a little paranoid. */
9330 if (curr_style > dis_style_comment_start)
9331 curr_style = dis_style_text;
9332
9333 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9334 curr += 2;
9335
9336 /* Reset the START to after the style marker. */
9337 start = curr;
9338 }
9339 else
9340 ++curr;
9341 }
9342 while (true);
9343
9344 return res;
9345 }
9346
9347 static int
print_insn(bfd_vma pc,disassemble_info * info,int intel_syntax)9348 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9349 {
9350 const struct dis386 *dp;
9351 int i;
9352 char *op_txt[MAX_OPERANDS];
9353 int needcomma;
9354 bool intel_swap_2_3;
9355 int sizeflag, orig_sizeflag;
9356 const char *p;
9357 struct dis_private priv;
9358 int prefix_length;
9359 int op_count;
9360 instr_info ins = {
9361 .info = info,
9362 .intel_syntax = intel_syntax >= 0
9363 ? intel_syntax
9364 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9365 .intel_mnemonic = !SYSV386_COMPAT,
9366 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9367 .start_pc = pc,
9368 .start_codep = priv.the_buffer,
9369 .codep = priv.the_buffer,
9370 .obufp = ins.obuf,
9371 .last_lock_prefix = -1,
9372 .last_repz_prefix = -1,
9373 .last_repnz_prefix = -1,
9374 .last_data_prefix = -1,
9375 .last_addr_prefix = -1,
9376 .last_rex_prefix = -1,
9377 .last_seg_prefix = -1,
9378 .fwait_prefix = -1,
9379 };
9380 char op_out[MAX_OPERANDS][100];
9381
9382 priv.orig_sizeflag = AFLAG | DFLAG;
9383 if ((info->mach & bfd_mach_i386_i386) != 0)
9384 ins.address_mode = mode_32bit;
9385 else if (info->mach == bfd_mach_i386_i8086)
9386 {
9387 ins.address_mode = mode_16bit;
9388 priv.orig_sizeflag = 0;
9389 }
9390 else
9391 ins.address_mode = mode_64bit;
9392
9393 for (p = info->disassembler_options; p != NULL;)
9394 {
9395 if (startswith (p, "amd64"))
9396 ins.isa64 = amd64;
9397 else if (startswith (p, "intel64"))
9398 ins.isa64 = intel64;
9399 else if (startswith (p, "x86-64"))
9400 {
9401 ins.address_mode = mode_64bit;
9402 priv.orig_sizeflag |= AFLAG | DFLAG;
9403 }
9404 else if (startswith (p, "i386"))
9405 {
9406 ins.address_mode = mode_32bit;
9407 priv.orig_sizeflag |= AFLAG | DFLAG;
9408 }
9409 else if (startswith (p, "i8086"))
9410 {
9411 ins.address_mode = mode_16bit;
9412 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9413 }
9414 else if (startswith (p, "intel"))
9415 {
9416 ins.intel_syntax = 1;
9417 if (startswith (p + 5, "-mnemonic"))
9418 ins.intel_mnemonic = true;
9419 }
9420 else if (startswith (p, "att"))
9421 {
9422 ins.intel_syntax = 0;
9423 if (startswith (p + 3, "-mnemonic"))
9424 ins.intel_mnemonic = false;
9425 }
9426 else if (startswith (p, "addr"))
9427 {
9428 if (ins.address_mode == mode_64bit)
9429 {
9430 if (p[4] == '3' && p[5] == '2')
9431 priv.orig_sizeflag &= ~AFLAG;
9432 else if (p[4] == '6' && p[5] == '4')
9433 priv.orig_sizeflag |= AFLAG;
9434 }
9435 else
9436 {
9437 if (p[4] == '1' && p[5] == '6')
9438 priv.orig_sizeflag &= ~AFLAG;
9439 else if (p[4] == '3' && p[5] == '2')
9440 priv.orig_sizeflag |= AFLAG;
9441 }
9442 }
9443 else if (startswith (p, "data"))
9444 {
9445 if (p[4] == '1' && p[5] == '6')
9446 priv.orig_sizeflag &= ~DFLAG;
9447 else if (p[4] == '3' && p[5] == '2')
9448 priv.orig_sizeflag |= DFLAG;
9449 }
9450 else if (startswith (p, "suffix"))
9451 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9452
9453 p = strchr (p, ',');
9454 if (p != NULL)
9455 p++;
9456 }
9457
9458 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9459 {
9460 i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9461 return -1;
9462 }
9463
9464 if (ins.intel_syntax)
9465 {
9466 ins.open_char = '[';
9467 ins.close_char = ']';
9468 ins.separator_char = '+';
9469 ins.scale_char = '*';
9470 }
9471 else
9472 {
9473 ins.open_char = '(';
9474 ins.close_char = ')';
9475 ins.separator_char = ',';
9476 ins.scale_char = ',';
9477 }
9478
9479 /* The output looks better if we put 7 bytes on a line, since that
9480 puts most long word instructions on a single line. */
9481 info->bytes_per_line = 7;
9482
9483 info->private_data = &priv;
9484 priv.max_fetched = priv.the_buffer;
9485 priv.insn_start = pc;
9486
9487 for (i = 0; i < MAX_OPERANDS; ++i)
9488 {
9489 op_out[i][0] = 0;
9490 ins.op_out[i] = op_out[i];
9491 }
9492
9493 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9494 {
9495 /* Getting here means we tried for data but didn't get it. That
9496 means we have an incomplete instruction of some sort. Just
9497 print the first byte as a prefix or a .byte pseudo-op. */
9498 if (ins.codep > priv.the_buffer)
9499 {
9500 const char *name = NULL;
9501
9502 if (ins.prefixes || ins.fwait_prefix >= 0 || (ins.rex & REX_OPCODE))
9503 name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9504 if (name != NULL)
9505 i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9506 else
9507 {
9508 /* Just print the first byte as a .byte instruction. */
9509 i386_dis_printf (&ins, dis_style_assembler_directive,
9510 ".byte ");
9511 i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9512 (unsigned int) priv.the_buffer[0]);
9513 }
9514
9515 return 1;
9516 }
9517
9518 return -1;
9519 }
9520
9521 sizeflag = priv.orig_sizeflag;
9522
9523 if (!ckprefix (&ins) || ins.rex_used)
9524 {
9525 /* Too many prefixes or unused REX prefixes. */
9526 for (i = 0;
9527 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9528 i++)
9529 i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9530 (i == 0 ? "" : " "),
9531 prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9532 return i;
9533 }
9534
9535 ins.insn_codep = ins.codep;
9536
9537 FETCH_DATA (info, ins.codep + 1);
9538 ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9539
9540 if (((ins.prefixes & PREFIX_FWAIT)
9541 && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9542 {
9543 /* Handle ins.prefixes before fwait. */
9544 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9545 i++)
9546 i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9547 prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9548 i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9549 return i + 1;
9550 }
9551
9552 if (*ins.codep == 0x0f)
9553 {
9554 unsigned char threebyte;
9555
9556 ins.codep++;
9557 FETCH_DATA (info, ins.codep + 1);
9558 threebyte = *ins.codep;
9559 dp = &dis386_twobyte[threebyte];
9560 ins.need_modrm = twobyte_has_modrm[threebyte];
9561 ins.codep++;
9562 }
9563 else
9564 {
9565 dp = &dis386[*ins.codep];
9566 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9567 ins.codep++;
9568 }
9569
9570 /* Save sizeflag for printing the extra ins.prefixes later before updating
9571 it for mnemonic and operand processing. The prefix names depend
9572 only on the address mode. */
9573 orig_sizeflag = sizeflag;
9574 if (ins.prefixes & PREFIX_ADDR)
9575 sizeflag ^= AFLAG;
9576 if ((ins.prefixes & PREFIX_DATA))
9577 sizeflag ^= DFLAG;
9578
9579 ins.end_codep = ins.codep;
9580 if (ins.need_modrm)
9581 {
9582 FETCH_DATA (info, ins.codep + 1);
9583 ins.modrm.mod = (*ins.codep >> 6) & 3;
9584 ins.modrm.reg = (*ins.codep >> 3) & 7;
9585 ins.modrm.rm = *ins.codep & 7;
9586 }
9587
9588 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9589 {
9590 get_sib (&ins, sizeflag);
9591 dofloat (&ins, sizeflag);
9592 }
9593 else
9594 {
9595 dp = get_valid_dis386 (dp, &ins);
9596 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9597 {
9598 get_sib (&ins, sizeflag);
9599 for (i = 0; i < MAX_OPERANDS; ++i)
9600 {
9601 ins.obufp = ins.op_out[i];
9602 ins.op_ad = MAX_OPERANDS - 1 - i;
9603 if (dp->op[i].rtn)
9604 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9605 /* For EVEX instruction after the last operand masking
9606 should be printed. */
9607 if (i == 0 && ins.vex.evex)
9608 {
9609 /* Don't print {%k0}. */
9610 if (ins.vex.mask_register_specifier)
9611 {
9612 const char *reg_name
9613 = att_names_mask[ins.vex.mask_register_specifier];
9614
9615 oappend (&ins, "{");
9616 oappend_register (&ins, reg_name);
9617 oappend (&ins, "}");
9618 }
9619 if (ins.vex.zeroing)
9620 oappend (&ins, "{z}");
9621
9622 /* S/G insns require a mask and don't allow
9623 zeroing-masking. */
9624 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9625 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9626 && (ins.vex.mask_register_specifier == 0
9627 || ins.vex.zeroing))
9628 oappend (&ins, "/(bad)");
9629 }
9630 }
9631
9632 /* Check whether rounding control was enabled for an insn not
9633 supporting it. */
9634 if (ins.modrm.mod == 3 && ins.vex.b
9635 && !(ins.evex_used & EVEX_b_used))
9636 {
9637 for (i = 0; i < MAX_OPERANDS; ++i)
9638 {
9639 ins.obufp = ins.op_out[i];
9640 if (*ins.obufp)
9641 continue;
9642 oappend (&ins, names_rounding[ins.vex.ll]);
9643 oappend (&ins, "bad}");
9644 break;
9645 }
9646 }
9647 }
9648 }
9649
9650 /* Clear instruction information. */
9651 info->insn_info_valid = 0;
9652 info->branch_delay_insns = 0;
9653 info->data_size = 0;
9654 info->insn_type = dis_noninsn;
9655 info->target = 0;
9656 info->target2 = 0;
9657
9658 /* Reset jump operation indicator. */
9659 ins.op_is_jump = false;
9660 {
9661 int jump_detection = 0;
9662
9663 /* Extract flags. */
9664 for (i = 0; i < MAX_OPERANDS; ++i)
9665 {
9666 if ((dp->op[i].rtn == OP_J)
9667 || (dp->op[i].rtn == OP_indirE))
9668 jump_detection |= 1;
9669 else if ((dp->op[i].rtn == BND_Fixup)
9670 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9671 jump_detection |= 2;
9672 else if ((dp->op[i].bytemode == cond_jump_mode)
9673 || (dp->op[i].bytemode == loop_jcxz_mode))
9674 jump_detection |= 4;
9675 }
9676
9677 /* Determine if this is a jump or branch. */
9678 if ((jump_detection & 0x3) == 0x3)
9679 {
9680 ins.op_is_jump = true;
9681 if (jump_detection & 0x4)
9682 info->insn_type = dis_condbranch;
9683 else
9684 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9685 ? dis_jsr : dis_branch;
9686 }
9687 }
9688
9689 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9690 are all 0s in inverted form. */
9691 if (ins.need_vex && ins.vex.register_specifier != 0)
9692 {
9693 i386_dis_printf (&ins, dis_style_text, "(bad)");
9694 return ins.end_codep - priv.the_buffer;
9695 }
9696
9697 /* If EVEX.z is set, there must be an actual mask register in use. */
9698 if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
9699 {
9700 i386_dis_printf (&ins, dis_style_text, "(bad)");
9701 return ins.end_codep - priv.the_buffer;
9702 }
9703
9704 switch (dp->prefix_requirement)
9705 {
9706 case PREFIX_DATA:
9707 /* If only the data prefix is marked as mandatory, its absence renders
9708 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9709 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9710 {
9711 i386_dis_printf (&ins, dis_style_text, "(bad)");
9712 return ins.end_codep - priv.the_buffer;
9713 }
9714 ins.used_prefixes |= PREFIX_DATA;
9715 /* Fall through. */
9716 case PREFIX_OPCODE:
9717 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9718 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9719 used by putop and MMX/SSE operand and may be overridden by the
9720 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9721 separately. */
9722 if (((ins.need_vex
9723 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9724 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9725 : (ins.prefixes
9726 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9727 && (ins.used_prefixes
9728 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9729 || (((ins.need_vex
9730 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9731 : ((ins.prefixes
9732 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9733 == PREFIX_DATA))
9734 && (ins.used_prefixes & PREFIX_DATA) == 0))
9735 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9736 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9737 {
9738 i386_dis_printf (&ins, dis_style_text, "(bad)");
9739 return ins.end_codep - priv.the_buffer;
9740 }
9741 break;
9742
9743 case PREFIX_IGNORED:
9744 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9745 origins in all_prefixes. */
9746 ins.used_prefixes &= ~PREFIX_OPCODE;
9747 if (ins.last_data_prefix >= 0)
9748 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9749 if (ins.last_repz_prefix >= 0)
9750 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9751 if (ins.last_repnz_prefix >= 0)
9752 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9753 break;
9754 }
9755
9756 /* Check if the REX prefix is used. */
9757 if ((ins.rex ^ ins.rex_used) == 0
9758 && !ins.need_vex && ins.last_rex_prefix >= 0)
9759 ins.all_prefixes[ins.last_rex_prefix] = 0;
9760
9761 /* Check if the SEG prefix is used. */
9762 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9763 | PREFIX_FS | PREFIX_GS)) != 0
9764 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9765 ins.all_prefixes[ins.last_seg_prefix] = 0;
9766
9767 /* Check if the ADDR prefix is used. */
9768 if ((ins.prefixes & PREFIX_ADDR) != 0
9769 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9770 ins.all_prefixes[ins.last_addr_prefix] = 0;
9771
9772 /* Check if the DATA prefix is used. */
9773 if ((ins.prefixes & PREFIX_DATA) != 0
9774 && (ins.used_prefixes & PREFIX_DATA) != 0
9775 && !ins.need_vex)
9776 ins.all_prefixes[ins.last_data_prefix] = 0;
9777
9778 /* Print the extra ins.prefixes. */
9779 prefix_length = 0;
9780 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9781 if (ins.all_prefixes[i])
9782 {
9783 const char *name;
9784 name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
9785 if (name == NULL)
9786 abort ();
9787 prefix_length += strlen (name) + 1;
9788 i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
9789 }
9790
9791 /* Check maximum code length. */
9792 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9793 {
9794 i386_dis_printf (&ins, dis_style_text, "(bad)");
9795 return MAX_CODE_LENGTH;
9796 }
9797
9798 /* Calculate the number of operands this instruction has. */
9799 op_count = 0;
9800 for (i = 0; i < MAX_OPERANDS; ++i)
9801 if (*ins.op_out[i] != '\0')
9802 ++op_count;
9803
9804 /* Calculate the number of spaces to print after the mnemonic. */
9805 ins.obufp = ins.mnemonicendp;
9806 if (op_count > 0)
9807 {
9808 i = strlen (ins.obuf) + prefix_length;
9809 if (i < 7)
9810 i = 7 - i;
9811 else
9812 i = 1;
9813 }
9814 else
9815 i = 0;
9816
9817 /* Print the instruction mnemonic along with any trailing whitespace. */
9818 i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9819
9820 /* The enter and bound instructions are printed with operands in the same
9821 order as the intel book; everything else is printed in reverse order. */
9822 intel_swap_2_3 = false;
9823 if (ins.intel_syntax || ins.two_source_ops)
9824 {
9825 for (i = 0; i < MAX_OPERANDS; ++i)
9826 op_txt[i] = ins.op_out[i];
9827
9828 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9829 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9830 {
9831 op_txt[2] = ins.op_out[3];
9832 op_txt[3] = ins.op_out[2];
9833 intel_swap_2_3 = true;
9834 }
9835
9836 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9837 {
9838 bool riprel;
9839
9840 ins.op_ad = ins.op_index[i];
9841 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9842 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9843 riprel = ins.op_riprel[i];
9844 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9845 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9846 }
9847 }
9848 else
9849 {
9850 for (i = 0; i < MAX_OPERANDS; ++i)
9851 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9852 }
9853
9854 needcomma = 0;
9855 for (i = 0; i < MAX_OPERANDS; ++i)
9856 if (*op_txt[i])
9857 {
9858 /* In Intel syntax embedded rounding / SAE are not separate operands.
9859 Instead they're attached to the prior register operand. Simply
9860 suppress emission of the comma to achieve that effect. */
9861 switch (i & -(ins.intel_syntax && dp))
9862 {
9863 case 2:
9864 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9865 needcomma = 0;
9866 break;
9867 case 3:
9868 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9869 needcomma = 0;
9870 break;
9871 }
9872 if (needcomma)
9873 i386_dis_printf (&ins, dis_style_text, ",");
9874 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9875 {
9876 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9877
9878 if (ins.op_is_jump)
9879 {
9880 info->insn_info_valid = 1;
9881 info->branch_delay_insns = 0;
9882 info->data_size = 0;
9883 info->target = target;
9884 info->target2 = 0;
9885 }
9886 (*info->print_address_func) (target, info);
9887 }
9888 else
9889 i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
9890 needcomma = 1;
9891 }
9892
9893 for (i = 0; i < MAX_OPERANDS; i++)
9894 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9895 {
9896 i386_dis_printf (&ins, dis_style_comment_start, " # ");
9897 (*info->print_address_func)
9898 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9899 + ins.op_address[ins.op_index[i]]),
9900 info);
9901 break;
9902 }
9903 return ins.codep - priv.the_buffer;
9904 }
9905
9906 /* Here for backwards compatibility. When gdb stops using
9907 print_insn_i386_att and print_insn_i386_intel these functions can
9908 disappear, and print_insn_i386 be merged into print_insn. */
9909 int
print_insn_i386_att(bfd_vma pc,disassemble_info * info)9910 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9911 {
9912 return print_insn (pc, info, 0);
9913 }
9914
9915 int
print_insn_i386_intel(bfd_vma pc,disassemble_info * info)9916 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9917 {
9918 return print_insn (pc, info, 1);
9919 }
9920
9921 int
print_insn_i386(bfd_vma pc,disassemble_info * info)9922 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9923 {
9924 return print_insn (pc, info, -1);
9925 }
9926
9927 static const char *float_mem[] = {
9928 /* d8 */
9929 "fadd{s|}",
9930 "fmul{s|}",
9931 "fcom{s|}",
9932 "fcomp{s|}",
9933 "fsub{s|}",
9934 "fsubr{s|}",
9935 "fdiv{s|}",
9936 "fdivr{s|}",
9937 /* d9 */
9938 "fld{s|}",
9939 "(bad)",
9940 "fst{s|}",
9941 "fstp{s|}",
9942 "fldenv{C|C}",
9943 "fldcw",
9944 "fNstenv{C|C}",
9945 "fNstcw",
9946 /* da */
9947 "fiadd{l|}",
9948 "fimul{l|}",
9949 "ficom{l|}",
9950 "ficomp{l|}",
9951 "fisub{l|}",
9952 "fisubr{l|}",
9953 "fidiv{l|}",
9954 "fidivr{l|}",
9955 /* db */
9956 "fild{l|}",
9957 "fisttp{l|}",
9958 "fist{l|}",
9959 "fistp{l|}",
9960 "(bad)",
9961 "fld{t|}",
9962 "(bad)",
9963 "fstp{t|}",
9964 /* dc */
9965 "fadd{l|}",
9966 "fmul{l|}",
9967 "fcom{l|}",
9968 "fcomp{l|}",
9969 "fsub{l|}",
9970 "fsubr{l|}",
9971 "fdiv{l|}",
9972 "fdivr{l|}",
9973 /* dd */
9974 "fld{l|}",
9975 "fisttp{ll|}",
9976 "fst{l||}",
9977 "fstp{l|}",
9978 "frstor{C|C}",
9979 "(bad)",
9980 "fNsave{C|C}",
9981 "fNstsw",
9982 /* de */
9983 "fiadd{s|}",
9984 "fimul{s|}",
9985 "ficom{s|}",
9986 "ficomp{s|}",
9987 "fisub{s|}",
9988 "fisubr{s|}",
9989 "fidiv{s|}",
9990 "fidivr{s|}",
9991 /* df */
9992 "fild{s|}",
9993 "fisttp{s|}",
9994 "fist{s|}",
9995 "fistp{s|}",
9996 "fbld",
9997 "fild{ll|}",
9998 "fbstp",
9999 "fistp{ll|}",
10000 };
10001
10002 static const unsigned char float_mem_mode[] = {
10003 /* d8 */
10004 d_mode,
10005 d_mode,
10006 d_mode,
10007 d_mode,
10008 d_mode,
10009 d_mode,
10010 d_mode,
10011 d_mode,
10012 /* d9 */
10013 d_mode,
10014 0,
10015 d_mode,
10016 d_mode,
10017 0,
10018 w_mode,
10019 0,
10020 w_mode,
10021 /* da */
10022 d_mode,
10023 d_mode,
10024 d_mode,
10025 d_mode,
10026 d_mode,
10027 d_mode,
10028 d_mode,
10029 d_mode,
10030 /* db */
10031 d_mode,
10032 d_mode,
10033 d_mode,
10034 d_mode,
10035 0,
10036 t_mode,
10037 0,
10038 t_mode,
10039 /* dc */
10040 q_mode,
10041 q_mode,
10042 q_mode,
10043 q_mode,
10044 q_mode,
10045 q_mode,
10046 q_mode,
10047 q_mode,
10048 /* dd */
10049 q_mode,
10050 q_mode,
10051 q_mode,
10052 q_mode,
10053 0,
10054 0,
10055 0,
10056 w_mode,
10057 /* de */
10058 w_mode,
10059 w_mode,
10060 w_mode,
10061 w_mode,
10062 w_mode,
10063 w_mode,
10064 w_mode,
10065 w_mode,
10066 /* df */
10067 w_mode,
10068 w_mode,
10069 w_mode,
10070 w_mode,
10071 t_mode,
10072 q_mode,
10073 t_mode,
10074 q_mode
10075 };
10076
10077 #define ST { OP_ST, 0 }
10078 #define STi { OP_STi, 0 }
10079
10080 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10081 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10082 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10083 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10084 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10085 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10086 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10087 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10088 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10089
10090 static const struct dis386 float_reg[][8] = {
10091 /* d8 */
10092 {
10093 { "fadd", { ST, STi }, 0 },
10094 { "fmul", { ST, STi }, 0 },
10095 { "fcom", { STi }, 0 },
10096 { "fcomp", { STi }, 0 },
10097 { "fsub", { ST, STi }, 0 },
10098 { "fsubr", { ST, STi }, 0 },
10099 { "fdiv", { ST, STi }, 0 },
10100 { "fdivr", { ST, STi }, 0 },
10101 },
10102 /* d9 */
10103 {
10104 { "fld", { STi }, 0 },
10105 { "fxch", { STi }, 0 },
10106 { FGRPd9_2 },
10107 { Bad_Opcode },
10108 { FGRPd9_4 },
10109 { FGRPd9_5 },
10110 { FGRPd9_6 },
10111 { FGRPd9_7 },
10112 },
10113 /* da */
10114 {
10115 { "fcmovb", { ST, STi }, 0 },
10116 { "fcmove", { ST, STi }, 0 },
10117 { "fcmovbe",{ ST, STi }, 0 },
10118 { "fcmovu", { ST, STi }, 0 },
10119 { Bad_Opcode },
10120 { FGRPda_5 },
10121 { Bad_Opcode },
10122 { Bad_Opcode },
10123 },
10124 /* db */
10125 {
10126 { "fcmovnb",{ ST, STi }, 0 },
10127 { "fcmovne",{ ST, STi }, 0 },
10128 { "fcmovnbe",{ ST, STi }, 0 },
10129 { "fcmovnu",{ ST, STi }, 0 },
10130 { FGRPdb_4 },
10131 { "fucomi", { ST, STi }, 0 },
10132 { "fcomi", { ST, STi }, 0 },
10133 { Bad_Opcode },
10134 },
10135 /* dc */
10136 {
10137 { "fadd", { STi, ST }, 0 },
10138 { "fmul", { STi, ST }, 0 },
10139 { Bad_Opcode },
10140 { Bad_Opcode },
10141 { "fsub{!M|r}", { STi, ST }, 0 },
10142 { "fsub{M|}", { STi, ST }, 0 },
10143 { "fdiv{!M|r}", { STi, ST }, 0 },
10144 { "fdiv{M|}", { STi, ST }, 0 },
10145 },
10146 /* dd */
10147 {
10148 { "ffree", { STi }, 0 },
10149 { Bad_Opcode },
10150 { "fst", { STi }, 0 },
10151 { "fstp", { STi }, 0 },
10152 { "fucom", { STi }, 0 },
10153 { "fucomp", { STi }, 0 },
10154 { Bad_Opcode },
10155 { Bad_Opcode },
10156 },
10157 /* de */
10158 {
10159 { "faddp", { STi, ST }, 0 },
10160 { "fmulp", { STi, ST }, 0 },
10161 { Bad_Opcode },
10162 { FGRPde_3 },
10163 { "fsub{!M|r}p", { STi, ST }, 0 },
10164 { "fsub{M|}p", { STi, ST }, 0 },
10165 { "fdiv{!M|r}p", { STi, ST }, 0 },
10166 { "fdiv{M|}p", { STi, ST }, 0 },
10167 },
10168 /* df */
10169 {
10170 { "ffreep", { STi }, 0 },
10171 { Bad_Opcode },
10172 { Bad_Opcode },
10173 { Bad_Opcode },
10174 { FGRPdf_4 },
10175 { "fucomip", { ST, STi }, 0 },
10176 { "fcomip", { ST, STi }, 0 },
10177 { Bad_Opcode },
10178 },
10179 };
10180
10181 static const char *const fgrps[][8] = {
10182 /* Bad opcode 0 */
10183 {
10184 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10185 },
10186
10187 /* d9_2 1 */
10188 {
10189 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10190 },
10191
10192 /* d9_4 2 */
10193 {
10194 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10195 },
10196
10197 /* d9_5 3 */
10198 {
10199 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10200 },
10201
10202 /* d9_6 4 */
10203 {
10204 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10205 },
10206
10207 /* d9_7 5 */
10208 {
10209 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10210 },
10211
10212 /* da_5 6 */
10213 {
10214 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10215 },
10216
10217 /* db_4 7 */
10218 {
10219 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10220 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10221 },
10222
10223 /* de_3 8 */
10224 {
10225 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10226 },
10227
10228 /* df_4 9 */
10229 {
10230 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10231 },
10232 };
10233
10234 static void
swap_operand(instr_info * ins)10235 swap_operand (instr_info *ins)
10236 {
10237 ins->mnemonicendp[0] = '.';
10238 ins->mnemonicendp[1] = 's';
10239 ins->mnemonicendp[2] = '\0';
10240 ins->mnemonicendp += 2;
10241 }
10242
10243 static void
OP_Skip_MODRM(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10244 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10245 int sizeflag ATTRIBUTE_UNUSED)
10246 {
10247 /* Skip mod/rm byte. */
10248 MODRM_CHECK;
10249 ins->codep++;
10250 }
10251
10252 static void
dofloat(instr_info * ins,int sizeflag)10253 dofloat (instr_info *ins, int sizeflag)
10254 {
10255 const struct dis386 *dp;
10256 unsigned char floatop;
10257
10258 floatop = ins->codep[-1];
10259
10260 if (ins->modrm.mod != 3)
10261 {
10262 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10263
10264 putop (ins, float_mem[fp_indx], sizeflag);
10265 ins->obufp = ins->op_out[0];
10266 ins->op_ad = 2;
10267 OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10268 return;
10269 }
10270 /* Skip mod/rm byte. */
10271 MODRM_CHECK;
10272 ins->codep++;
10273
10274 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10275 if (dp->name == NULL)
10276 {
10277 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10278
10279 /* Instruction fnstsw is only one with strange arg. */
10280 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10281 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10282 }
10283 else
10284 {
10285 putop (ins, dp->name, sizeflag);
10286
10287 ins->obufp = ins->op_out[0];
10288 ins->op_ad = 2;
10289 if (dp->op[0].rtn)
10290 (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10291
10292 ins->obufp = ins->op_out[1];
10293 ins->op_ad = 1;
10294 if (dp->op[1].rtn)
10295 (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10296 }
10297 }
10298
10299 static void
OP_ST(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10300 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10301 int sizeflag ATTRIBUTE_UNUSED)
10302 {
10303 oappend_register (ins, "%st");
10304 }
10305
10306 static void
OP_STi(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10307 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10308 int sizeflag ATTRIBUTE_UNUSED)
10309 {
10310 char scratch[8];
10311 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10312
10313 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10314 abort ();
10315 oappend_register (ins, scratch);
10316 }
10317
10318 /* Capital letters in template are macros. */
10319 static int
putop(instr_info * ins,const char * in_template,int sizeflag)10320 putop (instr_info *ins, const char *in_template, int sizeflag)
10321 {
10322 const char *p;
10323 int alt = 0;
10324 int cond = 1;
10325 unsigned int l = 0, len = 0;
10326 char last[4];
10327
10328 for (p = in_template; *p; p++)
10329 {
10330 if (len > l)
10331 {
10332 if (l >= sizeof (last) || !ISUPPER (*p))
10333 abort ();
10334 last[l++] = *p;
10335 continue;
10336 }
10337 switch (*p)
10338 {
10339 default:
10340 *ins->obufp++ = *p;
10341 break;
10342 case '%':
10343 len++;
10344 break;
10345 case '!':
10346 cond = 0;
10347 break;
10348 case '{':
10349 if (ins->intel_syntax)
10350 {
10351 while (*++p != '|')
10352 if (*p == '}' || *p == '\0')
10353 abort ();
10354 alt = 1;
10355 }
10356 break;
10357 case '|':
10358 while (*++p != '}')
10359 {
10360 if (*p == '\0')
10361 abort ();
10362 }
10363 break;
10364 case '}':
10365 alt = 0;
10366 break;
10367 case 'A':
10368 if (ins->intel_syntax)
10369 break;
10370 if ((ins->need_modrm && ins->modrm.mod != 3)
10371 || (sizeflag & SUFFIX_ALWAYS))
10372 *ins->obufp++ = 'b';
10373 break;
10374 case 'B':
10375 if (l == 0)
10376 {
10377 case_B:
10378 if (ins->intel_syntax)
10379 break;
10380 if (sizeflag & SUFFIX_ALWAYS)
10381 *ins->obufp++ = 'b';
10382 }
10383 else if (l == 1 && last[0] == 'L')
10384 {
10385 if (ins->address_mode == mode_64bit
10386 && !(ins->prefixes & PREFIX_ADDR))
10387 {
10388 *ins->obufp++ = 'a';
10389 *ins->obufp++ = 'b';
10390 *ins->obufp++ = 's';
10391 }
10392
10393 goto case_B;
10394 }
10395 else
10396 abort ();
10397 break;
10398 case 'C':
10399 if (ins->intel_syntax && !alt)
10400 break;
10401 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10402 {
10403 if (sizeflag & DFLAG)
10404 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10405 else
10406 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10407 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10408 }
10409 break;
10410 case 'D':
10411 if (l == 1)
10412 {
10413 switch (last[0])
10414 {
10415 case 'X':
10416 if (!ins->vex.evex || ins->vex.w)
10417 *ins->obufp++ = 'd';
10418 else
10419 oappend (ins, "{bad}");
10420 break;
10421 default:
10422 abort ();
10423 }
10424 break;
10425 }
10426 if (l)
10427 abort ();
10428 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10429 break;
10430 USED_REX (REX_W);
10431 if (ins->modrm.mod == 3)
10432 {
10433 if (ins->rex & REX_W)
10434 *ins->obufp++ = 'q';
10435 else
10436 {
10437 if (sizeflag & DFLAG)
10438 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10439 else
10440 *ins->obufp++ = 'w';
10441 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10442 }
10443 }
10444 else
10445 *ins->obufp++ = 'w';
10446 break;
10447 case 'E': /* For jcxz/jecxz */
10448 if (ins->address_mode == mode_64bit)
10449 {
10450 if (sizeflag & AFLAG)
10451 *ins->obufp++ = 'r';
10452 else
10453 *ins->obufp++ = 'e';
10454 }
10455 else
10456 if (sizeflag & AFLAG)
10457 *ins->obufp++ = 'e';
10458 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10459 break;
10460 case 'F':
10461 if (ins->intel_syntax)
10462 break;
10463 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10464 {
10465 if (sizeflag & AFLAG)
10466 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10467 else
10468 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10469 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10470 }
10471 break;
10472 case 'G':
10473 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10474 && !(sizeflag & SUFFIX_ALWAYS)))
10475 break;
10476 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10477 *ins->obufp++ = 'l';
10478 else
10479 *ins->obufp++ = 'w';
10480 if (!(ins->rex & REX_W))
10481 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10482 break;
10483 case 'H':
10484 if (l == 0)
10485 {
10486 if (ins->intel_syntax)
10487 break;
10488 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10489 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10490 {
10491 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10492 *ins->obufp++ = ',';
10493 *ins->obufp++ = 'p';
10494
10495 /* Set active_seg_prefix even if not set in 64-bit mode
10496 because here it is a valid branch hint. */
10497 if (ins->prefixes & PREFIX_DS)
10498 {
10499 ins->active_seg_prefix = PREFIX_DS;
10500 *ins->obufp++ = 't';
10501 }
10502 else
10503 {
10504 ins->active_seg_prefix = PREFIX_CS;
10505 *ins->obufp++ = 'n';
10506 }
10507 }
10508 }
10509 else if (l == 1 && last[0] == 'X')
10510 {
10511 if (!ins->vex.w)
10512 *ins->obufp++ = 'h';
10513 else
10514 oappend (ins, "{bad}");
10515 }
10516 else
10517 abort ();
10518 break;
10519 case 'K':
10520 USED_REX (REX_W);
10521 if (ins->rex & REX_W)
10522 *ins->obufp++ = 'q';
10523 else
10524 *ins->obufp++ = 'd';
10525 break;
10526 case 'L':
10527 abort ();
10528 case 'M':
10529 if (ins->intel_mnemonic != cond)
10530 *ins->obufp++ = 'r';
10531 break;
10532 case 'N':
10533 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10534 *ins->obufp++ = 'n';
10535 else
10536 ins->used_prefixes |= PREFIX_FWAIT;
10537 break;
10538 case 'O':
10539 USED_REX (REX_W);
10540 if (ins->rex & REX_W)
10541 *ins->obufp++ = 'o';
10542 else if (ins->intel_syntax && (sizeflag & DFLAG))
10543 *ins->obufp++ = 'q';
10544 else
10545 *ins->obufp++ = 'd';
10546 if (!(ins->rex & REX_W))
10547 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10548 break;
10549 case '@':
10550 if (ins->address_mode == mode_64bit
10551 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10552 || !(ins->prefixes & PREFIX_DATA)))
10553 {
10554 if (sizeflag & SUFFIX_ALWAYS)
10555 *ins->obufp++ = 'q';
10556 break;
10557 }
10558 /* Fall through. */
10559 case 'P':
10560 if (l == 0)
10561 {
10562 if ((ins->modrm.mod == 3 || !cond)
10563 && !(sizeflag & SUFFIX_ALWAYS))
10564 break;
10565 /* Fall through. */
10566 case 'T':
10567 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10568 || ((sizeflag & SUFFIX_ALWAYS)
10569 && ins->address_mode != mode_64bit))
10570 {
10571 *ins->obufp++ = (sizeflag & DFLAG)
10572 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10573 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10574 }
10575 else if (sizeflag & SUFFIX_ALWAYS)
10576 *ins->obufp++ = 'q';
10577 }
10578 else if (l == 1 && last[0] == 'L')
10579 {
10580 if ((ins->prefixes & PREFIX_DATA)
10581 || (ins->rex & REX_W)
10582 || (sizeflag & SUFFIX_ALWAYS))
10583 {
10584 USED_REX (REX_W);
10585 if (ins->rex & REX_W)
10586 *ins->obufp++ = 'q';
10587 else
10588 {
10589 if (sizeflag & DFLAG)
10590 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10591 else
10592 *ins->obufp++ = 'w';
10593 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10594 }
10595 }
10596 }
10597 else
10598 abort ();
10599 break;
10600 case 'Q':
10601 if (l == 0)
10602 {
10603 if (ins->intel_syntax && !alt)
10604 break;
10605 USED_REX (REX_W);
10606 if ((ins->need_modrm && ins->modrm.mod != 3)
10607 || (sizeflag & SUFFIX_ALWAYS))
10608 {
10609 if (ins->rex & REX_W)
10610 *ins->obufp++ = 'q';
10611 else
10612 {
10613 if (sizeflag & DFLAG)
10614 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10615 else
10616 *ins->obufp++ = 'w';
10617 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10618 }
10619 }
10620 }
10621 else if (l == 1 && last[0] == 'D')
10622 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10623 else if (l == 1 && last[0] == 'L')
10624 {
10625 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10626 : ins->address_mode != mode_64bit)
10627 break;
10628 if ((ins->rex & REX_W))
10629 {
10630 USED_REX (REX_W);
10631 *ins->obufp++ = 'q';
10632 }
10633 else if ((ins->address_mode == mode_64bit && cond)
10634 || (sizeflag & SUFFIX_ALWAYS))
10635 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10636 }
10637 else
10638 abort ();
10639 break;
10640 case 'R':
10641 USED_REX (REX_W);
10642 if (ins->rex & REX_W)
10643 *ins->obufp++ = 'q';
10644 else if (sizeflag & DFLAG)
10645 {
10646 if (ins->intel_syntax)
10647 *ins->obufp++ = 'd';
10648 else
10649 *ins->obufp++ = 'l';
10650 }
10651 else
10652 *ins->obufp++ = 'w';
10653 if (ins->intel_syntax && !p[1]
10654 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10655 *ins->obufp++ = 'e';
10656 if (!(ins->rex & REX_W))
10657 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10658 break;
10659 case 'S':
10660 if (l == 0)
10661 {
10662 case_S:
10663 if (ins->intel_syntax)
10664 break;
10665 if (sizeflag & SUFFIX_ALWAYS)
10666 {
10667 if (ins->rex & REX_W)
10668 *ins->obufp++ = 'q';
10669 else
10670 {
10671 if (sizeflag & DFLAG)
10672 *ins->obufp++ = 'l';
10673 else
10674 *ins->obufp++ = 'w';
10675 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10676 }
10677 }
10678 break;
10679 }
10680 if (l != 1)
10681 abort ();
10682 switch (last[0])
10683 {
10684 case 'L':
10685 if (ins->address_mode == mode_64bit
10686 && !(ins->prefixes & PREFIX_ADDR))
10687 {
10688 *ins->obufp++ = 'a';
10689 *ins->obufp++ = 'b';
10690 *ins->obufp++ = 's';
10691 }
10692
10693 goto case_S;
10694 case 'X':
10695 if (!ins->vex.evex || !ins->vex.w)
10696 *ins->obufp++ = 's';
10697 else
10698 oappend (ins, "{bad}");
10699 break;
10700 default:
10701 abort ();
10702 }
10703 break;
10704 case 'V':
10705 if (l == 0)
10706 abort ();
10707 else if (l == 1
10708 && (last[0] == 'L' || last[0] == 'X'))
10709 {
10710 if (last[0] == 'X')
10711 {
10712 *ins->obufp++ = '{';
10713 *ins->obufp++ = 'v';
10714 *ins->obufp++ = 'e';
10715 *ins->obufp++ = 'x';
10716 *ins->obufp++ = '}';
10717 }
10718 else if (ins->rex & REX_W)
10719 {
10720 *ins->obufp++ = 'a';
10721 *ins->obufp++ = 'b';
10722 *ins->obufp++ = 's';
10723 }
10724 }
10725 else
10726 abort ();
10727 goto case_S;
10728 case 'W':
10729 if (l == 0)
10730 {
10731 /* operand size flag for cwtl, cbtw */
10732 USED_REX (REX_W);
10733 if (ins->rex & REX_W)
10734 {
10735 if (ins->intel_syntax)
10736 *ins->obufp++ = 'd';
10737 else
10738 *ins->obufp++ = 'l';
10739 }
10740 else if (sizeflag & DFLAG)
10741 *ins->obufp++ = 'w';
10742 else
10743 *ins->obufp++ = 'b';
10744 if (!(ins->rex & REX_W))
10745 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10746 }
10747 else if (l == 1)
10748 {
10749 if (!ins->need_vex)
10750 abort ();
10751 if (last[0] == 'X')
10752 *ins->obufp++ = ins->vex.w ? 'd': 's';
10753 else if (last[0] == 'B')
10754 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10755 else
10756 abort ();
10757 }
10758 else
10759 abort ();
10760 break;
10761 case 'X':
10762 if (l != 0)
10763 abort ();
10764 if (ins->need_vex
10765 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10766 : ins->prefixes & PREFIX_DATA)
10767 {
10768 *ins->obufp++ = 'd';
10769 ins->used_prefixes |= PREFIX_DATA;
10770 }
10771 else
10772 *ins->obufp++ = 's';
10773 break;
10774 case 'Y':
10775 if (l == 1 && last[0] == 'X')
10776 {
10777 if (!ins->need_vex)
10778 abort ();
10779 if (ins->intel_syntax
10780 || ((ins->modrm.mod == 3 || ins->vex.b)
10781 && !(sizeflag & SUFFIX_ALWAYS)))
10782 break;
10783 switch (ins->vex.length)
10784 {
10785 case 128:
10786 *ins->obufp++ = 'x';
10787 break;
10788 case 256:
10789 *ins->obufp++ = 'y';
10790 break;
10791 case 512:
10792 if (!ins->vex.evex)
10793 default:
10794 abort ();
10795 }
10796 }
10797 else
10798 abort ();
10799 break;
10800 case 'Z':
10801 if (l == 0)
10802 {
10803 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10804 ins->modrm.mod = 3;
10805 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10806 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10807 }
10808 else if (l == 1 && last[0] == 'X')
10809 {
10810 if (!ins->vex.evex)
10811 abort ();
10812 if (ins->intel_syntax
10813 || ((ins->modrm.mod == 3 || ins->vex.b)
10814 && !(sizeflag & SUFFIX_ALWAYS)))
10815 break;
10816 switch (ins->vex.length)
10817 {
10818 case 128:
10819 *ins->obufp++ = 'x';
10820 break;
10821 case 256:
10822 *ins->obufp++ = 'y';
10823 break;
10824 case 512:
10825 *ins->obufp++ = 'z';
10826 break;
10827 default:
10828 abort ();
10829 }
10830 }
10831 else
10832 abort ();
10833 break;
10834 case '^':
10835 if (ins->intel_syntax)
10836 break;
10837 if (ins->isa64 == intel64 && (ins->rex & REX_W))
10838 {
10839 USED_REX (REX_W);
10840 *ins->obufp++ = 'q';
10841 break;
10842 }
10843 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10844 {
10845 if (sizeflag & DFLAG)
10846 *ins->obufp++ = 'l';
10847 else
10848 *ins->obufp++ = 'w';
10849 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10850 }
10851 break;
10852 }
10853
10854 if (len == l)
10855 len = l = 0;
10856 }
10857 *ins->obufp = 0;
10858 ins->mnemonicendp = ins->obufp;
10859 return 0;
10860 }
10861
10862 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
10863 the buffer pointed to by INS->obufp has space. A style marker is made
10864 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10865 digit, followed by another STYLE_MARKER_CHAR. This function assumes
10866 that the number of styles is not greater than 16. */
10867
10868 static void
oappend_insert_style(instr_info * ins,enum disassembler_style style)10869 oappend_insert_style (instr_info *ins, enum disassembler_style style)
10870 {
10871 unsigned num = (unsigned) style;
10872
10873 /* We currently assume that STYLE can be encoded as a single hex
10874 character. If more styles are added then this might start to fail,
10875 and we'll need to expand this code. */
10876 if (num > 0xf)
10877 abort ();
10878
10879 *ins->obufp++ = STYLE_MARKER_CHAR;
10880 *ins->obufp++ = (num < 10 ? ('0' + num)
10881 : ((num < 16) ? ('a' + (num - 10)) : '0'));
10882 *ins->obufp++ = STYLE_MARKER_CHAR;
10883
10884 /* This final null character is not strictly necessary, after inserting a
10885 style marker we should always be inserting some additional content.
10886 However, having the buffer null terminated doesn't cost much, and make
10887 it easier to debug what's going on. Also, if we do ever forget to add
10888 any additional content after this style marker, then the buffer will
10889 still be well formed. */
10890 *ins->obufp = '\0';
10891 }
10892
10893 static void
oappend_with_style(instr_info * ins,const char * s,enum disassembler_style style)10894 oappend_with_style (instr_info *ins, const char *s,
10895 enum disassembler_style style)
10896 {
10897 oappend_insert_style (ins, style);
10898 ins->obufp = stpcpy (ins->obufp, s);
10899 }
10900
10901 /* Like oappend_with_style but always with text style. */
10902
10903 static void
oappend(instr_info * ins,const char * s)10904 oappend (instr_info *ins, const char *s)
10905 {
10906 oappend_with_style (ins, s, dis_style_text);
10907 }
10908
10909 /* Add a single character C to the buffer pointer to by INS->obufp, marking
10910 the style for the character as STYLE. */
10911
10912 static void
oappend_char_with_style(instr_info * ins,const char c,enum disassembler_style style)10913 oappend_char_with_style (instr_info *ins, const char c,
10914 enum disassembler_style style)
10915 {
10916 oappend_insert_style (ins, style);
10917 *ins->obufp++ = c;
10918 *ins->obufp = '\0';
10919 }
10920
10921 /* Like oappend_char_with_style, but always uses dis_style_text. */
10922
10923 static void
oappend_char(instr_info * ins,const char c)10924 oappend_char (instr_info *ins, const char c)
10925 {
10926 oappend_char_with_style (ins, c, dis_style_text);
10927 }
10928
10929 static void
append_seg(instr_info * ins)10930 append_seg (instr_info *ins)
10931 {
10932 /* Only print the active segment register. */
10933 if (!ins->active_seg_prefix)
10934 return;
10935
10936 ins->used_prefixes |= ins->active_seg_prefix;
10937 switch (ins->active_seg_prefix)
10938 {
10939 case PREFIX_CS:
10940 oappend_register (ins, "%cs");
10941 break;
10942 case PREFIX_DS:
10943 oappend_register (ins, "%ds");
10944 break;
10945 case PREFIX_SS:
10946 oappend_register (ins, "%ss");
10947 break;
10948 case PREFIX_ES:
10949 oappend_register (ins, "%es");
10950 break;
10951 case PREFIX_FS:
10952 oappend_register (ins, "%fs");
10953 break;
10954 case PREFIX_GS:
10955 oappend_register (ins, "%gs");
10956 break;
10957 default:
10958 break;
10959 }
10960 oappend_char (ins, ':');
10961 }
10962
10963 static void
OP_indirE(instr_info * ins,int bytemode,int sizeflag)10964 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
10965 {
10966 if (!ins->intel_syntax)
10967 oappend (ins, "*");
10968 OP_E (ins, bytemode, sizeflag);
10969 }
10970
10971 static void
print_operand_value(instr_info * ins,bfd_vma disp,enum disassembler_style style)10972 print_operand_value (instr_info *ins, bfd_vma disp,
10973 enum disassembler_style style)
10974 {
10975 char tmp[30];
10976 unsigned int i = 0;
10977
10978 if (ins->address_mode == mode_64bit)
10979 {
10980 oappend_with_style (ins, "0x", style);
10981 sprintf_vma (tmp, disp);
10982 while (tmp[i] == '0' && tmp[i + 1])
10983 ++i;
10984 }
10985 else
10986 sprintf (tmp, "0x%x", (unsigned int) disp);
10987 oappend_with_style (ins, tmp + i, style);
10988 }
10989
10990 /* Like oappend, but called for immediate operands. */
10991
10992 static void
oappend_immediate(instr_info * ins,bfd_vma imm)10993 oappend_immediate (instr_info *ins, bfd_vma imm)
10994 {
10995 if (!ins->intel_syntax)
10996 oappend_char_with_style (ins, '$', dis_style_immediate);
10997 print_operand_value (ins, imm, dis_style_immediate);
10998 }
10999
11000 /* Put DISP in BUF as signed hex number. */
11001
11002 static void
print_displacement(instr_info * ins,bfd_vma disp)11003 print_displacement (instr_info *ins, bfd_vma disp)
11004 {
11005 bfd_signed_vma val = disp;
11006 char tmp[30];
11007 unsigned int i;
11008
11009 if (val < 0)
11010 {
11011 oappend_char_with_style (ins, '-', dis_style_address_offset);
11012 val = -disp;
11013
11014 /* Check for possible overflow. */
11015 if (val < 0)
11016 {
11017 switch (ins->address_mode)
11018 {
11019 case mode_64bit:
11020 oappend_with_style (ins, "0x8000000000000000",
11021 dis_style_address_offset);
11022 break;
11023 case mode_32bit:
11024 oappend_with_style (ins, "0x80000000",
11025 dis_style_address_offset);
11026 break;
11027 case mode_16bit:
11028 oappend_with_style (ins, "0x8000",
11029 dis_style_address_offset);
11030 break;
11031 }
11032 return;
11033 }
11034 }
11035
11036 oappend_with_style (ins, "0x", dis_style_address_offset);
11037
11038 sprintf_vma (tmp, (bfd_vma) val);
11039 for (i = 0; tmp[i] == '0'; i++)
11040 continue;
11041 if (tmp[i] == '\0')
11042 i--;
11043 oappend_with_style (ins, tmp + i, dis_style_address_offset);
11044 }
11045
11046 static void
intel_operand_size(instr_info * ins,int bytemode,int sizeflag)11047 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11048 {
11049 if (ins->vex.b)
11050 {
11051 if (!ins->vex.no_broadcast)
11052 switch (bytemode)
11053 {
11054 case x_mode:
11055 case evex_half_bcst_xmmq_mode:
11056 if (ins->vex.w)
11057 oappend (ins, "QWORD BCST ");
11058 else
11059 oappend (ins, "DWORD BCST ");
11060 break;
11061 case xh_mode:
11062 case evex_half_bcst_xmmqh_mode:
11063 case evex_half_bcst_xmmqdh_mode:
11064 oappend (ins, "WORD BCST ");
11065 break;
11066 default:
11067 ins->vex.no_broadcast = true;
11068 break;
11069 }
11070 return;
11071 }
11072 switch (bytemode)
11073 {
11074 case b_mode:
11075 case b_swap_mode:
11076 case db_mode:
11077 oappend (ins, "BYTE PTR ");
11078 break;
11079 case w_mode:
11080 case w_swap_mode:
11081 case dw_mode:
11082 oappend (ins, "WORD PTR ");
11083 break;
11084 case indir_v_mode:
11085 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11086 {
11087 oappend (ins, "QWORD PTR ");
11088 break;
11089 }
11090 /* Fall through. */
11091 case stack_v_mode:
11092 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11093 || (ins->rex & REX_W)))
11094 {
11095 oappend (ins, "QWORD PTR ");
11096 break;
11097 }
11098 /* Fall through. */
11099 case v_mode:
11100 case v_swap_mode:
11101 case dq_mode:
11102 USED_REX (REX_W);
11103 if (ins->rex & REX_W)
11104 oappend (ins, "QWORD PTR ");
11105 else if (bytemode == dq_mode)
11106 oappend (ins, "DWORD PTR ");
11107 else
11108 {
11109 if (sizeflag & DFLAG)
11110 oappend (ins, "DWORD PTR ");
11111 else
11112 oappend (ins, "WORD PTR ");
11113 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11114 }
11115 break;
11116 case z_mode:
11117 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11118 *ins->obufp++ = 'D';
11119 oappend (ins, "WORD PTR ");
11120 if (!(ins->rex & REX_W))
11121 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11122 break;
11123 case a_mode:
11124 if (sizeflag & DFLAG)
11125 oappend (ins, "QWORD PTR ");
11126 else
11127 oappend (ins, "DWORD PTR ");
11128 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11129 break;
11130 case movsxd_mode:
11131 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11132 oappend (ins, "WORD PTR ");
11133 else
11134 oappend (ins, "DWORD PTR ");
11135 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11136 break;
11137 case d_mode:
11138 case d_swap_mode:
11139 oappend (ins, "DWORD PTR ");
11140 break;
11141 case q_mode:
11142 case q_swap_mode:
11143 oappend (ins, "QWORD PTR ");
11144 break;
11145 case m_mode:
11146 if (ins->address_mode == mode_64bit)
11147 oappend (ins, "QWORD PTR ");
11148 else
11149 oappend (ins, "DWORD PTR ");
11150 break;
11151 case f_mode:
11152 if (sizeflag & DFLAG)
11153 oappend (ins, "FWORD PTR ");
11154 else
11155 oappend (ins, "DWORD PTR ");
11156 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11157 break;
11158 case t_mode:
11159 oappend (ins, "TBYTE PTR ");
11160 break;
11161 case x_mode:
11162 case xh_mode:
11163 case x_swap_mode:
11164 case evex_x_gscat_mode:
11165 case evex_x_nobcst_mode:
11166 case bw_unit_mode:
11167 if (ins->need_vex)
11168 {
11169 switch (ins->vex.length)
11170 {
11171 case 128:
11172 oappend (ins, "XMMWORD PTR ");
11173 break;
11174 case 256:
11175 oappend (ins, "YMMWORD PTR ");
11176 break;
11177 case 512:
11178 oappend (ins, "ZMMWORD PTR ");
11179 break;
11180 default:
11181 abort ();
11182 }
11183 }
11184 else
11185 oappend (ins, "XMMWORD PTR ");
11186 break;
11187 case xmm_mode:
11188 oappend (ins, "XMMWORD PTR ");
11189 break;
11190 case ymm_mode:
11191 oappend (ins, "YMMWORD PTR ");
11192 break;
11193 case xmmq_mode:
11194 case evex_half_bcst_xmmqh_mode:
11195 case evex_half_bcst_xmmq_mode:
11196 if (!ins->need_vex)
11197 abort ();
11198
11199 switch (ins->vex.length)
11200 {
11201 case 128:
11202 oappend (ins, "QWORD PTR ");
11203 break;
11204 case 256:
11205 oappend (ins, "XMMWORD PTR ");
11206 break;
11207 case 512:
11208 oappend (ins, "YMMWORD PTR ");
11209 break;
11210 default:
11211 abort ();
11212 }
11213 break;
11214 case xmmdw_mode:
11215 if (!ins->need_vex)
11216 abort ();
11217
11218 switch (ins->vex.length)
11219 {
11220 case 128:
11221 oappend (ins, "WORD PTR ");
11222 break;
11223 case 256:
11224 oappend (ins, "DWORD PTR ");
11225 break;
11226 case 512:
11227 oappend (ins, "QWORD PTR ");
11228 break;
11229 default:
11230 abort ();
11231 }
11232 break;
11233 case xmmqd_mode:
11234 case evex_half_bcst_xmmqdh_mode:
11235 if (!ins->need_vex)
11236 abort ();
11237
11238 switch (ins->vex.length)
11239 {
11240 case 128:
11241 oappend (ins, "DWORD PTR ");
11242 break;
11243 case 256:
11244 oappend (ins, "QWORD PTR ");
11245 break;
11246 case 512:
11247 oappend (ins, "XMMWORD PTR ");
11248 break;
11249 default:
11250 abort ();
11251 }
11252 break;
11253 case ymmq_mode:
11254 if (!ins->need_vex)
11255 abort ();
11256
11257 switch (ins->vex.length)
11258 {
11259 case 128:
11260 oappend (ins, "QWORD PTR ");
11261 break;
11262 case 256:
11263 oappend (ins, "YMMWORD PTR ");
11264 break;
11265 case 512:
11266 oappend (ins, "ZMMWORD PTR ");
11267 break;
11268 default:
11269 abort ();
11270 }
11271 break;
11272 case o_mode:
11273 oappend (ins, "OWORD PTR ");
11274 break;
11275 case vex_vsib_d_w_dq_mode:
11276 case vex_vsib_q_w_dq_mode:
11277 if (!ins->need_vex)
11278 abort ();
11279 if (ins->vex.w)
11280 oappend (ins, "QWORD PTR ");
11281 else
11282 oappend (ins, "DWORD PTR ");
11283 break;
11284 case mask_bd_mode:
11285 if (!ins->need_vex || ins->vex.length != 128)
11286 abort ();
11287 if (ins->vex.w)
11288 oappend (ins, "DWORD PTR ");
11289 else
11290 oappend (ins, "BYTE PTR ");
11291 break;
11292 case mask_mode:
11293 if (!ins->need_vex)
11294 abort ();
11295 if (ins->vex.w)
11296 oappend (ins, "QWORD PTR ");
11297 else
11298 oappend (ins, "WORD PTR ");
11299 break;
11300 case v_bnd_mode:
11301 case v_bndmk_mode:
11302 default:
11303 break;
11304 }
11305 }
11306
11307 static void
print_register(instr_info * ins,unsigned int reg,unsigned int rexmask,int bytemode,int sizeflag)11308 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11309 int bytemode, int sizeflag)
11310 {
11311 const char *const *names;
11312
11313 USED_REX (rexmask);
11314 if (ins->rex & rexmask)
11315 reg += 8;
11316
11317 switch (bytemode)
11318 {
11319 case b_mode:
11320 case b_swap_mode:
11321 if (reg & 4)
11322 USED_REX (0);
11323 if (ins->rex)
11324 names = att_names8rex;
11325 else
11326 names = att_names8;
11327 break;
11328 case w_mode:
11329 names = att_names16;
11330 break;
11331 case d_mode:
11332 case dw_mode:
11333 case db_mode:
11334 names = att_names32;
11335 break;
11336 case q_mode:
11337 names = att_names64;
11338 break;
11339 case m_mode:
11340 case v_bnd_mode:
11341 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11342 break;
11343 case bnd_mode:
11344 case bnd_swap_mode:
11345 if (reg > 0x3)
11346 {
11347 oappend (ins, "(bad)");
11348 return;
11349 }
11350 names = att_names_bnd;
11351 break;
11352 case indir_v_mode:
11353 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11354 {
11355 names = att_names64;
11356 break;
11357 }
11358 /* Fall through. */
11359 case stack_v_mode:
11360 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11361 || (ins->rex & REX_W)))
11362 {
11363 names = att_names64;
11364 break;
11365 }
11366 bytemode = v_mode;
11367 /* Fall through. */
11368 case v_mode:
11369 case v_swap_mode:
11370 case dq_mode:
11371 USED_REX (REX_W);
11372 if (ins->rex & REX_W)
11373 names = att_names64;
11374 else if (bytemode != v_mode && bytemode != v_swap_mode)
11375 names = att_names32;
11376 else
11377 {
11378 if (sizeflag & DFLAG)
11379 names = att_names32;
11380 else
11381 names = att_names16;
11382 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11383 }
11384 break;
11385 case movsxd_mode:
11386 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11387 names = att_names16;
11388 else
11389 names = att_names32;
11390 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11391 break;
11392 case va_mode:
11393 names = (ins->address_mode == mode_64bit
11394 ? att_names64 : att_names32);
11395 if (!(ins->prefixes & PREFIX_ADDR))
11396 names = (ins->address_mode == mode_16bit
11397 ? att_names16 : names);
11398 else
11399 {
11400 /* Remove "addr16/addr32". */
11401 ins->all_prefixes[ins->last_addr_prefix] = 0;
11402 names = (ins->address_mode != mode_32bit
11403 ? att_names32 : att_names16);
11404 ins->used_prefixes |= PREFIX_ADDR;
11405 }
11406 break;
11407 case mask_bd_mode:
11408 case mask_mode:
11409 if (reg > 0x7)
11410 {
11411 oappend (ins, "(bad)");
11412 return;
11413 }
11414 names = att_names_mask;
11415 break;
11416 case 0:
11417 return;
11418 default:
11419 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11420 return;
11421 }
11422 oappend_register (ins, names[reg]);
11423 }
11424
11425 static void
OP_E_memory(instr_info * ins,int bytemode,int sizeflag)11426 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11427 {
11428 bfd_vma disp = 0;
11429 int add = (ins->rex & REX_B) ? 8 : 0;
11430 int riprel = 0;
11431 int shift;
11432
11433 if (ins->vex.evex)
11434 {
11435 switch (bytemode)
11436 {
11437 case dw_mode:
11438 case w_mode:
11439 case w_swap_mode:
11440 shift = 1;
11441 break;
11442 case db_mode:
11443 case b_mode:
11444 shift = 0;
11445 break;
11446 case dq_mode:
11447 if (ins->address_mode != mode_64bit)
11448 {
11449 case d_mode:
11450 case d_swap_mode:
11451 shift = 2;
11452 break;
11453 }
11454 /* fall through */
11455 case vex_vsib_d_w_dq_mode:
11456 case vex_vsib_q_w_dq_mode:
11457 case evex_x_gscat_mode:
11458 shift = ins->vex.w ? 3 : 2;
11459 break;
11460 case xh_mode:
11461 case evex_half_bcst_xmmqh_mode:
11462 case evex_half_bcst_xmmqdh_mode:
11463 if (ins->vex.b)
11464 {
11465 shift = ins->vex.w ? 2 : 1;
11466 break;
11467 }
11468 /* Fall through. */
11469 case x_mode:
11470 case evex_half_bcst_xmmq_mode:
11471 if (ins->vex.b)
11472 {
11473 shift = ins->vex.w ? 3 : 2;
11474 break;
11475 }
11476 /* Fall through. */
11477 case xmmqd_mode:
11478 case xmmdw_mode:
11479 case xmmq_mode:
11480 case ymmq_mode:
11481 case evex_x_nobcst_mode:
11482 case x_swap_mode:
11483 switch (ins->vex.length)
11484 {
11485 case 128:
11486 shift = 4;
11487 break;
11488 case 256:
11489 shift = 5;
11490 break;
11491 case 512:
11492 shift = 6;
11493 break;
11494 default:
11495 abort ();
11496 }
11497 /* Make necessary corrections to shift for modes that need it. */
11498 if (bytemode == xmmq_mode
11499 || bytemode == evex_half_bcst_xmmqh_mode
11500 || bytemode == evex_half_bcst_xmmq_mode
11501 || (bytemode == ymmq_mode && ins->vex.length == 128))
11502 shift -= 1;
11503 else if (bytemode == xmmqd_mode
11504 || bytemode == evex_half_bcst_xmmqdh_mode)
11505 shift -= 2;
11506 else if (bytemode == xmmdw_mode)
11507 shift -= 3;
11508 break;
11509 case ymm_mode:
11510 shift = 5;
11511 break;
11512 case xmm_mode:
11513 shift = 4;
11514 break;
11515 case q_mode:
11516 case q_swap_mode:
11517 shift = 3;
11518 break;
11519 case bw_unit_mode:
11520 shift = ins->vex.w ? 1 : 0;
11521 break;
11522 default:
11523 abort ();
11524 }
11525 }
11526 else
11527 shift = 0;
11528
11529 USED_REX (REX_B);
11530 if (ins->intel_syntax)
11531 intel_operand_size (ins, bytemode, sizeflag);
11532 append_seg (ins);
11533
11534 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11535 {
11536 /* 32/64 bit address mode */
11537 int havedisp;
11538 int havebase;
11539 int needindex;
11540 int needaddr32;
11541 int base, rbase;
11542 int vindex = 0;
11543 int scale = 0;
11544 int addr32flag = !((sizeflag & AFLAG)
11545 || bytemode == v_bnd_mode
11546 || bytemode == v_bndmk_mode
11547 || bytemode == bnd_mode
11548 || bytemode == bnd_swap_mode);
11549 bool check_gather = false;
11550 const char *const *indexes = NULL;
11551
11552 havebase = 1;
11553 base = ins->modrm.rm;
11554
11555 if (base == 4)
11556 {
11557 vindex = ins->sib.index;
11558 USED_REX (REX_X);
11559 if (ins->rex & REX_X)
11560 vindex += 8;
11561 switch (bytemode)
11562 {
11563 case vex_vsib_d_w_dq_mode:
11564 case vex_vsib_q_w_dq_mode:
11565 if (!ins->need_vex)
11566 abort ();
11567 if (ins->vex.evex)
11568 {
11569 if (!ins->vex.v)
11570 vindex += 16;
11571 check_gather = ins->obufp == ins->op_out[1];
11572 }
11573
11574 switch (ins->vex.length)
11575 {
11576 case 128:
11577 indexes = att_names_xmm;
11578 break;
11579 case 256:
11580 if (!ins->vex.w
11581 || bytemode == vex_vsib_q_w_dq_mode)
11582 indexes = att_names_ymm;
11583 else
11584 indexes = att_names_xmm;
11585 break;
11586 case 512:
11587 if (!ins->vex.w
11588 || bytemode == vex_vsib_q_w_dq_mode)
11589 indexes = att_names_zmm;
11590 else
11591 indexes = att_names_ymm;
11592 break;
11593 default:
11594 abort ();
11595 }
11596 break;
11597 default:
11598 if (vindex != 4)
11599 indexes = ins->address_mode == mode_64bit && !addr32flag
11600 ? att_names64 : att_names32;
11601 break;
11602 }
11603 scale = ins->sib.scale;
11604 base = ins->sib.base;
11605 ins->codep++;
11606 }
11607 else
11608 {
11609 /* Check for mandatory SIB. */
11610 if (bytemode == vex_vsib_d_w_dq_mode
11611 || bytemode == vex_vsib_q_w_dq_mode
11612 || bytemode == vex_sibmem_mode)
11613 {
11614 oappend (ins, "(bad)");
11615 return;
11616 }
11617 }
11618 rbase = base + add;
11619
11620 switch (ins->modrm.mod)
11621 {
11622 case 0:
11623 if (base == 5)
11624 {
11625 havebase = 0;
11626 if (ins->address_mode == mode_64bit && !ins->has_sib)
11627 riprel = 1;
11628 disp = get32s (ins);
11629 if (riprel && bytemode == v_bndmk_mode)
11630 {
11631 oappend (ins, "(bad)");
11632 return;
11633 }
11634 }
11635 break;
11636 case 1:
11637 FETCH_DATA (ins->info, ins->codep + 1);
11638 disp = *ins->codep++;
11639 if ((disp & 0x80) != 0)
11640 disp -= 0x100;
11641 if (ins->vex.evex && shift > 0)
11642 disp <<= shift;
11643 break;
11644 case 2:
11645 disp = get32s (ins);
11646 break;
11647 }
11648
11649 needindex = 0;
11650 needaddr32 = 0;
11651 if (ins->has_sib
11652 && !havebase
11653 && !indexes
11654 && ins->address_mode != mode_16bit)
11655 {
11656 if (ins->address_mode == mode_64bit)
11657 {
11658 if (addr32flag)
11659 {
11660 /* Without base nor index registers, zero-extend the
11661 lower 32-bit displacement to 64 bits. */
11662 disp = (unsigned int) disp;
11663 needindex = 1;
11664 }
11665 needaddr32 = 1;
11666 }
11667 else
11668 {
11669 /* In 32-bit mode, we need index register to tell [offset]
11670 from [eiz*1 + offset]. */
11671 needindex = 1;
11672 }
11673 }
11674
11675 havedisp = (havebase
11676 || needindex
11677 || (ins->has_sib && (indexes || scale != 0)));
11678
11679 if (!ins->intel_syntax)
11680 if (ins->modrm.mod != 0 || base == 5)
11681 {
11682 if (havedisp || riprel)
11683 print_displacement (ins, disp);
11684 else
11685 print_operand_value (ins, disp, dis_style_address_offset);
11686 if (riprel)
11687 {
11688 set_op (ins, disp, true);
11689 oappend_char (ins, '(');
11690 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11691 dis_style_register);
11692 oappend_char (ins, ')');
11693 }
11694 }
11695
11696 if ((havebase || indexes || needindex || needaddr32 || riprel)
11697 && (ins->address_mode != mode_64bit
11698 || ((bytemode != v_bnd_mode)
11699 && (bytemode != v_bndmk_mode)
11700 && (bytemode != bnd_mode)
11701 && (bytemode != bnd_swap_mode))))
11702 ins->used_prefixes |= PREFIX_ADDR;
11703
11704 if (havedisp || (ins->intel_syntax && riprel))
11705 {
11706 oappend_char (ins, ins->open_char);
11707 if (ins->intel_syntax && riprel)
11708 {
11709 set_op (ins, disp, true);
11710 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11711 dis_style_register);
11712 }
11713 if (havebase)
11714 oappend_register
11715 (ins,
11716 (ins->address_mode == mode_64bit && !addr32flag
11717 ? att_names64 : att_names32)[rbase]);
11718 if (ins->has_sib)
11719 {
11720 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11721 print index to tell base + index from base. */
11722 if (scale != 0
11723 || needindex
11724 || indexes
11725 || (havebase && base != ESP_REG_NUM))
11726 {
11727 if (!ins->intel_syntax || havebase)
11728 oappend_char (ins, ins->separator_char);
11729 if (indexes)
11730 {
11731 if (ins->address_mode == mode_64bit || vindex < 16)
11732 oappend_register (ins, indexes[vindex]);
11733 else
11734 oappend (ins, "(bad)");
11735 }
11736 else
11737 oappend_register (ins,
11738 ins->address_mode == mode_64bit
11739 && !addr32flag
11740 ? att_index64
11741 : att_index32);
11742
11743 oappend_char (ins, ins->scale_char);
11744 oappend_char_with_style (ins, '0' + (1 << scale),
11745 dis_style_immediate);
11746 }
11747 }
11748 if (ins->intel_syntax
11749 && (disp || ins->modrm.mod != 0 || base == 5))
11750 {
11751 if (!havedisp || (bfd_signed_vma) disp >= 0)
11752 oappend_char (ins, '+');
11753 else if (ins->modrm.mod != 1 && disp != -disp)
11754 {
11755 oappend_char (ins, '-');
11756 disp = -disp;
11757 }
11758
11759 if (havedisp)
11760 print_displacement (ins, disp);
11761 else
11762 print_operand_value (ins, disp, dis_style_address_offset);
11763 }
11764
11765 oappend_char (ins, ins->close_char);
11766
11767 if (check_gather)
11768 {
11769 /* Both XMM/YMM/ZMM registers must be distinct. */
11770 int modrm_reg = ins->modrm.reg;
11771
11772 if (ins->rex & REX_R)
11773 modrm_reg += 8;
11774 if (!ins->vex.r)
11775 modrm_reg += 16;
11776 if (vindex == modrm_reg)
11777 oappend (ins, "/(bad)");
11778 }
11779 }
11780 else if (ins->intel_syntax)
11781 {
11782 if (ins->modrm.mod != 0 || base == 5)
11783 {
11784 if (!ins->active_seg_prefix)
11785 {
11786 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11787 oappend (ins, ":");
11788 }
11789 print_operand_value (ins, disp, dis_style_text);
11790 }
11791 }
11792 }
11793 else if (bytemode == v_bnd_mode
11794 || bytemode == v_bndmk_mode
11795 || bytemode == bnd_mode
11796 || bytemode == bnd_swap_mode
11797 || bytemode == vex_vsib_d_w_dq_mode
11798 || bytemode == vex_vsib_q_w_dq_mode)
11799 {
11800 oappend (ins, "(bad)");
11801 return;
11802 }
11803 else
11804 {
11805 /* 16 bit address mode */
11806 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11807 switch (ins->modrm.mod)
11808 {
11809 case 0:
11810 if (ins->modrm.rm == 6)
11811 {
11812 disp = get16 (ins);
11813 if ((disp & 0x8000) != 0)
11814 disp -= 0x10000;
11815 }
11816 break;
11817 case 1:
11818 FETCH_DATA (ins->info, ins->codep + 1);
11819 disp = *ins->codep++;
11820 if ((disp & 0x80) != 0)
11821 disp -= 0x100;
11822 if (ins->vex.evex && shift > 0)
11823 disp <<= shift;
11824 break;
11825 case 2:
11826 disp = get16 (ins);
11827 if ((disp & 0x8000) != 0)
11828 disp -= 0x10000;
11829 break;
11830 }
11831
11832 if (!ins->intel_syntax)
11833 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11834 print_displacement (ins, disp);
11835
11836 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11837 {
11838 oappend_char (ins, ins->open_char);
11839 oappend (ins, (ins->intel_syntax ? intel_index16
11840 : att_index16)[ins->modrm.rm]);
11841 if (ins->intel_syntax
11842 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11843 {
11844 if ((bfd_signed_vma) disp >= 0)
11845 oappend_char (ins, '+');
11846 else if (ins->modrm.mod != 1)
11847 {
11848 oappend_char (ins, '-');
11849 disp = -disp;
11850 }
11851
11852 print_displacement (ins, disp);
11853 }
11854
11855 oappend_char (ins, ins->close_char);
11856 }
11857 else if (ins->intel_syntax)
11858 {
11859 if (!ins->active_seg_prefix)
11860 {
11861 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11862 oappend (ins, ":");
11863 }
11864 print_operand_value (ins, disp & 0xffff, dis_style_text);
11865 }
11866 }
11867 if (ins->vex.b)
11868 {
11869 ins->evex_used |= EVEX_b_used;
11870
11871 /* Broadcast can only ever be valid for memory sources. */
11872 if (ins->obufp == ins->op_out[0])
11873 ins->vex.no_broadcast = true;
11874
11875 if (!ins->vex.no_broadcast
11876 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
11877 {
11878 if (bytemode == xh_mode)
11879 {
11880 if (ins->vex.w)
11881 oappend (ins, "{bad}");
11882 else
11883 {
11884 switch (ins->vex.length)
11885 {
11886 case 128:
11887 oappend (ins, "{1to8}");
11888 break;
11889 case 256:
11890 oappend (ins, "{1to16}");
11891 break;
11892 case 512:
11893 oappend (ins, "{1to32}");
11894 break;
11895 default:
11896 abort ();
11897 }
11898 }
11899 }
11900 else if (bytemode == q_mode
11901 || bytemode == ymmq_mode)
11902 ins->vex.no_broadcast = true;
11903 else if (ins->vex.w
11904 || bytemode == evex_half_bcst_xmmqdh_mode
11905 || bytemode == evex_half_bcst_xmmq_mode)
11906 {
11907 switch (ins->vex.length)
11908 {
11909 case 128:
11910 oappend (ins, "{1to2}");
11911 break;
11912 case 256:
11913 oappend (ins, "{1to4}");
11914 break;
11915 case 512:
11916 oappend (ins, "{1to8}");
11917 break;
11918 default:
11919 abort ();
11920 }
11921 }
11922 else if (bytemode == x_mode
11923 || bytemode == evex_half_bcst_xmmqh_mode)
11924 {
11925 switch (ins->vex.length)
11926 {
11927 case 128:
11928 oappend (ins, "{1to4}");
11929 break;
11930 case 256:
11931 oappend (ins, "{1to8}");
11932 break;
11933 case 512:
11934 oappend (ins, "{1to16}");
11935 break;
11936 default:
11937 abort ();
11938 }
11939 }
11940 else
11941 ins->vex.no_broadcast = true;
11942 }
11943 if (ins->vex.no_broadcast)
11944 oappend (ins, "{bad}");
11945 }
11946 }
11947
11948 static void
OP_E(instr_info * ins,int bytemode,int sizeflag)11949 OP_E (instr_info *ins, int bytemode, int sizeflag)
11950 {
11951 /* Skip mod/rm byte. */
11952 MODRM_CHECK;
11953 ins->codep++;
11954
11955 if (ins->modrm.mod == 3)
11956 {
11957 if ((sizeflag & SUFFIX_ALWAYS)
11958 && (bytemode == b_swap_mode
11959 || bytemode == bnd_swap_mode
11960 || bytemode == v_swap_mode))
11961 swap_operand (ins);
11962
11963 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
11964 }
11965 else
11966 OP_E_memory (ins, bytemode, sizeflag);
11967 }
11968
11969 static void
OP_G(instr_info * ins,int bytemode,int sizeflag)11970 OP_G (instr_info *ins, int bytemode, int sizeflag)
11971 {
11972 if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
11973 {
11974 oappend (ins, "(bad)");
11975 return;
11976 }
11977
11978 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
11979 }
11980
11981 #ifdef BFD64
11982 static bfd_vma
get64(instr_info * ins)11983 get64 (instr_info *ins)
11984 {
11985 bfd_vma x;
11986 unsigned int a;
11987 unsigned int b;
11988
11989 FETCH_DATA (ins->info, ins->codep + 8);
11990 a = *ins->codep++ & 0xff;
11991 a |= (*ins->codep++ & 0xff) << 8;
11992 a |= (*ins->codep++ & 0xff) << 16;
11993 a |= (*ins->codep++ & 0xffu) << 24;
11994 b = *ins->codep++ & 0xff;
11995 b |= (*ins->codep++ & 0xff) << 8;
11996 b |= (*ins->codep++ & 0xff) << 16;
11997 b |= (*ins->codep++ & 0xffu) << 24;
11998 x = a + ((bfd_vma) b << 32);
11999 return x;
12000 }
12001 #else
12002 static bfd_vma
get64(instr_info * ins ATTRIBUTE_UNUSED)12003 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12004 {
12005 abort ();
12006 return 0;
12007 }
12008 #endif
12009
12010 static bfd_signed_vma
get32(instr_info * ins)12011 get32 (instr_info *ins)
12012 {
12013 bfd_vma x = 0;
12014
12015 FETCH_DATA (ins->info, ins->codep + 4);
12016 x = *ins->codep++ & (bfd_vma) 0xff;
12017 x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12018 x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12019 x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12020 return x;
12021 }
12022
12023 static bfd_signed_vma
get32s(instr_info * ins)12024 get32s (instr_info *ins)
12025 {
12026 bfd_vma x = 0;
12027
12028 FETCH_DATA (ins->info, ins->codep + 4);
12029 x = *ins->codep++ & (bfd_vma) 0xff;
12030 x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12031 x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12032 x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12033
12034 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12035
12036 return x;
12037 }
12038
12039 static int
get16(instr_info * ins)12040 get16 (instr_info *ins)
12041 {
12042 int x = 0;
12043
12044 FETCH_DATA (ins->info, ins->codep + 2);
12045 x = *ins->codep++ & 0xff;
12046 x |= (*ins->codep++ & 0xff) << 8;
12047 return x;
12048 }
12049
12050 static void
set_op(instr_info * ins,bfd_vma op,bool riprel)12051 set_op (instr_info *ins, bfd_vma op, bool riprel)
12052 {
12053 ins->op_index[ins->op_ad] = ins->op_ad;
12054 if (ins->address_mode == mode_64bit)
12055 ins->op_address[ins->op_ad] = op;
12056 else /* Mask to get a 32-bit address. */
12057 ins->op_address[ins->op_ad] = op & 0xffffffff;
12058 ins->op_riprel[ins->op_ad] = riprel;
12059 }
12060
12061 static void
OP_REG(instr_info * ins,int code,int sizeflag)12062 OP_REG (instr_info *ins, int code, int sizeflag)
12063 {
12064 const char *s;
12065 int add;
12066
12067 switch (code)
12068 {
12069 case es_reg: case ss_reg: case cs_reg:
12070 case ds_reg: case fs_reg: case gs_reg:
12071 oappend_register (ins, att_names_seg[code - es_reg]);
12072 return;
12073 }
12074
12075 USED_REX (REX_B);
12076 if (ins->rex & REX_B)
12077 add = 8;
12078 else
12079 add = 0;
12080
12081 switch (code)
12082 {
12083 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12084 case sp_reg: case bp_reg: case si_reg: case di_reg:
12085 s = att_names16[code - ax_reg + add];
12086 break;
12087 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12088 USED_REX (0);
12089 /* Fall through. */
12090 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12091 if (ins->rex)
12092 s = att_names8rex[code - al_reg + add];
12093 else
12094 s = att_names8[code - al_reg];
12095 break;
12096 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12097 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12098 if (ins->address_mode == mode_64bit
12099 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12100 {
12101 s = att_names64[code - rAX_reg + add];
12102 break;
12103 }
12104 code += eAX_reg - rAX_reg;
12105 /* Fall through. */
12106 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12107 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12108 USED_REX (REX_W);
12109 if (ins->rex & REX_W)
12110 s = att_names64[code - eAX_reg + add];
12111 else
12112 {
12113 if (sizeflag & DFLAG)
12114 s = att_names32[code - eAX_reg + add];
12115 else
12116 s = att_names16[code - eAX_reg + add];
12117 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12118 }
12119 break;
12120 default:
12121 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12122 return;
12123 }
12124 oappend_register (ins, s);
12125 }
12126
12127 static void
OP_IMREG(instr_info * ins,int code,int sizeflag)12128 OP_IMREG (instr_info *ins, int code, int sizeflag)
12129 {
12130 const char *s;
12131
12132 switch (code)
12133 {
12134 case indir_dx_reg:
12135 if (!ins->intel_syntax)
12136 {
12137 oappend (ins, "(%dx)");
12138 return;
12139 }
12140 s = att_names16[dx_reg - ax_reg];
12141 break;
12142 case al_reg: case cl_reg:
12143 s = att_names8[code - al_reg];
12144 break;
12145 case eAX_reg:
12146 USED_REX (REX_W);
12147 if (ins->rex & REX_W)
12148 {
12149 s = *att_names64;
12150 break;
12151 }
12152 /* Fall through. */
12153 case z_mode_ax_reg:
12154 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12155 s = *att_names32;
12156 else
12157 s = *att_names16;
12158 if (!(ins->rex & REX_W))
12159 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12160 break;
12161 default:
12162 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12163 return;
12164 }
12165 oappend_register (ins, s);
12166 }
12167
12168 static void
OP_I(instr_info * ins,int bytemode,int sizeflag)12169 OP_I (instr_info *ins, int bytemode, int sizeflag)
12170 {
12171 bfd_signed_vma op;
12172 bfd_signed_vma mask = -1;
12173
12174 switch (bytemode)
12175 {
12176 case b_mode:
12177 FETCH_DATA (ins->info, ins->codep + 1);
12178 op = *ins->codep++;
12179 mask = 0xff;
12180 break;
12181 case v_mode:
12182 USED_REX (REX_W);
12183 if (ins->rex & REX_W)
12184 op = get32s (ins);
12185 else
12186 {
12187 if (sizeflag & DFLAG)
12188 {
12189 op = get32 (ins);
12190 mask = 0xffffffff;
12191 }
12192 else
12193 {
12194 op = get16 (ins);
12195 mask = 0xfffff;
12196 }
12197 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12198 }
12199 break;
12200 case d_mode:
12201 mask = 0xffffffff;
12202 op = get32 (ins);
12203 break;
12204 case w_mode:
12205 mask = 0xfffff;
12206 op = get16 (ins);
12207 break;
12208 case const_1_mode:
12209 if (ins->intel_syntax)
12210 oappend (ins, "1");
12211 return;
12212 default:
12213 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12214 return;
12215 }
12216
12217 op &= mask;
12218 oappend_immediate (ins, op);
12219 }
12220
12221 static void
OP_I64(instr_info * ins,int bytemode,int sizeflag)12222 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12223 {
12224 if (bytemode != v_mode || ins->address_mode != mode_64bit
12225 || !(ins->rex & REX_W))
12226 {
12227 OP_I (ins, bytemode, sizeflag);
12228 return;
12229 }
12230
12231 USED_REX (REX_W);
12232
12233 oappend_immediate (ins, get64 (ins));
12234 }
12235
12236 static void
OP_sI(instr_info * ins,int bytemode,int sizeflag)12237 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12238 {
12239 bfd_signed_vma op;
12240
12241 switch (bytemode)
12242 {
12243 case b_mode:
12244 case b_T_mode:
12245 FETCH_DATA (ins->info, ins->codep + 1);
12246 op = *ins->codep++;
12247 if ((op & 0x80) != 0)
12248 op -= 0x100;
12249 if (bytemode == b_T_mode)
12250 {
12251 if (ins->address_mode != mode_64bit
12252 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12253 {
12254 /* The operand-size prefix is overridden by a REX prefix. */
12255 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12256 op &= 0xffffffff;
12257 else
12258 op &= 0xffff;
12259 }
12260 }
12261 else
12262 {
12263 if (!(ins->rex & REX_W))
12264 {
12265 if (sizeflag & DFLAG)
12266 op &= 0xffffffff;
12267 else
12268 op &= 0xffff;
12269 }
12270 }
12271 break;
12272 case v_mode:
12273 /* The operand-size prefix is overridden by a REX prefix. */
12274 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12275 op = get32s (ins);
12276 else
12277 op = get16 (ins);
12278 break;
12279 default:
12280 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12281 return;
12282 }
12283
12284 oappend_immediate (ins, op);
12285 }
12286
12287 static void
OP_J(instr_info * ins,int bytemode,int sizeflag)12288 OP_J (instr_info *ins, int bytemode, int sizeflag)
12289 {
12290 bfd_vma disp;
12291 bfd_vma mask = -1;
12292 bfd_vma segment = 0;
12293
12294 switch (bytemode)
12295 {
12296 case b_mode:
12297 FETCH_DATA (ins->info, ins->codep + 1);
12298 disp = *ins->codep++;
12299 if ((disp & 0x80) != 0)
12300 disp -= 0x100;
12301 break;
12302 case v_mode:
12303 case dqw_mode:
12304 if ((sizeflag & DFLAG)
12305 || (ins->address_mode == mode_64bit
12306 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12307 || (ins->rex & REX_W))))
12308 disp = get32s (ins);
12309 else
12310 {
12311 disp = get16 (ins);
12312 if ((disp & 0x8000) != 0)
12313 disp -= 0x10000;
12314 /* In 16bit mode, address is wrapped around at 64k within
12315 the same segment. Otherwise, a data16 prefix on a jump
12316 instruction means that the pc is masked to 16 bits after
12317 the displacement is added! */
12318 mask = 0xffff;
12319 if ((ins->prefixes & PREFIX_DATA) == 0)
12320 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12321 & ~((bfd_vma) 0xffff));
12322 }
12323 if (ins->address_mode != mode_64bit
12324 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12325 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12326 break;
12327 default:
12328 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12329 return;
12330 }
12331 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12332 | segment;
12333 set_op (ins, disp, false);
12334 print_operand_value (ins, disp, dis_style_text);
12335 }
12336
12337 static void
OP_SEG(instr_info * ins,int bytemode,int sizeflag)12338 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12339 {
12340 if (bytemode == w_mode)
12341 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12342 else
12343 OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12344 }
12345
12346 static void
OP_DIR(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag)12347 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12348 {
12349 int seg, offset, res;
12350 char scratch[24];
12351
12352 if (sizeflag & DFLAG)
12353 {
12354 offset = get32 (ins);
12355 seg = get16 (ins);
12356 }
12357 else
12358 {
12359 offset = get16 (ins);
12360 seg = get16 (ins);
12361 }
12362 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12363
12364 res = snprintf (scratch, ARRAY_SIZE (scratch),
12365 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12366 seg, offset);
12367 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12368 abort ();
12369 oappend (ins, scratch);
12370 }
12371
12372 static void
OP_OFF(instr_info * ins,int bytemode,int sizeflag)12373 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12374 {
12375 bfd_vma off;
12376
12377 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12378 intel_operand_size (ins, bytemode, sizeflag);
12379 append_seg (ins);
12380
12381 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12382 off = get32 (ins);
12383 else
12384 off = get16 (ins);
12385
12386 if (ins->intel_syntax)
12387 {
12388 if (!ins->active_seg_prefix)
12389 {
12390 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12391 oappend (ins, ":");
12392 }
12393 }
12394 print_operand_value (ins, off, dis_style_address_offset);
12395 }
12396
12397 static void
OP_OFF64(instr_info * ins,int bytemode,int sizeflag)12398 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12399 {
12400 bfd_vma off;
12401
12402 if (ins->address_mode != mode_64bit
12403 || (ins->prefixes & PREFIX_ADDR))
12404 {
12405 OP_OFF (ins, bytemode, sizeflag);
12406 return;
12407 }
12408
12409 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12410 intel_operand_size (ins, bytemode, sizeflag);
12411 append_seg (ins);
12412
12413 off = get64 (ins);
12414
12415 if (ins->intel_syntax)
12416 {
12417 if (!ins->active_seg_prefix)
12418 {
12419 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12420 oappend (ins, ":");
12421 }
12422 }
12423 print_operand_value (ins, off, dis_style_address_offset);
12424 }
12425
12426 static void
ptr_reg(instr_info * ins,int code,int sizeflag)12427 ptr_reg (instr_info *ins, int code, int sizeflag)
12428 {
12429 const char *s;
12430
12431 *ins->obufp++ = ins->open_char;
12432 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12433 if (ins->address_mode == mode_64bit)
12434 {
12435 if (!(sizeflag & AFLAG))
12436 s = att_names32[code - eAX_reg];
12437 else
12438 s = att_names64[code - eAX_reg];
12439 }
12440 else if (sizeflag & AFLAG)
12441 s = att_names32[code - eAX_reg];
12442 else
12443 s = att_names16[code - eAX_reg];
12444 oappend_register (ins, s);
12445 oappend_char (ins, ins->close_char);
12446 }
12447
12448 static void
OP_ESreg(instr_info * ins,int code,int sizeflag)12449 OP_ESreg (instr_info *ins, int code, int sizeflag)
12450 {
12451 if (ins->intel_syntax)
12452 {
12453 switch (ins->codep[-1])
12454 {
12455 case 0x6d: /* insw/insl */
12456 intel_operand_size (ins, z_mode, sizeflag);
12457 break;
12458 case 0xa5: /* movsw/movsl/movsq */
12459 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12460 case 0xab: /* stosw/stosl */
12461 case 0xaf: /* scasw/scasl */
12462 intel_operand_size (ins, v_mode, sizeflag);
12463 break;
12464 default:
12465 intel_operand_size (ins, b_mode, sizeflag);
12466 }
12467 }
12468 oappend_register (ins, "%es");
12469 oappend_char (ins, ':');
12470 ptr_reg (ins, code, sizeflag);
12471 }
12472
12473 static void
OP_DSreg(instr_info * ins,int code,int sizeflag)12474 OP_DSreg (instr_info *ins, int code, int sizeflag)
12475 {
12476 if (ins->intel_syntax)
12477 {
12478 switch (ins->codep[-1])
12479 {
12480 case 0x6f: /* outsw/outsl */
12481 intel_operand_size (ins, z_mode, sizeflag);
12482 break;
12483 case 0xa5: /* movsw/movsl/movsq */
12484 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12485 case 0xad: /* lodsw/lodsl/lodsq */
12486 intel_operand_size (ins, v_mode, sizeflag);
12487 break;
12488 default:
12489 intel_operand_size (ins, b_mode, sizeflag);
12490 }
12491 }
12492 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12493 default segment register DS is printed. */
12494 if (!ins->active_seg_prefix)
12495 ins->active_seg_prefix = PREFIX_DS;
12496 append_seg (ins);
12497 ptr_reg (ins, code, sizeflag);
12498 }
12499
12500 static void
OP_C(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12501 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12502 int sizeflag ATTRIBUTE_UNUSED)
12503 {
12504 int add, res;
12505 char scratch[8];
12506
12507 if (ins->rex & REX_R)
12508 {
12509 USED_REX (REX_R);
12510 add = 8;
12511 }
12512 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12513 {
12514 ins->all_prefixes[ins->last_lock_prefix] = 0;
12515 ins->used_prefixes |= PREFIX_LOCK;
12516 add = 8;
12517 }
12518 else
12519 add = 0;
12520 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12521 ins->modrm.reg + add);
12522 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12523 abort ();
12524 oappend_register (ins, scratch);
12525 }
12526
12527 static void
OP_D(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12528 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12529 int sizeflag ATTRIBUTE_UNUSED)
12530 {
12531 int add, res;
12532 char scratch[8];
12533
12534 USED_REX (REX_R);
12535 if (ins->rex & REX_R)
12536 add = 8;
12537 else
12538 add = 0;
12539 res = snprintf (scratch, ARRAY_SIZE (scratch),
12540 ins->intel_syntax ? "dr%d" : "%%db%d",
12541 ins->modrm.reg + add);
12542 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12543 abort ();
12544 oappend (ins, scratch);
12545 }
12546
12547 static void
OP_T(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12548 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12549 int sizeflag ATTRIBUTE_UNUSED)
12550 {
12551 int res;
12552 char scratch[8];
12553
12554 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12555 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12556 abort ();
12557 oappend_register (ins, scratch);
12558 }
12559
12560 static void
OP_MMX(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12561 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12562 int sizeflag ATTRIBUTE_UNUSED)
12563 {
12564 int reg = ins->modrm.reg;
12565 const char *const *names;
12566
12567 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12568 if (ins->prefixes & PREFIX_DATA)
12569 {
12570 names = att_names_xmm;
12571 USED_REX (REX_R);
12572 if (ins->rex & REX_R)
12573 reg += 8;
12574 }
12575 else
12576 names = att_names_mm;
12577 oappend_register (ins, names[reg]);
12578 }
12579
12580 static void
print_vector_reg(instr_info * ins,unsigned int reg,int bytemode)12581 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12582 {
12583 const char *const *names;
12584
12585 if (bytemode == xmmq_mode
12586 || bytemode == evex_half_bcst_xmmqh_mode
12587 || bytemode == evex_half_bcst_xmmq_mode)
12588 {
12589 switch (ins->vex.length)
12590 {
12591 case 128:
12592 case 256:
12593 names = att_names_xmm;
12594 break;
12595 case 512:
12596 names = att_names_ymm;
12597 ins->evex_used |= EVEX_len_used;
12598 break;
12599 default:
12600 abort ();
12601 }
12602 }
12603 else if (bytemode == ymm_mode)
12604 names = att_names_ymm;
12605 else if (bytemode == tmm_mode)
12606 {
12607 if (reg >= 8)
12608 {
12609 oappend (ins, "(bad)");
12610 return;
12611 }
12612 names = att_names_tmm;
12613 }
12614 else if (ins->need_vex
12615 && bytemode != xmm_mode
12616 && bytemode != scalar_mode
12617 && bytemode != xmmdw_mode
12618 && bytemode != xmmqd_mode
12619 && bytemode != evex_half_bcst_xmmqdh_mode
12620 && bytemode != w_swap_mode
12621 && bytemode != b_mode
12622 && bytemode != w_mode
12623 && bytemode != d_mode
12624 && bytemode != q_mode)
12625 {
12626 ins->evex_used |= EVEX_len_used;
12627 switch (ins->vex.length)
12628 {
12629 case 128:
12630 names = att_names_xmm;
12631 break;
12632 case 256:
12633 if (ins->vex.w
12634 || bytemode != vex_vsib_q_w_dq_mode)
12635 names = att_names_ymm;
12636 else
12637 names = att_names_xmm;
12638 break;
12639 case 512:
12640 if (ins->vex.w
12641 || bytemode != vex_vsib_q_w_dq_mode)
12642 names = att_names_zmm;
12643 else
12644 names = att_names_ymm;
12645 break;
12646 default:
12647 abort ();
12648 }
12649 }
12650 else
12651 names = att_names_xmm;
12652 oappend_register (ins, names[reg]);
12653 }
12654
12655 static void
OP_XMM(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)12656 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12657 {
12658 unsigned int reg = ins->modrm.reg;
12659
12660 USED_REX (REX_R);
12661 if (ins->rex & REX_R)
12662 reg += 8;
12663 if (ins->vex.evex)
12664 {
12665 if (!ins->vex.r)
12666 reg += 16;
12667 }
12668
12669 if (bytemode == tmm_mode)
12670 ins->modrm.reg = reg;
12671 else if (bytemode == scalar_mode)
12672 ins->vex.no_broadcast = true;
12673
12674 print_vector_reg (ins, reg, bytemode);
12675 }
12676
12677 static void
OP_EM(instr_info * ins,int bytemode,int sizeflag)12678 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12679 {
12680 int reg;
12681 const char *const *names;
12682
12683 if (ins->modrm.mod != 3)
12684 {
12685 if (ins->intel_syntax
12686 && (bytemode == v_mode || bytemode == v_swap_mode))
12687 {
12688 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12689 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12690 }
12691 OP_E (ins, bytemode, sizeflag);
12692 return;
12693 }
12694
12695 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12696 swap_operand (ins);
12697
12698 /* Skip mod/rm byte. */
12699 MODRM_CHECK;
12700 ins->codep++;
12701 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12702 reg = ins->modrm.rm;
12703 if (ins->prefixes & PREFIX_DATA)
12704 {
12705 names = att_names_xmm;
12706 USED_REX (REX_B);
12707 if (ins->rex & REX_B)
12708 reg += 8;
12709 }
12710 else
12711 names = att_names_mm;
12712 oappend_register (ins, names[reg]);
12713 }
12714
12715 /* cvt* are the only instructions in sse2 which have
12716 both SSE and MMX operands and also have 0x66 prefix
12717 in their opcode. 0x66 was originally used to differentiate
12718 between SSE and MMX instruction(operands). So we have to handle the
12719 cvt* separately using OP_EMC and OP_MXC */
12720 static void
OP_EMC(instr_info * ins,int bytemode,int sizeflag)12721 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12722 {
12723 if (ins->modrm.mod != 3)
12724 {
12725 if (ins->intel_syntax && bytemode == v_mode)
12726 {
12727 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12728 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12729 }
12730 OP_E (ins, bytemode, sizeflag);
12731 return;
12732 }
12733
12734 /* Skip mod/rm byte. */
12735 MODRM_CHECK;
12736 ins->codep++;
12737 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12738 oappend_register (ins, att_names_mm[ins->modrm.rm]);
12739 }
12740
12741 static void
OP_MXC(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12742 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12743 int sizeflag ATTRIBUTE_UNUSED)
12744 {
12745 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12746 oappend_register (ins, att_names_mm[ins->modrm.reg]);
12747 }
12748
12749 static void
OP_EX(instr_info * ins,int bytemode,int sizeflag)12750 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12751 {
12752 int reg;
12753
12754 /* Skip mod/rm byte. */
12755 MODRM_CHECK;
12756 ins->codep++;
12757
12758 if (bytemode == dq_mode)
12759 bytemode = ins->vex.w ? q_mode : d_mode;
12760
12761 if (ins->modrm.mod != 3)
12762 {
12763 OP_E_memory (ins, bytemode, sizeflag);
12764 return;
12765 }
12766
12767 reg = ins->modrm.rm;
12768 USED_REX (REX_B);
12769 if (ins->rex & REX_B)
12770 reg += 8;
12771 if (ins->vex.evex)
12772 {
12773 USED_REX (REX_X);
12774 if ((ins->rex & REX_X))
12775 reg += 16;
12776 }
12777
12778 if ((sizeflag & SUFFIX_ALWAYS)
12779 && (bytemode == x_swap_mode
12780 || bytemode == w_swap_mode
12781 || bytemode == d_swap_mode
12782 || bytemode == q_swap_mode))
12783 swap_operand (ins);
12784
12785 if (bytemode == tmm_mode)
12786 ins->modrm.rm = reg;
12787
12788 print_vector_reg (ins, reg, bytemode);
12789 }
12790
12791 static void
OP_MS(instr_info * ins,int bytemode,int sizeflag)12792 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12793 {
12794 if (ins->modrm.mod == 3)
12795 OP_EM (ins, bytemode, sizeflag);
12796 else
12797 BadOp (ins);
12798 }
12799
12800 static void
OP_XS(instr_info * ins,int bytemode,int sizeflag)12801 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12802 {
12803 if (ins->modrm.mod == 3)
12804 OP_EX (ins, bytemode, sizeflag);
12805 else
12806 BadOp (ins);
12807 }
12808
12809 static void
OP_M(instr_info * ins,int bytemode,int sizeflag)12810 OP_M (instr_info *ins, int bytemode, int sizeflag)
12811 {
12812 if (ins->modrm.mod == 3)
12813 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12814 BadOp (ins);
12815 else
12816 OP_E (ins, bytemode, sizeflag);
12817 }
12818
12819 static void
OP_0f07(instr_info * ins,int bytemode,int sizeflag)12820 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12821 {
12822 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12823 BadOp (ins);
12824 else
12825 OP_E (ins, bytemode, sizeflag);
12826 }
12827
12828 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12829 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12830
12831 static void
NOP_Fixup(instr_info * ins,int opnd,int sizeflag)12832 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12833 {
12834 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12835 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
12836 else if (opnd == 0)
12837 OP_REG (ins, eAX_reg, sizeflag);
12838 else
12839 OP_IMREG (ins, eAX_reg, sizeflag);
12840 }
12841
12842 static const char *const Suffix3DNow[] = {
12843 /* 00 */ NULL, NULL, NULL, NULL,
12844 /* 04 */ NULL, NULL, NULL, NULL,
12845 /* 08 */ NULL, NULL, NULL, NULL,
12846 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12847 /* 10 */ NULL, NULL, NULL, NULL,
12848 /* 14 */ NULL, NULL, NULL, NULL,
12849 /* 18 */ NULL, NULL, NULL, NULL,
12850 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12851 /* 20 */ NULL, NULL, NULL, NULL,
12852 /* 24 */ NULL, NULL, NULL, NULL,
12853 /* 28 */ NULL, NULL, NULL, NULL,
12854 /* 2C */ NULL, NULL, NULL, NULL,
12855 /* 30 */ NULL, NULL, NULL, NULL,
12856 /* 34 */ NULL, NULL, NULL, NULL,
12857 /* 38 */ NULL, NULL, NULL, NULL,
12858 /* 3C */ NULL, NULL, NULL, NULL,
12859 /* 40 */ NULL, NULL, NULL, NULL,
12860 /* 44 */ NULL, NULL, NULL, NULL,
12861 /* 48 */ NULL, NULL, NULL, NULL,
12862 /* 4C */ NULL, NULL, NULL, NULL,
12863 /* 50 */ NULL, NULL, NULL, NULL,
12864 /* 54 */ NULL, NULL, NULL, NULL,
12865 /* 58 */ NULL, NULL, NULL, NULL,
12866 /* 5C */ NULL, NULL, NULL, NULL,
12867 /* 60 */ NULL, NULL, NULL, NULL,
12868 /* 64 */ NULL, NULL, NULL, NULL,
12869 /* 68 */ NULL, NULL, NULL, NULL,
12870 /* 6C */ NULL, NULL, NULL, NULL,
12871 /* 70 */ NULL, NULL, NULL, NULL,
12872 /* 74 */ NULL, NULL, NULL, NULL,
12873 /* 78 */ NULL, NULL, NULL, NULL,
12874 /* 7C */ NULL, NULL, NULL, NULL,
12875 /* 80 */ NULL, NULL, NULL, NULL,
12876 /* 84 */ NULL, NULL, NULL, NULL,
12877 /* 88 */ NULL, NULL, "pfnacc", NULL,
12878 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12879 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12880 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12881 /* 98 */ NULL, NULL, "pfsub", NULL,
12882 /* 9C */ NULL, NULL, "pfadd", NULL,
12883 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12884 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12885 /* A8 */ NULL, NULL, "pfsubr", NULL,
12886 /* AC */ NULL, NULL, "pfacc", NULL,
12887 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12888 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12889 /* B8 */ NULL, NULL, NULL, "pswapd",
12890 /* BC */ NULL, NULL, NULL, "pavgusb",
12891 /* C0 */ NULL, NULL, NULL, NULL,
12892 /* C4 */ NULL, NULL, NULL, NULL,
12893 /* C8 */ NULL, NULL, NULL, NULL,
12894 /* CC */ NULL, NULL, NULL, NULL,
12895 /* D0 */ NULL, NULL, NULL, NULL,
12896 /* D4 */ NULL, NULL, NULL, NULL,
12897 /* D8 */ NULL, NULL, NULL, NULL,
12898 /* DC */ NULL, NULL, NULL, NULL,
12899 /* E0 */ NULL, NULL, NULL, NULL,
12900 /* E4 */ NULL, NULL, NULL, NULL,
12901 /* E8 */ NULL, NULL, NULL, NULL,
12902 /* EC */ NULL, NULL, NULL, NULL,
12903 /* F0 */ NULL, NULL, NULL, NULL,
12904 /* F4 */ NULL, NULL, NULL, NULL,
12905 /* F8 */ NULL, NULL, NULL, NULL,
12906 /* FC */ NULL, NULL, NULL, NULL,
12907 };
12908
12909 static void
OP_3DNowSuffix(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12910 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12911 int sizeflag ATTRIBUTE_UNUSED)
12912 {
12913 const char *mnemonic;
12914
12915 FETCH_DATA (ins->info, ins->codep + 1);
12916 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12917 place where an 8-bit immediate would normally go. ie. the last
12918 byte of the instruction. */
12919 ins->obufp = ins->mnemonicendp;
12920 mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12921 if (mnemonic)
12922 ins->obufp = stpcpy (ins->obufp, mnemonic);
12923 else
12924 {
12925 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12926 of the opcode (0x0f0f) and the opcode suffix, we need to do
12927 all the ins->modrm processing first, and don't know until now that
12928 we have a bad opcode. This necessitates some cleaning up. */
12929 ins->op_out[0][0] = '\0';
12930 ins->op_out[1][0] = '\0';
12931 BadOp (ins);
12932 }
12933 ins->mnemonicendp = ins->obufp;
12934 }
12935
12936 static const struct op simd_cmp_op[] =
12937 {
12938 { STRING_COMMA_LEN ("eq") },
12939 { STRING_COMMA_LEN ("lt") },
12940 { STRING_COMMA_LEN ("le") },
12941 { STRING_COMMA_LEN ("unord") },
12942 { STRING_COMMA_LEN ("neq") },
12943 { STRING_COMMA_LEN ("nlt") },
12944 { STRING_COMMA_LEN ("nle") },
12945 { STRING_COMMA_LEN ("ord") }
12946 };
12947
12948 static const struct op vex_cmp_op[] =
12949 {
12950 { STRING_COMMA_LEN ("eq_uq") },
12951 { STRING_COMMA_LEN ("nge") },
12952 { STRING_COMMA_LEN ("ngt") },
12953 { STRING_COMMA_LEN ("false") },
12954 { STRING_COMMA_LEN ("neq_oq") },
12955 { STRING_COMMA_LEN ("ge") },
12956 { STRING_COMMA_LEN ("gt") },
12957 { STRING_COMMA_LEN ("true") },
12958 { STRING_COMMA_LEN ("eq_os") },
12959 { STRING_COMMA_LEN ("lt_oq") },
12960 { STRING_COMMA_LEN ("le_oq") },
12961 { STRING_COMMA_LEN ("unord_s") },
12962 { STRING_COMMA_LEN ("neq_us") },
12963 { STRING_COMMA_LEN ("nlt_uq") },
12964 { STRING_COMMA_LEN ("nle_uq") },
12965 { STRING_COMMA_LEN ("ord_s") },
12966 { STRING_COMMA_LEN ("eq_us") },
12967 { STRING_COMMA_LEN ("nge_uq") },
12968 { STRING_COMMA_LEN ("ngt_uq") },
12969 { STRING_COMMA_LEN ("false_os") },
12970 { STRING_COMMA_LEN ("neq_os") },
12971 { STRING_COMMA_LEN ("ge_oq") },
12972 { STRING_COMMA_LEN ("gt_oq") },
12973 { STRING_COMMA_LEN ("true_us") },
12974 };
12975
12976 static void
CMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12977 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12978 int sizeflag ATTRIBUTE_UNUSED)
12979 {
12980 unsigned int cmp_type;
12981
12982 FETCH_DATA (ins->info, ins->codep + 1);
12983 cmp_type = *ins->codep++ & 0xff;
12984 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12985 {
12986 char suffix[3];
12987 char *p = ins->mnemonicendp - 2;
12988 suffix[0] = p[0];
12989 suffix[1] = p[1];
12990 suffix[2] = '\0';
12991 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12992 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
12993 }
12994 else if (ins->need_vex
12995 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
12996 {
12997 char suffix[3];
12998 char *p = ins->mnemonicendp - 2;
12999 suffix[0] = p[0];
13000 suffix[1] = p[1];
13001 suffix[2] = '\0';
13002 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13003 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13004 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13005 }
13006 else
13007 {
13008 /* We have a reserved extension byte. Output it directly. */
13009 oappend_immediate (ins, cmp_type);
13010 }
13011 }
13012
13013 static void
OP_Mwait(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13014 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13015 {
13016 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13017 if (!ins->intel_syntax)
13018 {
13019 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13020 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13021 if (bytemode == eBX_reg)
13022 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13023 ins->two_source_ops = true;
13024 }
13025 /* Skip mod/rm byte. */
13026 MODRM_CHECK;
13027 ins->codep++;
13028 }
13029
13030 static void
OP_Monitor(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13031 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13032 int sizeflag ATTRIBUTE_UNUSED)
13033 {
13034 /* monitor %{e,r,}ax,%ecx,%edx" */
13035 if (!ins->intel_syntax)
13036 {
13037 const char *const *names = (ins->address_mode == mode_64bit
13038 ? att_names64 : att_names32);
13039
13040 if (ins->prefixes & PREFIX_ADDR)
13041 {
13042 /* Remove "addr16/addr32". */
13043 ins->all_prefixes[ins->last_addr_prefix] = 0;
13044 names = (ins->address_mode != mode_32bit
13045 ? att_names32 : att_names16);
13046 ins->used_prefixes |= PREFIX_ADDR;
13047 }
13048 else if (ins->address_mode == mode_16bit)
13049 names = att_names16;
13050 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13051 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13052 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13053 ins->two_source_ops = true;
13054 }
13055 /* Skip mod/rm byte. */
13056 MODRM_CHECK;
13057 ins->codep++;
13058 }
13059
13060 static void
BadOp(instr_info * ins)13061 BadOp (instr_info *ins)
13062 {
13063 /* Throw away prefixes and 1st. opcode byte. */
13064 ins->codep = ins->insn_codep + 1;
13065 ins->obufp = stpcpy (ins->obufp, "(bad)");
13066 }
13067
13068 static void
REP_Fixup(instr_info * ins,int bytemode,int sizeflag)13069 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13070 {
13071 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13072 lods and stos. */
13073 if (ins->prefixes & PREFIX_REPZ)
13074 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13075
13076 switch (bytemode)
13077 {
13078 case al_reg:
13079 case eAX_reg:
13080 case indir_dx_reg:
13081 OP_IMREG (ins, bytemode, sizeflag);
13082 break;
13083 case eDI_reg:
13084 OP_ESreg (ins, bytemode, sizeflag);
13085 break;
13086 case eSI_reg:
13087 OP_DSreg (ins, bytemode, sizeflag);
13088 break;
13089 default:
13090 abort ();
13091 break;
13092 }
13093 }
13094
13095 static void
SEP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13096 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13097 int sizeflag ATTRIBUTE_UNUSED)
13098 {
13099 if (ins->isa64 != amd64)
13100 return;
13101
13102 ins->obufp = ins->obuf;
13103 BadOp (ins);
13104 ins->mnemonicendp = ins->obufp;
13105 ++ins->codep;
13106 }
13107
13108 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13109 "bnd". */
13110
13111 static void
BND_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13112 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13113 int sizeflag ATTRIBUTE_UNUSED)
13114 {
13115 if (ins->prefixes & PREFIX_REPNZ)
13116 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13117 }
13118
13119 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13120 "notrack". */
13121
13122 static void
NOTRACK_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13123 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13124 int sizeflag ATTRIBUTE_UNUSED)
13125 {
13126 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13127 we've seen a PREFIX_DS. */
13128 if ((ins->prefixes & PREFIX_DS) != 0
13129 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13130 {
13131 /* NOTRACK prefix is only valid on indirect branch instructions.
13132 NB: DATA prefix is unsupported for Intel64. */
13133 ins->active_seg_prefix = 0;
13134 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13135 }
13136 }
13137
13138 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13139 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13140 */
13141
13142 static void
HLE_Fixup1(instr_info * ins,int bytemode,int sizeflag)13143 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13144 {
13145 if (ins->modrm.mod != 3
13146 && (ins->prefixes & PREFIX_LOCK) != 0)
13147 {
13148 if (ins->prefixes & PREFIX_REPZ)
13149 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13150 if (ins->prefixes & PREFIX_REPNZ)
13151 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13152 }
13153
13154 OP_E (ins, bytemode, sizeflag);
13155 }
13156
13157 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13158 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13159 */
13160
13161 static void
HLE_Fixup2(instr_info * ins,int bytemode,int sizeflag)13162 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13163 {
13164 if (ins->modrm.mod != 3)
13165 {
13166 if (ins->prefixes & PREFIX_REPZ)
13167 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13168 if (ins->prefixes & PREFIX_REPNZ)
13169 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13170 }
13171
13172 OP_E (ins, bytemode, sizeflag);
13173 }
13174
13175 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13176 "xrelease" for memory operand. No check for LOCK prefix. */
13177
13178 static void
HLE_Fixup3(instr_info * ins,int bytemode,int sizeflag)13179 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13180 {
13181 if (ins->modrm.mod != 3
13182 && ins->last_repz_prefix > ins->last_repnz_prefix
13183 && (ins->prefixes & PREFIX_REPZ) != 0)
13184 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13185
13186 OP_E (ins, bytemode, sizeflag);
13187 }
13188
13189 static void
CMPXCHG8B_Fixup(instr_info * ins,int bytemode,int sizeflag)13190 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13191 {
13192 USED_REX (REX_W);
13193 if (ins->rex & REX_W)
13194 {
13195 /* Change cmpxchg8b to cmpxchg16b. */
13196 char *p = ins->mnemonicendp - 2;
13197 ins->mnemonicendp = stpcpy (p, "16b");
13198 bytemode = o_mode;
13199 }
13200 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13201 {
13202 if (ins->prefixes & PREFIX_REPZ)
13203 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13204 if (ins->prefixes & PREFIX_REPNZ)
13205 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13206 }
13207
13208 OP_M (ins, bytemode, sizeflag);
13209 }
13210
13211 static void
XMM_Fixup(instr_info * ins,int reg,int sizeflag ATTRIBUTE_UNUSED)13212 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13213 {
13214 const char *const *names = att_names_xmm;
13215
13216 if (ins->need_vex)
13217 {
13218 switch (ins->vex.length)
13219 {
13220 case 128:
13221 break;
13222 case 256:
13223 names = att_names_ymm;
13224 break;
13225 default:
13226 abort ();
13227 }
13228 }
13229 oappend_register (ins, names[reg]);
13230 }
13231
13232 static void
FXSAVE_Fixup(instr_info * ins,int bytemode,int sizeflag)13233 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13234 {
13235 /* Add proper suffix to "fxsave" and "fxrstor". */
13236 USED_REX (REX_W);
13237 if (ins->rex & REX_W)
13238 {
13239 char *p = ins->mnemonicendp;
13240 *p++ = '6';
13241 *p++ = '4';
13242 *p = '\0';
13243 ins->mnemonicendp = p;
13244 }
13245 OP_M (ins, bytemode, sizeflag);
13246 }
13247
13248 /* Display the destination register operand for instructions with
13249 VEX. */
13250
13251 static void
OP_VEX(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13252 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13253 {
13254 int reg, modrm_reg, sib_index = -1;
13255 const char *const *names;
13256
13257 if (!ins->need_vex)
13258 abort ();
13259
13260 reg = ins->vex.register_specifier;
13261 ins->vex.register_specifier = 0;
13262 if (ins->address_mode != mode_64bit)
13263 {
13264 if (ins->vex.evex && !ins->vex.v)
13265 {
13266 oappend (ins, "(bad)");
13267 return;
13268 }
13269
13270 reg &= 7;
13271 }
13272 else if (ins->vex.evex && !ins->vex.v)
13273 reg += 16;
13274
13275 switch (bytemode)
13276 {
13277 case scalar_mode:
13278 oappend_register (ins, att_names_xmm[reg]);
13279 return;
13280
13281 case vex_vsib_d_w_dq_mode:
13282 case vex_vsib_q_w_dq_mode:
13283 /* This must be the 3rd operand. */
13284 if (ins->obufp != ins->op_out[2])
13285 abort ();
13286 if (ins->vex.length == 128
13287 || (bytemode != vex_vsib_d_w_dq_mode
13288 && !ins->vex.w))
13289 oappend_register (ins, att_names_xmm[reg]);
13290 else
13291 oappend_register (ins, att_names_ymm[reg]);
13292
13293 /* All 3 XMM/YMM registers must be distinct. */
13294 modrm_reg = ins->modrm.reg;
13295 if (ins->rex & REX_R)
13296 modrm_reg += 8;
13297
13298 if (ins->has_sib && ins->modrm.rm == 4)
13299 {
13300 sib_index = ins->sib.index;
13301 if (ins->rex & REX_X)
13302 sib_index += 8;
13303 }
13304
13305 if (reg == modrm_reg || reg == sib_index)
13306 strcpy (ins->obufp, "/(bad)");
13307 if (modrm_reg == sib_index || modrm_reg == reg)
13308 strcat (ins->op_out[0], "/(bad)");
13309 if (sib_index == modrm_reg || sib_index == reg)
13310 strcat (ins->op_out[1], "/(bad)");
13311
13312 return;
13313
13314 case tmm_mode:
13315 /* All 3 TMM registers must be distinct. */
13316 if (reg >= 8)
13317 oappend (ins, "(bad)");
13318 else
13319 {
13320 /* This must be the 3rd operand. */
13321 if (ins->obufp != ins->op_out[2])
13322 abort ();
13323 oappend_register (ins, att_names_tmm[reg]);
13324 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13325 strcpy (ins->obufp, "/(bad)");
13326 }
13327
13328 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13329 || ins->modrm.rm == reg)
13330 {
13331 if (ins->modrm.reg <= 8
13332 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13333 strcat (ins->op_out[0], "/(bad)");
13334 if (ins->modrm.rm <= 8
13335 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13336 strcat (ins->op_out[1], "/(bad)");
13337 }
13338
13339 return;
13340 }
13341
13342 switch (ins->vex.length)
13343 {
13344 case 128:
13345 switch (bytemode)
13346 {
13347 case x_mode:
13348 names = att_names_xmm;
13349 ins->evex_used |= EVEX_len_used;
13350 break;
13351 case dq_mode:
13352 if (ins->rex & REX_W)
13353 names = att_names64;
13354 else
13355 names = att_names32;
13356 break;
13357 case mask_bd_mode:
13358 case mask_mode:
13359 if (reg > 0x7)
13360 {
13361 oappend (ins, "(bad)");
13362 return;
13363 }
13364 names = att_names_mask;
13365 break;
13366 default:
13367 abort ();
13368 return;
13369 }
13370 break;
13371 case 256:
13372 switch (bytemode)
13373 {
13374 case x_mode:
13375 names = att_names_ymm;
13376 ins->evex_used |= EVEX_len_used;
13377 break;
13378 case mask_bd_mode:
13379 case mask_mode:
13380 if (reg > 0x7)
13381 {
13382 oappend (ins, "(bad)");
13383 return;
13384 }
13385 names = att_names_mask;
13386 break;
13387 default:
13388 /* See PR binutils/20893 for a reproducer. */
13389 oappend (ins, "(bad)");
13390 return;
13391 }
13392 break;
13393 case 512:
13394 names = att_names_zmm;
13395 ins->evex_used |= EVEX_len_used;
13396 break;
13397 default:
13398 abort ();
13399 break;
13400 }
13401 oappend_register (ins, names[reg]);
13402 }
13403
13404 static void
OP_VexR(instr_info * ins,int bytemode,int sizeflag)13405 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13406 {
13407 if (ins->modrm.mod == 3)
13408 OP_VEX (ins, bytemode, sizeflag);
13409 }
13410
13411 static void
OP_VexW(instr_info * ins,int bytemode,int sizeflag)13412 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13413 {
13414 OP_VEX (ins, bytemode, sizeflag);
13415
13416 if (ins->vex.w)
13417 {
13418 /* Swap 2nd and 3rd operands. */
13419 char *tmp = ins->op_out[2];
13420
13421 ins->op_out[2] = ins->op_out[1];
13422 ins->op_out[1] = tmp;
13423 }
13424 }
13425
13426 static void
OP_REG_VexI4(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13427 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13428 {
13429 int reg;
13430 const char *const *names = att_names_xmm;
13431
13432 FETCH_DATA (ins->info, ins->codep + 1);
13433 reg = *ins->codep++;
13434
13435 if (bytemode != x_mode && bytemode != scalar_mode)
13436 abort ();
13437
13438 reg >>= 4;
13439 if (ins->address_mode != mode_64bit)
13440 reg &= 7;
13441
13442 if (bytemode == x_mode && ins->vex.length == 256)
13443 names = att_names_ymm;
13444
13445 oappend_register (ins, names[reg]);
13446
13447 if (ins->vex.w)
13448 {
13449 /* Swap 3rd and 4th operands. */
13450 char *tmp = ins->op_out[3];
13451
13452 ins->op_out[3] = ins->op_out[2];
13453 ins->op_out[2] = tmp;
13454 }
13455 }
13456
13457 static void
OP_VexI4(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13458 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13459 int sizeflag ATTRIBUTE_UNUSED)
13460 {
13461 oappend_immediate (ins, ins->codep[-1] & 0xf);
13462 }
13463
13464 static void
VPCMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13465 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13466 int sizeflag ATTRIBUTE_UNUSED)
13467 {
13468 unsigned int cmp_type;
13469
13470 if (!ins->vex.evex)
13471 abort ();
13472
13473 FETCH_DATA (ins->info, ins->codep + 1);
13474 cmp_type = *ins->codep++ & 0xff;
13475 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13476 If it's the case, print suffix, otherwise - print the immediate. */
13477 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13478 && cmp_type != 3
13479 && cmp_type != 7)
13480 {
13481 char suffix[3];
13482 char *p = ins->mnemonicendp - 2;
13483
13484 /* vpcmp* can have both one- and two-lettered suffix. */
13485 if (p[0] == 'p')
13486 {
13487 p++;
13488 suffix[0] = p[0];
13489 suffix[1] = '\0';
13490 }
13491 else
13492 {
13493 suffix[0] = p[0];
13494 suffix[1] = p[1];
13495 suffix[2] = '\0';
13496 }
13497
13498 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13499 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13500 }
13501 else
13502 {
13503 /* We have a reserved extension byte. Output it directly. */
13504 oappend_immediate (ins, cmp_type);
13505 }
13506 }
13507
13508 static const struct op xop_cmp_op[] =
13509 {
13510 { STRING_COMMA_LEN ("lt") },
13511 { STRING_COMMA_LEN ("le") },
13512 { STRING_COMMA_LEN ("gt") },
13513 { STRING_COMMA_LEN ("ge") },
13514 { STRING_COMMA_LEN ("eq") },
13515 { STRING_COMMA_LEN ("neq") },
13516 { STRING_COMMA_LEN ("false") },
13517 { STRING_COMMA_LEN ("true") }
13518 };
13519
13520 static void
VPCOM_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13521 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13522 int sizeflag ATTRIBUTE_UNUSED)
13523 {
13524 unsigned int cmp_type;
13525
13526 FETCH_DATA (ins->info, ins->codep + 1);
13527 cmp_type = *ins->codep++ & 0xff;
13528 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13529 {
13530 char suffix[3];
13531 char *p = ins->mnemonicendp - 2;
13532
13533 /* vpcom* can have both one- and two-lettered suffix. */
13534 if (p[0] == 'm')
13535 {
13536 p++;
13537 suffix[0] = p[0];
13538 suffix[1] = '\0';
13539 }
13540 else
13541 {
13542 suffix[0] = p[0];
13543 suffix[1] = p[1];
13544 suffix[2] = '\0';
13545 }
13546
13547 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13548 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13549 }
13550 else
13551 {
13552 /* We have a reserved extension byte. Output it directly. */
13553 oappend_immediate (ins, cmp_type);
13554 }
13555 }
13556
13557 static const struct op pclmul_op[] =
13558 {
13559 { STRING_COMMA_LEN ("lql") },
13560 { STRING_COMMA_LEN ("hql") },
13561 { STRING_COMMA_LEN ("lqh") },
13562 { STRING_COMMA_LEN ("hqh") }
13563 };
13564
13565 static void
PCLMUL_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13566 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13567 int sizeflag ATTRIBUTE_UNUSED)
13568 {
13569 unsigned int pclmul_type;
13570
13571 FETCH_DATA (ins->info, ins->codep + 1);
13572 pclmul_type = *ins->codep++ & 0xff;
13573 switch (pclmul_type)
13574 {
13575 case 0x10:
13576 pclmul_type = 2;
13577 break;
13578 case 0x11:
13579 pclmul_type = 3;
13580 break;
13581 default:
13582 break;
13583 }
13584 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13585 {
13586 char suffix[4];
13587 char *p = ins->mnemonicendp - 3;
13588 suffix[0] = p[0];
13589 suffix[1] = p[1];
13590 suffix[2] = p[2];
13591 suffix[3] = '\0';
13592 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13593 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13594 }
13595 else
13596 {
13597 /* We have a reserved extension byte. Output it directly. */
13598 oappend_immediate (ins, pclmul_type);
13599 }
13600 }
13601
13602 static void
MOVSXD_Fixup(instr_info * ins,int bytemode,int sizeflag)13603 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13604 {
13605 /* Add proper suffix to "movsxd". */
13606 char *p = ins->mnemonicendp;
13607
13608 switch (bytemode)
13609 {
13610 case movsxd_mode:
13611 if (!ins->intel_syntax)
13612 {
13613 USED_REX (REX_W);
13614 if (ins->rex & REX_W)
13615 {
13616 *p++ = 'l';
13617 *p++ = 'q';
13618 break;
13619 }
13620 }
13621
13622 *p++ = 'x';
13623 *p++ = 'd';
13624 break;
13625 default:
13626 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13627 break;
13628 }
13629
13630 ins->mnemonicendp = p;
13631 *p = '\0';
13632 OP_E (ins, bytemode, sizeflag);
13633 }
13634
13635 static void
DistinctDest_Fixup(instr_info * ins,int bytemode,int sizeflag)13636 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13637 {
13638 unsigned int reg = ins->vex.register_specifier;
13639 unsigned int modrm_reg = ins->modrm.reg;
13640 unsigned int modrm_rm = ins->modrm.rm;
13641
13642 /* Calc destination register number. */
13643 if (ins->rex & REX_R)
13644 modrm_reg += 8;
13645 if (!ins->vex.r)
13646 modrm_reg += 16;
13647
13648 /* Calc src1 register number. */
13649 if (ins->address_mode != mode_64bit)
13650 reg &= 7;
13651 else if (ins->vex.evex && !ins->vex.v)
13652 reg += 16;
13653
13654 /* Calc src2 register number. */
13655 if (ins->modrm.mod == 3)
13656 {
13657 if (ins->rex & REX_B)
13658 modrm_rm += 8;
13659 if (ins->rex & REX_X)
13660 modrm_rm += 16;
13661 }
13662
13663 /* Destination and source registers must be distinct, output bad if
13664 dest == src1 or dest == src2. */
13665 if (modrm_reg == reg
13666 || (ins->modrm.mod == 3
13667 && modrm_reg == modrm_rm))
13668 {
13669 oappend (ins, "(bad)");
13670 }
13671 else
13672 OP_XMM (ins, bytemode, sizeflag);
13673 }
13674
13675 static void
OP_Rounding(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13676 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13677 {
13678 if (ins->modrm.mod != 3 || !ins->vex.b)
13679 return;
13680
13681 switch (bytemode)
13682 {
13683 case evex_rounding_64_mode:
13684 if (ins->address_mode != mode_64bit || !ins->vex.w)
13685 return;
13686 /* Fall through. */
13687 case evex_rounding_mode:
13688 ins->evex_used |= EVEX_b_used;
13689 oappend (ins, names_rounding[ins->vex.ll]);
13690 break;
13691 case evex_sae_mode:
13692 ins->evex_used |= EVEX_b_used;
13693 oappend (ins, "{");
13694 break;
13695 default:
13696 abort ();
13697 }
13698 oappend (ins, "sae}");
13699 }
13700