1 /* $NetBSD: intel_sdvo_regs.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2006-2007 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #ifndef __INTEL_SDVO_REGS_H__ 30 #define __INTEL_SDVO_REGS_H__ 31 32 #include <linux/compiler.h> 33 #include <linux/types.h> 34 35 /* 36 * SDVO command definitions and structures. 37 */ 38 39 #define SDVO_OUTPUT_FIRST (0) 40 #define SDVO_OUTPUT_TMDS0 (1 << 0) 41 #define SDVO_OUTPUT_RGB0 (1 << 1) 42 #define SDVO_OUTPUT_CVBS0 (1 << 2) 43 #define SDVO_OUTPUT_SVID0 (1 << 3) 44 #define SDVO_OUTPUT_YPRPB0 (1 << 4) 45 #define SDVO_OUTPUT_SCART0 (1 << 5) 46 #define SDVO_OUTPUT_LVDS0 (1 << 6) 47 #define SDVO_OUTPUT_TMDS1 (1 << 8) 48 #define SDVO_OUTPUT_RGB1 (1 << 9) 49 #define SDVO_OUTPUT_CVBS1 (1 << 10) 50 #define SDVO_OUTPUT_SVID1 (1 << 11) 51 #define SDVO_OUTPUT_YPRPB1 (1 << 12) 52 #define SDVO_OUTPUT_SCART1 (1 << 13) 53 #define SDVO_OUTPUT_LVDS1 (1 << 14) 54 #define SDVO_OUTPUT_LAST (14) 55 56 struct intel_sdvo_caps { 57 u8 vendor_id; 58 u8 device_id; 59 u8 device_rev_id; 60 u8 sdvo_version_major; 61 u8 sdvo_version_minor; 62 unsigned int sdvo_inputs_mask:2; 63 unsigned int smooth_scaling:1; 64 unsigned int sharp_scaling:1; 65 unsigned int up_scaling:1; 66 unsigned int down_scaling:1; 67 unsigned int stall_support:1; 68 unsigned int pad:1; 69 u16 output_flags; 70 } __packed; 71 72 /* Note: SDVO detailed timing flags match EDID misc flags. */ 73 #define DTD_FLAG_HSYNC_POSITIVE (1 << 1) 74 #define DTD_FLAG_VSYNC_POSITIVE (1 << 2) 75 #define DTD_FLAG_INTERLACE (1 << 7) 76 77 /* This matches the EDID DTD structure, more or less */ 78 struct intel_sdvo_dtd { 79 struct { 80 u16 clock; /* pixel clock, in 10kHz units */ 81 u8 h_active; /* lower 8 bits (pixels) */ 82 u8 h_blank; /* lower 8 bits (pixels) */ 83 u8 h_high; /* upper 4 bits each h_active, h_blank */ 84 u8 v_active; /* lower 8 bits (lines) */ 85 u8 v_blank; /* lower 8 bits (lines) */ 86 u8 v_high; /* upper 4 bits each v_active, v_blank */ 87 } part1; 88 89 struct { 90 u8 h_sync_off; /* lower 8 bits, from hblank start */ 91 u8 h_sync_width; /* lower 8 bits (pixels) */ 92 /* lower 4 bits each vsync offset, vsync width */ 93 u8 v_sync_off_width; 94 /* 95 * 2 high bits of hsync offset, 2 high bits of hsync width, 96 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 97 */ 98 u8 sync_off_width_high; 99 u8 dtd_flags; 100 u8 sdvo_flags; 101 /* bits 6-7 of vsync offset at bits 6-7 */ 102 u8 v_sync_off_high; 103 u8 reserved; 104 } part2; 105 } __packed; 106 107 struct intel_sdvo_pixel_clock_range { 108 u16 min; /* pixel clock, in 10kHz units */ 109 u16 max; /* pixel clock, in 10kHz units */ 110 } __packed; 111 112 struct intel_sdvo_preferred_input_timing_args { 113 u16 clock; 114 u16 width; 115 u16 height; 116 u8 interlace:1; 117 u8 scaled:1; 118 u8 pad:6; 119 } __packed; 120 121 /* I2C registers for SDVO */ 122 #define SDVO_I2C_ARG_0 0x07 123 #define SDVO_I2C_ARG_1 0x06 124 #define SDVO_I2C_ARG_2 0x05 125 #define SDVO_I2C_ARG_3 0x04 126 #define SDVO_I2C_ARG_4 0x03 127 #define SDVO_I2C_ARG_5 0x02 128 #define SDVO_I2C_ARG_6 0x01 129 #define SDVO_I2C_ARG_7 0x00 130 #define SDVO_I2C_OPCODE 0x08 131 #define SDVO_I2C_CMD_STATUS 0x09 132 #define SDVO_I2C_RETURN_0 0x0a 133 #define SDVO_I2C_RETURN_1 0x0b 134 #define SDVO_I2C_RETURN_2 0x0c 135 #define SDVO_I2C_RETURN_3 0x0d 136 #define SDVO_I2C_RETURN_4 0x0e 137 #define SDVO_I2C_RETURN_5 0x0f 138 #define SDVO_I2C_RETURN_6 0x10 139 #define SDVO_I2C_RETURN_7 0x11 140 #define SDVO_I2C_VENDOR_BEGIN 0x20 141 142 /* Status results */ 143 #define SDVO_CMD_STATUS_POWER_ON 0x0 144 #define SDVO_CMD_STATUS_SUCCESS 0x1 145 #define SDVO_CMD_STATUS_NOTSUPP 0x2 146 #define SDVO_CMD_STATUS_INVALID_ARG 0x3 147 #define SDVO_CMD_STATUS_PENDING 0x4 148 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 149 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 150 151 /* SDVO commands, argument/result registers */ 152 153 #define SDVO_CMD_RESET 0x01 154 155 /* Returns a struct intel_sdvo_caps */ 156 #define SDVO_CMD_GET_DEVICE_CAPS 0x02 157 158 #define SDVO_CMD_GET_FIRMWARE_REV 0x86 159 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 160 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 161 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 162 163 /* 164 * Reports which inputs are trained (managed to sync). 165 * 166 * Devices must have trained within 2 vsyncs of a mode change. 167 */ 168 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03 169 struct intel_sdvo_get_trained_inputs_response { 170 unsigned int input0_trained:1; 171 unsigned int input1_trained:1; 172 unsigned int pad:6; 173 } __packed; 174 175 /* Returns a struct intel_sdvo_output_flags of active outputs. */ 176 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 177 178 /* 179 * Sets the current set of active outputs. 180 * 181 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP 182 * on multi-output devices. 183 */ 184 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 185 186 /* 187 * Returns the current mapping of SDVO inputs to outputs on the device. 188 * 189 * Returns two struct intel_sdvo_output_flags structures. 190 */ 191 #define SDVO_CMD_GET_IN_OUT_MAP 0x06 192 struct intel_sdvo_in_out_map { 193 u16 in0, in1; 194 }; 195 196 /* 197 * Sets the current mapping of SDVO inputs to outputs on the device. 198 * 199 * Takes two struct i380_sdvo_output_flags structures. 200 */ 201 #define SDVO_CMD_SET_IN_OUT_MAP 0x07 202 203 /* 204 * Returns a struct intel_sdvo_output_flags of attached displays. 205 */ 206 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 207 208 /* 209 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. 210 */ 211 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 212 213 /* 214 * Takes a struct intel_sdvo_output_flags. 215 */ 216 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 217 218 /* 219 * Returns a struct intel_sdvo_output_flags of displays with hot plug 220 * interrupts enabled. 221 */ 222 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 223 224 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 225 struct intel_sdvo_get_interrupt_event_source_response { 226 u16 interrupt_status; 227 unsigned int ambient_light_interrupt:1; 228 unsigned int hdmi_audio_encrypt_change:1; 229 unsigned int pad:6; 230 } __packed; 231 232 /* 233 * Selects which input is affected by future input commands. 234 * 235 * Commands affected include SET_INPUT_TIMINGS_PART[12], 236 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 237 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 238 */ 239 #define SDVO_CMD_SET_TARGET_INPUT 0x10 240 struct intel_sdvo_set_target_input_args { 241 unsigned int target_1:1; 242 unsigned int pad:7; 243 } __packed; 244 245 /* 246 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by 247 * future output commands. 248 * 249 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 250 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 251 */ 252 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 253 254 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 255 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 256 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 257 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 258 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 259 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 260 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 261 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 262 /* Part 1 */ 263 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 264 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 265 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 266 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 267 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 268 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 269 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 270 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 271 /* Part 2 */ 272 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 273 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 274 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 275 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 276 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 277 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) 278 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) 279 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) 280 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) 281 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 282 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) 283 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) 284 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) 285 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) 286 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) 287 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) 288 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) 289 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 290 291 /* 292 * Generates a DTD based on the given width, height, and flags. 293 * 294 * This will be supported by any device supporting scaling or interlaced 295 * modes. 296 */ 297 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a 298 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 299 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 300 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 301 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 302 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 303 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 304 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 305 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) 306 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) 307 308 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 309 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 310 311 /* Returns a struct intel_sdvo_pixel_clock_range */ 312 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 313 /* Returns a struct intel_sdvo_pixel_clock_range */ 314 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 315 316 /* Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 317 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f 318 319 /* Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 320 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 321 /* Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 322 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 323 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0) 324 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1) 325 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 326 327 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 328 /* 6 bytes of bit flags for TV formats shared by all TV format functions */ 329 struct intel_sdvo_tv_format { 330 unsigned int ntsc_m:1; 331 unsigned int ntsc_j:1; 332 unsigned int ntsc_443:1; 333 unsigned int pal_b:1; 334 unsigned int pal_d:1; 335 unsigned int pal_g:1; 336 unsigned int pal_h:1; 337 unsigned int pal_i:1; 338 339 unsigned int pal_m:1; 340 unsigned int pal_n:1; 341 unsigned int pal_nc:1; 342 unsigned int pal_60:1; 343 unsigned int secam_b:1; 344 unsigned int secam_d:1; 345 unsigned int secam_g:1; 346 unsigned int secam_k:1; 347 348 unsigned int secam_k1:1; 349 unsigned int secam_l:1; 350 unsigned int secam_60:1; 351 unsigned int hdtv_std_smpte_240m_1080i_59:1; 352 unsigned int hdtv_std_smpte_240m_1080i_60:1; 353 unsigned int hdtv_std_smpte_260m_1080i_59:1; 354 unsigned int hdtv_std_smpte_260m_1080i_60:1; 355 unsigned int hdtv_std_smpte_274m_1080i_50:1; 356 357 unsigned int hdtv_std_smpte_274m_1080i_59:1; 358 unsigned int hdtv_std_smpte_274m_1080i_60:1; 359 unsigned int hdtv_std_smpte_274m_1080p_23:1; 360 unsigned int hdtv_std_smpte_274m_1080p_24:1; 361 unsigned int hdtv_std_smpte_274m_1080p_25:1; 362 unsigned int hdtv_std_smpte_274m_1080p_29:1; 363 unsigned int hdtv_std_smpte_274m_1080p_30:1; 364 unsigned int hdtv_std_smpte_274m_1080p_50:1; 365 366 unsigned int hdtv_std_smpte_274m_1080p_59:1; 367 unsigned int hdtv_std_smpte_274m_1080p_60:1; 368 unsigned int hdtv_std_smpte_295m_1080i_50:1; 369 unsigned int hdtv_std_smpte_295m_1080p_50:1; 370 unsigned int hdtv_std_smpte_296m_720p_59:1; 371 unsigned int hdtv_std_smpte_296m_720p_60:1; 372 unsigned int hdtv_std_smpte_296m_720p_50:1; 373 unsigned int hdtv_std_smpte_293m_480p_59:1; 374 375 unsigned int hdtv_std_smpte_170m_480i_59:1; 376 unsigned int hdtv_std_iturbt601_576i_50:1; 377 unsigned int hdtv_std_iturbt601_576p_50:1; 378 unsigned int hdtv_std_eia_7702a_480i_60:1; 379 unsigned int hdtv_std_eia_7702a_480p_60:1; 380 unsigned int pad:3; 381 } __packed; 382 383 #define SDVO_CMD_GET_TV_FORMAT 0x28 384 385 #define SDVO_CMD_SET_TV_FORMAT 0x29 386 387 /* Returns the resolutiosn that can be used with the given TV format */ 388 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 389 struct intel_sdvo_sdtv_resolution_request { 390 unsigned int ntsc_m:1; 391 unsigned int ntsc_j:1; 392 unsigned int ntsc_443:1; 393 unsigned int pal_b:1; 394 unsigned int pal_d:1; 395 unsigned int pal_g:1; 396 unsigned int pal_h:1; 397 unsigned int pal_i:1; 398 399 unsigned int pal_m:1; 400 unsigned int pal_n:1; 401 unsigned int pal_nc:1; 402 unsigned int pal_60:1; 403 unsigned int secam_b:1; 404 unsigned int secam_d:1; 405 unsigned int secam_g:1; 406 unsigned int secam_k:1; 407 408 unsigned int secam_k1:1; 409 unsigned int secam_l:1; 410 unsigned int secam_60:1; 411 unsigned int pad:5; 412 } __packed; 413 414 struct intel_sdvo_sdtv_resolution_reply { 415 unsigned int res_320x200:1; 416 unsigned int res_320x240:1; 417 unsigned int res_400x300:1; 418 unsigned int res_640x350:1; 419 unsigned int res_640x400:1; 420 unsigned int res_640x480:1; 421 unsigned int res_704x480:1; 422 unsigned int res_704x576:1; 423 424 unsigned int res_720x350:1; 425 unsigned int res_720x400:1; 426 unsigned int res_720x480:1; 427 unsigned int res_720x540:1; 428 unsigned int res_720x576:1; 429 unsigned int res_768x576:1; 430 unsigned int res_800x600:1; 431 unsigned int res_832x624:1; 432 433 unsigned int res_920x766:1; 434 unsigned int res_1024x768:1; 435 unsigned int res_1280x1024:1; 436 unsigned int pad:5; 437 } __packed; 438 439 /* Get supported resolution with squire pixel aspect ratio that can be 440 scaled for the requested HDTV format */ 441 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 442 443 struct intel_sdvo_hdtv_resolution_request { 444 unsigned int hdtv_std_smpte_240m_1080i_59:1; 445 unsigned int hdtv_std_smpte_240m_1080i_60:1; 446 unsigned int hdtv_std_smpte_260m_1080i_59:1; 447 unsigned int hdtv_std_smpte_260m_1080i_60:1; 448 unsigned int hdtv_std_smpte_274m_1080i_50:1; 449 unsigned int hdtv_std_smpte_274m_1080i_59:1; 450 unsigned int hdtv_std_smpte_274m_1080i_60:1; 451 unsigned int hdtv_std_smpte_274m_1080p_23:1; 452 453 unsigned int hdtv_std_smpte_274m_1080p_24:1; 454 unsigned int hdtv_std_smpte_274m_1080p_25:1; 455 unsigned int hdtv_std_smpte_274m_1080p_29:1; 456 unsigned int hdtv_std_smpte_274m_1080p_30:1; 457 unsigned int hdtv_std_smpte_274m_1080p_50:1; 458 unsigned int hdtv_std_smpte_274m_1080p_59:1; 459 unsigned int hdtv_std_smpte_274m_1080p_60:1; 460 unsigned int hdtv_std_smpte_295m_1080i_50:1; 461 462 unsigned int hdtv_std_smpte_295m_1080p_50:1; 463 unsigned int hdtv_std_smpte_296m_720p_59:1; 464 unsigned int hdtv_std_smpte_296m_720p_60:1; 465 unsigned int hdtv_std_smpte_296m_720p_50:1; 466 unsigned int hdtv_std_smpte_293m_480p_59:1; 467 unsigned int hdtv_std_smpte_170m_480i_59:1; 468 unsigned int hdtv_std_iturbt601_576i_50:1; 469 unsigned int hdtv_std_iturbt601_576p_50:1; 470 471 unsigned int hdtv_std_eia_7702a_480i_60:1; 472 unsigned int hdtv_std_eia_7702a_480p_60:1; 473 unsigned int pad:6; 474 } __packed; 475 476 struct intel_sdvo_hdtv_resolution_reply { 477 unsigned int res_640x480:1; 478 unsigned int res_800x600:1; 479 unsigned int res_1024x768:1; 480 unsigned int res_1280x960:1; 481 unsigned int res_1400x1050:1; 482 unsigned int res_1600x1200:1; 483 unsigned int res_1920x1440:1; 484 unsigned int res_2048x1536:1; 485 486 unsigned int res_2560x1920:1; 487 unsigned int res_3200x2400:1; 488 unsigned int res_3840x2880:1; 489 unsigned int pad1:5; 490 491 unsigned int res_848x480:1; 492 unsigned int res_1064x600:1; 493 unsigned int res_1280x720:1; 494 unsigned int res_1360x768:1; 495 unsigned int res_1704x960:1; 496 unsigned int res_1864x1050:1; 497 unsigned int res_1920x1080:1; 498 unsigned int res_2128x1200:1; 499 500 unsigned int res_2560x1400:1; 501 unsigned int res_2728x1536:1; 502 unsigned int res_3408x1920:1; 503 unsigned int res_4264x2400:1; 504 unsigned int res_5120x2880:1; 505 unsigned int pad2:3; 506 507 unsigned int res_768x480:1; 508 unsigned int res_960x600:1; 509 unsigned int res_1152x720:1; 510 unsigned int res_1124x768:1; 511 unsigned int res_1536x960:1; 512 unsigned int res_1680x1050:1; 513 unsigned int res_1728x1080:1; 514 unsigned int res_1920x1200:1; 515 516 unsigned int res_2304x1440:1; 517 unsigned int res_2456x1536:1; 518 unsigned int res_3072x1920:1; 519 unsigned int res_3840x2400:1; 520 unsigned int res_4608x2880:1; 521 unsigned int pad3:3; 522 523 unsigned int res_1280x1024:1; 524 unsigned int pad4:7; 525 526 unsigned int res_1280x768:1; 527 unsigned int pad5:7; 528 } __packed; 529 530 /* Get supported power state returns info for encoder and monitor, rely on 531 last SetTargetInput and SetTargetOutput calls */ 532 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 533 /* Get power state returns info for encoder and monitor, rely on last 534 SetTargetInput and SetTargetOutput calls */ 535 #define SDVO_CMD_GET_POWER_STATE 0x2b 536 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 537 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 538 # define SDVO_ENCODER_STATE_ON (1 << 0) 539 # define SDVO_ENCODER_STATE_STANDBY (1 << 1) 540 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 541 # define SDVO_ENCODER_STATE_OFF (1 << 3) 542 # define SDVO_MONITOR_STATE_ON (1 << 4) 543 # define SDVO_MONITOR_STATE_STANDBY (1 << 5) 544 # define SDVO_MONITOR_STATE_SUSPEND (1 << 6) 545 # define SDVO_MONITOR_STATE_OFF (1 << 7) 546 547 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d 548 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e 549 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f 550 /* 551 * The panel power sequencing parameters are in units of milliseconds. 552 * The high fields are bits 8:9 of the 10-bit values. 553 */ 554 struct sdvo_panel_power_sequencing { 555 u8 t0; 556 u8 t1; 557 u8 t2; 558 u8 t3; 559 u8 t4; 560 561 unsigned int t0_high:2; 562 unsigned int t1_high:2; 563 unsigned int t2_high:2; 564 unsigned int t3_high:2; 565 566 unsigned int t4_high:2; 567 unsigned int pad:6; 568 } __packed; 569 570 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 571 struct sdvo_max_backlight_reply { 572 u8 max_value; 573 u8 default_value; 574 } __packed; 575 576 #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 577 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32 578 579 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 580 struct sdvo_get_ambient_light_reply { 581 u16 trip_low; 582 u16 trip_high; 583 u16 value; 584 } __packed; 585 #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 586 struct sdvo_set_ambient_light_reply { 587 u16 trip_low; 588 u16 trip_high; 589 unsigned int enable:1; 590 unsigned int pad:7; 591 } __packed; 592 593 /* Set display power state */ 594 #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d 595 # define SDVO_DISPLAY_STATE_ON (1 << 0) 596 # define SDVO_DISPLAY_STATE_STANDBY (1 << 1) 597 # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2) 598 # define SDVO_DISPLAY_STATE_OFF (1 << 3) 599 600 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 601 struct intel_sdvo_enhancements_reply { 602 unsigned int flicker_filter:1; 603 unsigned int flicker_filter_adaptive:1; 604 unsigned int flicker_filter_2d:1; 605 unsigned int saturation:1; 606 unsigned int hue:1; 607 unsigned int brightness:1; 608 unsigned int contrast:1; 609 unsigned int overscan_h:1; 610 611 unsigned int overscan_v:1; 612 unsigned int hpos:1; 613 unsigned int vpos:1; 614 unsigned int sharpness:1; 615 unsigned int dot_crawl:1; 616 unsigned int dither:1; 617 unsigned int tv_chroma_filter:1; 618 unsigned int tv_luma_filter:1; 619 } __packed; 620 621 /* Picture enhancement limits below are dependent on the current TV format, 622 * and thus need to be queried and set after it. 623 */ 624 #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d 625 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b 626 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52 627 #define SDVO_CMD_GET_MAX_SATURATION 0x55 628 #define SDVO_CMD_GET_MAX_HUE 0x58 629 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 630 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e 631 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 632 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 633 #define SDVO_CMD_GET_MAX_HPOS 0x67 634 #define SDVO_CMD_GET_MAX_VPOS 0x6a 635 #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d 636 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 637 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 638 struct intel_sdvo_enhancement_limits_reply { 639 u16 max_value; 640 u16 default_value; 641 } __packed; 642 643 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f 644 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80 645 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0) 646 # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0) 647 # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2) 648 # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2) 649 # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4) 650 # define SDVO_LVDS_DUAL_CHANNEL (1 << 4) 651 652 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e 653 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f 654 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50 655 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51 656 #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53 657 #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54 658 #define SDVO_CMD_GET_SATURATION 0x56 659 #define SDVO_CMD_SET_SATURATION 0x57 660 #define SDVO_CMD_GET_HUE 0x59 661 #define SDVO_CMD_SET_HUE 0x5a 662 #define SDVO_CMD_GET_BRIGHTNESS 0x5c 663 #define SDVO_CMD_SET_BRIGHTNESS 0x5d 664 #define SDVO_CMD_GET_CONTRAST 0x5f 665 #define SDVO_CMD_SET_CONTRAST 0x60 666 #define SDVO_CMD_GET_OVERSCAN_H 0x62 667 #define SDVO_CMD_SET_OVERSCAN_H 0x63 668 #define SDVO_CMD_GET_OVERSCAN_V 0x65 669 #define SDVO_CMD_SET_OVERSCAN_V 0x66 670 #define SDVO_CMD_GET_HPOS 0x68 671 #define SDVO_CMD_SET_HPOS 0x69 672 #define SDVO_CMD_GET_VPOS 0x6b 673 #define SDVO_CMD_SET_VPOS 0x6c 674 #define SDVO_CMD_GET_SHARPNESS 0x6e 675 #define SDVO_CMD_SET_SHARPNESS 0x6f 676 #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75 677 #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76 678 #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 679 #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 680 struct intel_sdvo_enhancements_arg { 681 u16 value; 682 } __packed; 683 684 #define SDVO_CMD_GET_DOT_CRAWL 0x70 685 #define SDVO_CMD_SET_DOT_CRAWL 0x71 686 # define SDVO_DOT_CRAWL_ON (1 << 0) 687 # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1) 688 689 #define SDVO_CMD_GET_DITHER 0x72 690 #define SDVO_CMD_SET_DITHER 0x73 691 # define SDVO_DITHER_ON (1 << 0) 692 # define SDVO_DITHER_DEFAULT_ON (1 << 1) 693 694 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 695 # define SDVO_CONTROL_BUS_PROM (1 << 0) 696 # define SDVO_CONTROL_BUS_DDC1 (1 << 1) 697 # define SDVO_CONTROL_BUS_DDC2 (1 << 2) 698 # define SDVO_CONTROL_BUS_DDC3 (1 << 3) 699 700 /* HDMI op codes */ 701 #define SDVO_CMD_GET_SUPP_ENCODE 0x9d 702 #define SDVO_CMD_GET_ENCODE 0x9e 703 #define SDVO_CMD_SET_ENCODE 0x9f 704 #define SDVO_ENCODE_DVI 0x0 705 #define SDVO_ENCODE_HDMI 0x1 706 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b 707 #define SDVO_CMD_GET_PIXEL_REPLI 0x8c 708 #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d 709 #define SDVO_CMD_SET_COLORIMETRY 0x8e 710 #define SDVO_COLORIMETRY_RGB256 0x0 711 #define SDVO_COLORIMETRY_RGB220 0x1 712 #define SDVO_COLORIMETRY_YCrCb422 0x3 713 #define SDVO_COLORIMETRY_YCrCb444 0x4 714 #define SDVO_CMD_GET_COLORIMETRY 0x8f 715 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90 716 #define SDVO_CMD_SET_AUDIO_STAT 0x91 717 #define SDVO_CMD_GET_AUDIO_STAT 0x92 718 #define SDVO_AUDIO_ELD_VALID (1 << 0) 719 #define SDVO_AUDIO_PRESENCE_DETECT (1 << 1) 720 #define SDVO_AUDIO_CP_READY (1 << 2) 721 #define SDVO_CMD_SET_HBUF_INDEX 0x93 722 #define SDVO_HBUF_INDEX_ELD 0 723 #define SDVO_HBUF_INDEX_AVI_IF 1 724 #define SDVO_CMD_GET_HBUF_INDEX 0x94 725 #define SDVO_CMD_GET_HBUF_INFO 0x95 726 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 727 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97 728 #define SDVO_CMD_SET_HBUF_DATA 0x98 729 #define SDVO_CMD_GET_HBUF_DATA 0x99 730 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a 731 #define SDVO_CMD_GET_HBUF_TXRATE 0x9b 732 #define SDVO_HBUF_TX_DISABLED (0 << 6) 733 #define SDVO_HBUF_TX_ONCE (2 << 6) 734 #define SDVO_HBUF_TX_VSYNC (3 << 6) 735 #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c 736 #define SDVO_NEED_TO_STALL (1 << 7) 737 738 struct intel_sdvo_encode { 739 u8 dvi_rev; 740 u8 hdmi_rev; 741 } __packed; 742 743 #endif /* __INTEL_SDVO_REGS_H__ */ 744