1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include <math.h>
28 #include "rtl.h"
29 #include "regs.h"
30 #include "hard-reg-set.h"
31 #include "real.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "tree.h"
38 #include "expr.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "toplev.h"
43 #include "tm_p.h"
44 #include "target.h"
45 #include "target-def.h"
46
47 static void i960_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
48 static void i960_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
49 static void i960_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
50 HOST_WIDE_INT, tree));
51
52 /* Save the operands last given to a compare for use when we
53 generate a scc or bcc insn. */
54
55 rtx i960_compare_op0, i960_compare_op1;
56
57 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
58 macro in i960.h. */
59
60 int i960_maxbitalignment;
61 int i960_last_maxbitalignment;
62
63 /* Used to implement switching between MEM and ALU insn types, for better
64 C series performance. */
65
66 enum insn_types i960_last_insn_type;
67
68 /* The leaf-procedure return register. Set only if this is a leaf routine. */
69
70 static int i960_leaf_ret_reg;
71
72 /* True if replacing tail calls with jumps is OK. */
73
74 static int tail_call_ok;
75
76 /* A string containing a list of insns to emit in the epilogue so as to
77 restore all registers saved by the prologue. Created by the prologue
78 code as it saves registers away. */
79
80 char epilogue_string[1000];
81
82 /* A unique number (per function) for return labels. */
83
84 static int ret_label = 0;
85
86 /* This is true if FNDECL is either a varargs or a stdarg function.
87 This is used to help identify functions that use an argument block. */
88
89 #define VARARGS_STDARG_FUNCTION(FNDECL) \
90 (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
91 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL))))) \
92 != void_type_node)
93
94 /* Initialize the GCC target structure. */
95 #undef TARGET_ASM_ALIGNED_SI_OP
96 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
97
98 #undef TARGET_ASM_FUNCTION_PROLOGUE
99 #define TARGET_ASM_FUNCTION_PROLOGUE i960_output_function_prologue
100 #undef TARGET_ASM_FUNCTION_EPILOGUE
101 #define TARGET_ASM_FUNCTION_EPILOGUE i960_output_function_epilogue
102
103 #undef TARGET_ASM_OUTPUT_MI_THUNK
104 #define TARGET_ASM_OUTPUT_MI_THUNK i960_output_mi_thunk
105 #undef TARGET_CAN_ASM_OUTPUT_MI_THUNK
106 #define TARGET_CAN_ASM_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
107
108 struct gcc_target targetm = TARGET_INITIALIZER;
109
110 /* Override conflicting target switch options.
111 Doesn't actually detect if more than one -mARCH option is given, but
112 does handle the case of two blatantly conflicting -mARCH options.
113
114 Also initialize variables before compiling any files. */
115
116 void
i960_initialize()117 i960_initialize ()
118 {
119 if (TARGET_K_SERIES && TARGET_C_SERIES)
120 {
121 warning ("conflicting architectures defined - using C series");
122 target_flags &= ~TARGET_FLAG_K_SERIES;
123 }
124 if (TARGET_K_SERIES && TARGET_MC)
125 {
126 warning ("conflicting architectures defined - using K series");
127 target_flags &= ~TARGET_FLAG_MC;
128 }
129 if (TARGET_C_SERIES && TARGET_MC)
130 {
131 warning ("conflicting architectures defined - using C series");
132 target_flags &= ~TARGET_FLAG_MC;
133 }
134 if (TARGET_IC_COMPAT3_0)
135 {
136 flag_short_enums = 1;
137 flag_signed_char = 1;
138 target_flags |= TARGET_FLAG_CLEAN_LINKAGE;
139 if (TARGET_IC_COMPAT2_0)
140 {
141 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0");
142 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0;
143 }
144 }
145 if (TARGET_IC_COMPAT2_0)
146 {
147 flag_signed_char = 1;
148 target_flags |= TARGET_FLAG_CLEAN_LINKAGE;
149 }
150
151 if (TARGET_IC_COMPAT2_0)
152 {
153 i960_maxbitalignment = 8;
154 i960_last_maxbitalignment = 128;
155 }
156 else
157 {
158 i960_maxbitalignment = 128;
159 i960_last_maxbitalignment = 8;
160 }
161
162 /* Tell the compiler which flavor of TFmode we're using. */
163 real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
164 }
165
166 /* Return true if OP can be used as the source of an fp move insn. */
167
168 int
fpmove_src_operand(op,mode)169 fpmove_src_operand (op, mode)
170 rtx op;
171 enum machine_mode mode;
172 {
173 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
174 }
175
176 #if 0
177 /* Return true if OP is a register or zero. */
178
179 int
180 reg_or_zero_operand (op, mode)
181 rtx op;
182 enum machine_mode mode;
183 {
184 return register_operand (op, mode) || op == const0_rtx;
185 }
186 #endif
187
188 /* Return truth value of whether OP can be used as an operands in a three
189 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
190
191 int
arith_operand(op,mode)192 arith_operand (op, mode)
193 rtx op;
194 enum machine_mode mode;
195 {
196 return (register_operand (op, mode) || literal (op, mode));
197 }
198
199 /* Return truth value of whether OP can be used as an operands in a three
200 address logic insn, possibly complementing OP, of mode MODE. */
201
202 int
logic_operand(op,mode)203 logic_operand (op, mode)
204 rtx op;
205 enum machine_mode mode;
206 {
207 return (register_operand (op, mode)
208 || (GET_CODE (op) == CONST_INT
209 && INTVAL(op) >= -32 && INTVAL(op) < 32));
210 }
211
212 /* Return true if OP is a register or a valid floating point literal. */
213
214 int
fp_arith_operand(op,mode)215 fp_arith_operand (op, mode)
216 rtx op;
217 enum machine_mode mode;
218 {
219 return (register_operand (op, mode) || fp_literal (op, mode));
220 }
221
222 /* Return true if OP is a register or a valid signed integer literal. */
223
224 int
signed_arith_operand(op,mode)225 signed_arith_operand (op, mode)
226 rtx op;
227 enum machine_mode mode;
228 {
229 return (register_operand (op, mode) || signed_literal (op, mode));
230 }
231
232 /* Return truth value of whether OP is an integer which fits the
233 range constraining immediate operands in three-address insns. */
234
235 int
literal(op,mode)236 literal (op, mode)
237 rtx op;
238 enum machine_mode mode ATTRIBUTE_UNUSED;
239 {
240 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
241 }
242
243 /* Return true if OP is a float constant of 1. */
244
245 int
fp_literal_one(op,mode)246 fp_literal_one (op, mode)
247 rtx op;
248 enum machine_mode mode;
249 {
250 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
251 }
252
253 /* Return true if OP is a float constant of 0. */
254
255 int
fp_literal_zero(op,mode)256 fp_literal_zero (op, mode)
257 rtx op;
258 enum machine_mode mode;
259 {
260 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
261 }
262
263 /* Return true if OP is a valid floating point literal. */
264
265 int
fp_literal(op,mode)266 fp_literal(op, mode)
267 rtx op;
268 enum machine_mode mode;
269 {
270 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
271 }
272
273 /* Return true if OP is a valid signed immediate constant. */
274
275 int
signed_literal(op,mode)276 signed_literal(op, mode)
277 rtx op;
278 enum machine_mode mode ATTRIBUTE_UNUSED;
279 {
280 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
281 }
282
283 /* Return truth value of statement that OP is a symbolic memory
284 operand of mode MODE. */
285
286 int
symbolic_memory_operand(op,mode)287 symbolic_memory_operand (op, mode)
288 rtx op;
289 enum machine_mode mode ATTRIBUTE_UNUSED;
290 {
291 if (GET_CODE (op) == SUBREG)
292 op = SUBREG_REG (op);
293 if (GET_CODE (op) != MEM)
294 return 0;
295 op = XEXP (op, 0);
296 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
297 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
298 }
299
300 /* Return truth value of whether OP is EQ or NE. */
301
302 int
eq_or_neq(op,mode)303 eq_or_neq (op, mode)
304 rtx op;
305 enum machine_mode mode ATTRIBUTE_UNUSED;
306 {
307 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
308 }
309
310 /* OP is an integer register or a constant. */
311
312 int
arith32_operand(op,mode)313 arith32_operand (op, mode)
314 rtx op;
315 enum machine_mode mode;
316 {
317 if (register_operand (op, mode))
318 return 1;
319 return (CONSTANT_P (op));
320 }
321
322 /* Return true if OP is an integer constant which is a power of 2. */
323
324 int
power2_operand(op,mode)325 power2_operand (op,mode)
326 rtx op;
327 enum machine_mode mode ATTRIBUTE_UNUSED;
328 {
329 if (GET_CODE (op) != CONST_INT)
330 return 0;
331
332 return exact_log2 (INTVAL (op)) >= 0;
333 }
334
335 /* Return true if OP is an integer constant which is the complement of a
336 power of 2. */
337
338 int
cmplpower2_operand(op,mode)339 cmplpower2_operand (op, mode)
340 rtx op;
341 enum machine_mode mode ATTRIBUTE_UNUSED;
342 {
343 if (GET_CODE (op) != CONST_INT)
344 return 0;
345
346 return exact_log2 (~ INTVAL (op)) >= 0;
347 }
348
349 /* If VAL has only one bit set, return the index of that bit. Otherwise
350 return -1. */
351
352 int
bitpos(val)353 bitpos (val)
354 unsigned int val;
355 {
356 register int i;
357
358 for (i = 0; val != 0; i++, val >>= 1)
359 {
360 if (val & 1)
361 {
362 if (val != 1)
363 return -1;
364 return i;
365 }
366 }
367 return -1;
368 }
369
370 /* Return nonzero if OP is a mask, i.e. all one bits are consecutive.
371 The return value indicates how many consecutive nonzero bits exist
372 if this is a mask. This is the same as the next function, except that
373 it does not indicate what the start and stop bit positions are. */
374
375 int
is_mask(val)376 is_mask (val)
377 unsigned int val;
378 {
379 register int start, end = 0, i;
380
381 start = -1;
382 for (i = 0; val != 0; val >>= 1, i++)
383 {
384 if (val & 1)
385 {
386 if (start < 0)
387 start = i;
388
389 end = i;
390 continue;
391 }
392 /* Still looking for the first bit. */
393 if (start < 0)
394 continue;
395
396 /* We've seen the start of a bit sequence, and now a zero. There
397 must be more one bits, otherwise we would have exited the loop.
398 Therefore, it is not a mask. */
399 if (val)
400 return 0;
401 }
402
403 /* The bit string has ones from START to END bit positions only. */
404 return end - start + 1;
405 }
406
407 /* If VAL is a mask, then return nonzero, with S set to the starting bit
408 position and E set to the ending bit position of the mask. The return
409 value indicates how many consecutive bits exist in the mask. This is
410 the same as the previous function, except that it also indicates the
411 start and end bit positions of the mask. */
412
413 int
bitstr(val,s,e)414 bitstr (val, s, e)
415 unsigned int val;
416 int *s, *e;
417 {
418 register int start, end, i;
419
420 start = -1;
421 end = -1;
422 for (i = 0; val != 0; val >>= 1, i++)
423 {
424 if (val & 1)
425 {
426 if (start < 0)
427 start = i;
428
429 end = i;
430 continue;
431 }
432
433 /* Still looking for the first bit. */
434 if (start < 0)
435 continue;
436
437 /* We've seen the start of a bit sequence, and now a zero. There
438 must be more one bits, otherwise we would have exited the loop.
439 Therefor, it is not a mask. */
440 if (val)
441 {
442 start = -1;
443 end = -1;
444 break;
445 }
446 }
447
448 /* The bit string has ones from START to END bit positions only. */
449 *s = start;
450 *e = end;
451 return ((start < 0) ? 0 : end - start + 1);
452 }
453
454 /* Return the machine mode to use for a comparison. */
455
456 enum machine_mode
select_cc_mode(op,x)457 select_cc_mode (op, x)
458 RTX_CODE op;
459 rtx x ATTRIBUTE_UNUSED;
460 {
461 if (op == GTU || op == LTU || op == GEU || op == LEU)
462 return CC_UNSmode;
463 return CCmode;
464 }
465
466 /* X and Y are two things to compare using CODE. Emit the compare insn and
467 return the rtx for register 36 in the proper mode. */
468
469 rtx
gen_compare_reg(code,x,y)470 gen_compare_reg (code, x, y)
471 enum rtx_code code;
472 rtx x, y;
473 {
474 rtx cc_reg;
475 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
476 enum machine_mode mode
477 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
478
479 if (mode == SImode)
480 {
481 if (! arith_operand (x, mode))
482 x = force_reg (SImode, x);
483 if (! arith_operand (y, mode))
484 y = force_reg (SImode, y);
485 }
486
487 cc_reg = gen_rtx_REG (ccmode, 36);
488 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
489 gen_rtx_COMPARE (ccmode, x, y)));
490
491 return cc_reg;
492 }
493
494 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
495 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
496 are 4. Indexed addresses are cost 6. */
497
498 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
499
500 int
i960_address_cost(x)501 i960_address_cost (x)
502 rtx x;
503 {
504 #if 0
505 /* Handled before calling here. */
506 if (GET_CODE (x) == REG)
507 return 1;
508 #endif
509 /* This is a MEMA operand -- it's free. */
510 if (GET_CODE (x) == CONST_INT
511 && INTVAL (x) >= 0
512 && INTVAL (x) < 4096)
513 return 0;
514
515 if (GET_CODE (x) == PLUS)
516 {
517 rtx base = XEXP (x, 0);
518 rtx offset = XEXP (x, 1);
519
520 if (GET_CODE (base) == SUBREG)
521 base = SUBREG_REG (base);
522 if (GET_CODE (offset) == SUBREG)
523 offset = SUBREG_REG (offset);
524
525 if (GET_CODE (base) == REG)
526 {
527 if (GET_CODE (offset) == REG)
528 return 2;
529 if (GET_CODE (offset) == CONST_INT)
530 {
531 if ((unsigned)INTVAL (offset) < 2047)
532 return 2;
533 return 4;
534 }
535 if (CONSTANT_P (offset))
536 return 4;
537 }
538 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
539 return 6;
540
541 /* This is an invalid address. The return value doesn't matter, but
542 for convenience we make this more expensive than anything else. */
543 return 12;
544 }
545 if (GET_CODE (x) == MULT)
546 return 6;
547
548 /* Symbol_refs and other unrecognized addresses are cost 4. */
549 return 4;
550 }
551
552 /* Emit insns to move operands[1] into operands[0].
553
554 Return 1 if we have written out everything that needs to be done to
555 do the move. Otherwise, return 0 and the caller will emit the move
556 normally. */
557
558 int
emit_move_sequence(operands,mode)559 emit_move_sequence (operands, mode)
560 rtx *operands;
561 enum machine_mode mode;
562 {
563 /* We can only store registers to memory. */
564
565 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG
566 && (operands[1] != const0_rtx || current_function_args_size
567 || current_function_stdarg
568 || rtx_equal_function_value_matters))
569 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
570 operands[1] = force_reg (mode, operands[1]);
571
572 /* Storing multi-word values in unaligned hard registers to memory may
573 require a scratch since we have to store them a register at a time and
574 adding 4 to the memory address may not yield a valid insn. */
575 /* ??? We don't always need the scratch, but that would complicate things.
576 Maybe later. */
577 /* ??? We must also handle stores to pseudos here, because the pseudo may be
578 replaced with a MEM later. This would be cleaner if we didn't have
579 a separate pattern for unaligned DImode/TImode stores. */
580 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
581 && (GET_CODE (operands[0]) == MEM
582 || (GET_CODE (operands[0]) == REG
583 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
584 && GET_CODE (operands[1]) == REG
585 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
586 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
587 {
588 emit_insn (gen_rtx_PARALLEL
589 (VOIDmode,
590 gen_rtvec (2,
591 gen_rtx_SET (VOIDmode, operands[0], operands[1]),
592 gen_rtx_CLOBBER (VOIDmode,
593 gen_rtx_SCRATCH (Pmode)))));
594 return 1;
595 }
596
597 return 0;
598 }
599
600 /* Output assembler to move a double word value. */
601
602 const char *
i960_output_move_double(dst,src)603 i960_output_move_double (dst, src)
604 rtx dst, src;
605 {
606 rtx operands[5];
607
608 if (GET_CODE (dst) == REG
609 && GET_CODE (src) == REG)
610 {
611 if ((REGNO (src) & 1)
612 || (REGNO (dst) & 1))
613 {
614 /* We normally copy the low-numbered register first. However, if
615 the second source register is the same as the first destination
616 register, we must copy in the opposite order. */
617 if (REGNO (src) + 1 == REGNO (dst))
618 return "mov %D1,%D0\n\tmov %1,%0";
619 else
620 return "mov %1,%0\n\tmov %D1,%D0";
621 }
622 else
623 return "movl %1,%0";
624 }
625 else if (GET_CODE (dst) == REG
626 && GET_CODE (src) == CONST_INT
627 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
628 {
629 if (REGNO (dst) & 1)
630 return "mov %1,%0\n\tmov 0,%D0";
631 else
632 return "movl %1,%0";
633 }
634 else if (GET_CODE (dst) == REG
635 && GET_CODE (src) == MEM)
636 {
637 if (REGNO (dst) & 1)
638 {
639 /* One can optimize a few cases here, but you have to be
640 careful of clobbering registers used in the address and
641 edge conditions. */
642 operands[0] = dst;
643 operands[1] = src;
644 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 1);
645 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
646 operands[4] = adjust_address (operands[3], word_mode,
647 UNITS_PER_WORD);
648 output_asm_insn
649 ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
650 return "";
651 }
652 else
653 return "ldl %1,%0";
654 }
655 else if (GET_CODE (dst) == MEM
656 && GET_CODE (src) == REG)
657 {
658 if (REGNO (src) & 1)
659 {
660 operands[0] = dst;
661 operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
662 if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
663 abort ();
664 operands[2] = src;
665 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands);
666 return "";
667 }
668 return "stl %1,%0";
669 }
670 else
671 abort ();
672 }
673
674 /* Output assembler to move a double word zero. */
675
676 const char *
i960_output_move_double_zero(dst)677 i960_output_move_double_zero (dst)
678 rtx dst;
679 {
680 rtx operands[2];
681
682 operands[0] = dst;
683 {
684 operands[1] = adjust_address (dst, word_mode, 4);
685 output_asm_insn ("st g14,%0\n\tst g14,%1", operands);
686 }
687 return "";
688 }
689
690 /* Output assembler to move a quad word value. */
691
692 const char *
i960_output_move_quad(dst,src)693 i960_output_move_quad (dst, src)
694 rtx dst, src;
695 {
696 rtx operands[7];
697
698 if (GET_CODE (dst) == REG
699 && GET_CODE (src) == REG)
700 {
701 if ((REGNO (src) & 3)
702 || (REGNO (dst) & 3))
703 {
704 /* We normally copy starting with the low numbered register.
705 However, if there is an overlap such that the first dest reg
706 is <= the last source reg but not < the first source reg, we
707 must copy in the opposite order. */
708 if (REGNO (dst) <= REGNO (src) + 3
709 && REGNO (dst) >= REGNO (src))
710 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
711 else
712 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
713 }
714 else
715 return "movq %1,%0";
716 }
717 else if (GET_CODE (dst) == REG
718 && GET_CODE (src) == CONST_INT
719 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
720 {
721 if (REGNO (dst) & 3)
722 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
723 else
724 return "movq %1,%0";
725 }
726 else if (GET_CODE (dst) == REG
727 && GET_CODE (src) == MEM)
728 {
729 if (REGNO (dst) & 3)
730 {
731 /* One can optimize a few cases here, but you have to be
732 careful of clobbering registers used in the address and
733 edge conditions. */
734 operands[0] = dst;
735 operands[1] = src;
736 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 3);
737 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
738 operands[4]
739 = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
740 operands[5]
741 = adjust_address (operands[4], word_mode, UNITS_PER_WORD);
742 operands[6]
743 = adjust_address (operands[5], word_mode, UNITS_PER_WORD);
744 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
745 return "";
746 }
747 else
748 return "ldq %1,%0";
749 }
750 else if (GET_CODE (dst) == MEM
751 && GET_CODE (src) == REG)
752 {
753 if (REGNO (src) & 3)
754 {
755 operands[0] = dst;
756 operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
757 operands[2] = adjust_address (dst, word_mode, 2 * UNITS_PER_WORD);
758 operands[3] = adjust_address (dst, word_mode, 3 * UNITS_PER_WORD);
759 if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
760 abort ();
761 operands[4] = src;
762 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands);
763 return "";
764 }
765 return "stq %1,%0";
766 }
767 else
768 abort ();
769 }
770
771 /* Output assembler to move a quad word zero. */
772
773 const char *
i960_output_move_quad_zero(dst)774 i960_output_move_quad_zero (dst)
775 rtx dst;
776 {
777 rtx operands[4];
778
779 operands[0] = dst;
780 {
781 operands[1] = adjust_address (dst, word_mode, 4);
782 operands[2] = adjust_address (dst, word_mode, 8);
783 operands[3] = adjust_address (dst, word_mode, 12);
784 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands);
785 }
786 return "";
787 }
788
789
790 /* Emit insns to load a constant to non-floating point registers.
791 Uses several strategies to try to use as few insns as possible. */
792
793 const char *
i960_output_ldconst(dst,src)794 i960_output_ldconst (dst, src)
795 register rtx dst, src;
796 {
797 register int rsrc1;
798 register unsigned rsrc2;
799 enum machine_mode mode = GET_MODE (dst);
800 rtx operands[4];
801
802 operands[0] = operands[2] = dst;
803 operands[1] = operands[3] = src;
804
805 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
806 must be a ldconst insn. */
807
808 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
809 {
810 output_asm_insn ("ldconst %1,%0", operands);
811 return "";
812 }
813 else if (mode == TFmode)
814 {
815 REAL_VALUE_TYPE d;
816 long value_long[3];
817 int i;
818
819 if (fp_literal_zero (src, TFmode))
820 return "movt 0,%0";
821
822 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
823 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
824
825 output_asm_insn ("# ldconst %1,%0",operands);
826
827 for (i = 0; i < 3; i++)
828 {
829 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + i);
830 operands[1] = GEN_INT (value_long[i]);
831 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
832 operands);
833 }
834
835 return "";
836 }
837 else if (mode == DFmode)
838 {
839 rtx first, second;
840
841 if (fp_literal_zero (src, DFmode))
842 return "movl 0,%0";
843
844 split_double (src, &first, &second);
845
846 output_asm_insn ("# ldconst %1,%0",operands);
847
848 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
849 operands[1] = first;
850 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
851 operands);
852 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
853 operands[1] = second;
854 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
855 operands);
856 return "";
857 }
858 else if (mode == SFmode)
859 {
860 REAL_VALUE_TYPE d;
861 long value;
862
863 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
864 REAL_VALUE_TO_TARGET_SINGLE (d, value);
865
866 output_asm_insn ("# ldconst %1,%0",operands);
867 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
868 operands[1] = GEN_INT (value);
869 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
870 operands);
871 return "";
872 }
873 else if (mode == TImode)
874 {
875 /* ??? This is currently not handled at all. */
876 abort ();
877
878 /* Note: lowest order word goes in lowest numbered reg. */
879 rsrc1 = INTVAL (src);
880 if (rsrc1 >= 0 && rsrc1 < 32)
881 return "movq %1,%0";
882 else
883 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
884 /* Go pick up the low-order word. */
885 }
886 else if (mode == DImode)
887 {
888 rtx upperhalf, lowerhalf, xoperands[2];
889
890 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
891 split_double (src, &lowerhalf, &upperhalf);
892
893 else
894 abort ();
895
896 /* Note: lowest order word goes in lowest numbered reg. */
897 /* Numbers from 0 to 31 can be handled with a single insn. */
898 rsrc1 = INTVAL (lowerhalf);
899 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
900 return "movl %1,%0";
901
902 /* Output the upper half with a recursive call. */
903 xoperands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
904 xoperands[1] = upperhalf;
905 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
906 xoperands);
907 /* The lower word is emitted as normally. */
908 }
909 else
910 {
911 rsrc1 = INTVAL (src);
912 if (mode == QImode)
913 {
914 if (rsrc1 > 0xff)
915 rsrc1 &= 0xff;
916 }
917 else if (mode == HImode)
918 {
919 if (rsrc1 > 0xffff)
920 rsrc1 &= 0xffff;
921 }
922 }
923
924 if (rsrc1 >= 0)
925 {
926 /* ldconst 0..31,X -> mov 0..31,X */
927 if (rsrc1 < 32)
928 {
929 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
930 return "lda %1,%0";
931 return "mov %1,%0";
932 }
933
934 /* ldconst 32..63,X -> add 31,nn,X */
935 if (rsrc1 < 63)
936 {
937 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
938 return "lda %1,%0";
939 operands[1] = GEN_INT (rsrc1 - 31);
940 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
941 return "";
942 }
943 }
944 else if (rsrc1 < 0)
945 {
946 /* ldconst -1..-31 -> sub 0,0..31,X */
947 if (rsrc1 >= -31)
948 {
949 /* return 'sub -(%1),0,%0' */
950 operands[1] = GEN_INT (- rsrc1);
951 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
952 return "";
953 }
954
955 /* ldconst -32 -> not 31,X */
956 if (rsrc1 == -32)
957 {
958 operands[1] = GEN_INT (~rsrc1);
959 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
960 return "";
961 }
962 }
963
964 /* If const is a single bit. */
965 if (bitpos (rsrc1) >= 0)
966 {
967 operands[1] = GEN_INT (bitpos (rsrc1));
968 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
969 return "";
970 }
971
972 /* If const is a bit string of less than 6 bits (1..31 shifted). */
973 if (is_mask (rsrc1))
974 {
975 int s, e;
976
977 if (bitstr (rsrc1, &s, &e) < 6)
978 {
979 rsrc2 = ((unsigned int) rsrc1) >> s;
980 operands[1] = GEN_INT (rsrc2);
981 operands[2] = GEN_INT (s);
982 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
983 return "";
984 }
985 }
986
987 /* Unimplemented cases:
988 const is in range 0..31 but rotated around end of word:
989 ror 31,3,g0 -> ldconst 0xe0000003,g0
990
991 and any 2 instruction cases that might be worthwhile */
992
993 output_asm_insn ("ldconst %1,%0", operands);
994 return "";
995 }
996
997 /* Determine if there is an opportunity for a bypass optimization.
998 Bypass succeeds on the 960K* if the destination of the previous
999 instruction is the second operand of the current instruction.
1000 Bypass always succeeds on the C*.
1001
1002 Return 1 if the pattern should interchange the operands.
1003
1004 CMPBR_FLAG is true if this is for a compare-and-branch insn.
1005 OP1 and OP2 are the two source operands of a 3 operand insn. */
1006
1007 int
i960_bypass(insn,op1,op2,cmpbr_flag)1008 i960_bypass (insn, op1, op2, cmpbr_flag)
1009 register rtx insn, op1, op2;
1010 int cmpbr_flag;
1011 {
1012 register rtx prev_insn, prev_dest;
1013
1014 if (TARGET_C_SERIES)
1015 return 0;
1016
1017 /* Can't do this if op1 isn't a register. */
1018 if (! REG_P (op1))
1019 return 0;
1020
1021 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1022 if (cmpbr_flag && ! REG_P (op2))
1023 return 0;
1024
1025 prev_insn = prev_real_insn (insn);
1026
1027 if (prev_insn && GET_CODE (prev_insn) == INSN
1028 && GET_CODE (PATTERN (prev_insn)) == SET)
1029 {
1030 prev_dest = SET_DEST (PATTERN (prev_insn));
1031 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
1032 || (GET_CODE (prev_dest) == SUBREG
1033 && GET_CODE (SUBREG_REG (prev_dest)) == REG
1034 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
1035 return 1;
1036 }
1037 return 0;
1038 }
1039
1040 /* Output the code which declares the function name. This also handles
1041 leaf routines, which have special requirements, and initializes some
1042 global variables. */
1043
1044 void
i960_function_name_declare(file,name,fndecl)1045 i960_function_name_declare (file, name, fndecl)
1046 FILE *file;
1047 const char *name;
1048 tree fndecl;
1049 {
1050 register int i, j;
1051 int leaf_proc_ok;
1052 rtx insn;
1053
1054 /* Increment global return label. */
1055
1056 ret_label++;
1057
1058 /* Compute whether tail calls and leaf routine optimizations can be performed
1059 for this function. */
1060
1061 if (TARGET_TAILCALL)
1062 tail_call_ok = 1;
1063 else
1064 tail_call_ok = 0;
1065
1066 if (TARGET_LEAFPROC)
1067 leaf_proc_ok = 1;
1068 else
1069 leaf_proc_ok = 0;
1070
1071 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1072 argblock, because argblock uses g14 implicitly. */
1073
1074 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
1075 {
1076 tail_call_ok = 0;
1077 leaf_proc_ok = 0;
1078 }
1079
1080 /* See if caller passes in an address to return value. */
1081
1082 if (aggregate_value_p (DECL_RESULT (fndecl)))
1083 {
1084 tail_call_ok = 0;
1085 leaf_proc_ok = 0;
1086 }
1087
1088 /* Can not use tail calls or make this a leaf routine if there is a non
1089 zero frame size. */
1090
1091 if (get_frame_size () != 0)
1092 leaf_proc_ok = 0;
1093
1094 /* I don't understand this condition, and do not think that it is correct.
1095 Apparently this is just checking whether the frame pointer is used, and
1096 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1097
1098 if (tail_call_ok)
1099 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1100 if (GET_CODE (insn) == INSN
1101 && reg_mentioned_p (frame_pointer_rtx, insn))
1102 {
1103 tail_call_ok = 0;
1104 break;
1105 }
1106
1107 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1108
1109 if (leaf_proc_ok)
1110 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1111 if (GET_CODE (insn) == CALL_INSN)
1112 {
1113 leaf_proc_ok = 0;
1114 break;
1115 }
1116
1117 /* Can not be a leaf routine if any non-call clobbered registers are
1118 used in this function. */
1119
1120 if (leaf_proc_ok)
1121 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1122 if (regs_ever_live[i]
1123 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1124 {
1125 /* Global registers. */
1126 if (i < 16 && i > 7 && i != 13)
1127 leaf_proc_ok = 0;
1128 /* Local registers. */
1129 else if (i < 32)
1130 leaf_proc_ok = 0;
1131 }
1132
1133 /* Now choose a leaf return register, if we can find one, and if it is
1134 OK for this to be a leaf routine. */
1135
1136 i960_leaf_ret_reg = -1;
1137
1138 if (optimize && leaf_proc_ok)
1139 {
1140 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
1141 if (regs_ever_live[i] == 0)
1142 {
1143 i960_leaf_ret_reg = i;
1144 regs_ever_live[i] = 1;
1145 break;
1146 }
1147 }
1148
1149 /* Do this after choosing the leaf return register, so it will be listed
1150 if one was chosen. */
1151
1152 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
1153 fprintf (file, "\t# Registers used: ");
1154
1155 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1156 {
1157 if (regs_ever_live[i])
1158 {
1159 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
1160
1161 if (i > 15 && j == 0)
1162 {
1163 fprintf (file,"\n\t#\t\t ");
1164 j++;
1165 }
1166 }
1167 }
1168
1169 fprintf (file, "\n");
1170
1171 if (i960_leaf_ret_reg >= 0)
1172 {
1173 /* Make it a leaf procedure. */
1174
1175 if (TREE_PUBLIC (fndecl))
1176 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
1177
1178 fprintf (file, "\t.leafproc\t");
1179 assemble_name (file, name);
1180 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
1181 ASM_OUTPUT_LABEL (file, name);
1182 fprintf (file, "\tlda Li960R%d,g14\n", ret_label);
1183 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
1184 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
1185
1186 if (TARGET_C_SERIES)
1187 {
1188 fprintf (file, "\tlda 0,g14\n");
1189 i960_last_insn_type = I_TYPE_MEM;
1190 }
1191 else
1192 {
1193 fprintf (file, "\tmov 0,g14\n");
1194 i960_last_insn_type = I_TYPE_REG;
1195 }
1196 }
1197 else
1198 {
1199 ASM_OUTPUT_LABEL (file, name);
1200 i960_last_insn_type = I_TYPE_CTRL;
1201 }
1202 }
1203
1204 /* Compute and return the frame size. */
1205
1206 int
compute_frame_size(size)1207 compute_frame_size (size)
1208 int size;
1209 {
1210 int actual_fsize;
1211 int outgoing_args_size = current_function_outgoing_args_size;
1212
1213 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1214 as size is concerned. */
1215 actual_fsize = (size + 15) & -16;
1216 actual_fsize += (outgoing_args_size + 15) & -16;
1217
1218 return actual_fsize;
1219 }
1220
1221 /* Here register group is range of registers which can be moved by
1222 one i960 instruction. */
1223
1224 struct reg_group
1225 {
1226 char start_reg;
1227 char length;
1228 };
1229
1230 static int i960_form_reg_groups PARAMS ((int, int, int *, int, struct reg_group *));
1231 static int i960_reg_group_compare PARAMS ((const void *, const void *));
1232 static int i960_split_reg_group PARAMS ((struct reg_group *, int, int));
1233 static void i960_arg_size_and_align PARAMS ((enum machine_mode, tree, int *, int *));
1234
1235 /* The following functions forms the biggest as possible register
1236 groups with registers in STATE. REGS contain states of the
1237 registers in range [start, finish_reg). The function returns the
1238 number of groups formed. */
1239 static int
i960_form_reg_groups(start_reg,finish_reg,regs,state,reg_groups)1240 i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
1241 int start_reg;
1242 int finish_reg;
1243 int *regs;
1244 int state;
1245 struct reg_group *reg_groups;
1246 {
1247 int i;
1248 int nw = 0;
1249
1250 for (i = start_reg; i < finish_reg; )
1251 {
1252 if (regs [i] != state)
1253 {
1254 i++;
1255 continue;
1256 }
1257 else if (i % 2 != 0 || regs [i + 1] != state)
1258 reg_groups [nw].length = 1;
1259 else if (i % 4 != 0 || regs [i + 2] != state)
1260 reg_groups [nw].length = 2;
1261 else if (regs [i + 3] != state)
1262 reg_groups [nw].length = 3;
1263 else
1264 reg_groups [nw].length = 4;
1265 reg_groups [nw].start_reg = i;
1266 i += reg_groups [nw].length;
1267 nw++;
1268 }
1269 return nw;
1270 }
1271
1272 /* We sort register winodws in descending order by length. */
1273 static int
i960_reg_group_compare(group1,group2)1274 i960_reg_group_compare (group1, group2)
1275 const void *group1;
1276 const void *group2;
1277 {
1278 const struct reg_group *w1 = group1;
1279 const struct reg_group *w2 = group2;
1280
1281 if (w1->length > w2->length)
1282 return -1;
1283 else if (w1->length < w2->length)
1284 return 1;
1285 else
1286 return 0;
1287 }
1288
1289 /* Split the first register group in REG_GROUPS on subgroups one of
1290 which will contain SUBGROUP_LENGTH registers. The function
1291 returns new number of winodws. */
1292 static int
i960_split_reg_group(reg_groups,nw,subgroup_length)1293 i960_split_reg_group (reg_groups, nw, subgroup_length)
1294 struct reg_group *reg_groups;
1295 int nw;
1296 int subgroup_length;
1297 {
1298 if (subgroup_length < reg_groups->length - subgroup_length)
1299 /* This guarantees correct alignments of the two subgroups for
1300 i960 (see spliting for the group length 2, 3, 4). More
1301 generalized algorithm would require splitting the group more
1302 two subgroups. */
1303 subgroup_length = reg_groups->length - subgroup_length;
1304 /* More generalized algorithm would require to try merging
1305 subgroups here. But in case i960 it always results in failure
1306 because of register group alignment. */
1307 reg_groups[nw].length = reg_groups->length - subgroup_length;
1308 reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
1309 nw++;
1310 reg_groups->length = subgroup_length;
1311 qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare);
1312 return nw;
1313 }
1314
1315 /* Output code for the function prologue. */
1316
1317 static void
i960_output_function_prologue(file,size)1318 i960_output_function_prologue (file, size)
1319 FILE *file;
1320 HOST_WIDE_INT size;
1321 {
1322 register int i, j, nr;
1323 int n_saved_regs = 0;
1324 int n_remaining_saved_regs;
1325 HOST_WIDE_INT lvar_size;
1326 HOST_WIDE_INT actual_fsize, offset;
1327 int gnw, lnw;
1328 struct reg_group *g, *l;
1329 char tmpstr[1000];
1330 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1331 somewhere. */
1332 int regs[FIRST_PSEUDO_REGISTER];
1333 /* All global registers (which must be saved) divided by groups. */
1334 struct reg_group global_reg_groups [16];
1335 /* All local registers (which are available) divided by groups. */
1336 struct reg_group local_reg_groups [16];
1337
1338
1339 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1340 if (regs_ever_live[i]
1341 && ((! call_used_regs[i]) || (i > 7 && i < 12))
1342 /* No need to save the static chain pointer. */
1343 && ! (i == STATIC_CHAIN_REGNUM && current_function_needs_context))
1344 {
1345 regs[i] = -1;
1346 /* Count global registers that need saving. */
1347 if (i < 16)
1348 n_saved_regs++;
1349 }
1350 else
1351 regs[i] = 0;
1352
1353 n_remaining_saved_regs = n_saved_regs;
1354
1355 epilogue_string[0] = '\0';
1356
1357 if (current_function_profile)
1358 {
1359 /* When profiling, we may use registers 20 to 27 to save arguments, so
1360 they can't be used here for saving globals. J is the number of
1361 argument registers the mcount call will save. */
1362 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1363 ;
1364
1365 for (i = 20; i <= j + 20; i++)
1366 regs[i] = -1;
1367 }
1368
1369 gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups);
1370 lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups);
1371 qsort (global_reg_groups, gnw, sizeof (struct reg_group),
1372 i960_reg_group_compare);
1373 qsort (local_reg_groups, lnw, sizeof (struct reg_group),
1374 i960_reg_group_compare);
1375 for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;)
1376 {
1377 if (g->length == l->length)
1378 {
1379 fprintf (file, "\tmov%s %s,%s\n",
1380 ((g->length == 4) ? "q" :
1381 (g->length == 3) ? "t" :
1382 (g->length == 2) ? "l" : ""),
1383 reg_names[(unsigned char) g->start_reg],
1384 reg_names[(unsigned char) l->start_reg]);
1385 sprintf (tmpstr, "\tmov%s %s,%s\n",
1386 ((g->length == 4) ? "q" :
1387 (g->length == 3) ? "t" :
1388 (g->length == 2) ? "l" : ""),
1389 reg_names[(unsigned char) l->start_reg],
1390 reg_names[(unsigned char) g->start_reg]);
1391 strcat (epilogue_string, tmpstr);
1392 n_remaining_saved_regs -= g->length;
1393 for (i = 0; i < g->length; i++)
1394 {
1395 regs [i + g->start_reg] = 1;
1396 regs [i + l->start_reg] = -1;
1397 regs_ever_live [i + l->start_reg] = 1;
1398 }
1399 g++;
1400 l++;
1401 gnw--;
1402 lnw--;
1403 }
1404 else if (g->length > l->length)
1405 gnw = i960_split_reg_group (g, gnw, l->length);
1406 else
1407 lnw = i960_split_reg_group (l, lnw, g->length);
1408 }
1409
1410 actual_fsize = compute_frame_size (size) + 4 * n_remaining_saved_regs;
1411 #if 0
1412 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1413 size up to the nearest multiple of 16. I don't know whether this is
1414 necessary, or even desirable.
1415
1416 The frame pointer must be aligned, but the call instruction takes care of
1417 that. If we leave the stack pointer unaligned, we may save a little on
1418 dynamic stack allocation. And we don't lose, at least according to the
1419 i960CA manual. */
1420 actual_fsize = (actual_fsize + 15) & ~0xF;
1421 #endif
1422
1423 /* Check stack limit if necessary. */
1424 if (current_function_limit_stack)
1425 {
1426 rtx min_stack = stack_limit_rtx;
1427 if (actual_fsize != 0)
1428 min_stack = plus_constant (stack_limit_rtx, -actual_fsize);
1429
1430 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1431 into an arith_operand. Use register 20 as the temporary. */
1432 if (legitimate_address_p (Pmode, min_stack, 1)
1433 && !arith_operand (min_stack, Pmode))
1434 {
1435 rtx tmp = gen_rtx_MEM (Pmode, min_stack);
1436 fputs ("\tlda\t", file);
1437 i960_print_operand (file, tmp, 0);
1438 fputs (",r4\n", file);
1439 min_stack = gen_rtx_REG (Pmode, 20);
1440 }
1441 if (arith_operand (min_stack, Pmode))
1442 {
1443 fputs ("\tcmpo\tsp,", file);
1444 i960_print_operand (file, min_stack, 0);
1445 fputs ("\n\tfaultge.f\n", file);
1446 }
1447 else
1448 warning ("stack limit expression is not supported");
1449 }
1450
1451 /* Allocate space for register save and locals. */
1452 if (actual_fsize > 0)
1453 {
1454 if (actual_fsize < 32)
1455 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1456 else
1457 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1458 }
1459
1460 /* Take hardware register save area created by the call instruction
1461 into account, but store them before the argument block area. */
1462 lvar_size = actual_fsize - compute_frame_size (0) - n_remaining_saved_regs * 4;
1463 offset = STARTING_FRAME_OFFSET + lvar_size;
1464 /* Save registers on stack if needed. */
1465 /* ??? Is it worth to use the same algorithm as one for saving
1466 global registers in local registers? */
1467 for (i = 0, j = n_remaining_saved_regs; j > 0 && i < 16; i++)
1468 {
1469 if (regs[i] != -1)
1470 continue;
1471
1472 nr = 1;
1473
1474 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1475 nr = 2;
1476
1477 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1478 && offset % 4 == 0)
1479 nr = 3;
1480
1481 if (nr == 3 && regs[i+3] == -1)
1482 nr = 4;
1483
1484 fprintf (file,"\tst%s %s,%d(fp)\n",
1485 ((nr == 4) ? "q" :
1486 (nr == 3) ? "t" :
1487 (nr == 2) ? "l" : ""),
1488 reg_names[i], offset);
1489 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1490 ((nr == 4) ? "q" :
1491 (nr == 3) ? "t" :
1492 (nr == 2) ? "l" : ""),
1493 offset, reg_names[i]);
1494 strcat (epilogue_string, tmpstr);
1495 i += nr-1;
1496 j -= nr;
1497 offset += nr * 4;
1498 }
1499
1500 if (actual_fsize == 0)
1501 return;
1502
1503 fprintf (file, "\t#Prologue stats:\n");
1504 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1505
1506 if (lvar_size)
1507 fprintf (file, "\t# Local Variable Size: %d bytes\n", lvar_size);
1508 if (n_saved_regs)
1509 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1510 n_saved_regs, n_saved_regs * 4);
1511 fprintf (file, "\t#End Prologue#\n");
1512 }
1513
1514 /* Output code for the function profiler. */
1515
1516 void
output_function_profiler(file,labelno)1517 output_function_profiler (file, labelno)
1518 FILE *file;
1519 int labelno;
1520 {
1521 /* The last used parameter register. */
1522 int last_parm_reg;
1523 int i, j, increment;
1524 int varargs_stdarg_function
1525 = VARARGS_STDARG_FUNCTION (current_function_decl);
1526
1527 /* Figure out the last used parameter register. The proper thing to do
1528 is to walk incoming args of the function. A function might have live
1529 parameter registers even if it has no incoming args. Note that we
1530 don't have to save parameter registers g8 to g11 because they are
1531 call preserved. */
1532
1533 /* See also output_function_prologue, which tries to use local registers
1534 for preserved call-saved global registers. */
1535
1536 for (last_parm_reg = 7;
1537 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1538 last_parm_reg--)
1539 ;
1540
1541 /* Save parameter registers in regs r4 (20) to r11 (27). */
1542
1543 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1544 {
1545 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1546 increment = 4;
1547 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1548 increment = 3;
1549 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1550 increment = 2;
1551 else
1552 increment = 1;
1553
1554 fprintf (file, "\tmov%s g%d,r%d\n",
1555 (increment == 4 ? "q" : increment == 3 ? "t"
1556 : increment == 2 ? "l": ""), i, j);
1557 }
1558
1559 /* If this function uses the arg pointer, then save it in r3 and then
1560 set it to zero. */
1561
1562 if (current_function_args_size != 0 || varargs_stdarg_function)
1563 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1564
1565 /* Load location address into g0 and call mcount. */
1566
1567 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1568
1569 /* If this function uses the arg pointer, restore it. */
1570
1571 if (current_function_args_size != 0 || varargs_stdarg_function)
1572 fprintf (file, "\tmov r3,g14\n");
1573
1574 /* Restore parameter registers. */
1575
1576 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1577 {
1578 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1579 increment = 4;
1580 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1581 increment = 3;
1582 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1583 increment = 2;
1584 else
1585 increment = 1;
1586
1587 fprintf (file, "\tmov%s r%d,g%d\n",
1588 (increment == 4 ? "q" : increment == 3 ? "t"
1589 : increment == 2 ? "l": ""), j, i);
1590 }
1591 }
1592
1593 /* Output code for the function epilogue. */
1594
1595 static void
i960_output_function_epilogue(file,size)1596 i960_output_function_epilogue (file, size)
1597 FILE *file;
1598 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1599 {
1600 if (i960_leaf_ret_reg >= 0)
1601 {
1602 fprintf (file, "Li960R%d: ret\n", ret_label);
1603 return;
1604 }
1605
1606 if (*epilogue_string == 0)
1607 {
1608 register rtx tmp;
1609
1610 /* Emit a return insn, but only if control can fall through to here. */
1611
1612 tmp = get_last_insn ();
1613 while (tmp)
1614 {
1615 if (GET_CODE (tmp) == BARRIER)
1616 return;
1617 if (GET_CODE (tmp) == CODE_LABEL)
1618 break;
1619 if (GET_CODE (tmp) == JUMP_INSN)
1620 {
1621 if (GET_CODE (PATTERN (tmp)) == RETURN)
1622 return;
1623 break;
1624 }
1625 if (GET_CODE (tmp) == NOTE)
1626 {
1627 tmp = PREV_INSN (tmp);
1628 continue;
1629 }
1630 break;
1631 }
1632 fprintf (file, "Li960R%d: ret\n", ret_label);
1633 return;
1634 }
1635
1636 fprintf (file, "Li960R%d:\n", ret_label);
1637
1638 fprintf (file, "\t#EPILOGUE#\n");
1639
1640 /* Output the string created by the prologue which will restore all
1641 registers saved by the prologue. */
1642
1643 if (epilogue_string[0] != '\0')
1644 fprintf (file, "%s", epilogue_string);
1645
1646 /* Must clear g14 on return if this function set it.
1647 Only varargs/stdarg functions modify g14. */
1648
1649 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1650 fprintf (file, "\tmov 0,g14\n");
1651
1652 fprintf (file, "\tret\n");
1653 fprintf (file, "\t#End Epilogue#\n");
1654 }
1655
1656 /* Output code for a call insn. */
1657
1658 const char *
i960_output_call_insn(target,argsize_rtx,arg_pointer,insn)1659 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1660 register rtx target, argsize_rtx, arg_pointer, insn;
1661 {
1662 int argsize = INTVAL (argsize_rtx);
1663 rtx nexti = next_real_insn (insn);
1664 rtx operands[2];
1665 int varargs_stdarg_function
1666 = VARARGS_STDARG_FUNCTION (current_function_decl);
1667
1668 operands[0] = target;
1669 operands[1] = arg_pointer;
1670
1671 if (current_function_args_size != 0 || varargs_stdarg_function)
1672 output_asm_insn ("mov g14,r3", operands);
1673
1674 if (argsize > 48)
1675 output_asm_insn ("lda %a1,g14", operands);
1676 else if (current_function_args_size != 0 || varargs_stdarg_function)
1677 output_asm_insn ("mov 0,g14", operands);
1678
1679 /* The code used to assume that calls to SYMBOL_REFs could not be more
1680 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1681 feature is now implemented by relaxing in the GNU linker. It can convert
1682 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1683
1684 /* Nexti could be zero if the called routine is volatile. */
1685 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1686 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1687 {
1688 /* Delete following return insn. */
1689 if (nexti && no_labels_between_p (insn, nexti))
1690 delete_insn (nexti);
1691 output_asm_insn ("bx %0", operands);
1692 return "# notreached";
1693 }
1694
1695 output_asm_insn ("callx %0", operands);
1696
1697 /* If the caller sets g14 to the address of the argblock, then the caller
1698 must clear it after the return. */
1699
1700 if (current_function_args_size != 0 || varargs_stdarg_function)
1701 output_asm_insn ("mov r3,g14", operands);
1702 else if (argsize > 48)
1703 output_asm_insn ("mov 0,g14", operands);
1704
1705 return "";
1706 }
1707
1708 /* Output code for a return insn. */
1709
1710 const char *
i960_output_ret_insn(insn)1711 i960_output_ret_insn (insn)
1712 register rtx insn;
1713 {
1714 static char lbuf[20];
1715
1716 if (*epilogue_string != 0)
1717 {
1718 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1719 return "";
1720
1721 sprintf (lbuf, "b Li960R%d", ret_label);
1722 return lbuf;
1723 }
1724
1725 /* Must clear g14 on return if this function set it.
1726 Only varargs/stdarg functions modify g14. */
1727
1728 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1729 output_asm_insn ("mov 0,g14", 0);
1730
1731 if (i960_leaf_ret_reg >= 0)
1732 {
1733 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1734 return lbuf;
1735 }
1736 return "ret";
1737 }
1738
1739 /* Print the operand represented by rtx X formatted by code CODE. */
1740
1741 void
i960_print_operand(file,x,code)1742 i960_print_operand (file, x, code)
1743 FILE *file;
1744 rtx x;
1745 int code;
1746 {
1747 enum rtx_code rtxcode = x ? GET_CODE (x) : NIL;
1748
1749 if (rtxcode == REG)
1750 {
1751 switch (code)
1752 {
1753 case 'D':
1754 /* Second reg of a double or quad. */
1755 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1756 break;
1757
1758 case 'E':
1759 /* Third reg of a quad. */
1760 fprintf (file, "%s", reg_names[REGNO (x)+2]);
1761 break;
1762
1763 case 'F':
1764 /* Fourth reg of a quad. */
1765 fprintf (file, "%s", reg_names[REGNO (x)+3]);
1766 break;
1767
1768 case 0:
1769 fprintf (file, "%s", reg_names[REGNO (x)]);
1770 break;
1771
1772 default:
1773 abort ();
1774 }
1775 return;
1776 }
1777 else if (rtxcode == MEM)
1778 {
1779 output_address (XEXP (x, 0));
1780 return;
1781 }
1782 else if (rtxcode == CONST_INT)
1783 {
1784 HOST_WIDE_INT val = INTVAL (x);
1785 if (code == 'C')
1786 val = ~val;
1787 if (val > 9999 || val < -999)
1788 fprintf (file, "0x%x", val);
1789 else
1790 fprintf (file, "%d", val);
1791 return;
1792 }
1793 else if (rtxcode == CONST_DOUBLE)
1794 {
1795 char dstr[30];
1796
1797 if (x == CONST0_RTX (GET_MODE (x)))
1798 {
1799 fprintf (file, "0f0.0");
1800 return;
1801 }
1802 else if (x == CONST1_RTX (GET_MODE (x)))
1803 {
1804 fprintf (file, "0f1.0");
1805 return;
1806 }
1807
1808 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
1809 fprintf (file, "0f%s", dstr);
1810 return;
1811 }
1812
1813 switch(code)
1814 {
1815 case 'B':
1816 /* Branch or jump, depending on assembler. */
1817 if (TARGET_ASM_COMPAT)
1818 fputs ("j", file);
1819 else
1820 fputs ("b", file);
1821 break;
1822
1823 case 'S':
1824 /* Sign of condition. */
1825 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1826 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1827 fputs ("o", file);
1828 else if ((rtxcode == GT) || (rtxcode == LT)
1829 || (rtxcode == GE) || (rtxcode == LE))
1830 fputs ("i", file);
1831 else
1832 abort();
1833 break;
1834
1835 case 'I':
1836 /* Inverted condition. */
1837 rtxcode = reverse_condition (rtxcode);
1838 goto normal;
1839
1840 case 'X':
1841 /* Inverted condition w/ reversed operands. */
1842 rtxcode = reverse_condition (rtxcode);
1843 /* Fallthrough. */
1844
1845 case 'R':
1846 /* Reversed operand condition. */
1847 rtxcode = swap_condition (rtxcode);
1848 /* Fallthrough. */
1849
1850 case 'C':
1851 /* Normal condition. */
1852 normal:
1853 if (rtxcode == EQ) { fputs ("e", file); return; }
1854 else if (rtxcode == NE) { fputs ("ne", file); return; }
1855 else if (rtxcode == GT) { fputs ("g", file); return; }
1856 else if (rtxcode == GTU) { fputs ("g", file); return; }
1857 else if (rtxcode == LT) { fputs ("l", file); return; }
1858 else if (rtxcode == LTU) { fputs ("l", file); return; }
1859 else if (rtxcode == GE) { fputs ("ge", file); return; }
1860 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1861 else if (rtxcode == LE) { fputs ("le", file); return; }
1862 else if (rtxcode == LEU) { fputs ("le", file); return; }
1863 else abort ();
1864 break;
1865
1866 case '+':
1867 /* For conditional branches, substitute ".t" or ".f". */
1868 if (TARGET_BRANCH_PREDICT)
1869 {
1870 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1871 if (x)
1872 {
1873 int pred_val = INTVAL (XEXP (x, 0));
1874 fputs ((pred_val < REG_BR_PROB_BASE / 2 ? ".f" : ".t"), file);
1875 }
1876 }
1877 break;
1878
1879 case 0:
1880 output_addr_const (file, x);
1881 break;
1882
1883 default:
1884 abort ();
1885 }
1886
1887 return;
1888 }
1889
1890 /* Print a memory address as an operand to reference that memory location.
1891
1892 This is exactly the same as legitimate_address_p, except that it the prints
1893 addresses instead of recognizing them. */
1894
1895 void
i960_print_operand_addr(file,addr)1896 i960_print_operand_addr (file, addr)
1897 FILE *file;
1898 register rtx addr;
1899 {
1900 rtx breg, ireg;
1901 rtx scale, offset;
1902
1903 ireg = 0;
1904 breg = 0;
1905 offset = 0;
1906 scale = const1_rtx;
1907
1908 if (GET_CODE (addr) == REG)
1909 breg = addr;
1910 else if (CONSTANT_P (addr))
1911 offset = addr;
1912 else if (GET_CODE (addr) == PLUS)
1913 {
1914 rtx op0, op1;
1915
1916 op0 = XEXP (addr, 0);
1917 op1 = XEXP (addr, 1);
1918
1919 if (GET_CODE (op0) == REG)
1920 {
1921 breg = op0;
1922 if (GET_CODE (op1) == REG)
1923 ireg = op1;
1924 else if (CONSTANT_P (op1))
1925 offset = op1;
1926 else
1927 abort ();
1928 }
1929 else if (GET_CODE (op0) == PLUS)
1930 {
1931 if (GET_CODE (XEXP (op0, 0)) == MULT)
1932 {
1933 ireg = XEXP (XEXP (op0, 0), 0);
1934 scale = XEXP (XEXP (op0, 0), 1);
1935 if (GET_CODE (XEXP (op0, 1)) == REG)
1936 {
1937 breg = XEXP (op0, 1);
1938 offset = op1;
1939 }
1940 else
1941 abort ();
1942 }
1943 else if (GET_CODE (XEXP (op0, 0)) == REG)
1944 {
1945 breg = XEXP (op0, 0);
1946 if (GET_CODE (XEXP (op0, 1)) == REG)
1947 {
1948 ireg = XEXP (op0, 1);
1949 offset = op1;
1950 }
1951 else
1952 abort ();
1953 }
1954 else
1955 abort ();
1956 }
1957 else if (GET_CODE (op0) == MULT)
1958 {
1959 ireg = XEXP (op0, 0);
1960 scale = XEXP (op0, 1);
1961 if (GET_CODE (op1) == REG)
1962 breg = op1;
1963 else if (CONSTANT_P (op1))
1964 offset = op1;
1965 else
1966 abort ();
1967 }
1968 else
1969 abort ();
1970 }
1971 else if (GET_CODE (addr) == MULT)
1972 {
1973 ireg = XEXP (addr, 0);
1974 scale = XEXP (addr, 1);
1975 }
1976 else
1977 abort ();
1978
1979 if (offset)
1980 output_addr_const (file, offset);
1981 if (breg)
1982 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1983 if (ireg)
1984 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1985 }
1986
1987 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1988 that is a valid memory address for an instruction.
1989 The MODE argument is the machine mode for the MEM expression
1990 that wants to use this address.
1991
1992 On 80960, legitimate addresses are:
1993 base ld (g0),r0
1994 disp (12 or 32 bit) ld foo,r0
1995 base + index ld (g0)[g1*1],r0
1996 base + displ ld 0xf00(g0),r0
1997 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1998 index*scale + base ld (g0)[g1*4],r0
1999 index*scale + displ ld 0xf00[g1*4],r0
2000 index*scale ld [g1*4],r0
2001 index + base + displ ld 0xf00(g0)[g1*1],r0
2002
2003 In each case, scale can be 1, 2, 4, 8, or 16. */
2004
2005 /* This is exactly the same as i960_print_operand_addr, except that
2006 it recognizes addresses instead of printing them.
2007
2008 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2009 convert common non-canonical forms to canonical form so that they will
2010 be recognized. */
2011
2012 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2013 where a register is valid. */
2014
2015 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2016 ((GET_CODE (X) == REG \
2017 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2018 || (GET_CODE (X) == SUBREG \
2019 && GET_CODE (SUBREG_REG (X)) == REG \
2020 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2021 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2022
2023 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2024 ((GET_CODE (X) == REG \
2025 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2026 || (GET_CODE (X) == SUBREG \
2027 && GET_CODE (SUBREG_REG (X)) == REG \
2028 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2029 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2030
2031 int
legitimate_address_p(mode,addr,strict)2032 legitimate_address_p (mode, addr, strict)
2033 enum machine_mode mode ATTRIBUTE_UNUSED;
2034 register rtx addr;
2035 int strict;
2036 {
2037 if (RTX_OK_FOR_BASE_P (addr, strict))
2038 return 1;
2039 else if (CONSTANT_P (addr))
2040 return 1;
2041 else if (GET_CODE (addr) == PLUS)
2042 {
2043 rtx op0, op1;
2044
2045 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2046 return 0;
2047
2048 op0 = XEXP (addr, 0);
2049 op1 = XEXP (addr, 1);
2050
2051 if (RTX_OK_FOR_BASE_P (op0, strict))
2052 {
2053 if (RTX_OK_FOR_INDEX_P (op1, strict))
2054 return 1;
2055 else if (CONSTANT_P (op1))
2056 return 1;
2057 else
2058 return 0;
2059 }
2060 else if (GET_CODE (op0) == PLUS)
2061 {
2062 if (GET_CODE (XEXP (op0, 0)) == MULT)
2063 {
2064 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
2065 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
2066 return 0;
2067
2068 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
2069 && CONSTANT_P (op1))
2070 return 1;
2071 else
2072 return 0;
2073 }
2074 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
2075 {
2076 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
2077 && CONSTANT_P (op1))
2078 return 1;
2079 else
2080 return 0;
2081 }
2082 else
2083 return 0;
2084 }
2085 else if (GET_CODE (op0) == MULT)
2086 {
2087 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
2088 && SCALE_TERM_P (XEXP (op0, 1))))
2089 return 0;
2090
2091 if (RTX_OK_FOR_BASE_P (op1, strict))
2092 return 1;
2093 else if (CONSTANT_P (op1))
2094 return 1;
2095 else
2096 return 0;
2097 }
2098 else
2099 return 0;
2100 }
2101 else if (GET_CODE (addr) == MULT)
2102 {
2103 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2104 return 0;
2105
2106 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
2107 && SCALE_TERM_P (XEXP (addr, 1)));
2108 }
2109 else
2110 return 0;
2111 }
2112
2113 /* Try machine-dependent ways of modifying an illegitimate address
2114 to be legitimate. If we find one, return the new, valid address.
2115 This macro is used in only one place: `memory_address' in explow.c.
2116
2117 This converts some non-canonical addresses to canonical form so they
2118 can be recognized. */
2119
2120 rtx
legitimize_address(x,oldx,mode)2121 legitimize_address (x, oldx, mode)
2122 register rtx x;
2123 register rtx oldx ATTRIBUTE_UNUSED;
2124 enum machine_mode mode ATTRIBUTE_UNUSED;
2125 {
2126 if (GET_CODE (x) == SYMBOL_REF)
2127 {
2128 abort ();
2129 x = copy_to_reg (x);
2130 }
2131
2132 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2133 return x;
2134
2135 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2136 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2137 created by virtual register instantiation, register elimination, and
2138 similar optimizations. */
2139 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
2140 && GET_CODE (XEXP (x, 1)) == PLUS)
2141 x = gen_rtx_PLUS (Pmode,
2142 gen_rtx_PLUS (Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2143 XEXP (XEXP (x, 1), 1));
2144
2145 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2146 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2147 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2148 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2149 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2150 && CONSTANT_P (XEXP (x, 1)))
2151 {
2152 rtx constant, other;
2153
2154 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2155 {
2156 constant = XEXP (x, 1);
2157 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2158 }
2159 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2160 {
2161 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2162 other = XEXP (x, 1);
2163 }
2164 else
2165 constant = 0, other = 0;
2166
2167 if (constant)
2168 x = gen_rtx_PLUS (Pmode,
2169 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
2170 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2171 plus_constant (other, INTVAL (constant)));
2172 }
2173
2174 return x;
2175 }
2176
2177 #if 0
2178 /* Return the most stringent alignment that we are willing to consider
2179 objects of size SIZE and known alignment ALIGN as having. */
2180
2181 int
2182 i960_alignment (size, align)
2183 int size;
2184 int align;
2185 {
2186 int i;
2187
2188 if (! TARGET_STRICT_ALIGN)
2189 if (TARGET_IC_COMPAT2_0 || align >= 4)
2190 {
2191 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2192 if (i > align)
2193 align = i;
2194 }
2195
2196 return align;
2197 }
2198 #endif
2199
2200
2201 int
hard_regno_mode_ok(regno,mode)2202 hard_regno_mode_ok (regno, mode)
2203 int regno;
2204 enum machine_mode mode;
2205 {
2206 if (regno < 32)
2207 {
2208 switch (mode)
2209 {
2210 case CCmode: case CC_UNSmode: case CC_CHKmode:
2211 return 0;
2212
2213 case DImode: case DFmode:
2214 return (regno & 1) == 0;
2215
2216 case TImode: case TFmode:
2217 return (regno & 3) == 0;
2218
2219 default:
2220 return 1;
2221 }
2222 }
2223 else if (regno >= 32 && regno < 36)
2224 {
2225 switch (mode)
2226 {
2227 case SFmode: case DFmode: case TFmode:
2228 case SCmode: case DCmode:
2229 return 1;
2230
2231 default:
2232 return 0;
2233 }
2234 }
2235 else if (regno == 36)
2236 {
2237 switch (mode)
2238 {
2239 case CCmode: case CC_UNSmode: case CC_CHKmode:
2240 return 1;
2241
2242 default:
2243 return 0;
2244 }
2245 }
2246 else if (regno == 37)
2247 return 0;
2248
2249 abort ();
2250 }
2251
2252
2253 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2254 advantage of machine specific facts, such as knowing that the frame pointer
2255 is always 16 byte aligned. */
2256
2257 int
i960_expr_alignment(x,size)2258 i960_expr_alignment (x, size)
2259 rtx x;
2260 int size;
2261 {
2262 int align = 1;
2263
2264 if (x == 0)
2265 return 1;
2266
2267 switch (GET_CODE(x))
2268 {
2269 case CONST_INT:
2270 align = INTVAL(x);
2271
2272 if ((align & 0xf) == 0)
2273 align = 16;
2274 else if ((align & 0x7) == 0)
2275 align = 8;
2276 else if ((align & 0x3) == 0)
2277 align = 4;
2278 else if ((align & 0x1) == 0)
2279 align = 2;
2280 else
2281 align = 1;
2282 break;
2283
2284 case PLUS:
2285 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
2286 i960_expr_alignment (XEXP (x, 1), size));
2287 break;
2288
2289 case SYMBOL_REF:
2290 /* If this is a valid program, objects are guaranteed to be
2291 correctly aligned for whatever size the reference actually is. */
2292 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2293 break;
2294
2295 case REG:
2296 if (REGNO (x) == FRAME_POINTER_REGNUM)
2297 align = 16;
2298 break;
2299
2300 case ASHIFT:
2301 align = i960_expr_alignment (XEXP (x, 0), size);
2302
2303 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2304 {
2305 align = align << INTVAL (XEXP (x, 1));
2306 align = MIN (align, 16);
2307 }
2308 break;
2309
2310 case MULT:
2311 align = (i960_expr_alignment (XEXP (x, 0), size) *
2312 i960_expr_alignment (XEXP (x, 1), size));
2313
2314 align = MIN (align, 16);
2315 break;
2316 default:
2317 break;
2318 }
2319
2320 return align;
2321 }
2322
2323 /* Return true if it is possible to reference both BASE and OFFSET, which
2324 have alignment at least as great as 4 byte, as if they had alignment valid
2325 for an object of size SIZE. */
2326
2327 int
i960_improve_align(base,offset,size)2328 i960_improve_align (base, offset, size)
2329 rtx base;
2330 rtx offset;
2331 int size;
2332 {
2333 int i, j;
2334
2335 /* We have at least a word reference to the object, so we know it has to
2336 be aligned at least to 4 bytes. */
2337
2338 i = MIN (i960_expr_alignment (base, 4),
2339 i960_expr_alignment (offset, 4));
2340
2341 i = MAX (i, 4);
2342
2343 /* We know the size of the request. If strict align is not enabled, we
2344 can guess that the alignment is OK for the requested size. */
2345
2346 if (! TARGET_STRICT_ALIGN)
2347 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
2348 i = j;
2349
2350 return (i >= size);
2351 }
2352
2353 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2354 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2355
2356 int
i960_si_ti(base,offset)2357 i960_si_ti (base, offset)
2358 rtx base;
2359 rtx offset;
2360 {
2361 return i960_improve_align (base, offset, 16);
2362 }
2363
2364 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2365 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2366
2367 int
i960_si_di(base,offset)2368 i960_si_di (base, offset)
2369 rtx base;
2370 rtx offset;
2371 {
2372 return i960_improve_align (base, offset, 8);
2373 }
2374
2375 /* Return raw values of size and alignment (in words) for the data
2376 type being accessed. These values will be rounded by the caller. */
2377
2378 static void
i960_arg_size_and_align(mode,type,size_out,align_out)2379 i960_arg_size_and_align (mode, type, size_out, align_out)
2380 enum machine_mode mode;
2381 tree type;
2382 int *size_out;
2383 int *align_out;
2384 {
2385 int size, align;
2386
2387 /* Use formal alignment requirements of type being passed, except make
2388 it at least a word. If we don't have a type, this is a library call,
2389 and the parm has to be of scalar type. In this case, consider its
2390 formal alignment requirement to be its size in words. */
2391
2392 if (mode == BLKmode)
2393 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2394 else if (mode == VOIDmode)
2395 {
2396 /* End of parm list. */
2397 if (type == 0 || TYPE_MODE (type) != VOIDmode)
2398 abort ();
2399 size = 1;
2400 }
2401 else
2402 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2403
2404 if (type == 0)
2405 align = size;
2406 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2407 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2408 else
2409 align = 1;
2410
2411 *size_out = size;
2412 *align_out = align;
2413 }
2414
2415 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2416 Any arg that is bigger than 4 words is placed on the stack and all
2417 subsequent arguments are placed on the stack.
2418
2419 Additionally, parameters with an alignment requirement stronger than
2420 a word must be aligned appropriately. Note that this means that a
2421 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2422 passed in an odd/even register pair. */
2423
2424 /* Update CUM to advance past an argument described by MODE and TYPE. */
2425
2426 void
i960_function_arg_advance(cum,mode,type,named)2427 i960_function_arg_advance (cum, mode, type, named)
2428 CUMULATIVE_ARGS *cum;
2429 enum machine_mode mode;
2430 tree type;
2431 int named ATTRIBUTE_UNUSED;
2432 {
2433 int size, align;
2434
2435 i960_arg_size_and_align (mode, type, &size, &align);
2436
2437 if (size > 4 || cum->ca_nstackparms != 0
2438 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2439 || MUST_PASS_IN_STACK (mode, type))
2440 {
2441 /* Indicate that all the registers are in use, even if all are not,
2442 so va_start will compute the right value. */
2443 cum->ca_nregparms = NPARM_REGS;
2444 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2445 }
2446 else
2447 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2448 }
2449
2450 /* Return the register that the argument described by MODE and TYPE is
2451 passed in, or else return 0 if it is passed on the stack. */
2452
2453 rtx
i960_function_arg(cum,mode,type,named)2454 i960_function_arg (cum, mode, type, named)
2455 CUMULATIVE_ARGS *cum;
2456 enum machine_mode mode;
2457 tree type;
2458 int named ATTRIBUTE_UNUSED;
2459 {
2460 rtx ret;
2461 int size, align;
2462
2463 if (mode == VOIDmode)
2464 return 0;
2465
2466 i960_arg_size_and_align (mode, type, &size, &align);
2467
2468 if (size > 4 || cum->ca_nstackparms != 0
2469 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2470 || MUST_PASS_IN_STACK (mode, type))
2471 {
2472 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2473 ret = 0;
2474 }
2475 else
2476 {
2477 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2478 ret = gen_rtx_REG (mode, cum->ca_nregparms);
2479 }
2480
2481 return ret;
2482 }
2483
2484 /* Return the number of bits that an object of size N bytes is aligned to. */
2485
2486 int
i960_object_bytes_bitalign(n)2487 i960_object_bytes_bitalign (n)
2488 int n;
2489 {
2490 if (n > 8) n = 128;
2491 else if (n > 4) n = 64;
2492 else if (n > 2) n = 32;
2493 else if (n > 1) n = 16;
2494 else n = 8;
2495
2496 return n;
2497 }
2498
2499 /* Compute the alignment for an aggregate type TSIZE.
2500 Alignment is MAX (greatest member alignment,
2501 MIN (pragma align, structure size alignment)). */
2502
2503 int
i960_round_align(align,type)2504 i960_round_align (align, type)
2505 int align;
2506 tree type;
2507 {
2508 int new_align;
2509 tree tsize;
2510
2511 if (TARGET_OLD_ALIGN || TYPE_PACKED (type))
2512 return align;
2513 if (TREE_CODE (type) != RECORD_TYPE)
2514 return align;
2515 tsize = TYPE_SIZE (type);
2516
2517 if (! tsize || TREE_CODE (tsize) != INTEGER_CST)
2518 return align;
2519
2520 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2521 / BITS_PER_UNIT);
2522 /* Handle #pragma align. */
2523 if (new_align > i960_maxbitalignment)
2524 new_align = i960_maxbitalignment;
2525
2526 if (align < new_align)
2527 align = new_align;
2528
2529 return align;
2530 }
2531
2532 /* Do any needed setup for a varargs function. For the i960, we must
2533 create a register parameter block if one doesn't exist, and then copy
2534 all register parameters to memory. */
2535
2536 void
i960_setup_incoming_varargs(cum,mode,type,pretend_size,no_rtl)2537 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2538 CUMULATIVE_ARGS *cum;
2539 enum machine_mode mode ATTRIBUTE_UNUSED;
2540 tree type ATTRIBUTE_UNUSED;
2541 int *pretend_size ATTRIBUTE_UNUSED;
2542 int no_rtl;
2543 {
2544 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2545 int first_reg = cum->ca_nregparms;
2546
2547 /* Copy only unnamed register arguments to memory. If there are
2548 any stack parms, there are no unnamed arguments in registers, and
2549 an argument block was already allocated by the caller.
2550 Remember that any arg bigger than 4 words is passed on the stack as
2551 are all subsequent args.
2552
2553 If there are no stack arguments but there are exactly NPARM_REGS
2554 registers, either there were no extra arguments or the caller
2555 allocated an argument block. */
2556
2557 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
2558 {
2559 rtx label = gen_label_rtx ();
2560 rtx regblock, fake_arg_pointer_rtx;
2561
2562 /* Use a different rtx than arg_pointer_rtx so that cse and friends
2563 can go on believing that the argument pointer can never be zero. */
2564 fake_arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
2565
2566 /* If the argument pointer is 0, no arguments were passed on the stack
2567 and we need to allocate a chunk to save the registers (if any
2568 arguments were passed on the stack the caller would allocate the
2569 48 bytes as well). We must allocate all 48 bytes (12*4) because
2570 va_start assumes it. */
2571 emit_insn (gen_cmpsi (fake_arg_pointer_rtx, const0_rtx));
2572 emit_jump_insn (gen_bne (label));
2573 emit_insn (gen_rtx_SET (VOIDmode, fake_arg_pointer_rtx,
2574 stack_pointer_rtx));
2575 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2576 memory_address (SImode,
2577 plus_constant (stack_pointer_rtx,
2578 48))));
2579 emit_label (label);
2580
2581 /* ??? Note that we unnecessarily store one extra register for stdarg
2582 fns. We could optimize this, but it's kept as for now. */
2583 regblock = gen_rtx_MEM (BLKmode,
2584 plus_constant (arg_pointer_rtx, first_reg * 4));
2585 set_mem_alias_set (regblock, get_varargs_alias_set ());
2586 set_mem_align (regblock, BITS_PER_WORD);
2587 move_block_from_reg (first_reg, regblock,
2588 NPARM_REGS - first_reg,
2589 (NPARM_REGS - first_reg) * UNITS_PER_WORD);
2590 }
2591 }
2592
2593 /* Define the `__builtin_va_list' type for the ABI. */
2594
2595 tree
i960_build_va_list()2596 i960_build_va_list ()
2597 {
2598 return build_array_type (unsigned_type_node,
2599 build_index_type (size_one_node));
2600 }
2601
2602 /* Implement `va_start' for varargs and stdarg. */
2603
2604 void
i960_va_start(valist,nextarg)2605 i960_va_start (valist, nextarg)
2606 tree valist;
2607 rtx nextarg ATTRIBUTE_UNUSED;
2608 {
2609 tree s, t, base, num;
2610 rtx fake_arg_pointer_rtx;
2611
2612 /* The array type always decays to a pointer before we get here, so we
2613 can't use ARRAY_REF. */
2614 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2615 num = build1 (INDIRECT_REF, unsigned_type_node,
2616 build (PLUS_EXPR, unsigned_type_node, valist,
2617 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2618
2619 /* Use a different rtx than arg_pointer_rtx so that cse and friends
2620 can go on believing that the argument pointer can never be zero. */
2621 fake_arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
2622 s = make_tree (unsigned_type_node, fake_arg_pointer_rtx);
2623 t = build (MODIFY_EXPR, unsigned_type_node, base, s);
2624 TREE_SIDE_EFFECTS (t) = 1;
2625 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2626
2627 s = build_int_2 ((current_function_args_info.ca_nregparms
2628 + current_function_args_info.ca_nstackparms) * 4, 0);
2629 t = build (MODIFY_EXPR, unsigned_type_node, num, s);
2630 TREE_SIDE_EFFECTS (t) = 1;
2631 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2632 }
2633
2634 /* Implement `va_arg'. */
2635
2636 rtx
i960_va_arg(valist,type)2637 i960_va_arg (valist, type)
2638 tree valist, type;
2639 {
2640 HOST_WIDE_INT siz, ali;
2641 tree base, num, pad, next, this, t1, t2, int48;
2642 rtx addr_rtx;
2643
2644 /* The array type always decays to a pointer before we get here, so we
2645 can't use ARRAY_REF. */
2646 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2647 num = build1 (INDIRECT_REF, unsigned_type_node,
2648 build (PLUS_EXPR, unsigned_type_node, valist,
2649 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2650
2651 /* Round up sizeof(type) to a word. */
2652 siz = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
2653
2654 /* Round up alignment to a word. */
2655 ali = TYPE_ALIGN (type);
2656 if (ali < BITS_PER_WORD)
2657 ali = BITS_PER_WORD;
2658 ali /= BITS_PER_UNIT;
2659
2660 /* Align NUM appropriate for the argument. */
2661 pad = fold (build (PLUS_EXPR, unsigned_type_node, num,
2662 build_int_2 (ali - 1, 0)));
2663 pad = fold (build (BIT_AND_EXPR, unsigned_type_node, pad,
2664 build_int_2 (-ali, -1)));
2665 pad = save_expr (pad);
2666
2667 /* Increment VPAD past this argument. */
2668 next = fold (build (PLUS_EXPR, unsigned_type_node, pad,
2669 build_int_2 (siz, 0)));
2670 next = save_expr (next);
2671
2672 /* Find the offset for the current argument. Mind peculiar overflow
2673 from registers to stack. */
2674 int48 = build_int_2 (48, 0);
2675 if (siz > 16)
2676 t2 = integer_one_node;
2677 else
2678 t2 = fold (build (GT_EXPR, integer_type_node, next, int48));
2679 t1 = fold (build (LE_EXPR, integer_type_node, num, int48));
2680 t1 = fold (build (TRUTH_AND_EXPR, integer_type_node, t1, t2));
2681 this = fold (build (COND_EXPR, unsigned_type_node, t1, int48, pad));
2682
2683 /* Find the address for the current argument. */
2684 t1 = fold (build (PLUS_EXPR, unsigned_type_node, base, this));
2685 t1 = build1 (NOP_EXPR, ptr_type_node, t1);
2686 addr_rtx = expand_expr (t1, NULL_RTX, Pmode, EXPAND_NORMAL);
2687
2688 /* Increment NUM. */
2689 t1 = build (MODIFY_EXPR, unsigned_type_node, num, next);
2690 TREE_SIDE_EFFECTS (t1) = 1;
2691 expand_expr (t1, const0_rtx, VOIDmode, EXPAND_NORMAL);
2692
2693 return addr_rtx;
2694 }
2695
2696 /* Calculate the final size of the reg parm stack space for the current
2697 function, based on how many bytes would be allocated on the stack. */
2698
2699 int
i960_final_reg_parm_stack_space(const_size,var_size)2700 i960_final_reg_parm_stack_space (const_size, var_size)
2701 int const_size;
2702 tree var_size;
2703 {
2704 if (var_size || const_size > 48)
2705 return 48;
2706 else
2707 return 0;
2708 }
2709
2710 /* Calculate the size of the reg parm stack space. This is a bit complicated
2711 on the i960. */
2712
2713 int
i960_reg_parm_stack_space(fndecl)2714 i960_reg_parm_stack_space (fndecl)
2715 tree fndecl;
2716 {
2717 /* In this case, we are called from emit_library_call, and we don't need
2718 to pretend we have more space for parameters than what's apparent. */
2719 if (fndecl == 0)
2720 return 0;
2721
2722 /* In this case, we are called from locate_and_pad_parms when we're
2723 not IN_REGS, so we have an arg block. */
2724 if (fndecl != current_function_decl)
2725 return 48;
2726
2727 /* Otherwise, we have an arg block if the current function has more than
2728 48 bytes of parameters. */
2729 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2730 return 48;
2731 else
2732 return 0;
2733 }
2734
2735 /* Return the register class of a scratch register needed to copy IN into
2736 or out of a register in CLASS in MODE. If it can be done directly,
2737 NO_REGS is returned. */
2738
2739 enum reg_class
secondary_reload_class(class,mode,in)2740 secondary_reload_class (class, mode, in)
2741 enum reg_class class;
2742 enum machine_mode mode;
2743 rtx in;
2744 {
2745 int regno = -1;
2746
2747 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2748 regno = true_regnum (in);
2749
2750 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2751 LOCAL_OR_GLOBAL_REGS into anything. */
2752 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2753 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2754 return NO_REGS;
2755
2756 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2757 if (class == FP_REGS
2758 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2759 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2760 return NO_REGS;
2761
2762 return LOCAL_OR_GLOBAL_REGS;
2763 }
2764
2765 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2766 function unit it executed on. */
2767
2768 /* ??? This would make more sense as an attribute. */
2769
2770 void
i960_scan_opcode(p)2771 i960_scan_opcode (p)
2772 const char *p;
2773 {
2774 switch (*p)
2775 {
2776 case 'a':
2777 case 'd':
2778 case 'e':
2779 case 'm':
2780 case 'n':
2781 case 'o':
2782 case 'r':
2783 /* Ret is not actually of type REG, but it won't matter, because no
2784 insn will ever follow it. */
2785 case 'u':
2786 case 'x':
2787 i960_last_insn_type = I_TYPE_REG;
2788 break;
2789
2790 case 'b':
2791 if (p[1] == 'x' || p[3] == 'x')
2792 i960_last_insn_type = I_TYPE_MEM;
2793 i960_last_insn_type = I_TYPE_CTRL;
2794 break;
2795
2796 case 'f':
2797 case 't':
2798 i960_last_insn_type = I_TYPE_CTRL;
2799 break;
2800
2801 case 'c':
2802 if (p[1] == 'a')
2803 {
2804 if (p[4] == 'x')
2805 i960_last_insn_type = I_TYPE_MEM;
2806 else
2807 i960_last_insn_type = I_TYPE_CTRL;
2808 }
2809 else if (p[1] == 'm')
2810 {
2811 if (p[3] == 'd')
2812 i960_last_insn_type = I_TYPE_REG;
2813 else if (p[4] == 'b' || p[4] == 'j')
2814 i960_last_insn_type = I_TYPE_CTRL;
2815 else
2816 i960_last_insn_type = I_TYPE_REG;
2817 }
2818 else
2819 i960_last_insn_type = I_TYPE_REG;
2820 break;
2821
2822 case 'l':
2823 i960_last_insn_type = I_TYPE_MEM;
2824 break;
2825
2826 case 's':
2827 if (p[1] == 't')
2828 i960_last_insn_type = I_TYPE_MEM;
2829 else
2830 i960_last_insn_type = I_TYPE_REG;
2831 break;
2832 }
2833 }
2834
2835 static void
i960_output_mi_thunk(file,thunk,delta,vcall_offset,function)2836 i960_output_mi_thunk (file, thunk, delta, vcall_offset, function)
2837 FILE *file;
2838 tree thunk ATTRIBUTE_UNUSED;
2839 HOST_WIDE_INT delta;
2840 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
2841 tree function;
2842 {
2843 int d = delta;
2844 if (d < 0 && d > -32)
2845 fprintf (file, "\tsubo %d,g0,g0\n", -d);
2846 else if (d > 0 && d < 32)
2847 fprintf (file, "\taddo %d,g0,g0\n", d);
2848 else
2849 {
2850 fprintf (file, "\tldconst %d,r5\n", d);
2851 fprintf (file, "\taddo r5,g0,g0\n");
2852 }
2853 fprintf (file, "\tbx ");
2854 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2855 fprintf (file, "\n");
2856 }
2857