1 /* $NetBSD: i915_getparam.c,v 1.4 2021/12/19 11:32:01 riastradh Exp $ */
2
3 /*
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include <sys/cdefs.h>
8 __KERNEL_RCSID(0, "$NetBSD: i915_getparam.c,v 1.4 2021/12/19 11:32:01 riastradh Exp $");
9
10 #include "gem/i915_gem_mman.h"
11 #include "gt/intel_engine_user.h"
12
13 #include "i915_drv.h"
14 #include "i915_perf.h"
15
i915_getparam_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)16 int i915_getparam_ioctl(struct drm_device *dev, void *data,
17 struct drm_file *file_priv)
18 {
19 struct drm_i915_private *i915 = to_i915(dev);
20 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
21 drm_i915_getparam_t *param = data;
22 int value;
23
24 switch (param->param) {
25 case I915_PARAM_IRQ_ACTIVE:
26 case I915_PARAM_ALLOW_BATCHBUFFER:
27 case I915_PARAM_LAST_DISPATCH:
28 case I915_PARAM_HAS_EXEC_CONSTANTS:
29 /* Reject all old ums/dri params. */
30 return -ENODEV;
31 case I915_PARAM_CHIPSET_ID:
32 value = i915->drm.pdev->device;
33 break;
34 case I915_PARAM_REVISION:
35 value = i915->drm.pdev->revision;
36 break;
37 case I915_PARAM_NUM_FENCES_AVAIL:
38 value = i915->ggtt.num_fences;
39 break;
40 case I915_PARAM_HAS_OVERLAY:
41 value = !!i915->overlay;
42 break;
43 case I915_PARAM_HAS_BSD:
44 value = !!intel_engine_lookup_user(i915,
45 I915_ENGINE_CLASS_VIDEO, 0);
46 break;
47 case I915_PARAM_HAS_BLT:
48 value = !!intel_engine_lookup_user(i915,
49 I915_ENGINE_CLASS_COPY, 0);
50 break;
51 case I915_PARAM_HAS_VEBOX:
52 value = !!intel_engine_lookup_user(i915,
53 I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
54 break;
55 case I915_PARAM_HAS_BSD2:
56 value = !!intel_engine_lookup_user(i915,
57 I915_ENGINE_CLASS_VIDEO, 1);
58 break;
59 case I915_PARAM_HAS_LLC:
60 value = HAS_LLC(i915);
61 break;
62 case I915_PARAM_HAS_WT:
63 value = HAS_WT(i915);
64 break;
65 case I915_PARAM_HAS_ALIASING_PPGTT:
66 value = INTEL_PPGTT(i915);
67 break;
68 case I915_PARAM_HAS_SEMAPHORES:
69 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
70 break;
71 case I915_PARAM_HAS_SECURE_BATCHES:
72 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
73 break;
74 case I915_PARAM_CMD_PARSER_VERSION:
75 value = i915_cmd_parser_get_version(i915);
76 break;
77 case I915_PARAM_SUBSLICE_TOTAL:
78 value = intel_sseu_subslice_total(sseu);
79 if (!value)
80 return -ENODEV;
81 break;
82 case I915_PARAM_EU_TOTAL:
83 value = sseu->eu_total;
84 if (!value)
85 return -ENODEV;
86 break;
87 case I915_PARAM_HAS_GPU_RESET:
88 value = i915_modparams.enable_hangcheck &&
89 intel_has_gpu_reset(&i915->gt);
90 if (value && intel_has_reset_engine(&i915->gt))
91 value = 2;
92 break;
93 case I915_PARAM_HAS_RESOURCE_STREAMER:
94 value = 0;
95 break;
96 case I915_PARAM_HAS_POOLED_EU:
97 value = HAS_POOLED_EU(i915);
98 break;
99 case I915_PARAM_MIN_EU_IN_POOL:
100 value = sseu->min_eu_in_pool;
101 break;
102 case I915_PARAM_HUC_STATUS:
103 value = intel_huc_check_status(&i915->gt.uc.huc);
104 if (value < 0)
105 return value;
106 break;
107 case I915_PARAM_MMAP_GTT_VERSION:
108 /* Though we've started our numbering from 1, and so class all
109 * earlier versions as 0, in effect their value is undefined as
110 * the ioctl will report EINVAL for the unknown param!
111 */
112 value = i915_gem_mmap_gtt_version();
113 break;
114 case I915_PARAM_HAS_SCHEDULER:
115 value = i915->caps.scheduler;
116 break;
117
118 case I915_PARAM_MMAP_VERSION:
119 /* Remember to bump this if the version changes! */
120 #ifdef __NetBSD__
121 i915->quirks |= QUIRK_NETBSD_VERSION_CALLED;
122 #endif
123 /* FALLTHROUGH */
124 case I915_PARAM_HAS_GEM:
125 case I915_PARAM_HAS_PAGEFLIPPING:
126 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
127 case I915_PARAM_HAS_RELAXED_FENCING:
128 case I915_PARAM_HAS_COHERENT_RINGS:
129 case I915_PARAM_HAS_RELAXED_DELTA:
130 case I915_PARAM_HAS_GEN7_SOL_RESET:
131 case I915_PARAM_HAS_WAIT_TIMEOUT:
132 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
133 case I915_PARAM_HAS_PINNED_BATCHES:
134 case I915_PARAM_HAS_EXEC_NO_RELOC:
135 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
136 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
137 case I915_PARAM_HAS_EXEC_SOFTPIN:
138 case I915_PARAM_HAS_EXEC_ASYNC:
139 case I915_PARAM_HAS_EXEC_FENCE:
140 case I915_PARAM_HAS_EXEC_CAPTURE:
141 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
142 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
143 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
144 /* For the time being all of these are always true;
145 * if some supported hardware does not have one of these
146 * features this value needs to be provided from
147 * INTEL_INFO(), a feature macro, or similar.
148 */
149 value = 1;
150 break;
151 case I915_PARAM_HAS_CONTEXT_ISOLATION:
152 value = intel_engines_has_context_isolation(i915);
153 break;
154 case I915_PARAM_SLICE_MASK:
155 value = sseu->slice_mask;
156 if (!value)
157 return -ENODEV;
158 break;
159 case I915_PARAM_SUBSLICE_MASK:
160 value = sseu->subslice_mask[0];
161 if (!value)
162 return -ENODEV;
163 break;
164 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
165 value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
166 break;
167 case I915_PARAM_MMAP_GTT_COHERENT:
168 value = INTEL_INFO(i915)->has_coherent_ggtt;
169 break;
170 case I915_PARAM_PERF_REVISION:
171 value = i915_perf_ioctl_version();
172 break;
173 default:
174 DRM_DEBUG("Unknown parameter %d\n", param->param);
175 return -EINVAL;
176 }
177
178 if (put_user(value, param->value))
179 return -EFAULT;
180
181 return 0;
182 }
183