1 /* $NetBSD: wdc_obio.c,v 1.63 2021/03/05 07:15:53 rin Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Onno van der Linden.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.63 2021/03/05 07:15:53 rin Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/device.h>
38 #include <sys/kmem.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <sys/bus.h>
43 #include <machine/autoconf.h>
44 #include <machine/pio.h>
45
46 #include <dev/ata/atareg.h>
47 #include <dev/ata/atavar.h>
48 #include <dev/ic/wdcvar.h>
49
50 #include <dev/ofw/openfirm.h>
51
52 #include <macppc/dev/dbdma.h>
53
54 #define WDC_REG_NPORTS 8
55 #define WDC_AUXREG_OFFSET 0x16
56 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */
57 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */
58
59 #define WDC_OPTIONS_DMA 0x01
60
61 /*
62 * XXX This code currently doesn't even try to allow 32-bit data port use.
63 */
64
65 struct wdc_obio_softc {
66 struct wdc_softc sc_wdcdev;
67 struct ata_channel *sc_chanptr;
68 struct ata_channel sc_channel;
69 struct wdc_regs sc_wdc_regs;
70 bus_space_handle_t sc_dmaregh;
71 dbdma_regmap_t *sc_dmareg;
72 dbdma_command_t *sc_dmacmd;
73 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */
74 void *sc_ih, *sc_dma;
75 };
76
77 static int wdc_obio_match(device_t, cfdata_t, void *);
78 static void wdc_obio_attach(device_t, device_t, void *);
79 static int wdc_obio_detach(device_t, int);
80 static int wdc_obio_dma_init(void *, int, int, void *, size_t, int);
81 static void wdc_obio_dma_start(void *, int, int);
82 static int wdc_obio_dma_finish(void *, int, int, int);
83
84 static void wdc_obio_select(struct ata_channel *, int);
85 static void adjust_timing(struct ata_channel *);
86 static void ata4_adjust_timing(struct ata_channel *);
87
88 CFATTACH_DECL_NEW(wdc_obio, sizeof(struct wdc_obio_softc),
89 wdc_obio_match, wdc_obio_attach, wdc_obio_detach, NULL);
90
91 static const char * const ata_names[] = {
92 "heathrow-ata",
93 "keylargo-ata",
94 "ohare-ata",
95 NULL
96 };
97
98 int
wdc_obio_match(device_t parent,cfdata_t match,void * aux)99 wdc_obio_match(device_t parent, cfdata_t match, void *aux)
100 {
101 struct confargs *ca = aux;
102
103 /* XXX should not use name */
104 if (strcmp(ca->ca_name, "ATA") == 0 ||
105 strcmp(ca->ca_name, "ata") == 0 ||
106 strcmp(ca->ca_name, "ata0") == 0 ||
107 strcmp(ca->ca_name, "ide") == 0)
108 return 1;
109
110 if (of_compatible(ca->ca_node, ata_names))
111 return 1;
112
113 return 0;
114 }
115
116 void
wdc_obio_attach(device_t parent,device_t self,void * aux)117 wdc_obio_attach(device_t parent, device_t self, void *aux)
118 {
119 struct wdc_obio_softc *sc = device_private(self);
120 struct wdc_regs *wdr;
121 struct confargs *ca = aux;
122 struct ata_channel *chp = &sc->sc_channel;
123 int intr, i, type = IST_EDGE;
124 int use_dma = 0;
125 char path[80];
126
127 sc->sc_wdcdev.sc_atac.atac_dev = self;
128 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
129 WDC_OPTIONS_DMA) {
130 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1)
131 use_dma = 1; /* XXX Don't work yet. */
132 }
133
134 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) {
135 intr = ca->ca_intr[0];
136 aprint_normal(" irq %d", intr);
137 if (ca->ca_nintr > 8) {
138 type = ca->ca_intr[1] ? IST_LEVEL : IST_EDGE;
139 }
140 aprint_normal(", %s triggered", (type == IST_EDGE) ? "edge" : "level");
141 } else if (ca->ca_nintr == -1) {
142 intr = WDC_DEFAULT_PIO_IRQ;
143 aprint_normal(" irq property not found; using %d", intr);
144 } else {
145 aprint_error(": couldn't get irq property\n");
146 return;
147 }
148
149 if (use_dma)
150 aprint_normal(": DMA transfer");
151
152 aprint_normal("\n");
153
154 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
155
156 wdr->cmd_iot = wdr->ctl_iot = ca->ca_tag;
157
158 if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[0],
159 WDC_REG_NPORTS << 4, 0, &wdr->cmd_baseioh) ||
160 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
161 WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) {
162 aprint_error_dev(self, "couldn't map registers\n");
163 return;
164 }
165
166 for (i = 0; i < WDC_NREG; i++) {
167 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4,
168 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
169 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
170 WDC_REG_NPORTS << 4);
171 aprint_error_dev(self,
172 "couldn't subregion registers\n");
173 return;
174 }
175 }
176 #if 0
177 wdr->data32iot = wdr->cmd_iot;
178 wdr->data32ioh = wdr->cmd_ioh;
179 #endif
180
181 sc->sc_ih = intr_establish_xname(intr, type, IPL_BIO, wdcintr, chp,
182 device_xname(self));
183
184 if (use_dma) {
185 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20,
186 &sc->sc_dma);
187 /*
188 * XXX
189 * we don't use ca->ca_reg[3] for size here because at least
190 * on the PB3400c it says 0x200 for both IDE channels ( the
191 * one on the mainboard and the other on the mediabay ) but
192 * their start addresses are only 0x100 apart. Since those
193 * DMA registers are always 0x100 or less we don't really
194 * have to care though
195 */
196 if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[2],
197 0x100, BUS_SPACE_MAP_LINEAR, &sc->sc_dmaregh)) {
198
199 aprint_error_dev(self,
200 "unable to map DMA registers (%08x)\n",
201 ca->ca_reg[2]);
202 /* should unmap stuff here */
203 return;
204 }
205 sc->sc_dmareg = bus_space_vaddr(wdr->cmd_iot, sc->sc_dmaregh);
206
207 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
208 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
209 if (strcmp(ca->ca_name, "ata-4") == 0) {
210 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
211 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
212 sc->sc_wdcdev.sc_atac.atac_set_modes =
213 ata4_adjust_timing;
214 } else {
215 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
216 }
217 #ifdef notyet
218 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */
219 if (ohare) {
220 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3;
221 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1;
222 }
223 #endif
224 } else {
225 /* all non-DMA controllers can use adjust_timing */
226 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
227 sc->sc_dmacmd = NULL;
228 }
229
230 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
231 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 /*| ATAC_CAP_DATA32*/;
232 sc->sc_chanptr = chp;
233 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr;
234 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
235 sc->sc_wdcdev.wdc_maxdrives = 2;
236 sc->sc_wdcdev.dma_arg = sc;
237 sc->sc_wdcdev.dma_init = wdc_obio_dma_init;
238 sc->sc_wdcdev.dma_start = wdc_obio_dma_start;
239 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish;
240
241 chp->ch_channel = 0;
242 chp->ch_atac = &sc->sc_wdcdev.sc_atac;
243
244 wdc_init_shadow_regs(wdr);
245
246 #define OHARE_FEATURE_REG 0xf3000038
247
248 /* XXX Enable wdc1 by feature reg. */
249 memset(path, 0, sizeof(path));
250 OF_package_to_path(ca->ca_node, path, sizeof(path));
251 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) {
252 u_int x;
253
254 x = in32rb(OHARE_FEATURE_REG);
255 x |= 8;
256 out32rb(OHARE_FEATURE_REG, x);
257 }
258
259 wdcattach(chp);
260 }
261
262 /* Multiword DMA transfer timings */
263 struct ide_timings {
264 int cycle; /* minimum cycle time [ns] */
265 int active; /* minimum command active time [ns] */
266 };
267 static const struct ide_timings pio_timing[5] = {
268 { 600, 180 }, /* Mode 0 */
269 { 390, 150 }, /* 1 */
270 { 240, 105 }, /* 2 */
271 { 180, 90 }, /* 3 */
272 { 120, 75 } /* 4 */
273 };
274 static const struct ide_timings dma_timing[3] = {
275 { 480, 240 }, /* Mode 0 */
276 { 165, 90 }, /* Mode 1 */
277 { 120, 75 } /* Mode 2 */
278 };
279
280 static const struct ide_timings udma_timing[5] = {
281 { 120, 180 }, /* Mode 0 */
282 { 90, 150 }, /* Mode 1 */
283 { 60, 120 }, /* Mode 2 */
284 { 45, 90 }, /* Mode 3 */
285 { 30, 90 } /* Mode 4 */
286 };
287
288 #define TIME_TO_TICK(time) howmany((time), 30)
289 #define PIO_REC_OFFSET 4
290 #define PIO_REC_MIN 1
291 #define PIO_ACT_MIN 1
292 #define DMA_REC_OFFSET 1
293 #define DMA_REC_MIN 1
294 #define DMA_ACT_MIN 1
295
296 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */
297
298 #define CONFIG_REG (0x200) /* IDE access timing register */
299
300 void
wdc_obio_select(struct ata_channel * chp,int drive)301 wdc_obio_select(struct ata_channel *chp, int drive)
302 {
303 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
304 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
305
306 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh,
307 CONFIG_REG, sc->sc_dmaconf[drive]);
308 }
309
310 void
adjust_timing(struct ata_channel * chp)311 adjust_timing(struct ata_channel *chp)
312 {
313 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
314 int drive;
315 int min_cycle = 0, min_active = 0;
316 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
317
318 for (drive = 0; drive < 2; drive++) {
319 u_int conf = 0;
320 struct ata_drive_datas *drvp;
321
322 drvp = &chp->ch_drive[drive];
323 /* set up pio mode timings */
324 if (drvp->drive_type != ATA_DRIVET_NONE) {
325 int piomode = drvp->PIO_mode;
326 min_cycle = pio_timing[piomode].cycle;
327 min_active = pio_timing[piomode].active;
328
329 cycle_tick = TIME_TO_TICK(min_cycle);
330 act_tick = TIME_TO_TICK(min_active);
331 if (act_tick < PIO_ACT_MIN)
332 act_tick = PIO_ACT_MIN;
333 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
334 if (inact_tick < PIO_REC_MIN)
335 inact_tick = PIO_REC_MIN;
336 /* mask: 0x000007ff */
337 conf |= (inact_tick << 5) | act_tick;
338 }
339 /* Set up DMA mode timings */
340 if (drvp->drive_flags & ATA_DRIVE_DMA) {
341 int dmamode = drvp->DMA_mode;
342 min_cycle = dma_timing[dmamode].cycle;
343 min_active = dma_timing[dmamode].active;
344 cycle_tick = TIME_TO_TICK(min_cycle);
345 act_tick = TIME_TO_TICK(min_active);
346 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
347 if (inact_tick < DMA_REC_MIN)
348 inact_tick = DMA_REC_MIN;
349 half_tick = 0; /* XXX */
350 /* mask: 0xfffff800 */
351 conf |=
352 (half_tick << 21) |
353 (inact_tick << 16) | (act_tick << 11);
354 }
355 #ifdef DEBUG
356 if (conf) {
357 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n",
358 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick);
359 }
360 #endif
361 sc->sc_dmaconf[drive] = conf;
362 }
363 sc->sc_wdcdev.select = 0;
364 if (sc->sc_dmaconf[0]) {
365 wdc_obio_select(chp,0);
366 if (sc->sc_dmaconf[1] &&
367 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) {
368 sc->sc_wdcdev.select = wdc_obio_select;
369 }
370 } else if (sc->sc_dmaconf[1]) {
371 wdc_obio_select(chp,1);
372 }
373 }
374
375 void
ata4_adjust_timing(struct ata_channel * chp)376 ata4_adjust_timing(struct ata_channel *chp)
377 {
378 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
379 int drive;
380 int min_cycle = 0, min_active = 0;
381 int cycle_tick = 0, act_tick = 0, inact_tick = 0;
382
383 for (drive = 0; drive < 2; drive++) {
384 u_int conf = 0;
385 struct ata_drive_datas *drvp;
386
387 drvp = &chp->ch_drive[drive];
388 /* set up pio mode timings */
389
390 if (drvp->drive_type != ATA_DRIVET_NONE) {
391 int piomode = drvp->PIO_mode;
392 min_cycle = pio_timing[piomode].cycle;
393 min_active = pio_timing[piomode].active;
394
395 cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
396 act_tick = ATA4_TIME_TO_TICK(min_active);
397 inact_tick = cycle_tick - act_tick;
398 /* mask: 0x000003ff */
399 conf |= (inact_tick << 5) | act_tick;
400 }
401 /* set up dma mode timings */
402 if (drvp->drive_flags & ATA_DRIVE_DMA) {
403 int dmamode = drvp->DMA_mode;
404 min_cycle = dma_timing[dmamode].cycle;
405 min_active = dma_timing[dmamode].active;
406 cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
407 act_tick = ATA4_TIME_TO_TICK(min_active);
408 inact_tick = cycle_tick - act_tick;
409 /* mask: 0x001ffc00 */
410 conf |= (act_tick << 10) | (inact_tick << 15);
411 }
412 /* set up udma mode timings */
413 if (drvp->drive_flags & ATA_DRIVE_UDMA) {
414 int udmamode = drvp->UDMA_mode;
415 min_cycle = udma_timing[udmamode].cycle;
416 min_active = udma_timing[udmamode].active;
417 act_tick = ATA4_TIME_TO_TICK(min_active);
418 cycle_tick = ATA4_TIME_TO_TICK(min_cycle);
419 /* mask: 0x1ff00000 */
420 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000;
421 }
422 #ifdef DEBUG
423 if (conf) {
424 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n",
425 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick);
426 }
427 #endif
428 sc->sc_dmaconf[drive] = conf;
429 }
430 sc->sc_wdcdev.select = 0;
431 if (sc->sc_dmaconf[0]) {
432 wdc_obio_select(chp,0);
433 if (sc->sc_dmaconf[1] &&
434 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) {
435 sc->sc_wdcdev.select = wdc_obio_select;
436 }
437 } else if (sc->sc_dmaconf[1]) {
438 wdc_obio_select(chp,1);
439 }
440 }
441
442 int
wdc_obio_detach(device_t self,int flags)443 wdc_obio_detach(device_t self, int flags)
444 {
445 struct wdc_obio_softc *sc = device_private(self);
446 int error;
447
448 if ((error = wdcdetach(self, flags)) != 0)
449 return error;
450
451 intr_disestablish(sc->sc_ih);
452
453 /* Unmap our i/o space. */
454 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
455 sc->sc_wdcdev.regs->cmd_baseioh, WDC_REG_NPORTS << 4);
456
457 /* Unmap DMA registers. */
458 if (sc->sc_dmacmd != NULL) {
459
460 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
461 sc->sc_dmaregh, 0x100);
462 dbdma_free(sc->sc_dma, sizeof(dbdma_command_t) * 20);
463 }
464 return 0;
465 }
466
467 int
wdc_obio_dma_init(void * v,int channel,int drive,void * databuf,size_t datalen,int flags)468 wdc_obio_dma_init(void *v, int channel, int drive, void *databuf,
469 size_t datalen, int flags)
470 {
471 struct wdc_obio_softc *sc = v;
472 vaddr_t va = (vaddr_t)databuf;
473 dbdma_command_t *cmdp;
474 u_int cmd, offset;
475 int read = flags & WDC_DMA_READ;
476
477 cmdp = sc->sc_dmacmd;
478 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
479
480 offset = va & PGOFSET;
481
482 /* if va is not page-aligned, setup the first page */
483 if (offset != 0) {
484 int rest = PAGE_SIZE - offset; /* the rest of the page */
485
486 if (datalen > rest) { /* if continues to next page */
487 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va),
488 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
489 DBDMA_BRANCH_NEVER);
490 datalen -= rest;
491 va += rest;
492 cmdp++;
493 }
494 }
495
496 /* now va is page-aligned */
497 while (datalen > PAGE_SIZE) {
498 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va),
499 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
500 datalen -= PAGE_SIZE;
501 va += PAGE_SIZE;
502 cmdp++;
503 }
504
505 /* the last page (datalen <= PAGE_SIZE here) */
506 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
507 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va),
508 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
509 cmdp++;
510
511 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
512 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
513
514 return 0;
515 }
516
517 void
wdc_obio_dma_start(void * v,int channel,int drive)518 wdc_obio_dma_start(void *v, int channel, int drive)
519 {
520 struct wdc_obio_softc *sc = v;
521
522 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd);
523 }
524
525 int
wdc_obio_dma_finish(void * v,int channel,int drive,int read)526 wdc_obio_dma_finish(void *v, int channel, int drive, int read)
527 {
528 struct wdc_obio_softc *sc = v;
529
530 dbdma_stop(sc->sc_dmareg);
531 return 0;
532 }
533