1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the class that prints out the LLVM IR and machine
10 // functions using the MIR serialization format.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/CodeGen/MIRPrinter.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MIRYamlMapping.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/CodeGen/TargetFrameLowering.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCContext.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75
76 using namespace llvm;
77
78 static cl::opt<bool> SimplifyMIR(
79 "simplify-mir", cl::Hidden,
80 cl::desc("Leave out unnecessary information when printing MIR"));
81
82 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true),
83 cl::desc("Print MIR debug-locations"));
84
85 namespace {
86
87 /// This structure describes how to print out stack object references.
88 struct FrameIndexOperand {
89 std::string Name;
90 unsigned ID;
91 bool IsFixed;
92
FrameIndexOperand__anonc138dacb0111::FrameIndexOperand93 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
94 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
95
96 /// Return an ordinary stack object reference.
create__anonc138dacb0111::FrameIndexOperand97 static FrameIndexOperand create(StringRef Name, unsigned ID) {
98 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
99 }
100
101 /// Return a fixed stack object reference.
createFixed__anonc138dacb0111::FrameIndexOperand102 static FrameIndexOperand createFixed(unsigned ID) {
103 return FrameIndexOperand("", ID, /*IsFixed=*/true);
104 }
105 };
106
107 } // end anonymous namespace
108
109 namespace llvm {
110
111 /// This class prints out the machine functions using the MIR serialization
112 /// format.
113 class MIRPrinter {
114 raw_ostream &OS;
115 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
116 /// Maps from stack object indices to operand indices which will be used when
117 /// printing frame index machine operands.
118 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
119
120 public:
MIRPrinter(raw_ostream & OS)121 MIRPrinter(raw_ostream &OS) : OS(OS) {}
122
123 void print(const MachineFunction &MF);
124
125 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
126 const TargetRegisterInfo *TRI);
127 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
128 const MachineFrameInfo &MFI);
129 void convert(yaml::MachineFunction &MF,
130 const MachineConstantPool &ConstantPool);
131 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
132 const MachineJumpTableInfo &JTI);
133 void convertStackObjects(yaml::MachineFunction &YMF,
134 const MachineFunction &MF, ModuleSlotTracker &MST);
135 void convertCallSiteObjects(yaml::MachineFunction &YMF,
136 const MachineFunction &MF,
137 ModuleSlotTracker &MST);
138
139 private:
140 void initRegisterMaskIds(const MachineFunction &MF);
141 };
142
143 /// This class prints out the machine instructions using the MIR serialization
144 /// format.
145 class MIPrinter {
146 raw_ostream &OS;
147 ModuleSlotTracker &MST;
148 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
149 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
150 /// Synchronization scope names registered with LLVMContext.
151 SmallVector<StringRef, 8> SSNs;
152
153 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
154 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
155
156 public:
MIPrinter(raw_ostream & OS,ModuleSlotTracker & MST,const DenseMap<const uint32_t *,unsigned> & RegisterMaskIds,const DenseMap<int,FrameIndexOperand> & StackObjectOperandMapping)157 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
158 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
159 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
160 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
161 StackObjectOperandMapping(StackObjectOperandMapping) {}
162
163 void print(const MachineBasicBlock &MBB);
164
165 void print(const MachineInstr &MI);
166 void printStackObjectReference(int FrameIndex);
167 void print(const MachineInstr &MI, unsigned OpIdx,
168 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
169 bool ShouldPrintRegisterTies, LLT TypeToPrint,
170 bool PrintDef = true);
171 };
172
173 } // end namespace llvm
174
175 namespace llvm {
176 namespace yaml {
177
178 /// This struct serializes the LLVM IR module.
179 template <> struct BlockScalarTraits<Module> {
outputllvm::yaml::BlockScalarTraits180 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
181 Mod.print(OS, nullptr);
182 }
183
inputllvm::yaml::BlockScalarTraits184 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
185 llvm_unreachable("LLVM Module is supposed to be parsed separately");
186 return "";
187 }
188 };
189
190 } // end namespace yaml
191 } // end namespace llvm
192
printRegMIR(unsigned Reg,yaml::StringValue & Dest,const TargetRegisterInfo * TRI)193 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
194 const TargetRegisterInfo *TRI) {
195 raw_string_ostream OS(Dest.Value);
196 OS << printReg(Reg, TRI);
197 }
198
print(const MachineFunction & MF)199 void MIRPrinter::print(const MachineFunction &MF) {
200 initRegisterMaskIds(MF);
201
202 yaml::MachineFunction YamlMF;
203 YamlMF.Name = MF.getName();
204 YamlMF.Alignment = MF.getAlignment();
205 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
206 YamlMF.HasWinCFI = MF.hasWinCFI();
207
208 YamlMF.Legalized = MF.getProperties().hasProperty(
209 MachineFunctionProperties::Property::Legalized);
210 YamlMF.RegBankSelected = MF.getProperties().hasProperty(
211 MachineFunctionProperties::Property::RegBankSelected);
212 YamlMF.Selected = MF.getProperties().hasProperty(
213 MachineFunctionProperties::Property::Selected);
214 YamlMF.FailedISel = MF.getProperties().hasProperty(
215 MachineFunctionProperties::Property::FailedISel);
216
217 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
218 ModuleSlotTracker MST(MF.getFunction().getParent());
219 MST.incorporateFunction(MF.getFunction());
220 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
221 convertStackObjects(YamlMF, MF, MST);
222 convertCallSiteObjects(YamlMF, MF, MST);
223 for (auto &Sub : MF.DebugValueSubstitutions)
224 YamlMF.DebugValueSubstitutions.push_back({Sub.first.first, Sub.first.second,
225 Sub.second.first,
226 Sub.second.second});
227 if (const auto *ConstantPool = MF.getConstantPool())
228 convert(YamlMF, *ConstantPool);
229 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
230 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
231
232 const TargetMachine &TM = MF.getTarget();
233 YamlMF.MachineFuncInfo =
234 std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
235
236 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
237 bool IsNewlineNeeded = false;
238 for (const auto &MBB : MF) {
239 if (IsNewlineNeeded)
240 StrOS << "\n";
241 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
242 .print(MBB);
243 IsNewlineNeeded = true;
244 }
245 StrOS.flush();
246 yaml::Output Out(OS);
247 if (!SimplifyMIR)
248 Out.setWriteDefaultValues(true);
249 Out << YamlMF;
250 }
251
printCustomRegMask(const uint32_t * RegMask,raw_ostream & OS,const TargetRegisterInfo * TRI)252 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
253 const TargetRegisterInfo *TRI) {
254 assert(RegMask && "Can't print an empty register mask");
255 OS << StringRef("CustomRegMask(");
256
257 bool IsRegInRegMaskFound = false;
258 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
259 // Check whether the register is asserted in regmask.
260 if (RegMask[I / 32] & (1u << (I % 32))) {
261 if (IsRegInRegMaskFound)
262 OS << ',';
263 OS << printReg(I, TRI);
264 IsRegInRegMaskFound = true;
265 }
266 }
267
268 OS << ')';
269 }
270
printRegClassOrBank(unsigned Reg,yaml::StringValue & Dest,const MachineRegisterInfo & RegInfo,const TargetRegisterInfo * TRI)271 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
272 const MachineRegisterInfo &RegInfo,
273 const TargetRegisterInfo *TRI) {
274 raw_string_ostream OS(Dest.Value);
275 OS << printRegClassOrBank(Reg, RegInfo, TRI);
276 }
277
278 template <typename T>
279 static void
printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo & DebugVar,T & Object,ModuleSlotTracker & MST)280 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
281 T &Object, ModuleSlotTracker &MST) {
282 std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
283 &Object.DebugExpr.Value,
284 &Object.DebugLoc.Value}};
285 std::array<const Metadata *, 3> Metas{{DebugVar.Var,
286 DebugVar.Expr,
287 DebugVar.Loc}};
288 for (unsigned i = 0; i < 3; ++i) {
289 raw_string_ostream StrOS(*Outputs[i]);
290 Metas[i]->printAsOperand(StrOS, MST);
291 }
292 }
293
convert(yaml::MachineFunction & MF,const MachineRegisterInfo & RegInfo,const TargetRegisterInfo * TRI)294 void MIRPrinter::convert(yaml::MachineFunction &MF,
295 const MachineRegisterInfo &RegInfo,
296 const TargetRegisterInfo *TRI) {
297 MF.TracksRegLiveness = RegInfo.tracksLiveness();
298
299 // Print the virtual register definitions.
300 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
301 unsigned Reg = Register::index2VirtReg(I);
302 yaml::VirtualRegisterDefinition VReg;
303 VReg.ID = I;
304 if (RegInfo.getVRegName(Reg) != "")
305 continue;
306 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
307 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
308 if (PreferredReg)
309 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
310 MF.VirtualRegisters.push_back(VReg);
311 }
312
313 // Print the live ins.
314 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
315 yaml::MachineFunctionLiveIn LiveIn;
316 printRegMIR(LI.first, LiveIn.Register, TRI);
317 if (LI.second)
318 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
319 MF.LiveIns.push_back(LiveIn);
320 }
321
322 // Prints the callee saved registers.
323 if (RegInfo.isUpdatedCSRsInitialized()) {
324 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
325 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
326 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
327 yaml::FlowStringValue Reg;
328 printRegMIR(*I, Reg, TRI);
329 CalleeSavedRegisters.push_back(Reg);
330 }
331 MF.CalleeSavedRegisters = CalleeSavedRegisters;
332 }
333 }
334
convert(ModuleSlotTracker & MST,yaml::MachineFrameInfo & YamlMFI,const MachineFrameInfo & MFI)335 void MIRPrinter::convert(ModuleSlotTracker &MST,
336 yaml::MachineFrameInfo &YamlMFI,
337 const MachineFrameInfo &MFI) {
338 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
339 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
340 YamlMFI.HasStackMap = MFI.hasStackMap();
341 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
342 YamlMFI.StackSize = MFI.getStackSize();
343 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
344 YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
345 YamlMFI.AdjustsStack = MFI.adjustsStack();
346 YamlMFI.HasCalls = MFI.hasCalls();
347 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
348 ? MFI.getMaxCallFrameSize() : ~0u;
349 YamlMFI.CVBytesOfCalleeSavedRegisters =
350 MFI.getCVBytesOfCalleeSavedRegisters();
351 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
352 YamlMFI.HasVAStart = MFI.hasVAStart();
353 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
354 YamlMFI.HasTailCall = MFI.hasTailCall();
355 YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
356 if (MFI.getSavePoint()) {
357 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
358 StrOS << printMBBReference(*MFI.getSavePoint());
359 }
360 if (MFI.getRestorePoint()) {
361 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
362 StrOS << printMBBReference(*MFI.getRestorePoint());
363 }
364 }
365
convertStackObjects(yaml::MachineFunction & YMF,const MachineFunction & MF,ModuleSlotTracker & MST)366 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
367 const MachineFunction &MF,
368 ModuleSlotTracker &MST) {
369 const MachineFrameInfo &MFI = MF.getFrameInfo();
370 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
371
372 // Process fixed stack objects.
373 assert(YMF.FixedStackObjects.empty());
374 SmallVector<int, 32> FixedStackObjectsIdx;
375 const int BeginIdx = MFI.getObjectIndexBegin();
376 if (BeginIdx < 0)
377 FixedStackObjectsIdx.reserve(-BeginIdx);
378
379 unsigned ID = 0;
380 for (int I = BeginIdx; I < 0; ++I, ++ID) {
381 FixedStackObjectsIdx.push_back(-1); // Fill index for possible dead.
382 if (MFI.isDeadObjectIndex(I))
383 continue;
384
385 yaml::FixedMachineStackObject YamlObject;
386 YamlObject.ID = ID;
387 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
388 ? yaml::FixedMachineStackObject::SpillSlot
389 : yaml::FixedMachineStackObject::DefaultType;
390 YamlObject.Offset = MFI.getObjectOffset(I);
391 YamlObject.Size = MFI.getObjectSize(I);
392 YamlObject.Alignment = MFI.getObjectAlign(I);
393 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
394 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
395 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
396 // Save the ID' position in FixedStackObjects storage vector.
397 FixedStackObjectsIdx[ID] = YMF.FixedStackObjects.size();
398 YMF.FixedStackObjects.push_back(YamlObject);
399 StackObjectOperandMapping.insert(
400 std::make_pair(I, FrameIndexOperand::createFixed(ID)));
401 }
402
403 // Process ordinary stack objects.
404 assert(YMF.StackObjects.empty());
405 SmallVector<unsigned, 32> StackObjectsIdx;
406 const int EndIdx = MFI.getObjectIndexEnd();
407 if (EndIdx > 0)
408 StackObjectsIdx.reserve(EndIdx);
409 ID = 0;
410 for (int I = 0; I < EndIdx; ++I, ++ID) {
411 StackObjectsIdx.push_back(-1); // Fill index for possible dead.
412 if (MFI.isDeadObjectIndex(I))
413 continue;
414
415 yaml::MachineStackObject YamlObject;
416 YamlObject.ID = ID;
417 if (const auto *Alloca = MFI.getObjectAllocation(I))
418 YamlObject.Name.Value = std::string(
419 Alloca->hasName() ? Alloca->getName() : "");
420 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
421 ? yaml::MachineStackObject::SpillSlot
422 : MFI.isVariableSizedObjectIndex(I)
423 ? yaml::MachineStackObject::VariableSized
424 : yaml::MachineStackObject::DefaultType;
425 YamlObject.Offset = MFI.getObjectOffset(I);
426 YamlObject.Size = MFI.getObjectSize(I);
427 YamlObject.Alignment = MFI.getObjectAlign(I);
428 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
429
430 // Save the ID' position in StackObjects storage vector.
431 StackObjectsIdx[ID] = YMF.StackObjects.size();
432 YMF.StackObjects.push_back(YamlObject);
433 StackObjectOperandMapping.insert(std::make_pair(
434 I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
435 }
436
437 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
438 const int FrameIdx = CSInfo.getFrameIdx();
439 if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx))
440 continue;
441
442 yaml::StringValue Reg;
443 printRegMIR(CSInfo.getReg(), Reg, TRI);
444 if (!CSInfo.isSpilledToReg()) {
445 assert(FrameIdx >= MFI.getObjectIndexBegin() &&
446 FrameIdx < MFI.getObjectIndexEnd() &&
447 "Invalid stack object index");
448 if (FrameIdx < 0) { // Negative index means fixed objects.
449 auto &Object =
450 YMF.FixedStackObjects
451 [FixedStackObjectsIdx[FrameIdx + MFI.getNumFixedObjects()]];
452 Object.CalleeSavedRegister = Reg;
453 Object.CalleeSavedRestored = CSInfo.isRestored();
454 } else {
455 auto &Object = YMF.StackObjects[StackObjectsIdx[FrameIdx]];
456 Object.CalleeSavedRegister = Reg;
457 Object.CalleeSavedRestored = CSInfo.isRestored();
458 }
459 }
460 }
461 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
462 auto LocalObject = MFI.getLocalFrameObjectMap(I);
463 assert(LocalObject.first >= 0 && "Expected a locally mapped stack object");
464 YMF.StackObjects[StackObjectsIdx[LocalObject.first]].LocalOffset =
465 LocalObject.second;
466 }
467
468 // Print the stack object references in the frame information class after
469 // converting the stack objects.
470 if (MFI.hasStackProtectorIndex()) {
471 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
472 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
473 .printStackObjectReference(MFI.getStackProtectorIndex());
474 }
475
476 // Print the debug variable information.
477 for (const MachineFunction::VariableDbgInfo &DebugVar :
478 MF.getVariableDbgInfo()) {
479 assert(DebugVar.Slot >= MFI.getObjectIndexBegin() &&
480 DebugVar.Slot < MFI.getObjectIndexEnd() &&
481 "Invalid stack object index");
482 if (DebugVar.Slot < 0) { // Negative index means fixed objects.
483 auto &Object =
484 YMF.FixedStackObjects[FixedStackObjectsIdx[DebugVar.Slot +
485 MFI.getNumFixedObjects()]];
486 printStackObjectDbgInfo(DebugVar, Object, MST);
487 } else {
488 auto &Object = YMF.StackObjects[StackObjectsIdx[DebugVar.Slot]];
489 printStackObjectDbgInfo(DebugVar, Object, MST);
490 }
491 }
492 }
493
convertCallSiteObjects(yaml::MachineFunction & YMF,const MachineFunction & MF,ModuleSlotTracker & MST)494 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
495 const MachineFunction &MF,
496 ModuleSlotTracker &MST) {
497 const auto *TRI = MF.getSubtarget().getRegisterInfo();
498 for (auto CSInfo : MF.getCallSitesInfo()) {
499 yaml::CallSiteInfo YmlCS;
500 yaml::CallSiteInfo::MachineInstrLoc CallLocation;
501
502 // Prepare instruction position.
503 MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
504 CallLocation.BlockNum = CallI->getParent()->getNumber();
505 // Get call instruction offset from the beginning of block.
506 CallLocation.Offset =
507 std::distance(CallI->getParent()->instr_begin(), CallI);
508 YmlCS.CallLocation = CallLocation;
509 // Construct call arguments and theirs forwarding register info.
510 for (auto ArgReg : CSInfo.second) {
511 yaml::CallSiteInfo::ArgRegPair YmlArgReg;
512 YmlArgReg.ArgNo = ArgReg.ArgNo;
513 printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
514 YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
515 }
516 YMF.CallSitesInfo.push_back(YmlCS);
517 }
518
519 // Sort call info by position of call instructions.
520 llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
521 [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
522 if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
523 return A.CallLocation.Offset < B.CallLocation.Offset;
524 return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
525 });
526 }
527
convert(yaml::MachineFunction & MF,const MachineConstantPool & ConstantPool)528 void MIRPrinter::convert(yaml::MachineFunction &MF,
529 const MachineConstantPool &ConstantPool) {
530 unsigned ID = 0;
531 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
532 std::string Str;
533 raw_string_ostream StrOS(Str);
534 if (Constant.isMachineConstantPoolEntry()) {
535 Constant.Val.MachineCPVal->print(StrOS);
536 } else {
537 Constant.Val.ConstVal->printAsOperand(StrOS);
538 }
539
540 yaml::MachineConstantPoolValue YamlConstant;
541 YamlConstant.ID = ID++;
542 YamlConstant.Value = StrOS.str();
543 YamlConstant.Alignment = Constant.getAlign();
544 YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
545
546 MF.Constants.push_back(YamlConstant);
547 }
548 }
549
convert(ModuleSlotTracker & MST,yaml::MachineJumpTable & YamlJTI,const MachineJumpTableInfo & JTI)550 void MIRPrinter::convert(ModuleSlotTracker &MST,
551 yaml::MachineJumpTable &YamlJTI,
552 const MachineJumpTableInfo &JTI) {
553 YamlJTI.Kind = JTI.getEntryKind();
554 unsigned ID = 0;
555 for (const auto &Table : JTI.getJumpTables()) {
556 std::string Str;
557 yaml::MachineJumpTable::Entry Entry;
558 Entry.ID = ID++;
559 for (const auto *MBB : Table.MBBs) {
560 raw_string_ostream StrOS(Str);
561 StrOS << printMBBReference(*MBB);
562 Entry.Blocks.push_back(StrOS.str());
563 Str.clear();
564 }
565 YamlJTI.Entries.push_back(Entry);
566 }
567 }
568
initRegisterMaskIds(const MachineFunction & MF)569 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
570 const auto *TRI = MF.getSubtarget().getRegisterInfo();
571 unsigned I = 0;
572 for (const uint32_t *Mask : TRI->getRegMasks())
573 RegisterMaskIds.insert(std::make_pair(Mask, I++));
574 }
575
guessSuccessors(const MachineBasicBlock & MBB,SmallVectorImpl<MachineBasicBlock * > & Result,bool & IsFallthrough)576 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
577 SmallVectorImpl<MachineBasicBlock*> &Result,
578 bool &IsFallthrough) {
579 SmallPtrSet<MachineBasicBlock*,8> Seen;
580
581 for (const MachineInstr &MI : MBB) {
582 if (MI.isPHI())
583 continue;
584 for (const MachineOperand &MO : MI.operands()) {
585 if (!MO.isMBB())
586 continue;
587 MachineBasicBlock *Succ = MO.getMBB();
588 auto RP = Seen.insert(Succ);
589 if (RP.second)
590 Result.push_back(Succ);
591 }
592 }
593 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
594 IsFallthrough = I == MBB.end() || !I->isBarrier();
595 }
596
597 bool
canPredictBranchProbabilities(const MachineBasicBlock & MBB) const598 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
599 if (MBB.succ_size() <= 1)
600 return true;
601 if (!MBB.hasSuccessorProbabilities())
602 return true;
603
604 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
605 MBB.Probs.end());
606 BranchProbability::normalizeProbabilities(Normalized.begin(),
607 Normalized.end());
608 SmallVector<BranchProbability,8> Equal(Normalized.size());
609 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
610
611 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
612 }
613
canPredictSuccessors(const MachineBasicBlock & MBB) const614 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
615 SmallVector<MachineBasicBlock*,8> GuessedSuccs;
616 bool GuessedFallthrough;
617 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
618 if (GuessedFallthrough) {
619 const MachineFunction &MF = *MBB.getParent();
620 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
621 if (NextI != MF.end()) {
622 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
623 if (!is_contained(GuessedSuccs, Next))
624 GuessedSuccs.push_back(Next);
625 }
626 }
627 if (GuessedSuccs.size() != MBB.succ_size())
628 return false;
629 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
630 }
631
print(const MachineBasicBlock & MBB)632 void MIPrinter::print(const MachineBasicBlock &MBB) {
633 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
634 MBB.printName(OS,
635 MachineBasicBlock::PrintNameIr |
636 MachineBasicBlock::PrintNameAttributes,
637 &MST);
638 OS << ":\n";
639
640 bool HasLineAttributes = false;
641 // Print the successors
642 bool canPredictProbs = canPredictBranchProbabilities(MBB);
643 // Even if the list of successors is empty, if we cannot guess it,
644 // we need to print it to tell the parser that the list is empty.
645 // This is needed, because MI model unreachable as empty blocks
646 // with an empty successor list. If the parser would see that
647 // without the successor list, it would guess the code would
648 // fallthrough.
649 if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
650 !canPredictSuccessors(MBB)) {
651 OS.indent(2) << "successors: ";
652 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
653 if (I != MBB.succ_begin())
654 OS << ", ";
655 OS << printMBBReference(**I);
656 if (!SimplifyMIR || !canPredictProbs)
657 OS << '('
658 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
659 << ')';
660 }
661 OS << "\n";
662 HasLineAttributes = true;
663 }
664
665 // Print the live in registers.
666 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
667 if (MRI.tracksLiveness() && !MBB.livein_empty()) {
668 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
669 OS.indent(2) << "liveins: ";
670 bool First = true;
671 for (const auto &LI : MBB.liveins()) {
672 if (!First)
673 OS << ", ";
674 First = false;
675 OS << printReg(LI.PhysReg, &TRI);
676 if (!LI.LaneMask.all())
677 OS << ":0x" << PrintLaneMask(LI.LaneMask);
678 }
679 OS << "\n";
680 HasLineAttributes = true;
681 }
682
683 if (HasLineAttributes)
684 OS << "\n";
685 bool IsInBundle = false;
686 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
687 const MachineInstr &MI = *I;
688 if (IsInBundle && !MI.isInsideBundle()) {
689 OS.indent(2) << "}\n";
690 IsInBundle = false;
691 }
692 OS.indent(IsInBundle ? 4 : 2);
693 print(MI);
694 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
695 OS << " {";
696 IsInBundle = true;
697 }
698 OS << "\n";
699 }
700 if (IsInBundle)
701 OS.indent(2) << "}\n";
702 }
703
print(const MachineInstr & MI)704 void MIPrinter::print(const MachineInstr &MI) {
705 const auto *MF = MI.getMF();
706 const auto &MRI = MF->getRegInfo();
707 const auto &SubTarget = MF->getSubtarget();
708 const auto *TRI = SubTarget.getRegisterInfo();
709 assert(TRI && "Expected target register info");
710 const auto *TII = SubTarget.getInstrInfo();
711 assert(TII && "Expected target instruction info");
712 if (MI.isCFIInstruction())
713 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
714
715 SmallBitVector PrintedTypes(8);
716 bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
717 unsigned I = 0, E = MI.getNumOperands();
718 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
719 !MI.getOperand(I).isImplicit();
720 ++I) {
721 if (I)
722 OS << ", ";
723 print(MI, I, TRI, TII, ShouldPrintRegisterTies,
724 MI.getTypeToPrint(I, PrintedTypes, MRI),
725 /*PrintDef=*/false);
726 }
727
728 if (I)
729 OS << " = ";
730 if (MI.getFlag(MachineInstr::FrameSetup))
731 OS << "frame-setup ";
732 if (MI.getFlag(MachineInstr::FrameDestroy))
733 OS << "frame-destroy ";
734 if (MI.getFlag(MachineInstr::FmNoNans))
735 OS << "nnan ";
736 if (MI.getFlag(MachineInstr::FmNoInfs))
737 OS << "ninf ";
738 if (MI.getFlag(MachineInstr::FmNsz))
739 OS << "nsz ";
740 if (MI.getFlag(MachineInstr::FmArcp))
741 OS << "arcp ";
742 if (MI.getFlag(MachineInstr::FmContract))
743 OS << "contract ";
744 if (MI.getFlag(MachineInstr::FmAfn))
745 OS << "afn ";
746 if (MI.getFlag(MachineInstr::FmReassoc))
747 OS << "reassoc ";
748 if (MI.getFlag(MachineInstr::NoUWrap))
749 OS << "nuw ";
750 if (MI.getFlag(MachineInstr::NoSWrap))
751 OS << "nsw ";
752 if (MI.getFlag(MachineInstr::IsExact))
753 OS << "exact ";
754 if (MI.getFlag(MachineInstr::NoFPExcept))
755 OS << "nofpexcept ";
756 if (MI.getFlag(MachineInstr::NoMerge))
757 OS << "nomerge ";
758
759 OS << TII->getName(MI.getOpcode());
760 if (I < E)
761 OS << ' ';
762
763 bool NeedComma = false;
764 for (; I < E; ++I) {
765 if (NeedComma)
766 OS << ", ";
767 print(MI, I, TRI, TII, ShouldPrintRegisterTies,
768 MI.getTypeToPrint(I, PrintedTypes, MRI));
769 NeedComma = true;
770 }
771
772 // Print any optional symbols attached to this instruction as-if they were
773 // operands.
774 if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
775 if (NeedComma)
776 OS << ',';
777 OS << " pre-instr-symbol ";
778 MachineOperand::printSymbol(OS, *PreInstrSymbol);
779 NeedComma = true;
780 }
781 if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
782 if (NeedComma)
783 OS << ',';
784 OS << " post-instr-symbol ";
785 MachineOperand::printSymbol(OS, *PostInstrSymbol);
786 NeedComma = true;
787 }
788 if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) {
789 if (NeedComma)
790 OS << ',';
791 OS << " heap-alloc-marker ";
792 HeapAllocMarker->printAsOperand(OS, MST);
793 NeedComma = true;
794 }
795
796 if (auto Num = MI.peekDebugInstrNum()) {
797 if (NeedComma)
798 OS << ',';
799 OS << " debug-instr-number " << Num;
800 NeedComma = true;
801 }
802
803 if (PrintLocations) {
804 if (const DebugLoc &DL = MI.getDebugLoc()) {
805 if (NeedComma)
806 OS << ',';
807 OS << " debug-location ";
808 DL->printAsOperand(OS, MST);
809 }
810 }
811
812 if (!MI.memoperands_empty()) {
813 OS << " :: ";
814 const LLVMContext &Context = MF->getFunction().getContext();
815 const MachineFrameInfo &MFI = MF->getFrameInfo();
816 bool NeedComma = false;
817 for (const auto *Op : MI.memoperands()) {
818 if (NeedComma)
819 OS << ", ";
820 Op->print(OS, MST, SSNs, Context, &MFI, TII);
821 NeedComma = true;
822 }
823 }
824 }
825
printStackObjectReference(int FrameIndex)826 void MIPrinter::printStackObjectReference(int FrameIndex) {
827 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
828 assert(ObjectInfo != StackObjectOperandMapping.end() &&
829 "Invalid frame index");
830 const FrameIndexOperand &Operand = ObjectInfo->second;
831 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
832 Operand.Name);
833 }
834
formatOperandComment(std::string Comment)835 static std::string formatOperandComment(std::string Comment) {
836 if (Comment.empty())
837 return Comment;
838 return std::string(" /* " + Comment + " */");
839 }
840
print(const MachineInstr & MI,unsigned OpIdx,const TargetRegisterInfo * TRI,const TargetInstrInfo * TII,bool ShouldPrintRegisterTies,LLT TypeToPrint,bool PrintDef)841 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
842 const TargetRegisterInfo *TRI,
843 const TargetInstrInfo *TII,
844 bool ShouldPrintRegisterTies, LLT TypeToPrint,
845 bool PrintDef) {
846 const MachineOperand &Op = MI.getOperand(OpIdx);
847 std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
848
849 switch (Op.getType()) {
850 case MachineOperand::MO_Immediate:
851 if (MI.isOperandSubregIdx(OpIdx)) {
852 MachineOperand::printTargetFlags(OS, Op);
853 MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
854 break;
855 }
856 LLVM_FALLTHROUGH;
857 case MachineOperand::MO_Register:
858 case MachineOperand::MO_CImmediate:
859 case MachineOperand::MO_FPImmediate:
860 case MachineOperand::MO_MachineBasicBlock:
861 case MachineOperand::MO_ConstantPoolIndex:
862 case MachineOperand::MO_TargetIndex:
863 case MachineOperand::MO_JumpTableIndex:
864 case MachineOperand::MO_ExternalSymbol:
865 case MachineOperand::MO_GlobalAddress:
866 case MachineOperand::MO_RegisterLiveOut:
867 case MachineOperand::MO_Metadata:
868 case MachineOperand::MO_MCSymbol:
869 case MachineOperand::MO_CFIIndex:
870 case MachineOperand::MO_IntrinsicID:
871 case MachineOperand::MO_Predicate:
872 case MachineOperand::MO_BlockAddress:
873 case MachineOperand::MO_ShuffleMask: {
874 unsigned TiedOperandIdx = 0;
875 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
876 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
877 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
878 Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
879 ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
880 OS << formatOperandComment(MOComment);
881 break;
882 }
883 case MachineOperand::MO_FrameIndex:
884 printStackObjectReference(Op.getIndex());
885 break;
886 case MachineOperand::MO_RegisterMask: {
887 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
888 if (RegMaskInfo != RegisterMaskIds.end())
889 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
890 else
891 printCustomRegMask(Op.getRegMask(), OS, TRI);
892 break;
893 }
894 }
895 }
896
printIRValue(raw_ostream & OS,const Value & V,ModuleSlotTracker & MST)897 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V,
898 ModuleSlotTracker &MST) {
899 if (isa<GlobalValue>(V)) {
900 V.printAsOperand(OS, /*PrintType=*/false, MST);
901 return;
902 }
903 if (isa<Constant>(V)) {
904 // Machine memory operands can load/store to/from constant value pointers.
905 OS << '`';
906 V.printAsOperand(OS, /*PrintType=*/true, MST);
907 OS << '`';
908 return;
909 }
910 OS << "%ir.";
911 if (V.hasName()) {
912 printLLVMNameWithoutPrefix(OS, V.getName());
913 return;
914 }
915 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
916 MachineOperand::printIRSlotNumber(OS, Slot);
917 }
918
printMIR(raw_ostream & OS,const Module & M)919 void llvm::printMIR(raw_ostream &OS, const Module &M) {
920 yaml::Output Out(OS);
921 Out << const_cast<Module &>(M);
922 }
923
printMIR(raw_ostream & OS,const MachineFunction & MF)924 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
925 MIRPrinter Printer(OS);
926 Printer.print(MF);
927 }
928