1 /* $NetBSD: nouveau_nvkm_subdev_fb_ramgt215.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $ */
2
3 /*
4 * Copyright 2013 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 * Roy Spliet <rspliet@eclipso.eu>
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_fb_ramgt215.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $");
29
30 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
31 #include "ram.h"
32 #include "ramfuc.h"
33
34 #include <core/memory.h>
35 #include <core/option.h>
36 #include <subdev/bios.h>
37 #include <subdev/bios/M0205.h>
38 #include <subdev/bios/rammap.h>
39 #include <subdev/bios/timing.h>
40 #include <subdev/clk/gt215.h>
41 #include <subdev/gpio.h>
42
43 struct gt215_ramfuc {
44 struct ramfuc base;
45 struct ramfuc_reg r_0x001610;
46 struct ramfuc_reg r_0x001700;
47 struct ramfuc_reg r_0x002504;
48 struct ramfuc_reg r_0x004000;
49 struct ramfuc_reg r_0x004004;
50 struct ramfuc_reg r_0x004018;
51 struct ramfuc_reg r_0x004128;
52 struct ramfuc_reg r_0x004168;
53 struct ramfuc_reg r_0x100080;
54 struct ramfuc_reg r_0x100200;
55 struct ramfuc_reg r_0x100210;
56 struct ramfuc_reg r_0x100220[9];
57 struct ramfuc_reg r_0x100264;
58 struct ramfuc_reg r_0x1002d0;
59 struct ramfuc_reg r_0x1002d4;
60 struct ramfuc_reg r_0x1002dc;
61 struct ramfuc_reg r_0x10053c;
62 struct ramfuc_reg r_0x1005a0;
63 struct ramfuc_reg r_0x1005a4;
64 struct ramfuc_reg r_0x100700;
65 struct ramfuc_reg r_0x100714;
66 struct ramfuc_reg r_0x100718;
67 struct ramfuc_reg r_0x10071c;
68 struct ramfuc_reg r_0x100720;
69 struct ramfuc_reg r_0x100760;
70 struct ramfuc_reg r_0x1007a0;
71 struct ramfuc_reg r_0x1007e0;
72 struct ramfuc_reg r_0x100da0;
73 struct ramfuc_reg r_0x10f804;
74 struct ramfuc_reg r_0x1110e0;
75 struct ramfuc_reg r_0x111100;
76 struct ramfuc_reg r_0x111104;
77 struct ramfuc_reg r_0x1111e0;
78 struct ramfuc_reg r_0x111400;
79 struct ramfuc_reg r_0x611200;
80 struct ramfuc_reg r_mr[4];
81 struct ramfuc_reg r_gpio[4];
82 };
83
84 struct gt215_ltrain {
85 enum {
86 NVA3_TRAIN_UNKNOWN,
87 NVA3_TRAIN_UNSUPPORTED,
88 NVA3_TRAIN_ONCE,
89 NVA3_TRAIN_EXEC,
90 NVA3_TRAIN_DONE
91 } state;
92 u32 r_100720;
93 u32 r_1111e0;
94 u32 r_111400;
95 struct nvkm_memory *memory;
96 };
97
98 struct gt215_ram {
99 struct nvkm_ram base;
100 struct gt215_ramfuc fuc;
101 struct gt215_ltrain ltrain;
102 };
103
104 static void
gt215_link_train_calc(u32 * vals,struct gt215_ltrain * train)105 gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
106 {
107 int i, lo, hi;
108 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
109
110 for (i = 0; i < 8; i++) {
111 for (lo = 0; lo < 0x40; lo++) {
112 if (!(vals[lo] & 0x80000000))
113 continue;
114 if (vals[lo] & (0x101 << i))
115 break;
116 }
117
118 if (lo == 0x40)
119 return;
120
121 for (hi = lo + 1; hi < 0x40; hi++) {
122 if (!(vals[lo] & 0x80000000))
123 continue;
124 if (!(vals[hi] & (0x101 << i))) {
125 hi--;
126 break;
127 }
128 }
129
130 median[i] = ((hi - lo) >> 1) + lo;
131 bins[(median[i] & 0xf0) >> 4]++;
132 median[i] += 0x30;
133 }
134
135 /* Find the best value for 0x1111e0 */
136 for (i = 0; i < 4; i++) {
137 if (bins[i] > qty) {
138 bin = i + 3;
139 qty = bins[i];
140 }
141 }
142
143 train->r_100720 = 0;
144 for (i = 0; i < 8; i++) {
145 median[i] = max(median[i], (u8) (bin << 4));
146 median[i] = min(median[i], (u8) ((bin << 4) | 0xf));
147
148 train->r_100720 |= ((median[i] & 0x0f) << (i << 2));
149 }
150
151 train->r_1111e0 = 0x02000000 | (bin * 0x101);
152 train->r_111400 = 0x0;
153 }
154
155 /*
156 * Link training for (at least) DDR3
157 */
158 static int
gt215_link_train(struct gt215_ram * ram)159 gt215_link_train(struct gt215_ram *ram)
160 {
161 struct gt215_ltrain *train = &ram->ltrain;
162 struct gt215_ramfuc *fuc = &ram->fuc;
163 struct nvkm_subdev *subdev = &ram->base.fb->subdev;
164 struct nvkm_device *device = subdev->device;
165 struct nvkm_bios *bios = device->bios;
166 struct nvkm_clk *clk = device->clk;
167 u32 *result, r1700;
168 int ret, i;
169 struct nvbios_M0205T M0205T = { 0 };
170 u8 ver, hdr, cnt, len, snr, ssz;
171 unsigned int clk_current;
172 unsigned long flags;
173 unsigned long *f = &flags;
174
175 if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true)
176 return -ENOSYS;
177
178 /* XXX: Multiple partitions? */
179 result = kmalloc_array(64, sizeof(u32), GFP_KERNEL);
180 if (!result)
181 return -ENOMEM;
182
183 train->state = NVA3_TRAIN_EXEC;
184
185 /* Clock speeds for training and back */
186 nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T);
187 if (M0205T.freq == 0) {
188 kfree(result);
189 return -ENOENT;
190 }
191
192 clk_current = nvkm_clk_read(clk, nv_clk_src_mem);
193
194 ret = gt215_clk_pre(clk, f);
195 if (ret)
196 goto out;
197
198 /* First: clock up/down */
199 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000);
200 if (ret)
201 goto out;
202
203 /* Do this *after* calc, eliminates write in script */
204 nvkm_wr32(device, 0x111400, 0x00000000);
205 /* XXX: Magic writes that improve train reliability? */
206 nvkm_mask(device, 0x100674, 0x0000ffff, 0x00000000);
207 nvkm_mask(device, 0x1005e4, 0x0000ffff, 0x00000000);
208 nvkm_mask(device, 0x100b0c, 0x000000ff, 0x00000000);
209 nvkm_wr32(device, 0x100c04, 0x00000400);
210
211 /* Now the training script */
212 r1700 = ram_rd32(fuc, 0x001700);
213
214 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
215 ram_wr32(fuc, 0x611200, 0x3300);
216 ram_wait_vblank(fuc);
217 ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000);
218 ram_mask(fuc, 0x001610, 0x00000083, 0x00000003);
219 ram_mask(fuc, 0x100080, 0x00000020, 0x00000000);
220 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
221 ram_wr32(fuc, 0x001700, 0x00000000);
222
223 ram_train(fuc);
224
225 /* Reset */
226 ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000);
227 ram_wr32(fuc, 0x10053c, 0x0);
228 ram_wr32(fuc, 0x100720, train->r_100720);
229 ram_wr32(fuc, 0x1111e0, train->r_1111e0);
230 ram_wr32(fuc, 0x111400, train->r_111400);
231 ram_nuke(fuc, 0x100080);
232 ram_mask(fuc, 0x100080, 0x00000020, 0x00000020);
233 ram_nsec(fuc, 1000);
234
235 ram_wr32(fuc, 0x001700, r1700);
236 ram_mask(fuc, 0x001610, 0x00000083, 0x00000080);
237 ram_wr32(fuc, 0x611200, 0x3330);
238 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
239
240 ram_exec(fuc, true);
241
242 ram->base.func->calc(&ram->base, clk_current);
243 ram_exec(fuc, true);
244
245 /* Post-processing, avoids flicker */
246 nvkm_mask(device, 0x616308, 0x10, 0x10);
247 nvkm_mask(device, 0x616b08, 0x10, 0x10);
248
249 gt215_clk_post(clk, f);
250
251 ram_train_result(ram->base.fb, result, 64);
252 for (i = 0; i < 64; i++)
253 nvkm_debug(subdev, "Train: %08x", result[i]);
254 gt215_link_train_calc(result, train);
255
256 nvkm_debug(subdev, "Train: %08x %08x %08x", train->r_100720,
257 train->r_1111e0, train->r_111400);
258
259 kfree(result);
260
261 train->state = NVA3_TRAIN_DONE;
262
263 return ret;
264
265 out:
266 if(ret == -EBUSY)
267 f = NULL;
268
269 train->state = NVA3_TRAIN_UNSUPPORTED;
270
271 gt215_clk_post(clk, f);
272 kfree(result);
273 return ret;
274 }
275
276 static int
gt215_link_train_init(struct gt215_ram * ram)277 gt215_link_train_init(struct gt215_ram *ram)
278 {
279 static const u32 pattern[16] = {
280 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
281 0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
282 0x33333333, 0x55555555, 0x77777777, 0x66666666,
283 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
284 };
285 struct gt215_ltrain *train = &ram->ltrain;
286 struct nvkm_device *device = ram->base.fb->subdev.device;
287 struct nvkm_bios *bios = device->bios;
288 struct nvbios_M0205E M0205E;
289 u8 ver, hdr, cnt, len;
290 u32 r001700;
291 u64 addr;
292 int ret, i = 0;
293
294 train->state = NVA3_TRAIN_UNSUPPORTED;
295
296 /* We support type "5"
297 * XXX: training pattern table appears to be unused for this routine */
298 if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))
299 return -ENOENT;
300
301 if (M0205E.type != 5)
302 return 0;
303
304 train->state = NVA3_TRAIN_ONCE;
305
306 ret = nvkm_ram_get(device, NVKM_RAM_MM_NORMAL, 0x01, 16, 0x8000,
307 true, true, &ram->ltrain.memory);
308 if (ret)
309 return ret;
310
311 addr = nvkm_memory_addr(ram->ltrain.memory);
312
313 nvkm_wr32(device, 0x100538, 0x10000000 | (addr >> 16));
314 nvkm_wr32(device, 0x1005a8, 0x0000ffff);
315 nvkm_mask(device, 0x10f800, 0x00000001, 0x00000001);
316
317 for (i = 0; i < 0x30; i++) {
318 nvkm_wr32(device, 0x10f8c0, (i << 8) | i);
319 nvkm_wr32(device, 0x10f900, pattern[i % 16]);
320 }
321
322 for (i = 0; i < 0x30; i++) {
323 nvkm_wr32(device, 0x10f8e0, (i << 8) | i);
324 nvkm_wr32(device, 0x10f920, pattern[i % 16]);
325 }
326
327 /* And upload the pattern */
328 r001700 = nvkm_rd32(device, 0x1700);
329 nvkm_wr32(device, 0x1700, addr >> 16);
330 for (i = 0; i < 16; i++)
331 nvkm_wr32(device, 0x700000 + (i << 2), pattern[i]);
332 for (i = 0; i < 16; i++)
333 nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]);
334 nvkm_wr32(device, 0x1700, r001700);
335
336 train->r_100720 = nvkm_rd32(device, 0x100720);
337 train->r_1111e0 = nvkm_rd32(device, 0x1111e0);
338 train->r_111400 = nvkm_rd32(device, 0x111400);
339 return 0;
340 }
341
342 static void
gt215_link_train_fini(struct gt215_ram * ram)343 gt215_link_train_fini(struct gt215_ram *ram)
344 {
345 nvkm_memory_unref(&ram->ltrain.memory);
346 }
347
348 /*
349 * RAM reclocking
350 */
351 #define T(t) cfg->timing_10_##t
352 static int
gt215_ram_timing_calc(struct gt215_ram * ram,u32 * timing)353 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
354 {
355 struct nvbios_ramcfg *cfg = &ram->base.target.bios;
356 struct nvkm_subdev *subdev = &ram->base.fb->subdev;
357 struct nvkm_device *device = subdev->device;
358 int tUNK_base, tUNK_40_0, prevCL;
359 u32 cur2, cur3, cur7, cur8;
360
361 cur2 = nvkm_rd32(device, 0x100228);
362 cur3 = nvkm_rd32(device, 0x10022c);
363 cur7 = nvkm_rd32(device, 0x10023c);
364 cur8 = nvkm_rd32(device, 0x100240);
365
366
367 switch ((!T(CWL)) * ram->base.type) {
368 case NVKM_RAM_TYPE_DDR2:
369 T(CWL) = T(CL) - 1;
370 break;
371 case NVKM_RAM_TYPE_GDDR3:
372 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
373 break;
374 }
375
376 prevCL = (cur3 & 0x000000ff) + 1;
377 tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
378
379 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
380 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
381 max_t(u8,T(18), 1) << 16 |
382 (T(WTR) + 1 + T(CWL)) << 8 |
383 (5 + T(CL) - T(CWL));
384 timing[2] = (T(CWL) - 1) << 24 |
385 (T(RRD) << 16) |
386 (T(RCDWR) << 8) |
387 T(RCDRD);
388 timing[3] = (cur3 & 0x00ff0000) |
389 (0x30 + T(CL)) << 24 |
390 (0xb + T(CL)) << 8 |
391 (T(CL) - 1);
392 timing[4] = T(20) << 24 |
393 T(21) << 16 |
394 T(13) << 8 |
395 T(13);
396 timing[5] = T(RFC) << 24 |
397 max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
398 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
399 T(RP);
400 timing[6] = (0x5a + T(CL)) << 16 |
401 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
402 (0x50 + T(CL) - T(CWL));
403 timing[7] = (cur7 & 0xff000000) |
404 ((tUNK_base + T(CL)) << 16) |
405 0x202;
406 timing[8] = cur8 & 0xffffff00;
407
408 switch (ram->base.type) {
409 case NVKM_RAM_TYPE_DDR2:
410 case NVKM_RAM_TYPE_GDDR3:
411 tUNK_40_0 = prevCL - (cur8 & 0xff);
412 if (tUNK_40_0 > 0)
413 timing[8] |= T(CL);
414 break;
415 default:
416 break;
417 }
418
419 nvkm_debug(subdev, "Entry: 220: %08x %08x %08x %08x\n",
420 timing[0], timing[1], timing[2], timing[3]);
421 nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n",
422 timing[4], timing[5], timing[6], timing[7]);
423 nvkm_debug(subdev, " 240: %08x\n", timing[8]);
424 return 0;
425 }
426 #undef T
427
428 static void
nvkm_sddr2_dll_reset(struct gt215_ramfuc * fuc)429 nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc)
430 {
431 ram_mask(fuc, mr[0], 0x100, 0x100);
432 ram_nsec(fuc, 1000);
433 ram_mask(fuc, mr[0], 0x100, 0x000);
434 ram_nsec(fuc, 1000);
435 }
436
437 static void
nvkm_sddr3_dll_disable(struct gt215_ramfuc * fuc,u32 * mr)438 nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
439 {
440 u32 mr1_old = ram_rd32(fuc, mr[1]);
441
442 if (!(mr1_old & 0x1)) {
443 ram_wr32(fuc, 0x1002d4, 0x00000001);
444 ram_wr32(fuc, mr[1], mr[1]);
445 ram_nsec(fuc, 1000);
446 }
447 }
448
449 static void
nvkm_gddr3_dll_disable(struct gt215_ramfuc * fuc,u32 * mr)450 nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
451 {
452 u32 mr1_old = ram_rd32(fuc, mr[1]);
453
454 if (!(mr1_old & 0x40)) {
455 ram_wr32(fuc, mr[1], mr[1]);
456 ram_nsec(fuc, 1000);
457 }
458 }
459
460 static void
gt215_ram_lock_pll(struct gt215_ramfuc * fuc,struct gt215_clk_info * mclk)461 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
462 {
463 ram_wr32(fuc, 0x004004, mclk->pll);
464 ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
465 ram_mask(fuc, 0x004000, 0x00000010, 0x00000000);
466 ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
467 ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
468 }
469
470 static void
gt215_ram_gpio(struct gt215_ramfuc * fuc,u8 tag,u32 val)471 gt215_ram_gpio(struct gt215_ramfuc *fuc, u8 tag, u32 val)
472 {
473 struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio;
474 struct dcb_gpio_func func;
475 u32 reg, sh, gpio_val;
476 int ret;
477
478 if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) {
479 ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func);
480 if (ret)
481 return;
482
483 reg = func.line >> 3;
484 sh = (func.line & 0x7) << 2;
485 gpio_val = ram_rd32(fuc, gpio[reg]);
486 if (gpio_val & (8 << sh))
487 val = !val;
488 if (!(func.log[1] & 1))
489 val = !val;
490
491 ram_mask(fuc, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));
492 ram_nsec(fuc, 20000);
493 }
494 }
495
496 static int
gt215_ram_calc(struct nvkm_ram * base,u32 freq)497 gt215_ram_calc(struct nvkm_ram *base, u32 freq)
498 {
499 struct gt215_ram *ram = gt215_ram(base);
500 struct gt215_ramfuc *fuc = &ram->fuc;
501 struct gt215_ltrain *train = &ram->ltrain;
502 struct nvkm_subdev *subdev = &ram->base.fb->subdev;
503 struct nvkm_device *device = subdev->device;
504 struct nvkm_bios *bios = device->bios;
505 struct gt215_clk_info mclk;
506 struct nvkm_gpio *gpio = device->gpio;
507 struct nvkm_ram_data *next;
508 u8 ver, hdr, cnt, len, strap;
509 u32 data;
510 u32 r004018, r100760, r100da0, r111100, ctrl;
511 u32 unk714, unk718, unk71c;
512 int ret, i;
513 u32 timing[9];
514 bool pll2pll;
515
516 next = &ram->base.target;
517 next->freq = freq;
518 ram->base.next = next;
519
520 if (ram->ltrain.state == NVA3_TRAIN_ONCE)
521 gt215_link_train(ram);
522
523 /* lookup memory config data relevant to the target frequency */
524 data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
525 &next->bios);
526 if (!data || ver != 0x10 || hdr < 0x05) {
527 nvkm_error(subdev, "invalid/missing rammap entry\n");
528 return -EINVAL;
529 }
530
531 /* locate specific data set for the attached memory */
532 strap = nvbios_ramcfg_index(subdev);
533 if (strap >= cnt) {
534 nvkm_error(subdev, "invalid ramcfg strap\n");
535 return -EINVAL;
536 }
537
538 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
539 &ver, &hdr, &next->bios);
540 if (!data || ver != 0x10 || hdr < 0x09) {
541 nvkm_error(subdev, "invalid/missing ramcfg entry\n");
542 return -EINVAL;
543 }
544
545 /* lookup memory timings, if bios says they're present */
546 if (next->bios.ramcfg_timing != 0xff) {
547 data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
548 &ver, &hdr, &cnt, &len,
549 &next->bios);
550 if (!data || ver != 0x10 || hdr < 0x17) {
551 nvkm_error(subdev, "invalid/missing timing entry\n");
552 return -EINVAL;
553 }
554 }
555
556 ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk);
557 if (ret < 0) {
558 nvkm_error(subdev, "failed mclk calculation\n");
559 return ret;
560 }
561
562 gt215_ram_timing_calc(ram, timing);
563
564 ret = ram_init(fuc, ram->base.fb);
565 if (ret)
566 return ret;
567
568 /* Determine ram-specific MR values */
569 ram->base.mr[0] = ram_rd32(fuc, mr[0]);
570 ram->base.mr[1] = ram_rd32(fuc, mr[1]);
571 ram->base.mr[2] = ram_rd32(fuc, mr[2]);
572
573 switch (ram->base.type) {
574 case NVKM_RAM_TYPE_DDR2:
575 ret = nvkm_sddr2_calc(&ram->base);
576 break;
577 case NVKM_RAM_TYPE_DDR3:
578 ret = nvkm_sddr3_calc(&ram->base);
579 break;
580 case NVKM_RAM_TYPE_GDDR3:
581 ret = nvkm_gddr3_calc(&ram->base);
582 break;
583 default:
584 ret = -ENOSYS;
585 break;
586 }
587
588 if (ret)
589 return ret;
590
591 /* XXX: 750MHz seems rather arbitrary */
592 if (freq <= 750000) {
593 r004018 = 0x10000000;
594 r100760 = 0x22222222;
595 r100da0 = 0x00000010;
596 } else {
597 r004018 = 0x00000000;
598 r100760 = 0x00000000;
599 r100da0 = 0x00000000;
600 }
601
602 if (!next->bios.ramcfg_DLLoff)
603 r004018 |= 0x00004000;
604
605 /* pll2pll requires to switch to a safe clock first */
606 ctrl = ram_rd32(fuc, 0x004000);
607 pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
608
609 /* Pre, NVIDIA does this outside the script */
610 if (next->bios.ramcfg_10_02_10) {
611 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
612 } else {
613 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
614 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
615 }
616 /* Always disable this bit during reclock */
617 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
618
619 /* If switching from non-pll to pll, lock before disabling FB */
620 if (mclk.pll && !pll2pll) {
621 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
622 gt215_ram_lock_pll(fuc, &mclk);
623 }
624
625 /* Start with disabling some CRTCs and PFIFO? */
626 ram_wait_vblank(fuc);
627 ram_wr32(fuc, 0x611200, 0x3300);
628 ram_mask(fuc, 0x002504, 0x1, 0x1);
629 ram_nsec(fuc, 10000);
630 ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */
631 ram_block(fuc);
632 ram_nsec(fuc, 2000);
633
634 if (!next->bios.ramcfg_10_02_10) {
635 if (ram->base.type == NVKM_RAM_TYPE_GDDR3)
636 ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
637 else
638 ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
639 }
640
641 /* If we're disabling the DLL, do it now */
642 switch (next->bios.ramcfg_DLLoff * ram->base.type) {
643 case NVKM_RAM_TYPE_DDR3:
644 nvkm_sddr3_dll_disable(fuc, ram->base.mr);
645 break;
646 case NVKM_RAM_TYPE_GDDR3:
647 nvkm_gddr3_dll_disable(fuc, ram->base.mr);
648 break;
649 }
650
651 if (next->bios.timing_10_ODT)
652 gt215_ram_gpio(fuc, 0x2e, 1);
653
654 /* Brace RAM for impact */
655 ram_wr32(fuc, 0x1002d4, 0x00000001);
656 ram_wr32(fuc, 0x1002d0, 0x00000001);
657 ram_wr32(fuc, 0x1002d0, 0x00000001);
658 ram_wr32(fuc, 0x100210, 0x00000000);
659 ram_wr32(fuc, 0x1002dc, 0x00000001);
660 ram_nsec(fuc, 2000);
661
662 if (device->chipset == 0xa3 && freq <= 500000)
663 ram_mask(fuc, 0x100700, 0x00000006, 0x00000006);
664
665 /* Alter FBVDD/Q, apparently must be done with PLL disabled, thus
666 * set it to bypass */
667 if (nvkm_gpio_get(gpio, 0, 0x18, DCB_GPIO_UNUSED) ==
668 next->bios.ramcfg_FBVDDQ) {
669 data = ram_rd32(fuc, 0x004000) & 0x9;
670
671 if (data == 0x1)
672 ram_mask(fuc, 0x004000, 0x8, 0x8);
673 if (data & 0x1)
674 ram_mask(fuc, 0x004000, 0x1, 0x0);
675
676 gt215_ram_gpio(fuc, 0x18, !next->bios.ramcfg_FBVDDQ);
677
678 if (data & 0x1)
679 ram_mask(fuc, 0x004000, 0x1, 0x1);
680 }
681
682 /* Fiddle with clocks */
683 /* There's 4 scenario's
684 * pll->pll: first switch to a 324MHz clock, set up new PLL, switch
685 * clk->pll: Set up new PLL, switch
686 * pll->clk: Set up clock, switch
687 * clk->clk: Overwrite ctrl and other bits, switch */
688
689 /* Switch to regular clock - 324MHz */
690 if (pll2pll) {
691 ram_mask(fuc, 0x004000, 0x00000004, 0x00000004);
692 ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101);
693 ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
694 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
695 ram_wr32(fuc, 0x004018, 0x00001000);
696 gt215_ram_lock_pll(fuc, &mclk);
697 }
698
699 if (mclk.pll) {
700 ram_mask(fuc, 0x004000, 0x00000105, 0x00000105);
701 ram_wr32(fuc, 0x004018, 0x00001000 | r004018);
702 ram_wr32(fuc, 0x100da0, r100da0);
703 } else {
704 ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101);
705 ram_mask(fuc, 0x004000, 0x00000108, 0x00000008);
706 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
707 ram_wr32(fuc, 0x004018, 0x00009000 | r004018);
708 ram_wr32(fuc, 0x100da0, r100da0);
709 }
710 ram_nsec(fuc, 20000);
711
712 if (next->bios.rammap_10_04_08) {
713 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
714 next->bios.ramcfg_10_05 << 8 |
715 next->bios.ramcfg_10_05);
716 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
717 next->bios.ramcfg_10_07);
718 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
719 next->bios.ramcfg_10_03_0f << 16 |
720 next->bios.ramcfg_10_09_0f |
721 0x80000000);
722 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
723 } else {
724 if (train->state == NVA3_TRAIN_DONE) {
725 ram_wr32(fuc, 0x100080, 0x1020);
726 ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400);
727 ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0);
728 ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720);
729 }
730 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
731 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
732 ram_mask(fuc, 0x100760, 0x22222222, r100760);
733 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
734 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
735 }
736
737 if (device->chipset == 0xa3 && freq > 500000) {
738 ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
739 }
740
741 /* Final switch */
742 if (mclk.pll) {
743 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
744 ram_mask(fuc, 0x004000, 0x00000008, 0x00000000);
745 }
746
747 ram_wr32(fuc, 0x1002dc, 0x00000000);
748 ram_wr32(fuc, 0x1002d4, 0x00000001);
749 ram_wr32(fuc, 0x100210, 0x80000000);
750 ram_nsec(fuc, 2000);
751
752 /* Set RAM MR parameters and timings */
753 for (i = 2; i >= 0; i--) {
754 if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {
755 ram_wr32(fuc, mr[i], ram->base.mr[i]);
756 ram_nsec(fuc, 1000);
757 }
758 }
759
760 ram_wr32(fuc, 0x100220[3], timing[3]);
761 ram_wr32(fuc, 0x100220[1], timing[1]);
762 ram_wr32(fuc, 0x100220[6], timing[6]);
763 ram_wr32(fuc, 0x100220[7], timing[7]);
764 ram_wr32(fuc, 0x100220[2], timing[2]);
765 ram_wr32(fuc, 0x100220[4], timing[4]);
766 ram_wr32(fuc, 0x100220[5], timing[5]);
767 ram_wr32(fuc, 0x100220[0], timing[0]);
768 ram_wr32(fuc, 0x100220[8], timing[8]);
769
770 /* Misc */
771 ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
772
773 /* XXX: A lot of "chipset"/"ram type" specific stuff...? */
774 unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000130;
775 unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
776 unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
777 r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
778
779 /* NVA8 seems to skip various bits related to ramcfg_10_02_04 */
780 if (device->chipset == 0xa8) {
781 r111100 |= 0x08000000;
782 if (!next->bios.ramcfg_10_02_04)
783 unk714 |= 0x00000010;
784 } else {
785 if (next->bios.ramcfg_10_02_04) {
786 switch (ram->base.type) {
787 case NVKM_RAM_TYPE_DDR2:
788 case NVKM_RAM_TYPE_DDR3:
789 r111100 &= ~0x00000020;
790 if (next->bios.ramcfg_10_02_10)
791 r111100 |= 0x08000004;
792 else
793 r111100 |= 0x00000024;
794 break;
795 default:
796 break;
797 }
798 } else {
799 switch (ram->base.type) {
800 case NVKM_RAM_TYPE_DDR2:
801 case NVKM_RAM_TYPE_DDR3:
802 r111100 &= ~0x00000024;
803 r111100 |= 0x12800000;
804
805 if (next->bios.ramcfg_10_02_10)
806 r111100 |= 0x08000000;
807 unk714 |= 0x00000010;
808 break;
809 case NVKM_RAM_TYPE_GDDR3:
810 r111100 |= 0x30000000;
811 unk714 |= 0x00000020;
812 break;
813 default:
814 break;
815 }
816 }
817 }
818
819 unk714 |= (next->bios.ramcfg_10_04_01) << 8;
820
821 if (next->bios.ramcfg_10_02_20)
822 unk714 |= 0xf0000000;
823 if (next->bios.ramcfg_10_02_02)
824 unk718 |= 0x00000100;
825 if (next->bios.ramcfg_10_02_01)
826 unk71c |= 0x00000100;
827 if (next->bios.timing_10_24 != 0xff) {
828 unk718 &= ~0xf0000000;
829 unk718 |= next->bios.timing_10_24 << 28;
830 }
831 if (next->bios.ramcfg_10_02_10)
832 r111100 &= ~0x04020000;
833
834 ram_mask(fuc, 0x100714, 0xffffffff, unk714);
835 ram_mask(fuc, 0x10071c, 0xffffffff, unk71c);
836 ram_mask(fuc, 0x100718, 0xffffffff, unk718);
837 ram_mask(fuc, 0x111100, 0xffffffff, r111100);
838
839 if (!next->bios.timing_10_ODT)
840 gt215_ram_gpio(fuc, 0x2e, 0);
841
842 /* Reset DLL */
843 if (!next->bios.ramcfg_DLLoff)
844 nvkm_sddr2_dll_reset(fuc);
845
846 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) {
847 ram_nsec(fuc, 31000);
848 } else {
849 ram_nsec(fuc, 14000);
850 }
851
852 if (ram->base.type == NVKM_RAM_TYPE_DDR3) {
853 ram_wr32(fuc, 0x100264, 0x1);
854 ram_nsec(fuc, 2000);
855 }
856
857 ram_nuke(fuc, 0x100700);
858 ram_mask(fuc, 0x100700, 0x01000000, 0x01000000);
859 ram_mask(fuc, 0x100700, 0x01000000, 0x00000000);
860
861 /* Re-enable FB */
862 ram_unblock(fuc);
863 ram_wr32(fuc, 0x611200, 0x3330);
864
865 /* Post fiddlings */
866 if (next->bios.rammap_10_04_02)
867 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
868 if (next->bios.ramcfg_10_02_10) {
869 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
870 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
871 } else {
872 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
873 }
874
875 if (mclk.pll) {
876 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
877 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
878 } else {
879 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
880 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
881 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
882 }
883
884 return 0;
885 }
886
887 static int
gt215_ram_prog(struct nvkm_ram * base)888 gt215_ram_prog(struct nvkm_ram *base)
889 {
890 struct gt215_ram *ram = gt215_ram(base);
891 struct gt215_ramfuc *fuc = &ram->fuc;
892 struct nvkm_device *device = ram->base.fb->subdev.device;
893 bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true);
894
895 if (exec) {
896 nvkm_mask(device, 0x001534, 0x2, 0x2);
897
898 ram_exec(fuc, true);
899
900 /* Post-processing, avoids flicker */
901 nvkm_mask(device, 0x002504, 0x1, 0x0);
902 nvkm_mask(device, 0x001534, 0x2, 0x0);
903
904 nvkm_mask(device, 0x616308, 0x10, 0x10);
905 nvkm_mask(device, 0x616b08, 0x10, 0x10);
906 } else {
907 ram_exec(fuc, false);
908 }
909 return 0;
910 }
911
912 static void
gt215_ram_tidy(struct nvkm_ram * base)913 gt215_ram_tidy(struct nvkm_ram *base)
914 {
915 struct gt215_ram *ram = gt215_ram(base);
916 ram_exec(&ram->fuc, false);
917 }
918
919 static int
gt215_ram_init(struct nvkm_ram * base)920 gt215_ram_init(struct nvkm_ram *base)
921 {
922 struct gt215_ram *ram = gt215_ram(base);
923 gt215_link_train_init(ram);
924 return 0;
925 }
926
927 static void *
gt215_ram_dtor(struct nvkm_ram * base)928 gt215_ram_dtor(struct nvkm_ram *base)
929 {
930 struct gt215_ram *ram = gt215_ram(base);
931 gt215_link_train_fini(ram);
932 return ram;
933 }
934
935 static const struct nvkm_ram_func
936 gt215_ram_func = {
937 .dtor = gt215_ram_dtor,
938 .init = gt215_ram_init,
939 .calc = gt215_ram_calc,
940 .prog = gt215_ram_prog,
941 .tidy = gt215_ram_tidy,
942 };
943
944 int
gt215_ram_new(struct nvkm_fb * fb,struct nvkm_ram ** pram)945 gt215_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
946 {
947 struct gt215_ram *ram;
948 int ret, i;
949
950 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
951 return -ENOMEM;
952 *pram = &ram->base;
953
954 ret = nv50_ram_ctor(>215_ram_func, fb, &ram->base);
955 if (ret)
956 return ret;
957
958 ram->fuc.r_0x001610 = ramfuc_reg(0x001610);
959 ram->fuc.r_0x001700 = ramfuc_reg(0x001700);
960 ram->fuc.r_0x002504 = ramfuc_reg(0x002504);
961 ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
962 ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
963 ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
964 ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
965 ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
966 ram->fuc.r_0x100080 = ramfuc_reg(0x100080);
967 ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
968 ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
969 for (i = 0; i < 9; i++)
970 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
971 ram->fuc.r_0x100264 = ramfuc_reg(0x100264);
972 ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
973 ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
974 ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
975 ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
976 ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
977 ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
978 ram->fuc.r_0x100700 = ramfuc_reg(0x100700);
979 ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
980 ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
981 ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
982 ram->fuc.r_0x100720 = ramfuc_reg(0x100720);
983 ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
984 ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
985 ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
986 ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask);
987 ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
988 ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
989 ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
990 ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
991 ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0);
992 ram->fuc.r_0x111400 = ramfuc_reg(0x111400);
993 ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
994
995 if (ram->base.ranks > 1) {
996 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
997 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
998 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
999 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
1000 } else {
1001 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
1002 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
1003 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
1004 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
1005 }
1006 ram->fuc.r_gpio[0] = ramfuc_reg(0x00e104);
1007 ram->fuc.r_gpio[1] = ramfuc_reg(0x00e108);
1008 ram->fuc.r_gpio[2] = ramfuc_reg(0x00e120);
1009 ram->fuc.r_gpio[3] = ramfuc_reg(0x00e124);
1010
1011 return 0;
1012 }
1013