1 /* $NetBSD: imx6_clk.c,v 1.8 2024/09/01 08:08:24 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_clk.c,v 1.8 2024/09/01 08:08:24 skrll Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/types.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/sysctl.h> 39 #include <sys/cpufreq.h> 40 #include <sys/kmem.h> 41 #include <sys/param.h> 42 43 #include <arm/nxp/imx6_ccmreg.h> 44 #include <arm/nxp/imx6_ccmvar.h> 45 46 #include <dev/clk/clk_backend.h> 47 #include <dev/fdt/fdtvar.h> 48 49 /* Clock IDs - should match dt-bindings/clock/imx6qdl-clock.h */ 50 #define IMX6QCLK_DUMMY 0 51 #define IMX6QCLK_CKIL 1 52 #define IMX6QCLK_CKIH 2 53 #define IMX6QCLK_OSC 3 54 #define IMX6QCLK_PLL2_PFD0_352M 4 55 #define IMX6QCLK_PLL2_PFD1_594M 5 56 #define IMX6QCLK_PLL2_PFD2_396M 6 57 #define IMX6QCLK_PLL3_PFD0_720M 7 58 #define IMX6QCLK_PLL3_PFD1_540M 8 59 #define IMX6QCLK_PLL3_PFD2_508M 9 60 #define IMX6QCLK_PLL3_PFD3_454M 10 61 #define IMX6QCLK_PLL2_198M 11 62 #define IMX6QCLK_PLL3_120M 12 63 #define IMX6QCLK_PLL3_80M 13 64 #define IMX6QCLK_PLL3_60M 14 65 #define IMX6QCLK_TWD 15 66 #define IMX6QCLK_STEP 16 67 #define IMX6QCLK_PLL1_SW 17 68 #define IMX6QCLK_PERIPH_PRE 18 69 #define IMX6QCLK_PERIPH2_PRE 19 70 #define IMX6QCLK_PERIPH_CLK2_SEL 20 71 #define IMX6QCLK_PERIPH2_CLK2_SEL 21 72 #define IMX6QCLK_AXI_SEL 22 73 #define IMX6QCLK_ESAI_SEL 23 74 #define IMX6QCLK_ASRC_SEL 24 75 #define IMX6QCLK_SPDIF_SEL 25 76 #define IMX6QCLK_GPU2D_AXI 26 77 #define IMX6QCLK_GPU3D_AXI 27 78 #define IMX6QCLK_GPU2D_CORE_SEL 28 79 #define IMX6QCLK_GPU3D_CORE_SEL 29 80 #define IMX6QCLK_GPU3D_SHADER_SEL 30 81 #define IMX6QCLK_IPU1_SEL 31 82 #define IMX6QCLK_IPU2_SEL 32 83 #define IMX6QCLK_LDB_DI0_SEL 33 84 #define IMX6QCLK_LDB_DI1_SEL 34 85 #define IMX6QCLK_IPU1_DI0_PRE_SEL 35 86 #define IMX6QCLK_IPU1_DI1_PRE_SEL 36 87 #define IMX6QCLK_IPU2_DI0_PRE_SEL 37 88 #define IMX6QCLK_IPU2_DI1_PRE_SEL 38 89 #define IMX6QCLK_IPU1_DI0_SEL 39 90 #define IMX6QCLK_IPU1_DI1_SEL 40 91 #define IMX6QCLK_IPU2_DI0_SEL 41 92 #define IMX6QCLK_IPU2_DI1_SEL 42 93 #define IMX6QCLK_HSI_TX_SEL 43 94 #define IMX6QCLK_PCIE_AXI_SEL 44 95 #define IMX6QCLK_SSI1_SEL 45 96 #define IMX6QCLK_SSI2_SEL 46 97 #define IMX6QCLK_SSI3_SEL 47 98 #define IMX6QCLK_USDHC1_SEL 48 99 #define IMX6QCLK_USDHC2_SEL 49 100 #define IMX6QCLK_USDHC3_SEL 50 101 #define IMX6QCLK_USDHC4_SEL 51 102 #define IMX6QCLK_ENFC_SEL 52 103 #define IMX6QCLK_EIM_SEL 53 104 #define IMX6QCLK_EIM_SLOW_SEL 54 105 #define IMX6QCLK_VDO_AXI_SEL 55 106 #define IMX6QCLK_VPU_AXI_SEL 56 107 #define IMX6QCLK_CKO1_SEL 57 108 #define IMX6QCLK_PERIPH 58 109 #define IMX6QCLK_PERIPH2 59 110 #define IMX6QCLK_PERIPH_CLK2 60 111 #define IMX6QCLK_PERIPH2_CLK2 61 112 #define IMX6QCLK_IPG 62 113 #define IMX6QCLK_IPG_PER 63 114 #define IMX6QCLK_ESAI_PRED 64 115 #define IMX6QCLK_ESAI_PODF 65 116 #define IMX6QCLK_ASRC_PRED 66 117 #define IMX6QCLK_ASRC_PODF 67 118 #define IMX6QCLK_SPDIF_PRED 68 119 #define IMX6QCLK_SPDIF_PODF 69 120 #define IMX6QCLK_CAN_ROOT 70 121 #define IMX6QCLK_ECSPI_ROOT 71 122 #define IMX6QCLK_GPU2D_CORE_PODF 72 123 #define IMX6QCLK_GPU3D_CORE_PODF 73 124 #define IMX6QCLK_GPU3D_SHADER 74 125 #define IMX6QCLK_IPU1_PODF 75 126 #define IMX6QCLK_IPU2_PODF 76 127 #define IMX6QCLK_LDB_DI0_PODF 77 128 #define IMX6QCLK_LDB_DI1_PODF 78 129 #define IMX6QCLK_IPU1_DI0_PRE 79 130 #define IMX6QCLK_IPU1_DI1_PRE 80 131 #define IMX6QCLK_IPU2_DI0_PRE 81 132 #define IMX6QCLK_IPU2_DI1_PRE 82 133 #define IMX6QCLK_HSI_TX_PODF 83 134 #define IMX6QCLK_SSI1_PRED 84 135 #define IMX6QCLK_SSI1_PODF 85 136 #define IMX6QCLK_SSI2_PRED 86 137 #define IMX6QCLK_SSI2_PODF 87 138 #define IMX6QCLK_SSI3_PRED 88 139 #define IMX6QCLK_SSI3_PODF 89 140 #define IMX6QCLK_UART_SERIAL_PODF 90 141 #define IMX6QCLK_USDHC1_PODF 91 142 #define IMX6QCLK_USDHC2_PODF 92 143 #define IMX6QCLK_USDHC3_PODF 93 144 #define IMX6QCLK_USDHC4_PODF 94 145 #define IMX6QCLK_ENFC_PRED 95 146 #define IMX6QCLK_ENFC_PODF 96 147 #define IMX6QCLK_EIM_PODF 97 148 #define IMX6QCLK_EIM_SLOW_PODF 98 149 #define IMX6QCLK_VPU_AXI_PODF 99 150 #define IMX6QCLK_CKO1_PODF 100 151 #define IMX6QCLK_AXI 101 152 #define IMX6QCLK_MMDC_CH0_AXI_PODF 102 153 #define IMX6QCLK_MMDC_CH1_AXI_PODF 103 154 #define IMX6QCLK_ARM 104 155 #define IMX6QCLK_AHB 105 156 #define IMX6QCLK_APBH_DMA 106 157 #define IMX6QCLK_ASRC 107 158 #define IMX6QCLK_CAN1_IPG 108 159 #define IMX6QCLK_CAN1_SERIAL 109 160 #define IMX6QCLK_CAN2_IPG 110 161 #define IMX6QCLK_CAN2_SERIAL 111 162 #define IMX6QCLK_ECSPI1 112 163 #define IMX6QCLK_ECSPI2 113 164 #define IMX6QCLK_ECSPI3 114 165 #define IMX6QCLK_ECSPI4 115 166 #define IMX6QCLK_ECSPI5 116 /* i.MX6Q */ 167 #define IMX6QCLK_I2C4 116 /* i.MX6DL */ 168 #define IMX6QCLK_ENET 117 169 #define IMX6QCLK_ESAI_EXTAL 118 170 #define IMX6QCLK_GPT_IPG 119 171 #define IMX6QCLK_GPT_IPG_PER 120 172 #define IMX6QCLK_GPU2D_CORE 121 173 #define IMX6QCLK_GPU3D_CORE 122 174 #define IMX6QCLK_HDMI_IAHB 123 175 #define IMX6QCLK_HDMI_ISFR 124 176 #define IMX6QCLK_I2C1 125 177 #define IMX6QCLK_I2C2 126 178 #define IMX6QCLK_I2C3 127 179 #define IMX6QCLK_IIM 128 180 #define IMX6QCLK_ENFC 129 181 #define IMX6QCLK_IPU1 130 182 #define IMX6QCLK_IPU1_DI0 131 183 #define IMX6QCLK_IPU1_DI1 132 184 #define IMX6QCLK_IPU2 133 185 #define IMX6QCLK_IPU2_DI0 134 186 #define IMX6QCLK_LDB_DI0 135 187 #define IMX6QCLK_LDB_DI1 136 188 #define IMX6QCLK_IPU2_DI1 137 189 #define IMX6QCLK_HSI_TX 138 190 #define IMX6QCLK_MLB 139 191 #define IMX6QCLK_MMDC_CH0_AXI 140 192 #define IMX6QCLK_MMDC_CH1_AXI 141 193 #define IMX6QCLK_OCRAM 142 194 #define IMX6QCLK_OPENVG_AXI 143 195 #define IMX6QCLK_PCIE_AXI 144 196 #define IMX6QCLK_PWM1 145 197 #define IMX6QCLK_PWM2 146 198 #define IMX6QCLK_PWM3 147 199 #define IMX6QCLK_PWM4 148 200 #define IMX6QCLK_PER1_BCH 149 201 #define IMX6QCLK_GPMI_BCH_APB 150 202 #define IMX6QCLK_GPMI_BCH 151 203 #define IMX6QCLK_GPMI_IO 152 204 #define IMX6QCLK_GPMI_APB 153 205 #define IMX6QCLK_SATA 154 206 #define IMX6QCLK_SDMA 155 207 #define IMX6QCLK_SPBA 156 208 #define IMX6QCLK_SSI1 157 209 #define IMX6QCLK_SSI2 158 210 #define IMX6QCLK_SSI3 159 211 #define IMX6QCLK_UART_IPG 160 212 #define IMX6QCLK_UART_SERIAL 161 213 #define IMX6QCLK_USBOH3 162 214 #define IMX6QCLK_USDHC1 163 215 #define IMX6QCLK_USDHC2 164 216 #define IMX6QCLK_USDHC3 165 217 #define IMX6QCLK_USDHC4 166 218 #define IMX6QCLK_VDO_AXI 167 219 #define IMX6QCLK_VPU_AXI 168 220 #define IMX6QCLK_CKO1 169 221 #define IMX6QCLK_PLL1_SYS 170 222 #define IMX6QCLK_PLL2_BUS 171 223 #define IMX6QCLK_PLL3_USB_OTG 172 224 #define IMX6QCLK_PLL4_AUDIO 173 225 #define IMX6QCLK_PLL5_VIDEO 174 226 #define IMX6QCLK_PLL8_MLB 175 227 #define IMX6QCLK_PLL7_USB_HOST 176 228 #define IMX6QCLK_PLL6_ENET 177 229 #define IMX6QCLK_SSI1_IPG 178 230 #define IMX6QCLK_SSI2_IPG 179 231 #define IMX6QCLK_SSI3_IPG 180 232 #define IMX6QCLK_ROM 181 233 #define IMX6QCLK_USBPHY1 182 234 #define IMX6QCLK_USBPHY2 183 235 #define IMX6QCLK_LDB_DI0_DIV_3_5 184 236 #define IMX6QCLK_LDB_DI1_DIV_3_5 185 237 #define IMX6QCLK_SATA_REF 186 238 #define IMX6QCLK_SATA_REF_100M 187 239 #define IMX6QCLK_PCIE_REF 188 240 #define IMX6QCLK_PCIE_REF_125M 189 241 #define IMX6QCLK_ENET_REF 190 242 #define IMX6QCLK_USBPHY1_GATE 191 243 #define IMX6QCLK_USBPHY2_GATE 192 244 #define IMX6QCLK_PLL4_POST_DIV 193 245 #define IMX6QCLK_PLL5_POST_DIV 194 246 #define IMX6QCLK_PLL5_VIDEO_DIV 195 247 #define IMX6QCLK_EIM_SLOW 196 248 #define IMX6QCLK_SPDIF 197 249 #define IMX6QCLK_CKO2_SEL 198 250 #define IMX6QCLK_CKO2_PODF 199 251 #define IMX6QCLK_CKO2 200 252 #define IMX6QCLK_CKO 201 253 #define IMX6QCLK_VDOA 202 254 #define IMX6QCLK_PLL4_AUDIO_DIV 203 255 #define IMX6QCLK_LVDS1_SEL 204 256 #define IMX6QCLK_LVDS2_SEL 205 257 #define IMX6QCLK_LVDS1_GATE 206 258 #define IMX6QCLK_LVDS2_GATE 207 259 #define IMX6QCLK_ESAI_IPG 208 260 #define IMX6QCLK_ESAI_MEM 209 261 #define IMX6QCLK_ASRC_IPG 210 262 #define IMX6QCLK_ASRC_MEM 211 263 #define IMX6QCLK_LVDS1_IN 212 264 #define IMX6QCLK_LVDS2_IN 213 265 #define IMX6QCLK_ANACLK1 214 266 #define IMX6QCLK_ANACLK2 215 267 #define IMX6QCLK_PLL1_BYPASS_SRC 216 268 #define IMX6QCLK_PLL2_BYPASS_SRC 217 269 #define IMX6QCLK_PLL3_BYPASS_SRC 218 270 #define IMX6QCLK_PLL4_BYPASS_SRC 219 271 #define IMX6QCLK_PLL5_BYPASS_SRC 220 272 #define IMX6QCLK_PLL6_BYPASS_SRC 221 273 #define IMX6QCLK_PLL7_BYPASS_SRC 222 274 #define IMX6QCLK_PLL1 223 275 #define IMX6QCLK_PLL2 224 276 #define IMX6QCLK_PLL3 225 277 #define IMX6QCLK_PLL4 226 278 #define IMX6QCLK_PLL5 227 279 #define IMX6QCLK_PLL6 228 280 #define IMX6QCLK_PLL7 229 281 #define IMX6QCLK_PLL1_BYPASS 230 282 #define IMX6QCLK_PLL2_BYPASS 231 283 #define IMX6QCLK_PLL3_BYPASS 232 284 #define IMX6QCLK_PLL4_BYPASS 233 285 #define IMX6QCLK_PLL5_BYPASS 234 286 #define IMX6QCLK_PLL6_BYPASS 235 287 #define IMX6QCLK_PLL7_BYPASS 236 288 #define IMX6QCLK_GPT_3M 237 289 #define IMX6QCLK_VIDEO_27M 238 290 #define IMX6QCLK_MIPI_CORE_CFG 239 291 #define IMX6QCLK_MIPI_IPG 240 292 #define IMX6QCLK_CAAM_MEM 241 293 #define IMX6QCLK_CAAM_ACLK 242 294 #define IMX6QCLK_CAAM_IPG 243 295 #define IMX6QCLK_SPDIF_GCLK 244 296 #define IMX6QCLK_UART_SEL 245 297 #define IMX6QCLK_IPG_PER_SEL 246 298 #define IMX6QCLK_ECSPI_SEL 247 299 #define IMX6QCLK_CAN_SEL 248 300 #define IMX6QCLK_MMDC_CH1_AXI_CG 249 301 #define IMX6QCLK_PRE0 250 302 #define IMX6QCLK_PRE1 251 303 #define IMX6QCLK_PRE2 252 304 #define IMX6QCLK_PRE3 253 305 #define IMX6QCLK_PRG0_AXI 254 306 #define IMX6QCLK_PRG1_AXI 255 307 #define IMX6QCLK_PRG0_APB 256 308 #define IMX6QCLK_PRG1_APB 257 309 #define IMX6QCLK_PRE_AXI 258 310 #define IMX6QCLK_MLB_SEL 259 311 #define IMX6QCLK_MLB_PODF 260 312 #define IMX6QCLK_END 261 313 /* Clock Parents Tables */ 314 static const char *step_p[] = { 315 "osc", 316 "pll2_pfd2_396m" 317 }; 318 319 static const char *pll1_sw_p[] = { 320 "pll1_sys", 321 "step" 322 }; 323 324 static const char *periph_pre_p[] = { 325 "pll2_bus", 326 "pll2_pfd2_396m", 327 "pll2_pfd0_352m", 328 "pll2_198m" 329 }; 330 331 static const char *periph_clk2_p[] = { 332 "pll3_usb_otg", 333 "osc", 334 "osc", 335 "dummy" 336 }; 337 338 static const char *periph2_clk2_p[] = { 339 "pll3_usb_otg", 340 "pll2_bus" 341 }; 342 343 static const char *axi_p[] = { 344 "periph", 345 "pll2_pfd2_396m", 346 "periph", 347 "pll3_pfd1_540m" 348 }; 349 350 static const char *audio_p[] = { 351 "pll4_audio_div", 352 "pll3_pfd2_508m", 353 "pll3_pfd3_454m", 354 "pll3_usb_otg" 355 }; 356 357 static const char *gpu2d_core_p[] = { 358 "axi", 359 "pll3_usb_otg", 360 "pll2_pfd0_352m", 361 "pll2_pfd2_396m" 362 }; 363 364 static const char *gpu3d_core_p[] = { 365 "mmdc_ch0_axi", 366 "pll3_usb_otg", 367 "pll2_pfd1_594m", 368 "pll2_pfd2_396m" 369 }; 370 371 static const char *gpu3d_shader_p[] = { 372 "mmdc_ch0_axi", 373 "pll3_usb_otg", 374 "pll2_pfd1_594m", 375 "pll3_pfd0_720m" 376 }; 377 378 static const char *ipu_p[] = { 379 "mmdc_ch0_axi", 380 "pll2_pfd2_396m", 381 "pll3_120m", 382 "pll3_pfd1_540m" 383 }; 384 385 static const char *pll_bypass_src_p[] = { 386 "osc", 387 "lvds1_in", 388 "lvds2_in", 389 "dummy" 390 }; 391 392 static const char *pll1_bypass_p[] = { 393 "pll1", 394 "pll1_bypass_src" 395 }; 396 397 static const char *pll2_bypass_p[] = { 398 "pll2", 399 "pll2_bypass_src" 400 }; 401 402 static const char *pll3_bypass_p[] = { 403 "pll3", 404 "pll3_bypass_src" 405 }; 406 407 static const char *pll4_bypass_p[] = { 408 "pll4", 409 "pll4_bypass_src" 410 }; 411 412 static const char *pll5_bypass_p[] = { 413 "pll5", 414 "pll5_bypass_src" 415 }; 416 417 static const char *pll6_bypass_p[] = { 418 "pll6", 419 "pll6_bypass_src" 420 }; 421 422 static const char *pll7_bypass_p[] = { 423 "pll7", 424 "pll7_bypass_src" 425 }; 426 427 static const char *ipu_di_pre_p[] = { 428 "mmdc_ch0_axi", 429 "pll3_usb_otg", 430 "pll5_video_div", 431 "pll2_pfd0_352m", 432 "pll2_pfd2_396m", 433 "pll3_pfd1_540m" 434 }; 435 436 static const char *ipu1_di0_p[] = { 437 "ipu1_di0_pre", 438 "dummy", 439 "dummy", 440 "ldb_di0", 441 "ldb_di1" 442 }; 443 444 static const char *ipu1_di1_p[] = { 445 "ipu1_di1_pre", 446 "dummy", 447 "dummy", 448 "ldb_di0", 449 "ldb_di1" 450 }; 451 452 static const char *ipu2_di0_p[] = { 453 "ipu2_di0_pre", 454 "dummy", 455 "dummy", 456 "ldb_di0", 457 "ldb_di1" 458 }; 459 460 static const char *ipu2_di1_p[] = { 461 "ipu2_di1_pre", 462 "dummy", 463 "dummy", 464 "ldb_di0", 465 "ldb_di1" 466 }; 467 468 static const char *ldb_di_p[] = { 469 "pll5_video_div", 470 "pll2_pfd0_352m", 471 "pll2_pfd2_396m", 472 "mmdc_ch1_axi", 473 "pll3_usb_otg" 474 }; 475 476 static const char *periph_p[] = { 477 "periph_pre", 478 "periph_clk2" 479 }; 480 481 static const char *periph2_p[] = { 482 "periph2_pre", 483 "periph2_clk2" 484 }; 485 486 static const char *vdo_axi_p[] = { 487 "axi", 488 "ahb" 489 }; 490 491 static const char *vpu_axi_p[] = { 492 "axi", 493 "pll2_pfd2_396m", 494 "pll2_pfd0_352m" 495 }; 496 497 static const char *cko1_p[] = { 498 "pll3_usb_otg", 499 "pll2_bus", 500 "pll1_sys", 501 "pll5_video_div", 502 "dummy", 503 "axi", 504 "enfc", 505 "ipu1_di0", 506 "ipu1_di1", 507 "ipu2_di0", 508 "ipu2_di1", 509 "ahb", 510 "ipg", 511 "ipg_per", 512 "ckil", 513 "pll4_audio_div" 514 }; 515 516 static const char *cko2_p[] = { 517 "mmdc_ch0_axi", 518 "mmdc_ch1_axi", 519 "usdhc4", 520 "usdhc1", 521 "gpu2d_axi", 522 "dummy", 523 "ecspi_root", 524 "gpu3d_axi", 525 "usdhc3", 526 "dummy", 527 "arm", 528 "ipu1", 529 "ipu2", 530 "vdo_axi", 531 "osc", 532 "gpu2d_core", 533 "gpu3d_core", 534 "usdhc2", 535 "ssi1", 536 "ssi2", 537 "ssi3", 538 "gpu3d_shader", 539 "vpu_axi", 540 "can_root", 541 "ldb_di0", 542 "ldb_di1", 543 "esai_extal", 544 "eim_slow", 545 "uart_serial", 546 "spdif", 547 "asrc", 548 "hsi_tx" 549 }; 550 551 static const char *cko_p[] = { 552 "cko1", 553 "cko2" 554 }; 555 556 static const char *hsi_tx_p[] = { 557 "pll3_120m", 558 "pll2_pfd2_396m" 559 }; 560 561 static const char *pcie_axi_p[] = { 562 "axi", 563 "ahb" 564 }; 565 566 static const char *ssi_p[] = { 567 "pll3_pfd2_508m", 568 "pll3_pfd3_454m", 569 "pll4_audio_div" 570 }; 571 572 static const char *usdhc_p[] = { 573 "pll2_pfd2_396m", 574 "pll2_pfd0_352m" 575 }; 576 577 static const char *eim_p[] = { 578 "pll2_pfd2_396m", 579 "pll3_usb_otg", 580 "axi", 581 "pll2_pfd0_352m" 582 }; 583 584 static const char *eim_slow_p[] = { 585 "axi", 586 "pll3_usb_otg", 587 "pll2_pfd2_396m", 588 "pll2_pfd0_352m" 589 }; 590 591 static const char *enfc_p[] = { 592 "pll2_pfd0_352m", 593 "pll2_bus", 594 "pll3_usb_otg", 595 "pll2_pfd2_396m" 596 }; 597 598 static const char *lvds_p[] = { 599 "dummy", 600 "dummy", 601 "dummy", 602 "dummy", 603 "dummy", 604 "dummy", 605 "pll4_audio", 606 "pll5_video", 607 "pll8_mlb", 608 "enet_ref", 609 "pcie_ref_125m", 610 "sata_ref_100m" 611 }; 612 613 /* DT clock ID to clock name mappings */ 614 static struct imx_clock_id { 615 u_int id; 616 const char *name; 617 } imx6q_clock_ids[] = { 618 { IMX6QCLK_DUMMY, "dummy" }, 619 { IMX6QCLK_CKIL, "ckil" }, 620 { IMX6QCLK_CKIH, "ckih1" }, 621 { IMX6QCLK_OSC, "osc" }, 622 { IMX6QCLK_PLL2_PFD0_352M, "pll2_pfd0_352m" }, 623 { IMX6QCLK_PLL2_PFD1_594M, "pll2_pfd1_594m" }, 624 { IMX6QCLK_PLL2_PFD2_396M, "pll2_pfd2_396m" }, 625 { IMX6QCLK_PLL3_PFD0_720M, "pll3_pfd0_720m" }, 626 { IMX6QCLK_PLL3_PFD1_540M, "pll3_pfd1_540m" }, 627 { IMX6QCLK_PLL3_PFD2_508M, "pll3_pfd2_508m" }, 628 { IMX6QCLK_PLL3_PFD3_454M, "pll3_pfd3_454m" }, 629 { IMX6QCLK_PLL2_198M, "pll2_198m" }, 630 { IMX6QCLK_PLL3_120M, "pll3_120m" }, 631 { IMX6QCLK_PLL3_80M, "pll3_80m" }, 632 { IMX6QCLK_PLL3_60M, "pll3_60m" }, 633 { IMX6QCLK_TWD, "twd" }, 634 { IMX6QCLK_STEP, "step" }, 635 { IMX6QCLK_PLL1_SW, "pll1_sw" }, 636 { IMX6QCLK_PERIPH_PRE, "periph_pre" }, 637 { IMX6QCLK_PERIPH2_PRE, "periph2_pre" }, 638 { IMX6QCLK_PERIPH_CLK2_SEL, "periph_clk2_sel" }, 639 { IMX6QCLK_PERIPH2_CLK2_SEL, "periph2_clk2_sel" }, 640 { IMX6QCLK_AXI_SEL, "axi_sel" }, 641 { IMX6QCLK_ESAI_SEL, "esai_sel" }, 642 { IMX6QCLK_ASRC_SEL, "asrc_sel" }, 643 { IMX6QCLK_SPDIF_SEL, "spdif_sel" }, 644 { IMX6QCLK_GPU2D_AXI, "gpu2d_axi" }, 645 { IMX6QCLK_GPU3D_AXI, "gpu3d_axi" }, 646 { IMX6QCLK_GPU2D_CORE_SEL, "gpu2d_core_sel" }, 647 { IMX6QCLK_GPU3D_CORE_SEL, "gpu3d_core_sel" }, 648 { IMX6QCLK_GPU3D_SHADER_SEL, "gpu3d_shader_sel" }, 649 { IMX6QCLK_IPU1_SEL, "ipu1_sel" }, 650 { IMX6QCLK_IPU2_SEL, "ipu2_sel" }, 651 { IMX6QCLK_LDB_DI0_SEL, "ldb_di0_sel" }, 652 { IMX6QCLK_LDB_DI1_SEL, "ldb_di1_sel" }, 653 { IMX6QCLK_IPU1_DI0_PRE_SEL, "ipu1_di0_pre_sel" }, 654 { IMX6QCLK_IPU1_DI1_PRE_SEL, "ipu1_di1_pre_sel" }, 655 { IMX6QCLK_IPU2_DI0_PRE_SEL, "ipu2_di0_pre_sel" }, 656 { IMX6QCLK_IPU2_DI1_PRE_SEL, "ipu2_di1_pre_sel" }, 657 { IMX6QCLK_IPU1_DI0_SEL, "ipu1_di0_sel" }, 658 { IMX6QCLK_IPU1_DI1_SEL, "ipu1_di1_sel" }, 659 { IMX6QCLK_IPU2_DI0_SEL, "ipu2_di0_sel" }, 660 { IMX6QCLK_IPU2_DI1_SEL, "ipu2_di1_sel" }, 661 { IMX6QCLK_HSI_TX_SEL, "hsi_tx_sel" }, 662 { IMX6QCLK_PCIE_AXI_SEL, "pcie_axi_sel" }, 663 { IMX6QCLK_SSI1_SEL, "ssi1_sel" }, 664 { IMX6QCLK_SSI2_SEL, "ssi2_sel" }, 665 { IMX6QCLK_SSI3_SEL, "ssi3_sel" }, 666 { IMX6QCLK_USDHC1_SEL, "usdhc1_sel" }, 667 { IMX6QCLK_USDHC2_SEL, "usdhc2_sel" }, 668 { IMX6QCLK_USDHC3_SEL, "usdhc3_sel" }, 669 { IMX6QCLK_USDHC4_SEL, "usdhc4_sel" }, 670 { IMX6QCLK_ENFC_SEL, "enfc_sel" }, 671 { IMX6QCLK_EIM_SEL, "eim_sel" }, 672 { IMX6QCLK_EIM_SLOW_SEL, "eim_slow_sel" }, 673 { IMX6QCLK_VDO_AXI_SEL, "vdo_axi_sel" }, 674 { IMX6QCLK_VPU_AXI_SEL, "vpu_axi_sel" }, 675 { IMX6QCLK_CKO1_SEL, "cko1_sel" }, 676 { IMX6QCLK_PERIPH, "periph" }, 677 { IMX6QCLK_PERIPH2, "periph2" }, 678 { IMX6QCLK_PERIPH_CLK2, "periph_clk2" }, 679 { IMX6QCLK_PERIPH2_CLK2, "periph2_clk2" }, 680 { IMX6QCLK_IPG, "ipg" }, 681 { IMX6QCLK_IPG_PER, "ipg_per" }, 682 { IMX6QCLK_ESAI_PRED, "esai_pred" }, 683 { IMX6QCLK_ESAI_PODF, "esai_podf" }, 684 { IMX6QCLK_ASRC_PRED, "asrc_pred" }, 685 { IMX6QCLK_ASRC_PODF, "asrc_podf" }, 686 { IMX6QCLK_SPDIF_PRED, "spdif_pred" }, 687 { IMX6QCLK_SPDIF_PODF, "spdif_podf" }, 688 { IMX6QCLK_CAN_ROOT, "can_root" }, 689 { IMX6QCLK_ECSPI_ROOT, "ecspi_root" }, 690 { IMX6QCLK_GPU2D_CORE_PODF, "gpu2d_core_podf" }, 691 { IMX6QCLK_GPU3D_CORE_PODF, "gpu3d_core_podf" }, 692 { IMX6QCLK_GPU3D_SHADER, "gpu3d_shader" }, 693 { IMX6QCLK_IPU1_PODF, "ipu1_podf" }, 694 { IMX6QCLK_IPU2_PODF, "ipu2_podf" }, 695 { IMX6QCLK_LDB_DI0_PODF, "ldb_di0_podf" }, 696 { IMX6QCLK_LDB_DI1_PODF, "ldb_di1_podf" }, 697 { IMX6QCLK_IPU1_DI0_PRE, "ipu1_di0_pre" }, 698 { IMX6QCLK_IPU1_DI1_PRE, "ipu1_di1_pre" }, 699 { IMX6QCLK_IPU2_DI0_PRE, "ipu2_di0_pre" }, 700 { IMX6QCLK_IPU2_DI1_PRE, "ipu2_di1_pre" }, 701 { IMX6QCLK_HSI_TX_PODF, "hsi_tx_podf" }, 702 { IMX6QCLK_SSI1_PRED, "ssi1_pred" }, 703 { IMX6QCLK_SSI1_PODF, "ssi1_podf" }, 704 { IMX6QCLK_SSI2_PRED, "ssi2_pred" }, 705 { IMX6QCLK_SSI2_PODF, "ssi2_podf" }, 706 { IMX6QCLK_SSI3_PRED, "ssi3_pred" }, 707 { IMX6QCLK_SSI3_PODF, "ssi3_podf" }, 708 { IMX6QCLK_UART_SERIAL_PODF, "uart_serial_podf" }, 709 { IMX6QCLK_USDHC1_PODF, "usdhc1_podf" }, 710 { IMX6QCLK_USDHC2_PODF, "usdhc2_podf" }, 711 { IMX6QCLK_USDHC3_PODF, "usdhc3_podf" }, 712 { IMX6QCLK_USDHC4_PODF, "usdhc4_podf" }, 713 { IMX6QCLK_ENFC_PRED, "enfc_pred" }, 714 { IMX6QCLK_ENFC_PODF, "enfc_podf" }, 715 { IMX6QCLK_EIM_PODF, "eim_podf" }, 716 { IMX6QCLK_EIM_SLOW_PODF, "eim_slow_podf" }, 717 { IMX6QCLK_VPU_AXI_PODF, "vpu_axi_podf" }, 718 { IMX6QCLK_CKO1_PODF, "cko1_podf" }, 719 { IMX6QCLK_AXI, "axi" }, 720 { IMX6QCLK_MMDC_CH0_AXI_PODF, "mmdc_ch0_axi_podf" }, 721 { IMX6QCLK_MMDC_CH1_AXI_PODF, "mmdc_ch1_axi_podf" }, 722 { IMX6QCLK_ARM, "arm" }, 723 { IMX6QCLK_AHB, "ahb" }, 724 { IMX6QCLK_APBH_DMA, "apbh_dma" }, 725 { IMX6QCLK_ASRC, "asrc" }, 726 { IMX6QCLK_CAN1_IPG, "can1_ipg" }, 727 { IMX6QCLK_CAN1_SERIAL, "can1_serial" }, 728 { IMX6QCLK_CAN2_IPG, "can2_ipg" }, 729 { IMX6QCLK_CAN2_SERIAL, "can2_serial" }, 730 { IMX6QCLK_ECSPI1, "ecspi1" }, 731 { IMX6QCLK_ECSPI2, "ecspi2" }, 732 { IMX6QCLK_ECSPI3, "ecspi3" }, 733 { IMX6QCLK_ECSPI4, "ecspi4" }, 734 { IMX6QCLK_ECSPI5, "ecspi5" }, 735 { IMX6QCLK_ENET, "enet" }, 736 { IMX6QCLK_ESAI_EXTAL, "esai_extal" }, 737 { IMX6QCLK_GPT_IPG, "gpt_ipg" }, 738 { IMX6QCLK_GPT_IPG_PER, "gpt_ipg_per" }, 739 { IMX6QCLK_GPU2D_CORE, "gpu2d_core" }, 740 { IMX6QCLK_GPU3D_CORE, "gpu3d_core" }, 741 { IMX6QCLK_HDMI_IAHB, "hdmi_iahb" }, 742 { IMX6QCLK_HDMI_ISFR, "hdmi_isfr" }, 743 { IMX6QCLK_I2C1, "i2c1" }, 744 { IMX6QCLK_I2C2, "i2c2" }, 745 { IMX6QCLK_I2C3, "i2c3" }, 746 { IMX6QCLK_IIM, "iim" }, 747 { IMX6QCLK_ENFC, "enfc" }, 748 { IMX6QCLK_IPU1, "ipu1" }, 749 { IMX6QCLK_IPU1_DI0, "ipu1_di0" }, 750 { IMX6QCLK_IPU1_DI1, "ipu1_di1" }, 751 { IMX6QCLK_IPU2, "ipu2" }, 752 { IMX6QCLK_IPU2_DI0, "ipu2_di0" }, 753 { IMX6QCLK_LDB_DI0, "ldb_di0" }, 754 { IMX6QCLK_LDB_DI1, "ldb_di1" }, 755 { IMX6QCLK_IPU2_DI1, "ipu2_di1" }, 756 { IMX6QCLK_HSI_TX, "hsi_tx" }, 757 { IMX6QCLK_MLB, "mlb" }, 758 { IMX6QCLK_MMDC_CH0_AXI, "mmdc_ch0_axi" }, 759 { IMX6QCLK_MMDC_CH1_AXI, "mmdc_ch1_axi" }, 760 { IMX6QCLK_OCRAM, "ocram" }, 761 { IMX6QCLK_OPENVG_AXI, "openvg_axi" }, 762 { IMX6QCLK_PCIE_AXI, "pcie_axi" }, 763 { IMX6QCLK_PWM1, "pwm1" }, 764 { IMX6QCLK_PWM2, "pwm2" }, 765 { IMX6QCLK_PWM3, "pwm3" }, 766 { IMX6QCLK_PWM4, "pwm4" }, 767 { IMX6QCLK_PER1_BCH, "per1_bch" }, 768 { IMX6QCLK_GPMI_BCH_APB, "gpmi_bch_apb" }, 769 { IMX6QCLK_GPMI_BCH, "gpmi_bch" }, 770 { IMX6QCLK_GPMI_IO, "gpmi_io" }, 771 { IMX6QCLK_GPMI_APB, "gpmi_apb" }, 772 { IMX6QCLK_SATA, "sata" }, 773 { IMX6QCLK_SDMA, "sdma" }, 774 { IMX6QCLK_SPBA, "spba" }, 775 { IMX6QCLK_SSI1, "ssi1" }, 776 { IMX6QCLK_SSI2, "ssi2" }, 777 { IMX6QCLK_SSI3, "ssi3" }, 778 { IMX6QCLK_UART_IPG, "uart_ipg" }, 779 { IMX6QCLK_UART_SERIAL, "uart_serial" }, 780 { IMX6QCLK_USBOH3, "usboh3" }, 781 { IMX6QCLK_USDHC1, "usdhc1" }, 782 { IMX6QCLK_USDHC2, "usdhc2" }, 783 { IMX6QCLK_USDHC3, "usdhc3" }, 784 { IMX6QCLK_USDHC4, "usdhc4" }, 785 { IMX6QCLK_VDO_AXI, "vdo_axi" }, 786 { IMX6QCLK_VPU_AXI, "vpu_axi" }, 787 { IMX6QCLK_CKO1, "cko1" }, 788 { IMX6QCLK_PLL1_SYS, "pll1_sys" }, 789 { IMX6QCLK_PLL2_BUS, "pll2_bus" }, 790 { IMX6QCLK_PLL3_USB_OTG, "pll3_usb_otg" }, 791 { IMX6QCLK_PLL4_AUDIO, "pll4_audio" }, 792 { IMX6QCLK_PLL5_VIDEO, "pll5_video" }, 793 { IMX6QCLK_PLL8_MLB, "pll8_mlb" }, 794 { IMX6QCLK_PLL7_USB_HOST, "pll7_usb_host" }, 795 { IMX6QCLK_PLL6_ENET, "pll6_enet" }, 796 { IMX6QCLK_SSI1_IPG, "ssi1_ipg" }, 797 { IMX6QCLK_SSI2_IPG, "ssi2_ipg" }, 798 { IMX6QCLK_SSI3_IPG, "ssi3_ipg" }, 799 { IMX6QCLK_ROM, "rom" }, 800 { IMX6QCLK_USBPHY1, "usbphy1" }, 801 { IMX6QCLK_USBPHY2, "usbphy2" }, 802 { IMX6QCLK_LDB_DI0_DIV_3_5, "ldb_di0_div_3_5" }, 803 { IMX6QCLK_LDB_DI1_DIV_3_5, "ldb_di1_div_3_5" }, 804 { IMX6QCLK_SATA_REF, "sata_ref" }, 805 { IMX6QCLK_SATA_REF_100M, "sata_ref_100m" }, 806 { IMX6QCLK_PCIE_REF, "pcie_ref" }, 807 { IMX6QCLK_PCIE_REF_125M, "pcie_ref_125m" }, 808 { IMX6QCLK_ENET_REF, "enet_ref" }, 809 { IMX6QCLK_USBPHY1_GATE, "usbphy1_gate" }, 810 { IMX6QCLK_USBPHY2_GATE, "usbphy2_gate" }, 811 { IMX6QCLK_PLL4_POST_DIV, "pll4_post_div" }, 812 { IMX6QCLK_PLL5_POST_DIV, "pll5_post_div" }, 813 { IMX6QCLK_PLL5_VIDEO_DIV, "pll5_video_div" }, 814 { IMX6QCLK_EIM_SLOW, "eim_slow" }, 815 { IMX6QCLK_SPDIF, "spdif" }, 816 { IMX6QCLK_CKO2_SEL, "cko2_sel" }, 817 { IMX6QCLK_CKO2_PODF, "cko2_podf" }, 818 { IMX6QCLK_CKO2, "cko2" }, 819 { IMX6QCLK_CKO, "cko" }, 820 { IMX6QCLK_VDOA, "vdoa" }, 821 { IMX6QCLK_PLL4_AUDIO_DIV, "pll4_audio_div" }, 822 { IMX6QCLK_LVDS1_SEL, "lvds1_sel" }, 823 { IMX6QCLK_LVDS2_SEL, "lvds2_sel" }, 824 { IMX6QCLK_LVDS1_GATE, "lvds1_gate" }, 825 { IMX6QCLK_LVDS2_GATE, "lvds2_gate" }, 826 { IMX6QCLK_ESAI_IPG, "esai_ipg" }, 827 { IMX6QCLK_ESAI_MEM, "esai_mem" }, 828 { IMX6QCLK_ASRC_IPG, "asrc_ipg" }, 829 { IMX6QCLK_ASRC_MEM, "asrc_mem" }, 830 { IMX6QCLK_LVDS1_IN, "lvds1_in" }, 831 { IMX6QCLK_LVDS2_IN, "lvds2_in" }, 832 { IMX6QCLK_ANACLK1, "anaclk1" }, 833 { IMX6QCLK_ANACLK2, "anaclk2" }, 834 { IMX6QCLK_PLL1_BYPASS_SRC, "pll1_bypass_src" }, 835 { IMX6QCLK_PLL2_BYPASS_SRC, "pll2_bypass_src" }, 836 { IMX6QCLK_PLL3_BYPASS_SRC, "pll3_bypass_src" }, 837 { IMX6QCLK_PLL4_BYPASS_SRC, "pll4_bypass_src" }, 838 { IMX6QCLK_PLL5_BYPASS_SRC, "pll5_bypass_src" }, 839 { IMX6QCLK_PLL6_BYPASS_SRC, "pll6_bypass_src" }, 840 { IMX6QCLK_PLL7_BYPASS_SRC, "pll7_bypass_src" }, 841 { IMX6QCLK_PLL1, "pll1" }, 842 { IMX6QCLK_PLL2, "pll2" }, 843 { IMX6QCLK_PLL3, "pll3" }, 844 { IMX6QCLK_PLL4, "pll4" }, 845 { IMX6QCLK_PLL5, "pll5" }, 846 { IMX6QCLK_PLL6, "pll6" }, 847 { IMX6QCLK_PLL7, "pll7" }, 848 { IMX6QCLK_PLL1_BYPASS, "pll1_bypass" }, 849 { IMX6QCLK_PLL2_BYPASS, "pll2_bypass" }, 850 { IMX6QCLK_PLL3_BYPASS, "pll3_bypass" }, 851 { IMX6QCLK_PLL4_BYPASS, "pll4_bypass" }, 852 { IMX6QCLK_PLL5_BYPASS, "pll5_bypass" }, 853 { IMX6QCLK_PLL6_BYPASS, "pll6_bypass" }, 854 { IMX6QCLK_PLL7_BYPASS, "pll7_bypass" }, 855 { IMX6QCLK_GPT_3M, "gpt_3m" }, 856 { IMX6QCLK_VIDEO_27M, "video_27m" }, 857 { IMX6QCLK_MIPI_CORE_CFG, "mipi_core_cfg" }, 858 { IMX6QCLK_MIPI_IPG, "mipi_ipg" }, 859 { IMX6QCLK_CAAM_MEM, "caam_mem" }, 860 { IMX6QCLK_CAAM_ACLK, "caam_aclk" }, 861 { IMX6QCLK_CAAM_IPG, "caam_ipg" }, 862 { IMX6QCLK_SPDIF_GCLK, "spdif_gclk" }, 863 { IMX6QCLK_UART_SEL, "uart_sel" }, 864 { IMX6QCLK_IPG_PER_SEL, "ipg_per_sel" }, 865 { IMX6QCLK_ECSPI_SEL, "ecspi_sel" }, 866 { IMX6QCLK_CAN_SEL, "can_sel" }, 867 { IMX6QCLK_MMDC_CH1_AXI_CG, "mmdc_ch1_axi_cg" }, 868 { IMX6QCLK_PRE0, "pre0" }, 869 { IMX6QCLK_PRE1, "pre1" }, 870 { IMX6QCLK_PRE2, "pre2" }, 871 { IMX6QCLK_PRE3, "pre3" }, 872 { IMX6QCLK_PRG0_AXI, "prg0_axi" }, 873 { IMX6QCLK_PRG1_AXI, "prg1_axi" }, 874 { IMX6QCLK_PRG0_APB, "prg0_apb" }, 875 { IMX6QCLK_PRG1_APB, "prg1_apb" }, 876 { IMX6QCLK_PRE_AXI, "pre_axi" }, 877 { IMX6QCLK_MLB_SEL, "mlb_sel" }, 878 { IMX6QCLK_MLB_PODF, "mlb_podf" }, 879 { IMX6QCLK_END, "end" }, 880 }; 881 882 /* Clock Divider Tables */ 883 static const int enet_ref_tbl[] = { 20, 10, 5, 4, 0 }; 884 static const int post_div_tbl[] = { 4, 2, 1, 0 }; 885 static const int audiovideo_div_tbl[] = { 1, 2, 1, 4, 0 }; 886 887 static struct imx6_clk imx6q_clks[] = { 888 CLK_FIXED("dummy", 0), 889 890 CLK_FIXED("ckil", IMX6_CKIL_FREQ), 891 CLK_FIXED("ckih1", IMX6_CKIH_FREQ), 892 CLK_FIXED("osc", IMX6_OSC_FREQ), 893 CLK_FIXED("anaclk1", IMX6_ANACLK1_FREQ), 894 CLK_FIXED("anaclk2", IMX6_ANACLK2_FREQ), 895 896 CLK_FIXED_FACTOR("sata_ref", "pll6_enet", 5, 1), 897 CLK_FIXED_FACTOR("pcie_ref", "pll6_enet", 4, 1), 898 CLK_FIXED_FACTOR("pll2_198m", "pll2_pfd2_396m", 2, 1), 899 CLK_FIXED_FACTOR("pll3_120m", "pll3_usb_otg", 4, 1), 900 CLK_FIXED_FACTOR("pll3_80m", "pll3_usb_otg", 6, 1), 901 CLK_FIXED_FACTOR("pll3_60m", "pll3_usb_otg", 8, 1), 902 CLK_FIXED_FACTOR("twd", "arm", 2, 1), 903 CLK_FIXED_FACTOR("gpt_3m", "osc", 8, 1), 904 CLK_FIXED_FACTOR("video_27m", "pll3_pfd1_540m", 20, 1), 905 CLK_FIXED_FACTOR("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1), 906 CLK_FIXED_FACTOR("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1), 907 CLK_FIXED_FACTOR("ldb_di0_div_3_5", "ldb_di0_sel", 7, 2), 908 CLK_FIXED_FACTOR("ldb_di1_div_3_5", "ldb_di1_sel", 7, 2), 909 910 CLK_PFD("pll2_pfd0_352m", "pll2_bus", PFD_528, 0), 911 CLK_PFD("pll2_pfd1_594m", "pll2_bus", PFD_528, 1), 912 CLK_PFD("pll2_pfd2_396m", "pll2_bus", PFD_528, 2), 913 CLK_PFD("pll3_pfd0_720m", "pll3_usb_otg", PFD_480, 0), 914 CLK_PFD("pll3_pfd1_540m", "pll3_usb_otg", PFD_480, 1), 915 CLK_PFD("pll3_pfd2_508m", "pll3_usb_otg", PFD_480, 2), 916 CLK_PFD("pll3_pfd3_454m", "pll3_usb_otg", PFD_480, 3), 917 918 CLK_PLL("pll1", "osc", SYS, PLL_ARM, DIV_SELECT, POWERDOWN, 0), 919 CLK_PLL("pll2", "osc", GENERIC, PLL_SYS, DIV_SELECT, POWERDOWN, 0), 920 CLK_PLL("pll3", "osc", USB, PLL_USB1, DIV_SELECT, POWER, 0), 921 CLK_PLL("pll4", "osc", AUDIO_VIDEO, PLL_AUDIO, DIV_SELECT, POWERDOWN, 0), 922 CLK_PLL("pll5", "osc", AUDIO_VIDEO, PLL_VIDEO, DIV_SELECT, POWERDOWN, 0), 923 CLK_PLL("pll6", "osc", ENET, PLL_ENET, DIV_SELECT, POWERDOWN, 500000000), 924 CLK_PLL("pll7", "osc", USB, PLL_USB2, DIV_SELECT, POWER, 0), 925 926 CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF), 927 CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF), 928 CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF), 929 CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED), 930 CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF), 931 CLK_DIV("asrc_pred", "asrc_sel", CDCDR, SPDIF1_CLK_PRED), 932 CLK_DIV("asrc_podf", "asrc_pred", CDCDR, SPDIF1_CLK_PODF), 933 CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED), 934 CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF), 935 CLK_DIV("ecspi_root", "pll3_60m", CSCDR2, ECSPI_CLK_PODF), 936 CLK_DIV("can_root", "pll3_60m", CSCMR2, CAN_CLK_PODF), 937 CLK_DIV("uart_serial_podf", "pll3_80m", CSCDR1, UART_CLK_PODF), 938 CLK_DIV("gpu2d_core_podf", "gpu2d_core_sel", CBCMR, GPU2D_CORE_CLK_PODF), 939 CLK_DIV("gpu3d_core_podf", "gpu3d_core_sel", CBCMR, GPU3D_CORE_PODF), 940 CLK_DIV("gpu3d_shader", "gpu3d_shader_sel", CBCMR, GPU3D_SHADER_PODF), 941 CLK_DIV("ipu1_podf", "ipu1_sel", CSCDR3, IPU1_HSP_PODF), 942 CLK_DIV("ipu2_podf", "ipu2_sel", CSCDR3, IPU2_HSP_PODF), 943 CLK_DIV("ldb_di0_podf", "ldb_di0_div_3_5", CSCMR2, LDB_DI0_IPU_DIV), 944 CLK_DIV("ldb_di1_podf", "ldb_di1_div_3_5", CSCMR2, LDB_DI1_IPU_DIV), 945 CLK_DIV("ipu1_di0_pre", "ipu1_di0_pre_sel", CHSCCDR, IPU1_DI0_PODF), 946 CLK_DIV("ipu1_di1_pre", "ipu1_di1_pre_sel", CHSCCDR, IPU1_DI1_PODF), 947 CLK_DIV("ipu2_di0_pre", "ipu2_di0_pre_sel", CSCDR2, IPU2_DI0_PODF), 948 CLK_DIV("ipu2_di1_pre", "ipu2_di1_pre_sel", CSCDR2, IPU2_DI1_PODF), 949 CLK_DIV("hsi_tx_podf", "hsi_tx_sel", CDCDR, HSI_TX_PODF), 950 CLK_DIV("ssi1_pred", "ssi1_sel", CS1CDR, SSI1_CLK_PRED), 951 CLK_DIV("ssi1_podf", "ssi1_pred", CS1CDR, SSI1_CLK_PODF), 952 CLK_DIV("ssi2_pred", "ssi2_sel", CS2CDR, SSI2_CLK_PRED), 953 CLK_DIV("ssi2_podf", "ssi2_pred", CS2CDR, SSI2_CLK_PODF), 954 CLK_DIV("ssi3_pred", "ssi3_sel", CS1CDR, SSI3_CLK_PRED), 955 CLK_DIV("ssi3_podf", "ssi3_pred", CS1CDR, SSI3_CLK_PODF), 956 CLK_DIV("usdhc1_podf", "usdhc1_sel", CSCDR1, USDHC1_PODF), 957 CLK_DIV("usdhc2_podf", "usdhc2_sel", CSCDR1, USDHC2_PODF), 958 CLK_DIV("usdhc3_podf", "usdhc3_sel", CSCDR1, USDHC3_PODF), 959 CLK_DIV("usdhc4_podf", "usdhc4_sel", CSCDR1, USDHC4_PODF), 960 CLK_DIV("enfc_pred", "enfc_sel", CS2CDR, ENFC_CLK_PRED), 961 CLK_DIV("enfc_podf", "enfc_pred", CS2CDR, ENFC_CLK_PODF), 962 CLK_DIV("vpu_axi_podf", "vpu_axi_sel", CSCDR1, VPU_AXI_PODF), 963 CLK_DIV("cko1_podf", "cko1_sel", CCOSR, CLKO1_DIV), 964 CLK_DIV("cko2_podf", "cko2_sel", CCOSR, CLKO2_DIV), 965 CLK_DIV("ipg_per", "ipg", CSCMR1, PERCLK_PODF), 966 CLK_DIV("eim_podf", "eim_sel", CSCMR1, ACLK_PODF), 967 CLK_DIV("eim_slow_podf", "eim_slow_sel", CSCMR1, ACLK_EIM_SLOW_PODF), 968 969 CLK_DIV_BUSY("axi", "axi_sel", CBCDR, AXI_PODF, CDHIPR, AXI_PODF_BUSY), 970 CLK_DIV_BUSY("mmdc_ch0_axi_podf", "periph", CBCDR, MMDC_CH0_AXI_PODF, CDHIPR, MMDC_CH0_PODF_BUSY), 971 CLK_DIV_BUSY("mmdc_ch1_axi_podf", "periph2", CBCDR, MMDC_CH1_AXI_PODF, CDHIPR, MMDC_CH1_PODF_BUSY), 972 CLK_DIV_BUSY("arm", "pll1_sw", CACRR, ARM_PODF, CDHIPR, ARM_PODF_BUSY), 973 CLK_DIV_BUSY("ahb", "periph", CBCDR, AHB_PODF, CDHIPR, AHB_PODF_BUSY), 974 975 CLK_DIV_TABLE("pll4_post_div", "pll4_audio", PLL_AUDIO, POST_DIV_SELECT, post_div_tbl), 976 CLK_DIV_TABLE("pll4_audio_div", "pll4_post_div", MISC2, AUDIO_DIV_LSB, audiovideo_div_tbl), 977 CLK_DIV_TABLE("pll5_post_div", "pll5_video", PLL_VIDEO, POST_DIV_SELECT, post_div_tbl), 978 CLK_DIV_TABLE("pll5_video_div", "pll5_post_div", MISC2, VIDEO_DIV, audiovideo_div_tbl), 979 CLK_DIV_TABLE("enet_ref", "pll6_enet", PLL_ENET, DIV_SELECT, enet_ref_tbl), 980 981 CLK_MUX("step", step_p, CCM, CCSR, STEP_SEL), 982 CLK_MUX("pll1_sw", pll1_sw_p, CCM, CCSR, PLL1_SW_CLK_SEL), 983 CLK_MUX("periph_pre", periph_pre_p, CCM, CBCMR, PRE_PERIPH_CLK_SEL), 984 CLK_MUX("periph2_pre", periph_pre_p, CCM, CBCMR, PRE_PERIPH2_CLK_SEL), 985 CLK_MUX("periph_clk2_sel", periph_clk2_p, CCM,CBCMR, PERIPH_CLK2_SEL), 986 CLK_MUX("periph2_clk2_sel", periph2_clk2_p, CCM,CBCMR, PERIPH2_CLK2_SEL), 987 CLK_MUX("axi_sel", axi_p, CCM, CBCDR, AXI_SEL), 988 CLK_MUX("asrc_sel", audio_p, CCM, CDCDR, SPDIF1_CLK_SEL), 989 CLK_MUX("spdif_sel", audio_p, CCM, CDCDR, SPDIF0_CLK_SEL), 990 CLK_MUX("gpu2d_core_sel", gpu2d_core_p, CCM, CBCMR, GPU2D_CLK_SEL), 991 CLK_MUX("gpu3d_core_sel", gpu3d_core_p, CCM, CBCMR, GPU3D_CORE_CLK_SEL), 992 CLK_MUX("gpu3d_shader_sel", gpu3d_shader_p, CCM,CBCMR, GPU3D_SHADER_CLK_SEL), 993 CLK_MUX("esai_sel", audio_p, CCM, CSCMR2, ESAI_CLK_SEL), 994 CLK_MUX("ipu1_sel", ipu_p, CCM, CSCDR3, IPU1_HSP_CLK_SEL), 995 CLK_MUX("ipu2_sel", ipu_p, CCM, CSCDR3, IPU2_HSP_CLK_SEL), 996 CLK_MUX("ipu1_di0_pre_sel", ipu_di_pre_p, CCM, CHSCCDR, IPU1_DI0_PRE_CLK_SEL), 997 CLK_MUX("ipu1_di1_pre_sel", ipu_di_pre_p, CCM, CHSCCDR, IPU1_DI1_PRE_CLK_SEL), 998 CLK_MUX("ipu2_di0_pre_sel", ipu_di_pre_p, CCM, CSCDR2, IPU2_DI0_PRE_CLK_SEL), 999 CLK_MUX("ipu2_di1_pre_sel", ipu_di_pre_p, CCM, CSCDR2, IPU2_DI1_PRE_CLK_SEL), 1000 CLK_MUX("ipu1_di0_sel", ipu1_di0_p, CCM, CHSCCDR, IPU1_DI0_CLK_SEL), 1001 CLK_MUX("ipu1_di1_sel", ipu1_di1_p, CCM, CHSCCDR, IPU1_DI1_CLK_SEL), 1002 CLK_MUX("ipu2_di0_sel", ipu2_di0_p, CCM, CSCDR2, IPU2_DI0_CLK_SEL), 1003 CLK_MUX("ipu2_di1_sel", ipu2_di1_p, CCM, CSCDR2, IPU2_DI1_CLK_SEL), 1004 CLK_MUX("ldb_di0_sel", ldb_di_p, CCM, CS2CDR, LDB_DI0_CLK_SEL), 1005 CLK_MUX("ldb_di1_sel", ldb_di_p, CCM, CS2CDR, LDB_DI1_CLK_SEL), 1006 CLK_MUX("vdo_axi_sel", vdo_axi_p, CCM, CBCMR, VDOAXI_CLK_SEL), 1007 CLK_MUX("vpu_axi_sel", vpu_axi_p, CCM, CBCMR, VPU_AXI_CLK_SEL), 1008 CLK_MUX("cko1_sel", cko1_p, CCM, CCOSR, CLKO1_SEL), 1009 CLK_MUX("cko2_sel", cko2_p, CCM, CCOSR, CLKO2_SEL), 1010 CLK_MUX("cko", cko_p, CCM, CCOSR, CLK_OUT_SEL), 1011 CLK_MUX("hsi_tx_sel", hsi_tx_p, CCM, CDCDR, HSI_TX_CLK_SEL), 1012 CLK_MUX("pcie_axi_sel", pcie_axi_p, CCM, CBCMR, PCIE_AXI_CLK_SEL), 1013 CLK_MUX("ssi1_sel", ssi_p, CCM, CSCMR1, SSI1_CLK_SEL), 1014 CLK_MUX("ssi2_sel", ssi_p, CCM, CSCMR1, SSI2_CLK_SEL), 1015 CLK_MUX("ssi3_sel", ssi_p, CCM, CSCMR1, SSI3_CLK_SEL), 1016 CLK_MUX("usdhc1_sel", usdhc_p, CCM, CSCMR1, USDHC1_CLK_SEL), 1017 CLK_MUX("usdhc2_sel", usdhc_p, CCM, CSCMR1, USDHC2_CLK_SEL), 1018 CLK_MUX("usdhc3_sel", usdhc_p, CCM, CSCMR1, USDHC3_CLK_SEL), 1019 CLK_MUX("usdhc4_sel", usdhc_p, CCM, CSCMR1, USDHC4_CLK_SEL), 1020 CLK_MUX("eim_sel", eim_p, CCM, CSCMR1, ACLK_SEL), 1021 CLK_MUX("eim_slow_sel", eim_slow_p, CCM, CSCMR1, ACLK_EIM_SLOW_SEL), 1022 CLK_MUX("enfc_sel", enfc_p, CCM, CS2CDR, ENFC_CLK_SEL), 1023 1024 CLK_MUX("pll1_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_ARM, BYPASS_CLK_SRC), 1025 CLK_MUX("pll2_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_SYS, BYPASS_CLK_SRC), 1026 CLK_MUX("pll3_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_USB1, BYPASS_CLK_SRC), 1027 CLK_MUX("pll4_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_AUDIO, BYPASS_CLK_SRC), 1028 CLK_MUX("pll5_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_VIDEO, BYPASS_CLK_SRC), 1029 CLK_MUX("pll6_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_ENET, BYPASS_CLK_SRC), 1030 CLK_MUX("pll7_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_USB2, BYPASS_CLK_SRC), 1031 CLK_MUX("pll1_bypass", pll1_bypass_p, CCM_ANALOG, PLL_ARM, BYPASS), 1032 CLK_MUX("pll2_bypass", pll2_bypass_p, CCM_ANALOG, PLL_SYS, BYPASS), 1033 CLK_MUX("pll3_bypass", pll3_bypass_p, CCM_ANALOG, PLL_USB1, BYPASS), 1034 CLK_MUX("pll4_bypass", pll4_bypass_p, CCM_ANALOG, PLL_AUDIO, BYPASS), 1035 CLK_MUX("pll5_bypass", pll5_bypass_p, CCM_ANALOG, PLL_VIDEO, BYPASS), 1036 CLK_MUX("pll6_bypass", pll6_bypass_p, CCM_ANALOG, PLL_ENET, BYPASS), 1037 CLK_MUX("pll7_bypass", pll7_bypass_p, CCM_ANALOG, PLL_USB2, BYPASS), 1038 1039 CLK_MUX("lvds1_sel", lvds_p, CCM_ANALOG, MISC1, LVDS_CLK1_SRC), 1040 CLK_MUX("lvds2_sel", lvds_p, CCM_ANALOG, MISC1, LVDS_CLK2_SRC), 1041 1042 CLK_MUX_BUSY("periph", periph_p, CBCDR, PERIPH_CLK_SEL, CDHIPR, PERIPH_CLK_SEL_BUSY), 1043 CLK_MUX_BUSY("periph2", periph2_p, CBCDR, PERIPH2_CLK_SEL, CDHIPR, PERIPH2_CLK_SEL_BUSY), 1044 1045 CLK_GATE("apbh_dma", "usdhc3", CCM, CCGR0, APBHDMA_HCLK_ENABLE), 1046 CLK_GATE("asrc", "asrc_podf", CCM, CCGR0, ASRC_CLK_ENABLE), 1047 CLK_GATE("asrc_ipg", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE), 1048 CLK_GATE("asrc_mem", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE), 1049 CLK_GATE("caam_mem", "ahb", CCM, CCGR0, CAAM_SECURE_MEM_CLK_ENABLE), 1050 CLK_GATE("caam_aclk", "ahb", CCM, CCGR0, CAAM_WRAPPER_ACLK_ENABLE), 1051 CLK_GATE("caam_ipg", "ipg", CCM, CCGR0, CAAM_WRAPPER_IPG_ENABLE), 1052 CLK_GATE("can1_ipg", "ipg", CCM, CCGR0, CAN1_CLK_ENABLE), 1053 CLK_GATE("can1_serial", "can_root", CCM, CCGR0, CAN1_SERIAL_CLK_ENABLE), 1054 CLK_GATE("can2_ipg", "ipg", CCM, CCGR0, CAN2_CLK_ENABLE), 1055 CLK_GATE("can2_serial", "can_root", CCM, CCGR0, CAN2_SERIAL_CLK_ENABLE), 1056 CLK_GATE("ecspi1", "ecspi_root", CCM, CCGR1, ECSPI1_CLK_ENABLE), 1057 CLK_GATE("ecspi2", "ecspi_root", CCM, CCGR1, ECSPI2_CLK_ENABLE), 1058 CLK_GATE("ecspi3", "ecspi_root", CCM, CCGR1, ECSPI3_CLK_ENABLE), 1059 CLK_GATE("ecspi4", "ecspi_root", CCM, CCGR1, ECSPI4_CLK_ENABLE), 1060 CLK_GATE("ecspi5", "ecspi_root", CCM, CCGR1, ECSPI5_CLK_ENABLE), 1061 CLK_GATE("enet", "ipg", CCM, CCGR1, ENET_CLK_ENABLE), 1062 CLK_GATE("esai_extal", "esai_podf", CCM, CCGR1, ESAI_CLK_ENABLE), 1063 CLK_GATE("esai_ipg", "ahb", CCM, CCGR1, ESAI_CLK_ENABLE), 1064 CLK_GATE("esai_mem", "ahb", CCM, CCGR1, ESAI_CLK_ENABLE), 1065 CLK_GATE("gpt_ipg", "ipg", CCM, CCGR1, GPT_CLK_ENABLE), 1066 CLK_GATE("gpt_ipg_per", "ipg_per", CCM, CCGR1, GPT_SERIAL_CLK_ENABLE), 1067 CLK_GATE("gpu2d_core", "gpu2d_core_podf", CCM, CCGR1, GPU2D_CLK_ENABLE), 1068 CLK_GATE("gpu3d_core", "gpu3d_core_podf", CCM, CCGR1, GPU3D_CLK_ENABLE), 1069 CLK_GATE("hdmi_iahb", "ahb", CCM, CCGR2, HDMI_TX_IAHBCLK_ENABLE), 1070 CLK_GATE("hdmi_isfr", "video_27m", CCM, CCGR2, HDMI_TX_ISFRCLK_ENABLE), 1071 CLK_GATE("i2c1", "ipg_per", CCM, CCGR2, I2C1_SERIAL_CLK_ENABLE), 1072 CLK_GATE("i2c2", "ipg_per", CCM, CCGR2, I2C2_SERIAL_CLK_ENABLE), 1073 CLK_GATE("i2c3", "ipg_per", CCM, CCGR2, I2C3_SERIAL_CLK_ENABLE), 1074 CLK_GATE("iim", "ipg", CCM, CCGR2, IIM_CLK_ENABLE), 1075 CLK_GATE("enfc", "enfc_podf", CCM, CCGR2, IOMUX_IPT_CLK_IO_CLK_ENABLE), 1076 CLK_GATE("vdoa", "vdo_axi", CCM, CCGR2, IPSYNC_VDOA_IPG_CLK_ENABLE), 1077 CLK_GATE("ipu1", "ipu1_podf", CCM, CCGR3, IPU1_IPU_CLK_ENABLE), 1078 CLK_GATE("ipu1_di0", "ipu1_di0_sel", CCM, CCGR3, IPU1_IPU_DI0_CLK_ENABLE), 1079 CLK_GATE("ipu1_di1", "ipu1_di1_sel", CCM, CCGR3, IPU1_IPU_DI1_CLK_ENABLE), 1080 CLK_GATE("ipu2", "ipu2_podf", CCM, CCGR3, IPU2_IPU_CLK_ENABLE), 1081 CLK_GATE("ipu2_di0", "ipu2_di0_sel", CCM, CCGR3, IPU2_IPU_DI0_CLK_ENABLE), 1082 CLK_GATE("ldb_di0", "ldb_di0_podf", CCM, CCGR3, LDB_DI0_CLK_ENABLE), 1083 CLK_GATE("ldb_di1", "ldb_di1_podf", CCM, CCGR3, LDB_DI1_CLK_ENABLE), 1084 CLK_GATE("ipu2_di1", "ipu2_di1_sel", CCM, CCGR3, IPU2_IPU_DI1_CLK_ENABLE), 1085 CLK_GATE("hsi_tx", "hsi_tx_podf", CCM, CCGR3, MIPI_CORE_CFG_CLK_ENABLE), 1086 CLK_GATE("mipi_core_cfg", "video_27m", CCM, CCGR3, MIPI_CORE_CFG_CLK_ENABLE), 1087 CLK_GATE("mipi_ipg", "ipg", CCM, CCGR3, MIPI_CORE_CFG_CLK_ENABLE), 1088 CLK_GATE("mlb", "axi", CCM, CCGR3, MLB_CLK_ENABLE), 1089 CLK_GATE("mmdc_ch0_axi", "mmdc_ch0_axi_podf", CCM, CCGR3, MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE), 1090 CLK_GATE("mmdc_ch1_axi", "mmdc_ch1_axi_podf", CCM, CCGR3, MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE), 1091 CLK_GATE("ocram", "ahb", CCM, CCGR3, OCRAM_CLK_ENABLE), 1092 CLK_GATE("openvg_axi", "axi", CCM, CCGR3, OPENVGAXICLK_CLK_ROOT_ENABLE), 1093 CLK_GATE("pcie_axi", "pcie_axi_sel", CCM, CCGR4, PCIE_ROOT_ENABLE), 1094 CLK_GATE("per1_bch", "usdhc3", CCM, CCGR4, PL301_MX6QPER1_BCHCLK_ENABLE), 1095 CLK_GATE("pwm1", "ipg_per", CCM, CCGR4, PWM1_CLK_ENABLE), 1096 CLK_GATE("pwm2", "ipg_per", CCM, CCGR4, PWM2_CLK_ENABLE), 1097 CLK_GATE("pwm3", "ipg_per", CCM, CCGR4, PWM3_CLK_ENABLE), 1098 CLK_GATE("pwm4", "ipg_per", CCM, CCGR4, PWM4_CLK_ENABLE), 1099 CLK_GATE("gpmi_bch_apb", "usdhc3", CCM, CCGR4, RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE), 1100 CLK_GATE("gpmi_bch", "usdhc4", CCM, CCGR4, RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE), 1101 CLK_GATE("gpmi_io", "enfc", CCM, CCGR4, RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE), 1102 CLK_GATE("gpmi_apb", "usdhc3", CCM, CCGR4, RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE), 1103 CLK_GATE("rom", "ahb", CCM, CCGR5, ROM_CLK_ENABLE), 1104 CLK_GATE("sata", "ahb", CCM, CCGR5, SATA_CLK_ENABLE), 1105 CLK_GATE("sdma", "ahb", CCM, CCGR5, SDMA_CLK_ENABLE), 1106 CLK_GATE("spba", "ipg", CCM, CCGR5, SPBA_CLK_ENABLE), 1107 CLK_GATE("spdif", "spdif_podf", CCM, CCGR5, SPDIF_CLK_ENABLE), 1108 CLK_GATE("spdif_gclk", "ipg", CCM, CCGR5, SPDIF_CLK_ENABLE), 1109 CLK_GATE("ssi1_ipg", "ipg", CCM, CCGR5, SSI1_CLK_ENABLE), 1110 CLK_GATE("ssi2_ipg", "ipg", CCM, CCGR5, SSI2_CLK_ENABLE), 1111 CLK_GATE("ssi3_ipg", "ipg", CCM, CCGR5, SSI3_CLK_ENABLE), 1112 CLK_GATE("ssi1", "ssi1_podf", CCM, CCGR5, SSI1_CLK_ENABLE), 1113 CLK_GATE("ssi2", "ssi2_podf", CCM, CCGR5, SSI2_CLK_ENABLE), 1114 CLK_GATE("ssi3", "ssi3_podf", CCM, CCGR5, SSI3_CLK_ENABLE), 1115 CLK_GATE("uart_ipg", "ipg", CCM, CCGR5, UART_CLK_ENABLE), 1116 CLK_GATE("uart_serial", "uart_serial_podf", CCM, CCGR5, UART_SERIAL_CLK_ENABLE), 1117 CLK_GATE("usboh3", "ipg", CCM, CCGR6, USBOH3_CLK_ENABLE), 1118 CLK_GATE("usdhc1", "usdhc1_podf", CCM, CCGR6, USDHC1_CLK_ENABLE), 1119 CLK_GATE("usdhc2", "usdhc2_podf", CCM, CCGR6, USDHC2_CLK_ENABLE), 1120 CLK_GATE("usdhc3", "usdhc3_podf", CCM, CCGR6, USDHC3_CLK_ENABLE), 1121 CLK_GATE("usdhc4", "usdhc4_podf", CCM, CCGR6, USDHC4_CLK_ENABLE), 1122 CLK_GATE("eim_slow", "eim_slow_podf", CCM, CCGR6, EIM_SLOW_CLK_ENABLE), 1123 CLK_GATE("vdo_axi", "vdo_axi_sel", CCM, CCGR6, VDOAXICLK_CLK_ENABLE), 1124 CLK_GATE("vpu_axi", "vpu_axi_podf", CCM, CCGR6, VPU_CLK_ENABLE), 1125 CLK_GATE("cko1", "cko1_podf", CCM, CCOSR, CLKO1_EN), 1126 CLK_GATE("cko2", "cko2_podf", CCM, CCOSR, CLKO2_EN), 1127 1128 CLK_GATE("sata_ref_100m", "sata_ref", CCM_ANALOG, PLL_ENET, ENABLE_100M), 1129 CLK_GATE("pcie_ref_125m", "pcie_ref", CCM_ANALOG, PLL_ENET, ENABLE_125M), 1130 1131 CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE), 1132 CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE), 1133 CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE), 1134 CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE), 1135 CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE), 1136 CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE), 1137 CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE), 1138 1139 CLK_GATE("usbphy1", "pll3_usb_otg", CCM_ANALOG, PLL_USB1, RESERVED), 1140 CLK_GATE("usbphy2", "pll7_usb_host", CCM_ANALOG, PLL_USB2, RESERVED), 1141 1142 CLK_GATE_EXCLUSIVE("lvds1_gate", "lvds1_sel", CCM_ANALOG, MISC1, LVDS_CLK1_OBEN, LVDS_CLK1_IBEN), 1143 CLK_GATE_EXCLUSIVE("lvds2_gate", "lvds2_sel", CCM_ANALOG, MISC1, LVDS_CLK2_OBEN, LVDS_CLK2_IBEN), 1144 CLK_GATE_EXCLUSIVE("lvds1_in", "anaclk1", CCM_ANALOG, MISC1, LVDS_CLK1_IBEN, LVDS_CLK1_OBEN), 1145 CLK_GATE_EXCLUSIVE("lvds2_in", "anaclk2", CCM_ANALOG, MISC1, LVDS_CLK2_IBEN, LVDS_CLK2_OBEN), 1146 }; 1147 1148 struct imxccm_init_parent imxccm6q_init_parents[] = { 1149 { "pll1_bypass", "pll1" }, 1150 { "pll2_bypass", "pll2" }, 1151 { "pll3_bypass", "pll3" }, 1152 { "pll4_bypass", "pll4" }, 1153 { "pll5_bypass", "pll5" }, 1154 { "pll6_bypass", "pll6" }, 1155 { "pll7_bypass", "pll7" }, 1156 { "lvds1_sel", "sata_ref_100m" }, 1157 { 0 }, 1158 }; 1159 1160 1161 static struct imx6_clk * 1162 imx6q_clk_find_by_id(struct imx6ccm_softc *sc, u_int clock_id) 1163 { 1164 for (int n = 0; n < __arraycount(imx6q_clock_ids); n++) { 1165 if (imx6q_clock_ids[n].id == clock_id) { 1166 const char *name = imx6q_clock_ids[n].name; 1167 return imx6_clk_find(sc, name); 1168 } 1169 } 1170 1171 return NULL; 1172 } 1173 1174 static struct clk * 1175 imx6q_get_clock_by_id(struct imx6ccm_softc *sc, u_int clock_id) 1176 { 1177 struct imx6_clk *iclk; 1178 iclk = imx6q_clk_find_by_id(sc, clock_id); 1179 1180 if (iclk == NULL) 1181 return NULL; 1182 1183 return &iclk->base; 1184 } 1185 1186 static struct clk *imx6q_clk_decode(device_t, int, const void *, size_t); 1187 1188 static const struct fdtbus_clock_controller_func imx6q_ccm_fdtclock_funcs = { 1189 .decode = imx6q_clk_decode 1190 }; 1191 1192 static struct clk * 1193 imx6q_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len) 1194 { 1195 struct clk *clk; 1196 struct imx6ccm_softc *sc = device_private(dev); 1197 1198 /* #clock-cells should be 1 */ 1199 if (len != 4) 1200 return NULL; 1201 1202 const u_int clock_id = be32dec(data); 1203 1204 clk = imx6q_get_clock_by_id(sc, clock_id); 1205 if (clk) 1206 return clk; 1207 1208 return NULL; 1209 } 1210 1211 static void 1212 imx6q_clk_fixed_from_fdt(struct imx6ccm_softc *sc, const char *name) 1213 { 1214 struct imx6_clk *iclk = (struct imx6_clk *)imx6_get_clock(sc, name); 1215 1216 KASSERTMSG((iclk != NULL), "failed to find clock %s", name); 1217 1218 char *path = kmem_asprintf("/clocks/%s", name); 1219 int phandle = OF_finddevice(path); 1220 KASSERTMSG((phandle >= 0), "failed to find device %s", path); 1221 kmem_free(path, strlen(path) + 1); 1222 1223 if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0) 1224 iclk->clk.fixed.rate = 0; 1225 } 1226 1227 static int imx6qccm_match(device_t, cfdata_t, void *); 1228 static void imx6qccm_attach(device_t, device_t, void *); 1229 1230 CFATTACH_DECL_NEW(imx6ccm, sizeof(struct imx6ccm_softc), 1231 imx6qccm_match, imx6qccm_attach, NULL, NULL); 1232 1233 static const struct device_compatible_entry compat_data[] = { 1234 { .compat = "fsl,imx6q-ccm" }, 1235 DEVICE_COMPAT_EOL 1236 }; 1237 1238 static int 1239 imx6qccm_match(device_t parent, cfdata_t cfdata, void *aux) 1240 { 1241 struct fdt_attach_args * const faa = aux; 1242 1243 return of_compatible_match(faa->faa_phandle, compat_data); 1244 } 1245 1246 static void 1247 imx6qccm_attach(device_t parent, device_t self, void *aux) 1248 { 1249 struct imx6ccm_softc * const sc = device_private(self); 1250 struct fdt_attach_args * const faa = aux; 1251 bus_addr_t addr; 1252 bus_size_t size; 1253 1254 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 1255 aprint_error(": couldn't get registers\n"); 1256 return; 1257 } 1258 1259 sc->sc_dev = self; 1260 sc->sc_iot = faa->faa_bst; 1261 1262 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 1263 aprint_error(": can't map ccm registers\n"); 1264 return; 1265 } 1266 1267 int phandle = OF_finddevice("/soc/bus/anatop"); 1268 1269 if (phandle == -1) { 1270 aprint_error(": can't find anatop device\n"); 1271 return; 1272 } 1273 1274 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1275 aprint_error(": can't get anatop registers\n"); 1276 return; 1277 } 1278 1279 1280 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh_analog)) { 1281 aprint_error(": can't map anatop registers\n"); 1282 return; 1283 } 1284 1285 aprint_naive("\n"); 1286 aprint_normal(": Clock Control Module\n"); 1287 1288 imx6ccm_attach_common(self, &imx6q_clks[0], __arraycount(imx6q_clks), 1289 imxccm6q_init_parents); 1290 1291 imx6q_clk_fixed_from_fdt(sc, "ckil"); 1292 imx6q_clk_fixed_from_fdt(sc, "ckih1"); 1293 imx6q_clk_fixed_from_fdt(sc, "osc"); 1294 1295 fdtbus_register_clock_controller(self, faa->faa_phandle, 1296 &imx6q_ccm_fdtclock_funcs); 1297 } 1298