1 /* $NetBSD: nouveau_nvkm_subdev_fb_gp102.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_fb_gp102.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $");
28
29 #include "gf100.h"
30 #include "ram.h"
31
32 #include <core/firmware.h>
33 #include <core/memory.h>
34 #include <nvfw/fw.h>
35 #include <nvfw/hs.h>
36 #include <engine/nvdec.h>
37
38 #include <linux/nbsd-namespace.h>
39
40 int
gp102_fb_vpr_scrub(struct nvkm_fb * fb)41 gp102_fb_vpr_scrub(struct nvkm_fb *fb)
42 {
43 struct nvkm_subdev *subdev = &fb->subdev;
44 struct nvkm_device *device = subdev->device;
45 struct nvkm_falcon *falcon = &device->nvdec[0]->falcon;
46 struct nvkm_blob *blob = &fb->vpr_scrubber;
47 const struct nvfw_bin_hdr *hsbin_hdr;
48 const struct nvfw_hs_header *fw_hdr;
49 const struct nvfw_hs_load_header *lhdr;
50 void *scrub_data;
51 u32 patch_loc, patch_sig;
52 int ret;
53
54 nvkm_falcon_get(falcon, subdev);
55
56 hsbin_hdr = nvfw_bin_hdr(subdev, blob->data);
57 fw_hdr = nvfw_hs_header(subdev, blob->data + hsbin_hdr->header_offset);
58 lhdr = nvfw_hs_load_header(subdev, blob->data + fw_hdr->hdr_offset);
59 scrub_data = blob->data + hsbin_hdr->data_offset;
60
61 patch_loc = *(u32 *)(blob->data + fw_hdr->patch_loc);
62 patch_sig = *(u32 *)(blob->data + fw_hdr->patch_sig);
63 if (falcon->debug) {
64 memcpy(scrub_data + patch_loc,
65 blob->data + fw_hdr->sig_dbg_offset + patch_sig,
66 fw_hdr->sig_dbg_size);
67 } else {
68 memcpy(scrub_data + patch_loc,
69 blob->data + fw_hdr->sig_prod_offset + patch_sig,
70 fw_hdr->sig_prod_size);
71 }
72
73 nvkm_falcon_reset(falcon);
74 nvkm_falcon_bind_context(falcon, NULL);
75
76 nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off,
77 lhdr->non_sec_code_size,
78 lhdr->non_sec_code_off >> 8, 0, false);
79 nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0],
80 ALIGN(lhdr->apps[0], 0x100),
81 lhdr->apps[1],
82 lhdr->apps[0] >> 8, 0, true);
83 nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0,
84 lhdr->data_size, 0);
85
86 nvkm_falcon_set_start_addr(falcon, 0x0);
87 nvkm_falcon_start(falcon);
88
89 ret = nvkm_falcon_wait_for_halt(falcon, 500);
90 if (ret < 0) {
91 ret = -ETIMEDOUT;
92 goto end;
93 }
94
95 /* put nvdec in clean state - without reset it will remain in HS mode */
96 nvkm_falcon_reset(falcon);
97 end:
98 nvkm_falcon_put(falcon, subdev);
99 return ret;
100 }
101
102 bool
gp102_fb_vpr_scrub_required(struct nvkm_fb * fb)103 gp102_fb_vpr_scrub_required(struct nvkm_fb *fb)
104 {
105 struct nvkm_device *device = fb->subdev.device;
106 nvkm_wr32(device, 0x100cd0, 0x2);
107 return (nvkm_rd32(device, 0x100cd0) & 0x00000010) != 0;
108 }
109
110 static const struct nvkm_fb_func
111 gp102_fb = {
112 .dtor = gf100_fb_dtor,
113 .oneinit = gf100_fb_oneinit,
114 .init = gp100_fb_init,
115 .init_remapper = gp100_fb_init_remapper,
116 .init_page = gm200_fb_init_page,
117 .vpr.scrub_required = gp102_fb_vpr_scrub_required,
118 .vpr.scrub = gp102_fb_vpr_scrub,
119 .ram_new = gp100_ram_new,
120 };
121
122 int
gp102_fb_new_(const struct nvkm_fb_func * func,struct nvkm_device * device,int index,struct nvkm_fb ** pfb)123 gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
124 int index, struct nvkm_fb **pfb)
125 {
126 int ret = gf100_fb_new_(func, device, index, pfb);
127 if (ret)
128 return ret;
129
130 nvkm_firmware_load_blob(&(*pfb)->subdev, "nvdec/scrubber", "", 0,
131 &(*pfb)->vpr_scrubber);
132 return 0;
133 }
134
135 int
gp102_fb_new(struct nvkm_device * device,int index,struct nvkm_fb ** pfb)136 gp102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
137 {
138 return gp102_fb_new_(&gp102_fb, device, index, pfb);
139 }
140
141 MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin");
142 MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin");
143 MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin");
144 MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin");
145 MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin");
146