1 /* $NetBSD: nouveau_nvkm_engine_gr_gp100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gp100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
28
29 #include "gf100.h"
30 #include "ctxgf100.h"
31
32 #include <nvif/class.h>
33
34 /*******************************************************************************
35 * PGRAPH engine/subdev functions
36 ******************************************************************************/
37 void
gp100_gr_zbc_clear_color(struct gf100_gr * gr,int zbc)38 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
39 {
40 struct nvkm_device *device = gr->base.engine.subdev.device;
41 const int znum = zbc - 1;
42 const u32 zoff = znum * 4;
43
44 if (gr->zbc_color[zbc].format) {
45 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);
46 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);
47 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);
48 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);
49 }
50
51 nvkm_mask(device, 0x418100 + ((znum / 4) * 4),
52 0x0000007f << ((znum % 4) * 7),
53 gr->zbc_color[zbc].format << ((znum % 4) * 7));
54 }
55
56 void
gp100_gr_zbc_clear_depth(struct gf100_gr * gr,int zbc)57 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
58 {
59 struct nvkm_device *device = gr->base.engine.subdev.device;
60 const int znum = zbc - 1;
61 const u32 zoff = znum * 4;
62
63 if (gr->zbc_depth[zbc].format)
64 nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);
65 nvkm_mask(device, 0x41814c + ((znum / 4) * 4),
66 0x0000007f << ((znum % 4) * 7),
67 gr->zbc_depth[zbc].format << ((znum % 4) * 7));
68 }
69
70 const struct gf100_gr_func_zbc
71 gp100_gr_zbc = {
72 .clear_color = gp100_gr_zbc_clear_color,
73 .clear_depth = gp100_gr_zbc_clear_depth,
74 };
75
76 void
gp100_gr_init_shader_exceptions(struct gf100_gr * gr,int gpc,int tpc)77 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
78 {
79 struct nvkm_device *device = gr->base.engine.subdev.device;
80 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
81 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
82 }
83
84 static void
gp100_gr_init_419c9c(struct gf100_gr * gr)85 gp100_gr_init_419c9c(struct gf100_gr *gr)
86 {
87 struct nvkm_device *device = gr->base.engine.subdev.device;
88 nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
89 nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
90 }
91
92 void
gp100_gr_init_fecs_exceptions(struct gf100_gr * gr)93 gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
94 {
95 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002);
96 }
97
98 void
gp100_gr_init_rop_active_fbps(struct gf100_gr * gr)99 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
100 {
101 struct nvkm_device *device = gr->base.engine.subdev.device;
102 /*XXX: otherwise identical to gm200 aside from mask.. do everywhere? */
103 const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;
104 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
105 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
106 }
107
108 static const struct gf100_gr_func
109 gp100_gr = {
110 .oneinit_tiles = gm200_gr_oneinit_tiles,
111 .oneinit_sm_id = gm200_gr_oneinit_sm_id,
112 .init = gf100_gr_init,
113 .init_gpc_mmu = gm200_gr_init_gpc_mmu,
114 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
115 .init_zcull = gf117_gr_init_zcull,
116 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
117 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
118 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
119 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
120 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
121 .init_419cc0 = gf100_gr_init_419cc0,
122 .init_419c9c = gp100_gr_init_419c9c,
123 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
124 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
125 .init_504430 = gm107_gr_init_504430,
126 .init_shader_exceptions = gp100_gr_init_shader_exceptions,
127 .trap_mp = gf100_gr_trap_mp,
128 .rops = gm200_gr_rops,
129 .gpc_nr = 6,
130 .tpc_nr = 5,
131 .ppc_nr = 2,
132 .grctx = &gp100_grctx,
133 .zbc = &gp100_gr_zbc,
134 .sclass = {
135 { -1, -1, FERMI_TWOD_A },
136 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
137 { -1, -1, PASCAL_A, &gf100_fermi },
138 { -1, -1, PASCAL_COMPUTE_A },
139 {}
140 }
141 };
142
143 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin");
144 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin");
145 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin");
146 MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin");
147 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin");
148 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin");
149 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin");
150 MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin");
151 MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin");
152 MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin");
153 MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin");
154 MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin");
155
156 static const struct gf100_gr_fwif
157 gp100_gr_fwif[] = {
158 { 0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
159 {}
160 };
161
162 int
gp100_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)163 gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
164 {
165 return gf100_gr_new_(gp100_gr_fwif, device, index, pgr);
166 }
167