1 /* $NetBSD: amdgpu_gmc_v8_0.c,v 1.6 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v8_0.c,v 1.6 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32
33 #include <drm/drm_cache.h>
34 #include "amdgpu.h"
35 #include "gmc_v8_0.h"
36 #include "amdgpu_ucode.h"
37 #include "amdgpu_amdkfd.h"
38 #include "amdgpu_gem.h"
39
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42
43 #include "bif/bif_5_0_d.h"
44 #include "bif/bif_5_0_sh_mask.h"
45
46 #include "oss/oss_3_0_d.h"
47 #include "oss/oss_3_0_sh_mask.h"
48
49 #include "dce/dce_10_0_d.h"
50 #include "dce/dce_10_0_sh_mask.h"
51
52 #include "vid.h"
53 #include "vi.h"
54
55 #include "amdgpu_atombios.h"
56
57 #include "ivsrcid/ivsrcid_vislands30.h"
58
59 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
60 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
61 static int gmc_v8_0_wait_for_idle(void *handle);
62
63 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
64 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
65 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
66 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
67 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
68 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
69 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
70
71 static const u32 golden_settings_tonga_a11[] =
72 {
73 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
74 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
75 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
76 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
77 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
78 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
79 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
80 };
81
82 static const u32 tonga_mgcg_cgcg_init[] =
83 {
84 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
85 };
86
87 static const u32 golden_settings_fiji_a10[] =
88 {
89 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
90 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
91 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
92 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
93 };
94
95 static const u32 fiji_mgcg_cgcg_init[] =
96 {
97 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
98 };
99
100 static const u32 golden_settings_polaris11_a11[] =
101 {
102 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
103 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
104 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
105 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
106 };
107
108 static const u32 golden_settings_polaris10_a11[] =
109 {
110 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
111 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
112 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
113 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
114 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
115 };
116
117 static const u32 cz_mgcg_cgcg_init[] =
118 {
119 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
120 };
121
122 static const u32 stoney_mgcg_cgcg_init[] =
123 {
124 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
125 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
126 };
127
128 static const u32 golden_settings_stoney_common[] =
129 {
130 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
131 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
132 };
133
gmc_v8_0_init_golden_registers(struct amdgpu_device * adev)134 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
135 {
136 switch (adev->asic_type) {
137 case CHIP_FIJI:
138 amdgpu_device_program_register_sequence(adev,
139 fiji_mgcg_cgcg_init,
140 ARRAY_SIZE(fiji_mgcg_cgcg_init));
141 amdgpu_device_program_register_sequence(adev,
142 golden_settings_fiji_a10,
143 ARRAY_SIZE(golden_settings_fiji_a10));
144 break;
145 case CHIP_TONGA:
146 amdgpu_device_program_register_sequence(adev,
147 tonga_mgcg_cgcg_init,
148 ARRAY_SIZE(tonga_mgcg_cgcg_init));
149 amdgpu_device_program_register_sequence(adev,
150 golden_settings_tonga_a11,
151 ARRAY_SIZE(golden_settings_tonga_a11));
152 break;
153 case CHIP_POLARIS11:
154 case CHIP_POLARIS12:
155 case CHIP_VEGAM:
156 amdgpu_device_program_register_sequence(adev,
157 golden_settings_polaris11_a11,
158 ARRAY_SIZE(golden_settings_polaris11_a11));
159 break;
160 case CHIP_POLARIS10:
161 amdgpu_device_program_register_sequence(adev,
162 golden_settings_polaris10_a11,
163 ARRAY_SIZE(golden_settings_polaris10_a11));
164 break;
165 case CHIP_CARRIZO:
166 amdgpu_device_program_register_sequence(adev,
167 cz_mgcg_cgcg_init,
168 ARRAY_SIZE(cz_mgcg_cgcg_init));
169 break;
170 case CHIP_STONEY:
171 amdgpu_device_program_register_sequence(adev,
172 stoney_mgcg_cgcg_init,
173 ARRAY_SIZE(stoney_mgcg_cgcg_init));
174 amdgpu_device_program_register_sequence(adev,
175 golden_settings_stoney_common,
176 ARRAY_SIZE(golden_settings_stoney_common));
177 break;
178 default:
179 break;
180 }
181 }
182
gmc_v8_0_mc_stop(struct amdgpu_device * adev)183 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
184 {
185 u32 blackout;
186
187 gmc_v8_0_wait_for_idle(adev);
188
189 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
190 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
191 /* Block CPU access */
192 WREG32(mmBIF_FB_EN, 0);
193 /* blackout the MC */
194 blackout = REG_SET_FIELD(blackout,
195 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
197 }
198 /* wait for the MC to settle */
199 udelay(100);
200 }
201
gmc_v8_0_mc_resume(struct amdgpu_device * adev)202 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
203 {
204 u32 tmp;
205
206 /* unblackout the MC */
207 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
208 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
209 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
210 /* allow CPU access */
211 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
212 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
213 WREG32(mmBIF_FB_EN, tmp);
214 }
215
216 /**
217 * gmc_v8_0_init_microcode - load ucode images from disk
218 *
219 * @adev: amdgpu_device pointer
220 *
221 * Use the firmware interface to load the ucode images into
222 * the driver (not loaded into hw).
223 * Returns 0 on success, error on failure.
224 */
gmc_v8_0_init_microcode(struct amdgpu_device * adev)225 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
226 {
227 const char *chip_name;
228 char fw_name[30];
229 int err;
230
231 DRM_DEBUG("\n");
232
233 switch (adev->asic_type) {
234 case CHIP_TONGA:
235 chip_name = "tonga";
236 break;
237 case CHIP_POLARIS11:
238 if (((adev->pdev->device == 0x67ef) &&
239 ((adev->pdev->revision == 0xe0) ||
240 (adev->pdev->revision == 0xe5))) ||
241 ((adev->pdev->device == 0x67ff) &&
242 ((adev->pdev->revision == 0xcf) ||
243 (adev->pdev->revision == 0xef) ||
244 (adev->pdev->revision == 0xff))))
245 chip_name = "polaris11_k";
246 else if ((adev->pdev->device == 0x67ef) &&
247 (adev->pdev->revision == 0xe2))
248 chip_name = "polaris11_k";
249 else
250 chip_name = "polaris11";
251 break;
252 case CHIP_POLARIS10:
253 if ((adev->pdev->device == 0x67df) &&
254 ((adev->pdev->revision == 0xe1) ||
255 (adev->pdev->revision == 0xf7)))
256 chip_name = "polaris10_k";
257 else
258 chip_name = "polaris10";
259 break;
260 case CHIP_POLARIS12:
261 if (((adev->pdev->device == 0x6987) &&
262 ((adev->pdev->revision == 0xc0) ||
263 (adev->pdev->revision == 0xc3))) ||
264 ((adev->pdev->device == 0x6981) &&
265 ((adev->pdev->revision == 0x00) ||
266 (adev->pdev->revision == 0x01) ||
267 (adev->pdev->revision == 0x10))))
268 chip_name = "polaris12_k";
269 else
270 chip_name = "polaris12";
271 break;
272 case CHIP_FIJI:
273 case CHIP_CARRIZO:
274 case CHIP_STONEY:
275 case CHIP_VEGAM:
276 return 0;
277 default: BUG();
278 }
279
280 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
281 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
282 if (err)
283 goto out;
284 err = amdgpu_ucode_validate(adev->gmc.fw);
285
286 out:
287 if (err) {
288 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
289 release_firmware(adev->gmc.fw);
290 adev->gmc.fw = NULL;
291 }
292 return err;
293 }
294
295 /**
296 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
297 *
298 * @adev: amdgpu_device pointer
299 *
300 * Load the GDDR MC ucode into the hw (VI).
301 * Returns 0 on success, error on failure.
302 */
gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device * adev)303 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
304 {
305 const struct mc_firmware_header_v1_0 *hdr;
306 const __le32 *fw_data = NULL;
307 const __le32 *io_mc_regs = NULL;
308 u32 running;
309 int i, ucode_size, regs_size;
310
311 /* Skip MC ucode loading on SR-IOV capable boards.
312 * vbios does this for us in asic_init in that case.
313 * Skip MC ucode loading on VF, because hypervisor will do that
314 * for this adaptor.
315 */
316 if (amdgpu_sriov_bios(adev))
317 return 0;
318
319 if (!adev->gmc.fw)
320 return -EINVAL;
321
322 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
323 amdgpu_ucode_print_mc_hdr(&hdr->header);
324
325 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
326 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
327 io_mc_regs = (const __le32 *)
328 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
329 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
330 fw_data = (const __le32 *)
331 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
332
333 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
334
335 if (running == 0) {
336 /* reset the engine and set to writable */
337 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
338 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
339
340 /* load mc io regs */
341 for (i = 0; i < regs_size; i++) {
342 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
343 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
344 }
345 /* load the MC ucode */
346 for (i = 0; i < ucode_size; i++)
347 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
348
349 /* put the engine back into the active state */
350 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
351 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
352 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
353
354 /* wait for training to complete */
355 for (i = 0; i < adev->usec_timeout; i++) {
356 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
357 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
358 break;
359 udelay(1);
360 }
361 for (i = 0; i < adev->usec_timeout; i++) {
362 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
363 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
364 break;
365 udelay(1);
366 }
367 }
368
369 return 0;
370 }
371
gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device * adev)372 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
373 {
374 const struct mc_firmware_header_v1_0 *hdr;
375 const __le32 *fw_data = NULL;
376 const __le32 *io_mc_regs = NULL;
377 u32 data;
378 int i, ucode_size, regs_size;
379
380 /* Skip MC ucode loading on SR-IOV capable boards.
381 * vbios does this for us in asic_init in that case.
382 * Skip MC ucode loading on VF, because hypervisor will do that
383 * for this adaptor.
384 */
385 if (amdgpu_sriov_bios(adev))
386 return 0;
387
388 if (!adev->gmc.fw)
389 return -EINVAL;
390
391 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
392 amdgpu_ucode_print_mc_hdr(&hdr->header);
393
394 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
395 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
396 io_mc_regs = (const __le32 *)
397 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
398 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
399 fw_data = (const __le32 *)
400 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
401
402 data = RREG32(mmMC_SEQ_MISC0);
403 data &= ~(0x40);
404 WREG32(mmMC_SEQ_MISC0, data);
405
406 /* load mc io regs */
407 for (i = 0; i < regs_size; i++) {
408 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
409 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
410 }
411
412 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
413 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
414
415 /* load the MC ucode */
416 for (i = 0; i < ucode_size; i++)
417 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
418
419 /* put the engine back into the active state */
420 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
421 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
422 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
423
424 /* wait for training to complete */
425 for (i = 0; i < adev->usec_timeout; i++) {
426 data = RREG32(mmMC_SEQ_MISC0);
427 if (data & 0x80)
428 break;
429 udelay(1);
430 }
431
432 return 0;
433 }
434
gmc_v8_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)435 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
436 struct amdgpu_gmc *mc)
437 {
438 u64 base = 0;
439
440 if (!amdgpu_sriov_vf(adev))
441 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
442 base <<= 24;
443
444 amdgpu_gmc_vram_location(adev, mc, base);
445 amdgpu_gmc_gart_location(adev, mc);
446 }
447
448 /**
449 * gmc_v8_0_mc_program - program the GPU memory controller
450 *
451 * @adev: amdgpu_device pointer
452 *
453 * Set the location of vram, gart, and AGP in the GPU's
454 * physical address space (VI).
455 */
gmc_v8_0_mc_program(struct amdgpu_device * adev)456 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
457 {
458 u32 tmp;
459 int i, j;
460
461 /* Initialize HDP */
462 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
463 WREG32((0xb05 + j), 0x00000000);
464 WREG32((0xb06 + j), 0x00000000);
465 WREG32((0xb07 + j), 0x00000000);
466 WREG32((0xb08 + j), 0x00000000);
467 WREG32((0xb09 + j), 0x00000000);
468 }
469 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
470
471 if (gmc_v8_0_wait_for_idle((void *)adev)) {
472 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
473 }
474 if (adev->mode_info.num_crtc) {
475 /* Lockout access through VGA aperture*/
476 tmp = RREG32(mmVGA_HDP_CONTROL);
477 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
478 WREG32(mmVGA_HDP_CONTROL, tmp);
479
480 /* disable VGA render */
481 tmp = RREG32(mmVGA_RENDER_CONTROL);
482 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
483 WREG32(mmVGA_RENDER_CONTROL, tmp);
484 }
485 /* Update configuration */
486 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
487 adev->gmc.vram_start >> 12);
488 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
489 adev->gmc.vram_end >> 12);
490 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
491 adev->vram_scratch.gpu_addr >> 12);
492
493 if (amdgpu_sriov_vf(adev)) {
494 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
495 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
496 WREG32(mmMC_VM_FB_LOCATION, tmp);
497 /* XXX double check these! */
498 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
499 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
500 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
501 }
502
503 WREG32(mmMC_VM_AGP_BASE, 0);
504 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
505 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
506 if (gmc_v8_0_wait_for_idle((void *)adev)) {
507 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
508 }
509
510 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
511
512 tmp = RREG32(mmHDP_MISC_CNTL);
513 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
514 WREG32(mmHDP_MISC_CNTL, tmp);
515
516 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
517 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
518 }
519
520 /**
521 * gmc_v8_0_mc_init - initialize the memory controller driver params
522 *
523 * @adev: amdgpu_device pointer
524 *
525 * Look up the amount of vram, vram width, and decide how to place
526 * vram and gart within the GPU's physical address space (VI).
527 * Returns 0 for success.
528 */
gmc_v8_0_mc_init(struct amdgpu_device * adev)529 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
530 {
531 int r;
532
533 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
534 if (!adev->gmc.vram_width) {
535 u32 tmp;
536 int chansize, numchan;
537
538 /* Get VRAM informations */
539 tmp = RREG32(mmMC_ARB_RAMCFG);
540 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
541 chansize = 64;
542 } else {
543 chansize = 32;
544 }
545 tmp = RREG32(mmMC_SHARED_CHMAP);
546 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
547 case 0:
548 default:
549 numchan = 1;
550 break;
551 case 1:
552 numchan = 2;
553 break;
554 case 2:
555 numchan = 4;
556 break;
557 case 3:
558 numchan = 8;
559 break;
560 case 4:
561 numchan = 3;
562 break;
563 case 5:
564 numchan = 6;
565 break;
566 case 6:
567 numchan = 10;
568 break;
569 case 7:
570 numchan = 12;
571 break;
572 case 8:
573 numchan = 16;
574 break;
575 }
576 adev->gmc.vram_width = numchan * chansize;
577 }
578 /* size in MB on si */
579 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
580 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
581
582 if (!(adev->flags & AMD_IS_APU)) {
583 r = amdgpu_device_resize_fb_bar(adev);
584 if (r)
585 return r;
586 }
587 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
588 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
589
590 #ifdef __NetBSD__
591 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt;
592 #endif
593
594 #ifdef CONFIG_X86_64
595 if (adev->flags & AMD_IS_APU) {
596 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
597 adev->gmc.aper_size = adev->gmc.real_vram_size;
598 }
599 #endif
600
601 /* In case the PCI BAR is larger than the actual amount of vram */
602 adev->gmc.visible_vram_size = adev->gmc.aper_size;
603 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
604 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
605
606 /* set the gart size */
607 if (amdgpu_gart_size == -1) {
608 switch (adev->asic_type) {
609 case CHIP_POLARIS10: /* all engines support GPUVM */
610 case CHIP_POLARIS11: /* all engines support GPUVM */
611 case CHIP_POLARIS12: /* all engines support GPUVM */
612 case CHIP_VEGAM: /* all engines support GPUVM */
613 default:
614 adev->gmc.gart_size = 256ULL << 20;
615 break;
616 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
617 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
618 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
619 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
620 adev->gmc.gart_size = 1024ULL << 20;
621 break;
622 }
623 } else {
624 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
625 }
626
627 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
628
629 return 0;
630 }
631
632 /**
633 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
634 *
635 * @adev: amdgpu_device pointer
636 * @pasid: pasid to be flush
637 *
638 * Flush the TLB for the requested pasid.
639 */
gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub)640 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
641 uint16_t pasid, uint32_t flush_type,
642 bool all_hub)
643 {
644 int vmid;
645 unsigned int tmp;
646
647 if (adev->in_gpu_reset)
648 return -EIO;
649
650 for (vmid = 1; vmid < 16; vmid++) {
651
652 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
653 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
654 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
655 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
656 RREG32(mmVM_INVALIDATE_RESPONSE);
657 break;
658 }
659 }
660
661 return 0;
662
663 }
664
665 /*
666 * GART
667 * VMID 0 is the physical GPU addresses as used by the kernel.
668 * VMIDs 1-15 are used for userspace clients and are handled
669 * by the amdgpu vm/hsa code.
670 */
671
672 /**
673 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
674 *
675 * @adev: amdgpu_device pointer
676 * @vmid: vm instance to flush
677 *
678 * Flush the TLB for the requested page table (VI).
679 */
gmc_v8_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)680 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
681 uint32_t vmhub, uint32_t flush_type)
682 {
683 /* bits 0-15 are the VM contexts0-15 */
684 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
685 }
686
gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)687 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
688 unsigned vmid, uint64_t pd_addr)
689 {
690 uint32_t reg;
691
692 if (vmid < 8)
693 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
694 else
695 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
696 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
697
698 /* bits 0-15 are the VM contexts0-15 */
699 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
700
701 return pd_addr;
702 }
703
gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned vmid,unsigned pasid)704 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
705 unsigned pasid)
706 {
707 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
708 }
709
710 /*
711 * PTE format on VI:
712 * 63:40 reserved
713 * 39:12 4k physical page base address
714 * 11:7 fragment
715 * 6 write
716 * 5 read
717 * 4 exe
718 * 3 reserved
719 * 2 snooped
720 * 1 system
721 * 0 valid
722 *
723 * PDE format on VI:
724 * 63:59 block fragment size
725 * 58:40 reserved
726 * 39:1 physical base address of PTE
727 * bits 5:1 must be 0.
728 * 0 valid
729 */
730
gmc_v8_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)731 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
732 uint64_t *addr, uint64_t *flags)
733 {
734 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
735 }
736
gmc_v8_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)737 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
738 struct amdgpu_bo_va_mapping *mapping,
739 uint64_t *flags)
740 {
741 *flags &= ~AMDGPU_PTE_EXECUTABLE;
742 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
743 *flags &= ~AMDGPU_PTE_PRT;
744 }
745
746 /**
747 * gmc_v8_0_set_fault_enable_default - update VM fault handling
748 *
749 * @adev: amdgpu_device pointer
750 * @value: true redirects VM faults to the default page
751 */
gmc_v8_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)752 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
753 bool value)
754 {
755 u32 tmp;
756
757 tmp = RREG32(mmVM_CONTEXT1_CNTL);
758 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
759 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
760 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
761 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
762 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
763 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
764 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
765 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
766 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
767 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
768 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
769 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
770 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
771 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
772 WREG32(mmVM_CONTEXT1_CNTL, tmp);
773 }
774
775 /**
776 * gmc_v8_0_set_prt - set PRT VM fault
777 *
778 * @adev: amdgpu_device pointer
779 * @enable: enable/disable VM fault handling for PRT
780 */
gmc_v8_0_set_prt(struct amdgpu_device * adev,bool enable)781 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
782 {
783 u32 tmp;
784
785 if (enable && !adev->gmc.prt_warning) {
786 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
787 adev->gmc.prt_warning = true;
788 }
789
790 tmp = RREG32(mmVM_PRT_CNTL);
791 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
792 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
793 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
794 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
795 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
796 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
797 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
798 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
799 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
800 L2_CACHE_STORE_INVALID_ENTRIES, enable);
801 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
802 L1_TLB_STORE_INVALID_ENTRIES, enable);
803 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
804 MASK_PDE0_FAULT, enable);
805 WREG32(mmVM_PRT_CNTL, tmp);
806
807 if (enable) {
808 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
809 uint32_t high = adev->vm_manager.max_pfn -
810 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
811
812 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
813 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
814 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
815 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
816 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
817 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
818 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
819 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
820 } else {
821 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
822 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
823 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
824 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
825 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
826 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
827 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
828 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
829 }
830 }
831
832 /**
833 * gmc_v8_0_gart_enable - gart enable
834 *
835 * @adev: amdgpu_device pointer
836 *
837 * This sets up the TLBs, programs the page tables for VMID0,
838 * sets up the hw for VMIDs 1-15 which are allocated on
839 * demand, and sets up the global locations for the LDS, GDS,
840 * and GPUVM for FSA64 clients (VI).
841 * Returns 0 for success, errors for failure.
842 */
gmc_v8_0_gart_enable(struct amdgpu_device * adev)843 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
844 {
845 uint64_t table_addr;
846 int r, i;
847 u32 tmp, field;
848
849 if (adev->gart.bo == NULL) {
850 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
851 return -EINVAL;
852 }
853 r = amdgpu_gart_table_vram_pin(adev);
854 if (r)
855 return r;
856
857 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
858
859 /* Setup TLB control */
860 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
861 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
862 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
863 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
864 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
865 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
866 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
867 /* Setup L2 cache */
868 tmp = RREG32(mmVM_L2_CNTL);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
876 WREG32(mmVM_L2_CNTL, tmp);
877 tmp = RREG32(mmVM_L2_CNTL2);
878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
880 WREG32(mmVM_L2_CNTL2, tmp);
881
882 field = adev->vm_manager.fragment_size;
883 tmp = RREG32(mmVM_L2_CNTL3);
884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
886 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
887 WREG32(mmVM_L2_CNTL3, tmp);
888 /* XXX: set to enable PTE/PDE in system memory */
889 tmp = RREG32(mmVM_L2_CNTL4);
890 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
891 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
892 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
893 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
894 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
895 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
896 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
897 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
898 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
899 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
900 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
901 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
902 WREG32(mmVM_L2_CNTL4, tmp);
903 /* setup context0 */
904 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
905 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
906 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
907 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
908 (u32)(adev->dummy_page_addr >> 12));
909 WREG32(mmVM_CONTEXT0_CNTL2, 0);
910 tmp = RREG32(mmVM_CONTEXT0_CNTL);
911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
912 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
913 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
914 WREG32(mmVM_CONTEXT0_CNTL, tmp);
915
916 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
917 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
918 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
919
920 /* empty context1-15 */
921 /* FIXME start with 4G, once using 2 level pt switch to full
922 * vm size space
923 */
924 /* set vm size, must be a multiple of 4 */
925 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
926 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
927 for (i = 1; i < 16; i++) {
928 if (i < 8)
929 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
930 table_addr >> 12);
931 else
932 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
933 table_addr >> 12);
934 }
935
936 /* enable context1-15 */
937 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
938 (u32)(adev->dummy_page_addr >> 12));
939 WREG32(mmVM_CONTEXT1_CNTL2, 4);
940 tmp = RREG32(mmVM_CONTEXT1_CNTL);
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
942 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
943 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
944 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
945 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
946 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
947 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
948 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
949 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
950 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
951 adev->vm_manager.block_size - 9);
952 WREG32(mmVM_CONTEXT1_CNTL, tmp);
953 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
954 gmc_v8_0_set_fault_enable_default(adev, false);
955 else
956 gmc_v8_0_set_fault_enable_default(adev, true);
957
958 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
959 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
960 (unsigned)(adev->gmc.gart_size >> 20),
961 (unsigned long long)table_addr);
962 adev->gart.ready = true;
963 return 0;
964 }
965
gmc_v8_0_gart_init(struct amdgpu_device * adev)966 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
967 {
968 int r;
969
970 if (adev->gart.bo) {
971 WARN(1, "R600 PCIE GART already initialized\n");
972 return 0;
973 }
974 /* Initialize common gart structure */
975 r = amdgpu_gart_init(adev);
976 if (r)
977 return r;
978 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
979 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
980 return amdgpu_gart_table_vram_alloc(adev);
981 }
982
983 /**
984 * gmc_v8_0_gart_disable - gart disable
985 *
986 * @adev: amdgpu_device pointer
987 *
988 * This disables all VM page table (VI).
989 */
gmc_v8_0_gart_disable(struct amdgpu_device * adev)990 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
991 {
992 u32 tmp;
993
994 /* Disable all tables */
995 WREG32(mmVM_CONTEXT0_CNTL, 0);
996 WREG32(mmVM_CONTEXT1_CNTL, 0);
997 /* Setup TLB control */
998 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
999 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
1000 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
1001 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
1002 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
1003 /* Setup L2 cache */
1004 tmp = RREG32(mmVM_L2_CNTL);
1005 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
1006 WREG32(mmVM_L2_CNTL, tmp);
1007 WREG32(mmVM_L2_CNTL2, 0);
1008 amdgpu_gart_table_vram_unpin(adev);
1009 }
1010
1011 /**
1012 * gmc_v8_0_vm_decode_fault - print human readable fault info
1013 *
1014 * @adev: amdgpu_device pointer
1015 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
1016 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1017 *
1018 * Print human readable fault information (VI).
1019 */
gmc_v8_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client,unsigned pasid)1020 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1021 u32 addr, u32 mc_client, unsigned pasid)
1022 {
1023 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1024 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1025 PROTECTIONS);
1026 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1027 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1028 u32 mc_id;
1029
1030 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1031 MEMORY_CLIENT_ID);
1032
1033 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1034 protections, vmid, pasid, addr,
1035 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1036 MEMORY_CLIENT_RW) ?
1037 "write" : "read", block, mc_client, mc_id);
1038 }
1039
gmc_v8_0_convert_vram_type(int mc_seq_vram_type)1040 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1041 {
1042 switch (mc_seq_vram_type) {
1043 case MC_SEQ_MISC0__MT__GDDR1:
1044 return AMDGPU_VRAM_TYPE_GDDR1;
1045 case MC_SEQ_MISC0__MT__DDR2:
1046 return AMDGPU_VRAM_TYPE_DDR2;
1047 case MC_SEQ_MISC0__MT__GDDR3:
1048 return AMDGPU_VRAM_TYPE_GDDR3;
1049 case MC_SEQ_MISC0__MT__GDDR4:
1050 return AMDGPU_VRAM_TYPE_GDDR4;
1051 case MC_SEQ_MISC0__MT__GDDR5:
1052 return AMDGPU_VRAM_TYPE_GDDR5;
1053 case MC_SEQ_MISC0__MT__HBM:
1054 return AMDGPU_VRAM_TYPE_HBM;
1055 case MC_SEQ_MISC0__MT__DDR3:
1056 return AMDGPU_VRAM_TYPE_DDR3;
1057 default:
1058 return AMDGPU_VRAM_TYPE_UNKNOWN;
1059 }
1060 }
1061
gmc_v8_0_early_init(void * handle)1062 static int gmc_v8_0_early_init(void *handle)
1063 {
1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065
1066 gmc_v8_0_set_gmc_funcs(adev);
1067 gmc_v8_0_set_irq_funcs(adev);
1068
1069 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1070 adev->gmc.shared_aperture_end =
1071 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1072 adev->gmc.private_aperture_start =
1073 adev->gmc.shared_aperture_end + 1;
1074 adev->gmc.private_aperture_end =
1075 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1076
1077 return 0;
1078 }
1079
gmc_v8_0_late_init(void * handle)1080 static int gmc_v8_0_late_init(void *handle)
1081 {
1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083
1084 amdgpu_bo_late_init(adev);
1085
1086 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1087 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1088 else
1089 return 0;
1090 }
1091
gmc_v8_0_get_vbios_fb_size(struct amdgpu_device * adev)1092 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1093 {
1094 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1095 unsigned size;
1096
1097 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1098 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1099 } else {
1100 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1101 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1102 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1103 4);
1104 }
1105 /* return 0 if the pre-OS buffer uses up most of vram */
1106 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1107 return 0;
1108 return size;
1109 }
1110
1111 #define mmMC_SEQ_MISC0_FIJI 0xA71
1112
gmc_v8_0_sw_init(void * handle)1113 static int gmc_v8_0_sw_init(void *handle)
1114 {
1115 int r;
1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1117
1118 adev->num_vmhubs = 1;
1119
1120 if (adev->flags & AMD_IS_APU) {
1121 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1122 } else {
1123 u32 tmp;
1124
1125 if ((adev->asic_type == CHIP_FIJI) ||
1126 (adev->asic_type == CHIP_VEGAM))
1127 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1128 else
1129 tmp = RREG32(mmMC_SEQ_MISC0);
1130 tmp &= MC_SEQ_MISC0__MT__MASK;
1131 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1132 }
1133
1134 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1135 if (r)
1136 return r;
1137
1138 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1139 if (r)
1140 return r;
1141
1142 /* Adjust VM size here.
1143 * Currently set to 4GB ((1 << 20) 4k pages).
1144 * Max GPUVM size for cayman and SI is 40 bits.
1145 */
1146 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1147
1148 /* Set the internal MC address mask
1149 * This is the max address of the GPU's
1150 * internal address space.
1151 */
1152 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1153
1154 #ifdef __NetBSD__
1155 r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(40));
1156 #else
1157 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1158 #endif
1159 if (r) {
1160 pr_warn("amdgpu: No suitable DMA available\n");
1161 return r;
1162 }
1163 adev->need_swiotlb = drm_need_swiotlb(40);
1164
1165 r = gmc_v8_0_init_microcode(adev);
1166 if (r) {
1167 DRM_ERROR("Failed to load mc firmware!\n");
1168 return r;
1169 }
1170
1171 r = gmc_v8_0_mc_init(adev);
1172 if (r)
1173 return r;
1174
1175 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1176
1177 /* Memory manager */
1178 r = amdgpu_bo_init(adev);
1179 if (r)
1180 return r;
1181
1182 r = gmc_v8_0_gart_init(adev);
1183 if (r)
1184 return r;
1185
1186 /*
1187 * number of VMs
1188 * VMID 0 is reserved for System
1189 * amdgpu graphics/compute will use VMIDs 1-7
1190 * amdkfd will use VMIDs 8-15
1191 */
1192 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1193 amdgpu_vm_manager_init(adev);
1194
1195 /* base offset of vram pages */
1196 if (adev->flags & AMD_IS_APU) {
1197 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1198
1199 tmp <<= 22;
1200 adev->vm_manager.vram_base_offset = tmp;
1201 } else {
1202 adev->vm_manager.vram_base_offset = 0;
1203 }
1204
1205 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1206 GFP_KERNEL);
1207 if (!adev->gmc.vm_fault_info)
1208 return -ENOMEM;
1209 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1210
1211 return 0;
1212 }
1213
gmc_v8_0_sw_fini(void * handle)1214 static int gmc_v8_0_sw_fini(void *handle)
1215 {
1216 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218 amdgpu_gem_force_release(adev);
1219 amdgpu_vm_manager_fini(adev);
1220 kfree(adev->gmc.vm_fault_info);
1221 amdgpu_gart_table_vram_free(adev);
1222 amdgpu_bo_fini(adev);
1223 amdgpu_gart_fini(adev);
1224 release_firmware(adev->gmc.fw);
1225 adev->gmc.fw = NULL;
1226
1227 return 0;
1228 }
1229
gmc_v8_0_hw_init(void * handle)1230 static int gmc_v8_0_hw_init(void *handle)
1231 {
1232 int r;
1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235 gmc_v8_0_init_golden_registers(adev);
1236
1237 gmc_v8_0_mc_program(adev);
1238
1239 if (adev->asic_type == CHIP_TONGA) {
1240 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1241 if (r) {
1242 DRM_ERROR("Failed to load MC firmware!\n");
1243 return r;
1244 }
1245 } else if (adev->asic_type == CHIP_POLARIS11 ||
1246 adev->asic_type == CHIP_POLARIS10 ||
1247 adev->asic_type == CHIP_POLARIS12) {
1248 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1249 if (r) {
1250 DRM_ERROR("Failed to load MC firmware!\n");
1251 return r;
1252 }
1253 }
1254
1255 r = gmc_v8_0_gart_enable(adev);
1256 if (r)
1257 return r;
1258
1259 return r;
1260 }
1261
gmc_v8_0_hw_fini(void * handle)1262 static int gmc_v8_0_hw_fini(void *handle)
1263 {
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265
1266 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1267 gmc_v8_0_gart_disable(adev);
1268
1269 return 0;
1270 }
1271
gmc_v8_0_suspend(void * handle)1272 static int gmc_v8_0_suspend(void *handle)
1273 {
1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275
1276 gmc_v8_0_hw_fini(adev);
1277
1278 return 0;
1279 }
1280
gmc_v8_0_resume(void * handle)1281 static int gmc_v8_0_resume(void *handle)
1282 {
1283 int r;
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285
1286 r = gmc_v8_0_hw_init(adev);
1287 if (r)
1288 return r;
1289
1290 amdgpu_vmid_reset_all(adev);
1291
1292 return 0;
1293 }
1294
gmc_v8_0_is_idle(void * handle)1295 static bool gmc_v8_0_is_idle(void *handle)
1296 {
1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298 u32 tmp = RREG32(mmSRBM_STATUS);
1299
1300 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1301 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1302 return false;
1303
1304 return true;
1305 }
1306
gmc_v8_0_wait_for_idle(void * handle)1307 static int gmc_v8_0_wait_for_idle(void *handle)
1308 {
1309 unsigned i;
1310 u32 tmp;
1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312
1313 for (i = 0; i < adev->usec_timeout; i++) {
1314 /* read MC_STATUS */
1315 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1316 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1317 SRBM_STATUS__MCC_BUSY_MASK |
1318 SRBM_STATUS__MCD_BUSY_MASK |
1319 SRBM_STATUS__VMC_BUSY_MASK |
1320 SRBM_STATUS__VMC1_BUSY_MASK);
1321 if (!tmp)
1322 return 0;
1323 udelay(1);
1324 }
1325 return -ETIMEDOUT;
1326
1327 }
1328
gmc_v8_0_check_soft_reset(void * handle)1329 static bool gmc_v8_0_check_soft_reset(void *handle)
1330 {
1331 u32 srbm_soft_reset = 0;
1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333 u32 tmp = RREG32(mmSRBM_STATUS);
1334
1335 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1336 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1337 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1338
1339 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1340 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1341 if (!(adev->flags & AMD_IS_APU))
1342 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1343 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1344 }
1345 if (srbm_soft_reset) {
1346 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1347 return true;
1348 } else {
1349 adev->gmc.srbm_soft_reset = 0;
1350 return false;
1351 }
1352 }
1353
gmc_v8_0_pre_soft_reset(void * handle)1354 static int gmc_v8_0_pre_soft_reset(void *handle)
1355 {
1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357
1358 if (!adev->gmc.srbm_soft_reset)
1359 return 0;
1360
1361 gmc_v8_0_mc_stop(adev);
1362 if (gmc_v8_0_wait_for_idle(adev)) {
1363 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1364 }
1365
1366 return 0;
1367 }
1368
gmc_v8_0_soft_reset(void * handle)1369 static int gmc_v8_0_soft_reset(void *handle)
1370 {
1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372 u32 srbm_soft_reset;
1373
1374 if (!adev->gmc.srbm_soft_reset)
1375 return 0;
1376 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1377
1378 if (srbm_soft_reset) {
1379 u32 tmp;
1380
1381 tmp = RREG32(mmSRBM_SOFT_RESET);
1382 tmp |= srbm_soft_reset;
1383 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1384 WREG32(mmSRBM_SOFT_RESET, tmp);
1385 tmp = RREG32(mmSRBM_SOFT_RESET);
1386
1387 udelay(50);
1388
1389 tmp &= ~srbm_soft_reset;
1390 WREG32(mmSRBM_SOFT_RESET, tmp);
1391 tmp = RREG32(mmSRBM_SOFT_RESET);
1392
1393 /* Wait a little for things to settle down */
1394 udelay(50);
1395 }
1396
1397 return 0;
1398 }
1399
gmc_v8_0_post_soft_reset(void * handle)1400 static int gmc_v8_0_post_soft_reset(void *handle)
1401 {
1402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404 if (!adev->gmc.srbm_soft_reset)
1405 return 0;
1406
1407 gmc_v8_0_mc_resume(adev);
1408 return 0;
1409 }
1410
gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)1411 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1412 struct amdgpu_irq_src *src,
1413 unsigned type,
1414 enum amdgpu_interrupt_state state)
1415 {
1416 u32 tmp;
1417 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1418 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1419 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1420 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1421 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1422 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1423 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1424
1425 switch (state) {
1426 case AMDGPU_IRQ_STATE_DISABLE:
1427 /* system context */
1428 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1429 tmp &= ~bits;
1430 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1431 /* VMs */
1432 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1433 tmp &= ~bits;
1434 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1435 break;
1436 case AMDGPU_IRQ_STATE_ENABLE:
1437 /* system context */
1438 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1439 tmp |= bits;
1440 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1441 /* VMs */
1442 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1443 tmp |= bits;
1444 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1445 break;
1446 default:
1447 break;
1448 }
1449
1450 return 0;
1451 }
1452
gmc_v8_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1453 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1454 struct amdgpu_irq_src *source,
1455 struct amdgpu_iv_entry *entry)
1456 {
1457 u32 addr, status, mc_client, vmid;
1458
1459 if (amdgpu_sriov_vf(adev)) {
1460 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1461 entry->src_id, entry->src_data[0]);
1462 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1463 return 0;
1464 }
1465
1466 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1467 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1468 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1469 /* reset addr and status */
1470 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1471
1472 if (!addr && !status)
1473 return 0;
1474
1475 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1476 gmc_v8_0_set_fault_enable_default(adev, false);
1477
1478 if (printk_ratelimit()) {
1479 struct amdgpu_task_info task_info;
1480
1481 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1482 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1483
1484 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1485 entry->src_id, entry->src_data[0], task_info.process_name,
1486 task_info.tgid, task_info.task_name, task_info.pid);
1487 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1488 addr);
1489 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1490 status);
1491 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1492 entry->pasid);
1493 }
1494
1495 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1496 VMID);
1497 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1498 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1499 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1500 u32 protections = REG_GET_FIELD(status,
1501 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1502 PROTECTIONS);
1503
1504 info->vmid = vmid;
1505 info->mc_id = REG_GET_FIELD(status,
1506 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1507 MEMORY_CLIENT_ID);
1508 info->status = status;
1509 info->page_addr = addr;
1510 info->prot_valid = protections & 0x7 ? true : false;
1511 info->prot_read = protections & 0x8 ? true : false;
1512 info->prot_write = protections & 0x10 ? true : false;
1513 info->prot_exec = protections & 0x20 ? true : false;
1514 mb();
1515 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1516 }
1517
1518 return 0;
1519 }
1520
fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1521 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1522 bool enable)
1523 {
1524 uint32_t data;
1525
1526 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1527 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1528 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1529 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1530
1531 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1532 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1533 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1534
1535 data = RREG32(mmMC_HUB_MISC_VM_CG);
1536 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1537 WREG32(mmMC_HUB_MISC_VM_CG, data);
1538
1539 data = RREG32(mmMC_XPB_CLK_GAT);
1540 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1541 WREG32(mmMC_XPB_CLK_GAT, data);
1542
1543 data = RREG32(mmATC_MISC_CG);
1544 data |= ATC_MISC_CG__ENABLE_MASK;
1545 WREG32(mmATC_MISC_CG, data);
1546
1547 data = RREG32(mmMC_CITF_MISC_WR_CG);
1548 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1549 WREG32(mmMC_CITF_MISC_WR_CG, data);
1550
1551 data = RREG32(mmMC_CITF_MISC_RD_CG);
1552 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1553 WREG32(mmMC_CITF_MISC_RD_CG, data);
1554
1555 data = RREG32(mmMC_CITF_MISC_VM_CG);
1556 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1557 WREG32(mmMC_CITF_MISC_VM_CG, data);
1558
1559 data = RREG32(mmVM_L2_CG);
1560 data |= VM_L2_CG__ENABLE_MASK;
1561 WREG32(mmVM_L2_CG, data);
1562 } else {
1563 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1564 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1565 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1566
1567 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1568 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1569 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1570
1571 data = RREG32(mmMC_HUB_MISC_VM_CG);
1572 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1573 WREG32(mmMC_HUB_MISC_VM_CG, data);
1574
1575 data = RREG32(mmMC_XPB_CLK_GAT);
1576 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1577 WREG32(mmMC_XPB_CLK_GAT, data);
1578
1579 data = RREG32(mmATC_MISC_CG);
1580 data &= ~ATC_MISC_CG__ENABLE_MASK;
1581 WREG32(mmATC_MISC_CG, data);
1582
1583 data = RREG32(mmMC_CITF_MISC_WR_CG);
1584 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1585 WREG32(mmMC_CITF_MISC_WR_CG, data);
1586
1587 data = RREG32(mmMC_CITF_MISC_RD_CG);
1588 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1589 WREG32(mmMC_CITF_MISC_RD_CG, data);
1590
1591 data = RREG32(mmMC_CITF_MISC_VM_CG);
1592 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1593 WREG32(mmMC_CITF_MISC_VM_CG, data);
1594
1595 data = RREG32(mmVM_L2_CG);
1596 data &= ~VM_L2_CG__ENABLE_MASK;
1597 WREG32(mmVM_L2_CG, data);
1598 }
1599 }
1600
fiji_update_mc_light_sleep(struct amdgpu_device * adev,bool enable)1601 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1602 bool enable)
1603 {
1604 uint32_t data;
1605
1606 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1607 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1608 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1609 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1610
1611 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1612 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1613 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1614
1615 data = RREG32(mmMC_HUB_MISC_VM_CG);
1616 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1617 WREG32(mmMC_HUB_MISC_VM_CG, data);
1618
1619 data = RREG32(mmMC_XPB_CLK_GAT);
1620 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1621 WREG32(mmMC_XPB_CLK_GAT, data);
1622
1623 data = RREG32(mmATC_MISC_CG);
1624 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1625 WREG32(mmATC_MISC_CG, data);
1626
1627 data = RREG32(mmMC_CITF_MISC_WR_CG);
1628 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1629 WREG32(mmMC_CITF_MISC_WR_CG, data);
1630
1631 data = RREG32(mmMC_CITF_MISC_RD_CG);
1632 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1633 WREG32(mmMC_CITF_MISC_RD_CG, data);
1634
1635 data = RREG32(mmMC_CITF_MISC_VM_CG);
1636 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1637 WREG32(mmMC_CITF_MISC_VM_CG, data);
1638
1639 data = RREG32(mmVM_L2_CG);
1640 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1641 WREG32(mmVM_L2_CG, data);
1642 } else {
1643 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1644 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1645 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1646
1647 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1648 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1649 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1650
1651 data = RREG32(mmMC_HUB_MISC_VM_CG);
1652 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1653 WREG32(mmMC_HUB_MISC_VM_CG, data);
1654
1655 data = RREG32(mmMC_XPB_CLK_GAT);
1656 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1657 WREG32(mmMC_XPB_CLK_GAT, data);
1658
1659 data = RREG32(mmATC_MISC_CG);
1660 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1661 WREG32(mmATC_MISC_CG, data);
1662
1663 data = RREG32(mmMC_CITF_MISC_WR_CG);
1664 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1665 WREG32(mmMC_CITF_MISC_WR_CG, data);
1666
1667 data = RREG32(mmMC_CITF_MISC_RD_CG);
1668 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1669 WREG32(mmMC_CITF_MISC_RD_CG, data);
1670
1671 data = RREG32(mmMC_CITF_MISC_VM_CG);
1672 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1673 WREG32(mmMC_CITF_MISC_VM_CG, data);
1674
1675 data = RREG32(mmVM_L2_CG);
1676 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1677 WREG32(mmVM_L2_CG, data);
1678 }
1679 }
1680
gmc_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1681 static int gmc_v8_0_set_clockgating_state(void *handle,
1682 enum amd_clockgating_state state)
1683 {
1684 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1685
1686 if (amdgpu_sriov_vf(adev))
1687 return 0;
1688
1689 switch (adev->asic_type) {
1690 case CHIP_FIJI:
1691 fiji_update_mc_medium_grain_clock_gating(adev,
1692 state == AMD_CG_STATE_GATE);
1693 fiji_update_mc_light_sleep(adev,
1694 state == AMD_CG_STATE_GATE);
1695 break;
1696 default:
1697 break;
1698 }
1699 return 0;
1700 }
1701
gmc_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)1702 static int gmc_v8_0_set_powergating_state(void *handle,
1703 enum amd_powergating_state state)
1704 {
1705 return 0;
1706 }
1707
gmc_v8_0_get_clockgating_state(void * handle,u32 * flags)1708 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1709 {
1710 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1711 int data;
1712
1713 if (amdgpu_sriov_vf(adev))
1714 *flags = 0;
1715
1716 /* AMD_CG_SUPPORT_MC_MGCG */
1717 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1718 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1719 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1720
1721 /* AMD_CG_SUPPORT_MC_LS */
1722 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1723 *flags |= AMD_CG_SUPPORT_MC_LS;
1724 }
1725
1726 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1727 .name = "gmc_v8_0",
1728 .early_init = gmc_v8_0_early_init,
1729 .late_init = gmc_v8_0_late_init,
1730 .sw_init = gmc_v8_0_sw_init,
1731 .sw_fini = gmc_v8_0_sw_fini,
1732 .hw_init = gmc_v8_0_hw_init,
1733 .hw_fini = gmc_v8_0_hw_fini,
1734 .suspend = gmc_v8_0_suspend,
1735 .resume = gmc_v8_0_resume,
1736 .is_idle = gmc_v8_0_is_idle,
1737 .wait_for_idle = gmc_v8_0_wait_for_idle,
1738 .check_soft_reset = gmc_v8_0_check_soft_reset,
1739 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1740 .soft_reset = gmc_v8_0_soft_reset,
1741 .post_soft_reset = gmc_v8_0_post_soft_reset,
1742 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1743 .set_powergating_state = gmc_v8_0_set_powergating_state,
1744 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1745 };
1746
1747 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1748 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1749 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1750 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1751 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1752 .set_prt = gmc_v8_0_set_prt,
1753 .get_vm_pde = gmc_v8_0_get_vm_pde,
1754 .get_vm_pte = gmc_v8_0_get_vm_pte
1755 };
1756
1757 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1758 .set = gmc_v8_0_vm_fault_interrupt_state,
1759 .process = gmc_v8_0_process_interrupt,
1760 };
1761
gmc_v8_0_set_gmc_funcs(struct amdgpu_device * adev)1762 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1763 {
1764 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1765 }
1766
gmc_v8_0_set_irq_funcs(struct amdgpu_device * adev)1767 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1768 {
1769 adev->gmc.vm_fault.num_types = 1;
1770 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1771 }
1772
1773 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1774 {
1775 .type = AMD_IP_BLOCK_TYPE_GMC,
1776 .major = 8,
1777 .minor = 0,
1778 .rev = 0,
1779 .funcs = &gmc_v8_0_ip_funcs,
1780 };
1781
1782 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1783 {
1784 .type = AMD_IP_BLOCK_TYPE_GMC,
1785 .major = 8,
1786 .minor = 1,
1787 .rev = 0,
1788 .funcs = &gmc_v8_0_ip_funcs,
1789 };
1790
1791 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1792 {
1793 .type = AMD_IP_BLOCK_TYPE_GMC,
1794 .major = 8,
1795 .minor = 5,
1796 .rev = 0,
1797 .funcs = &gmc_v8_0_ip_funcs,
1798 };
1799