1 /* $NetBSD: nouveau_nvkm_engine_nvdec_gm107.c,v 1.2 2021/12/18 23:45:37 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_nvdec_gm107.c,v 1.2 2021/12/18 23:45:37 riastradh Exp $");
26
27 #include "priv.h"
28
29 static const struct nvkm_falcon_func
30 gm107_nvdec_flcn = {
31 .debug = 0xd00,
32 .fbif = 0x600,
33 .load_imem = nvkm_falcon_v1_load_imem,
34 .load_dmem = nvkm_falcon_v1_load_dmem,
35 .read_dmem = nvkm_falcon_v1_read_dmem,
36 .bind_context = nvkm_falcon_v1_bind_context,
37 .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
38 .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
39 .set_start_addr = nvkm_falcon_v1_set_start_addr,
40 .start = nvkm_falcon_v1_start,
41 .enable = nvkm_falcon_v1_enable,
42 .disable = nvkm_falcon_v1_disable,
43 };
44
45 static const struct nvkm_nvdec_func
46 gm107_nvdec = {
47 .flcn = &gm107_nvdec_flcn,
48 };
49
50 static int
gm107_nvdec_nofw(struct nvkm_nvdec * nvdec,int ver,const struct nvkm_nvdec_fwif * fwif)51 gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
52 const struct nvkm_nvdec_fwif *fwif)
53 {
54 return 0;
55 }
56
57 static const struct nvkm_nvdec_fwif
58 gm107_nvdec_fwif[] = {
59 { -1, gm107_nvdec_nofw, &gm107_nvdec },
60 {}
61 };
62
63 int
gm107_nvdec_new(struct nvkm_device * device,int index,struct nvkm_nvdec ** pnvdec)64 gm107_nvdec_new(struct nvkm_device *device, int index,
65 struct nvkm_nvdec **pnvdec)
66 {
67 return nvkm_nvdec_new_(gm107_nvdec_fwif, device, index, pnvdec);
68 }
69