1 /* $NetBSD: nouveau_nvkm_engine_gr_gm107.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2013 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gm107.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
28
29 #include "gf100.h"
30 #include "ctxgf100.h"
31
32 #include <subdev/bios.h>
33 #include <subdev/bios/bit.h>
34 #include <subdev/bios/init.h>
35 #include <subdev/bios/P0260.h>
36 #include <subdev/fb.h>
37
38 #include <nvif/class.h>
39
40 /*******************************************************************************
41 * PGRAPH register lists
42 ******************************************************************************/
43
44 static const struct gf100_gr_init
45 gm107_gr_init_main_0[] = {
46 { 0x40880c, 1, 0x04, 0x00000000 },
47 { 0x408910, 1, 0x04, 0x00000000 },
48 { 0x408984, 1, 0x04, 0x00000000 },
49 { 0x41a8a0, 1, 0x04, 0x00000000 },
50 { 0x400080, 1, 0x04, 0x003003c2 },
51 { 0x400088, 1, 0x04, 0x0001bfe7 },
52 { 0x40008c, 1, 0x04, 0x00060000 },
53 { 0x400090, 1, 0x04, 0x00000030 },
54 { 0x40013c, 1, 0x04, 0x003901f3 },
55 { 0x400140, 1, 0x04, 0x00000100 },
56 { 0x400144, 1, 0x04, 0x00000000 },
57 { 0x400148, 1, 0x04, 0x00000110 },
58 { 0x400138, 1, 0x04, 0x00000000 },
59 { 0x400130, 2, 0x04, 0x00000000 },
60 { 0x400124, 1, 0x04, 0x00000002 },
61 {}
62 };
63
64 static const struct gf100_gr_init
65 gm107_gr_init_ds_0[] = {
66 { 0x405844, 1, 0x04, 0x00ffffff },
67 { 0x405850, 1, 0x04, 0x00000000 },
68 { 0x405900, 1, 0x04, 0x00000000 },
69 { 0x405908, 1, 0x04, 0x00000000 },
70 {}
71 };
72
73 const struct gf100_gr_init
74 gm107_gr_init_scc_0[] = {
75 { 0x40803c, 1, 0x04, 0x00000010 },
76 {}
77 };
78
79 static const struct gf100_gr_init
80 gm107_gr_init_sked_0[] = {
81 { 0x407010, 1, 0x04, 0x00000000 },
82 { 0x407040, 1, 0x04, 0x40440424 },
83 { 0x407048, 1, 0x04, 0x0000000a },
84 {}
85 };
86
87 const struct gf100_gr_init
88 gm107_gr_init_prop_0[] = {
89 { 0x418408, 1, 0x04, 0x00000000 },
90 { 0x4184a0, 1, 0x04, 0x00000000 },
91 {}
92 };
93
94 const struct gf100_gr_init
95 gm107_gr_init_setup_1[] = {
96 { 0x4188c8, 2, 0x04, 0x00000000 },
97 { 0x4188d0, 1, 0x04, 0x00010000 },
98 { 0x4188d4, 1, 0x04, 0x00010201 },
99 {}
100 };
101
102 const struct gf100_gr_init
103 gm107_gr_init_zcull_0[] = {
104 { 0x418910, 1, 0x04, 0x00010001 },
105 { 0x418914, 1, 0x04, 0x00000301 },
106 { 0x418918, 1, 0x04, 0x00800000 },
107 { 0x418930, 2, 0x04, 0x00000000 },
108 { 0x418980, 1, 0x04, 0x77777770 },
109 { 0x418984, 3, 0x04, 0x77777777 },
110 {}
111 };
112
113 const struct gf100_gr_init
114 gm107_gr_init_gpc_unk_1[] = {
115 { 0x418d00, 1, 0x04, 0x00000000 },
116 { 0x418f00, 1, 0x04, 0x00000400 },
117 { 0x418f08, 1, 0x04, 0x00000000 },
118 { 0x418e08, 1, 0x04, 0x00000000 },
119 {}
120 };
121
122 static const struct gf100_gr_init
123 gm107_gr_init_tpccs_0[] = {
124 { 0x419dc4, 1, 0x04, 0x00000000 },
125 { 0x419dc8, 1, 0x04, 0x00000501 },
126 { 0x419dd0, 1, 0x04, 0x00000000 },
127 { 0x419dd4, 1, 0x04, 0x00000100 },
128 { 0x419dd8, 1, 0x04, 0x00000001 },
129 { 0x419ddc, 1, 0x04, 0x00000002 },
130 { 0x419de0, 1, 0x04, 0x00000001 },
131 { 0x419d0c, 1, 0x04, 0x00000000 },
132 { 0x419d10, 1, 0x04, 0x00000014 },
133 {}
134 };
135
136 const struct gf100_gr_init
137 gm107_gr_init_tex_0[] = {
138 { 0x419ab0, 1, 0x04, 0x00000000 },
139 { 0x419ab8, 1, 0x04, 0x000000e7 },
140 { 0x419abc, 1, 0x04, 0x00000000 },
141 { 0x419acc, 1, 0x04, 0x000000ff },
142 { 0x419ac0, 1, 0x04, 0x00000000 },
143 { 0x419aa8, 2, 0x04, 0x00000000 },
144 { 0x419ad0, 2, 0x04, 0x00000000 },
145 { 0x419ae0, 2, 0x04, 0x00000000 },
146 { 0x419af0, 4, 0x04, 0x00000000 },
147 {}
148 };
149
150 static const struct gf100_gr_init
151 gm107_gr_init_pe_0[] = {
152 { 0x419900, 1, 0x04, 0x000000ff },
153 { 0x41980c, 1, 0x04, 0x00000010 },
154 { 0x419844, 1, 0x04, 0x00000000 },
155 { 0x419838, 1, 0x04, 0x000000ff },
156 { 0x419850, 1, 0x04, 0x00000004 },
157 { 0x419854, 2, 0x04, 0x00000000 },
158 { 0x419894, 3, 0x04, 0x00100401 },
159 {}
160 };
161
162 const struct gf100_gr_init
163 gm107_gr_init_l1c_0[] = {
164 { 0x419c98, 1, 0x04, 0x00000000 },
165 { 0x419cc0, 2, 0x04, 0x00000000 },
166 {}
167 };
168
169 static const struct gf100_gr_init
170 gm107_gr_init_sm_0[] = {
171 { 0x419e30, 1, 0x04, 0x000000ff },
172 { 0x419e00, 1, 0x04, 0x00000000 },
173 { 0x419ea0, 1, 0x04, 0x00000000 },
174 { 0x419ee4, 1, 0x04, 0x00000000 },
175 { 0x419ea4, 1, 0x04, 0x00000100 },
176 { 0x419ea8, 1, 0x04, 0x01000000 },
177 { 0x419ee8, 1, 0x04, 0x00000091 },
178 { 0x419eb4, 1, 0x04, 0x00000000 },
179 { 0x419ebc, 2, 0x04, 0x00000000 },
180 { 0x419edc, 1, 0x04, 0x000c1810 },
181 { 0x419ed8, 1, 0x04, 0x00000000 },
182 { 0x419ee0, 1, 0x04, 0x00000000 },
183 { 0x419f74, 1, 0x04, 0x00005155 },
184 { 0x419f80, 4, 0x04, 0x00000000 },
185 {}
186 };
187
188 static const struct gf100_gr_init
189 gm107_gr_init_l1c_1[] = {
190 { 0x419ccc, 2, 0x04, 0x00000000 },
191 { 0x419c80, 1, 0x04, 0x3f006022 },
192 { 0x419c88, 1, 0x04, 0x00000000 },
193 {}
194 };
195
196 static const struct gf100_gr_init
197 gm107_gr_init_pes_0[] = {
198 { 0x41be50, 1, 0x04, 0x000000ff },
199 { 0x41be04, 1, 0x04, 0x00000000 },
200 { 0x41be08, 1, 0x04, 0x00000004 },
201 { 0x41be0c, 1, 0x04, 0x00000008 },
202 { 0x41be10, 1, 0x04, 0x0e3b8bc7 },
203 { 0x41be14, 2, 0x04, 0x00000000 },
204 { 0x41be3c, 5, 0x04, 0x00100401 },
205 {}
206 };
207
208 const struct gf100_gr_init
209 gm107_gr_init_wwdx_0[] = {
210 { 0x41bfd4, 1, 0x04, 0x00800000 },
211 { 0x41bfdc, 1, 0x04, 0x00000000 },
212 {}
213 };
214
215 const struct gf100_gr_init
216 gm107_gr_init_cbm_0[] = {
217 { 0x41becc, 1, 0x04, 0x00000000 },
218 {}
219 };
220
221 static const struct gf100_gr_init
222 gm107_gr_init_be_0[] = {
223 { 0x408890, 1, 0x04, 0x000000ff },
224 { 0x408850, 1, 0x04, 0x00000004 },
225 { 0x408878, 1, 0x04, 0x00c81603 },
226 { 0x40887c, 1, 0x04, 0x80543432 },
227 { 0x408880, 1, 0x04, 0x0010581e },
228 { 0x408884, 1, 0x04, 0x00001205 },
229 { 0x408974, 1, 0x04, 0x000000ff },
230 { 0x408914, 8, 0x04, 0x00000000 },
231 { 0x408950, 1, 0x04, 0x00000000 },
232 { 0x408954, 1, 0x04, 0x0000ffff },
233 { 0x408958, 1, 0x04, 0x00000034 },
234 { 0x40895c, 1, 0x04, 0x8531a003 },
235 { 0x408960, 1, 0x04, 0x0561985a },
236 { 0x408964, 1, 0x04, 0x04e15c4f },
237 { 0x408968, 1, 0x04, 0x02808833 },
238 { 0x40896c, 1, 0x04, 0x01f02438 },
239 { 0x408970, 1, 0x04, 0x00012c00 },
240 { 0x408988, 1, 0x04, 0x08040201 },
241 { 0x40898c, 1, 0x04, 0x80402010 },
242 {}
243 };
244
245 static const struct gf100_gr_init
246 gm107_gr_init_sm_1[] = {
247 { 0x419e5c, 1, 0x04, 0x00000000 },
248 { 0x419e58, 1, 0x04, 0x00000000 },
249 {}
250 };
251
252 static const struct gf100_gr_pack
253 gm107_gr_pack_mmio[] = {
254 { gm107_gr_init_main_0 },
255 { gk110_gr_init_fe_0 },
256 { gf100_gr_init_pri_0 },
257 { gf100_gr_init_rstr2d_0 },
258 { gf100_gr_init_pd_0 },
259 { gm107_gr_init_ds_0 },
260 { gm107_gr_init_scc_0 },
261 { gm107_gr_init_sked_0 },
262 { gk110_gr_init_cwd_0 },
263 { gm107_gr_init_prop_0 },
264 { gk208_gr_init_gpc_unk_0 },
265 { gf100_gr_init_setup_0 },
266 { gf100_gr_init_crstr_0 },
267 { gm107_gr_init_setup_1 },
268 { gm107_gr_init_zcull_0 },
269 { gf100_gr_init_gpm_0 },
270 { gm107_gr_init_gpc_unk_1 },
271 { gf100_gr_init_gcc_0 },
272 { gk104_gr_init_gpc_unk_2 },
273 { gm107_gr_init_tpccs_0 },
274 { gm107_gr_init_tex_0 },
275 { gm107_gr_init_pe_0 },
276 { gm107_gr_init_l1c_0 },
277 { gf100_gr_init_mpc_0 },
278 { gm107_gr_init_sm_0 },
279 { gm107_gr_init_l1c_1 },
280 { gm107_gr_init_pes_0 },
281 { gm107_gr_init_wwdx_0 },
282 { gm107_gr_init_cbm_0 },
283 { gm107_gr_init_be_0 },
284 { gm107_gr_init_sm_1 },
285 {}
286 };
287
288 /*******************************************************************************
289 * PGRAPH engine/subdev functions
290 ******************************************************************************/
291
292 void
gm107_gr_init_400054(struct gf100_gr * gr)293 gm107_gr_init_400054(struct gf100_gr *gr)
294 {
295 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63);
296 }
297
298 void
gm107_gr_init_shader_exceptions(struct gf100_gr * gr,int gpc,int tpc)299 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
300 {
301 struct nvkm_device *device = gr->base.engine.subdev.device;
302 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
303 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
304 }
305
306 void
gm107_gr_init_504430(struct gf100_gr * gr,int gpc,int tpc)307 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
308 {
309 struct nvkm_device *device = gr->base.engine.subdev.device;
310 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
311 }
312
313 static void
gm107_gr_init_bios_2(struct gf100_gr * gr)314 gm107_gr_init_bios_2(struct gf100_gr *gr)
315 {
316 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
317 struct nvkm_device *device = subdev->device;
318 struct nvkm_bios *bios = device->bios;
319 struct bit_entry bit_P;
320 if (!bit_entry(bios, 'P', &bit_P) &&
321 bit_P.version == 2 && bit_P.length >= 0x2c) {
322 u32 data = nvbios_rd32(bios, bit_P.offset + 0x28);
323 if (data) {
324 u8 ver = nvbios_rd08(bios, data + 0x00);
325 u8 hdr = nvbios_rd08(bios, data + 0x01);
326 if (ver == 0x20 && hdr >= 8) {
327 data = nvbios_rd32(bios, data + 0x04);
328 if (data) {
329 u32 save = nvkm_rd32(device, 0x619444);
330 nvbios_init(subdev, data);
331 nvkm_wr32(device, 0x619444, save);
332 }
333 }
334 }
335 }
336 }
337
338 void
gm107_gr_init_bios(struct gf100_gr * gr)339 gm107_gr_init_bios(struct gf100_gr *gr)
340 {
341 static const struct {
342 u32 ctrl;
343 u32 data;
344 } regs[] = {
345 { 0x419ed8, 0x419ee0 },
346 { 0x419ad0, 0x419ad4 },
347 { 0x419ae0, 0x419ae4 },
348 { 0x419af0, 0x419af4 },
349 { 0x419af8, 0x419afc },
350 };
351 struct nvkm_device *device = gr->base.engine.subdev.device;
352 struct nvkm_bios *bios = device->bios;
353 struct nvbios_P0260E infoE;
354 struct nvbios_P0260X infoX;
355 int E = -1, X;
356 u8 ver, hdr;
357
358 while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
359 if (X = -1, E < ARRAY_SIZE(regs)) {
360 nvkm_wr32(device, regs[E].ctrl, infoE.data);
361 while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
362 nvkm_wr32(device, regs[E].data, infoX.data);
363 }
364 }
365 }
366
367 static void
gm107_gr_init_gpc_mmu(struct gf100_gr * gr)368 gm107_gr_init_gpc_mmu(struct gf100_gr *gr)
369 {
370 struct nvkm_device *device = gr->base.engine.subdev.device;
371 struct nvkm_fb *fb = device->fb;
372
373 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
374 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
375 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
376 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
377 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
378 }
379
380 #include "fuc/hubgm107.fuc5.h"
381
382 static struct gf100_gr_ucode
383 gm107_gr_fecs_ucode = {
384 .code.data = gm107_grhub_code,
385 .code.size = sizeof(gm107_grhub_code),
386 .data.data = gm107_grhub_data,
387 .data.size = sizeof(gm107_grhub_data),
388 };
389
390 #include "fuc/gpcgm107.fuc5.h"
391
392 static struct gf100_gr_ucode
393 gm107_gr_gpccs_ucode = {
394 .code.data = gm107_grgpc_code,
395 .code.size = sizeof(gm107_grgpc_code),
396 .data.data = gm107_grgpc_data,
397 .data.size = sizeof(gm107_grgpc_data),
398 };
399
400 static const struct gf100_gr_func
401 gm107_gr = {
402 .oneinit_tiles = gf100_gr_oneinit_tiles,
403 .oneinit_sm_id = gf100_gr_oneinit_sm_id,
404 .init = gf100_gr_init,
405 .init_gpc_mmu = gm107_gr_init_gpc_mmu,
406 .init_bios = gm107_gr_init_bios,
407 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
408 .init_zcull = gf117_gr_init_zcull,
409 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
410 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
411 .init_bios_2 = gm107_gr_init_bios_2,
412 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
413 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
414 .init_419cc0 = gf100_gr_init_419cc0,
415 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
416 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
417 .init_504430 = gm107_gr_init_504430,
418 .init_shader_exceptions = gm107_gr_init_shader_exceptions,
419 .init_400054 = gm107_gr_init_400054,
420 .trap_mp = gf100_gr_trap_mp,
421 .mmio = gm107_gr_pack_mmio,
422 .fecs.ucode = &gm107_gr_fecs_ucode,
423 .gpccs.ucode = &gm107_gr_gpccs_ucode,
424 .rops = gf100_gr_rops,
425 .ppc_nr = 2,
426 .grctx = &gm107_grctx,
427 .zbc = &gf100_gr_zbc,
428 .sclass = {
429 { -1, -1, FERMI_TWOD_A },
430 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
431 { -1, -1, MAXWELL_A, &gf100_fermi },
432 { -1, -1, MAXWELL_COMPUTE_A },
433 {}
434 }
435 };
436
437 static const struct gf100_gr_fwif
438 gm107_gr_fwif[] = {
439 { -1, gf100_gr_load, &gm107_gr },
440 { -1, gf100_gr_nofw, &gm107_gr },
441 {}
442 };
443
444 int
gm107_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)445 gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
446 {
447 return gf100_gr_new_(gm107_gr_fwif, device, index, pgr);
448 }
449