1 /* $NetBSD: amdgpu_gfxhub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfxhub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "gfxhub_v1_0.h"
30
31 #include "gc/gc_9_0_offset.h"
32 #include "gc/gc_9_0_sh_mask.h"
33 #include "gc/gc_9_0_default.h"
34 #include "vega10_enum.h"
35
36 #include "soc15_common.h"
37
gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device * adev)38 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
39 {
40 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
41 }
42
gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)43 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
44 uint64_t page_table_base)
45 {
46 /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
47 int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
48 - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
49
50 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
51 offset * vmid, lower_32_bits(page_table_base));
52
53 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
54 offset * vmid, upper_32_bits(page_table_base));
55 }
56
gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device * adev)57 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
58 {
59 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
60
61 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
62
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
64 (u32)(adev->gmc.gart_start >> 12));
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
66 (u32)(adev->gmc.gart_start >> 44));
67
68 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
69 (u32)(adev->gmc.gart_end >> 12));
70 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
71 (u32)(adev->gmc.gart_end >> 44));
72 }
73
gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device * adev)74 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
75 {
76 uint64_t value;
77
78 /* Program the AGP BAR */
79 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
80 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
81 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
82
83 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
84 /* Program the system aperture low logical page number. */
85 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
86 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
87
88 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
89 /*
90 * Raven2 has a HW issue that it is unable to use the
91 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
92 * So here is the workaround that increase system
93 * aperture high address (add 1) to get rid of the VM
94 * fault and hardware hang.
95 */
96 WREG32_SOC15_RLC(GC, 0,
97 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
98 max((adev->gmc.fb_end >> 18) + 0x1,
99 adev->gmc.agp_end >> 18));
100 else
101 WREG32_SOC15_RLC(
102 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
103 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
104
105 /* Set default page address. */
106 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
107 adev->vm_manager.vram_base_offset;
108 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
109 (u32)(value >> 12));
110 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
111 (u32)(value >> 44));
112
113 /* Program "protection fault". */
114 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
115 (u32)(adev->dummy_page_addr >> 12));
116 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
117 (u32)((u64)adev->dummy_page_addr >> 44));
118
119 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
120 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
121 }
122 }
123
gfxhub_v1_0_init_tlb_regs(struct amdgpu_device * adev)124 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
125 {
126 uint32_t tmp;
127
128 /* Setup TLB control */
129 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
130
131 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
134 ENABLE_ADVANCED_DRIVER_MODEL, 1);
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
136 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
137 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
138 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
139 MTYPE, MTYPE_UC);/* XXX for emulation. */
140 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
141
142 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
143 }
144
gfxhub_v1_0_init_cache_regs(struct amdgpu_device * adev)145 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
146 {
147 uint32_t tmp;
148
149 /* Setup L2 cache */
150 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
152 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
153 /* XXX for emulation, Refer to closed source code.*/
154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
155 0);
156 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
157 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
158 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
160
161 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
164 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
165
166 tmp = mmVM_L2_CNTL3_DEFAULT;
167 if (adev->gmc.translate_further) {
168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
170 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
171 } else {
172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
173 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
174 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
175 }
176 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
177
178 tmp = mmVM_L2_CNTL4_DEFAULT;
179 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
181 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
182 }
183
gfxhub_v1_0_enable_system_domain(struct amdgpu_device * adev)184 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
185 {
186 uint32_t tmp;
187
188 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
192 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
193 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
194 }
195
gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device * adev)196 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
197 {
198 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
199 0XFFFFFFFF);
200 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
201 0x0000000F);
202
203 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
204 0);
205 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
206 0);
207
208 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
209 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
210
211 }
212
gfxhub_v1_0_setup_vmid_config(struct amdgpu_device * adev)213 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
214 {
215 unsigned num_level, block_size;
216 uint32_t tmp;
217 int i;
218
219 num_level = adev->vm_manager.num_level;
220 block_size = adev->vm_manager.block_size;
221 if (adev->gmc.translate_further)
222 num_level -= 1;
223 else
224 block_size -= 9;
225
226 for (i = 0; i <= 14; i++) {
227 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
230 num_level);
231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
232 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
234 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
235 1);
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
237 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
238 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
239 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
241 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
242 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
243 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
244 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
245 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
247 PAGE_TABLE_BLOCK_SIZE,
248 block_size);
249 /* Send no-retry XNACK on fault to suppress VM fault storm. */
250 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
251 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
252 !amdgpu_noretry);
253 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
254 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
255 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
256 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
257 lower_32_bits(adev->vm_manager.max_pfn - 1));
258 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
259 upper_32_bits(adev->vm_manager.max_pfn - 1));
260 }
261 }
262
gfxhub_v1_0_program_invalidation(struct amdgpu_device * adev)263 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
264 {
265 unsigned i;
266
267 for (i = 0 ; i < 18; ++i) {
268 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
269 2 * i, 0xffffffff);
270 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
271 2 * i, 0x1f);
272 }
273 }
274
gfxhub_v1_0_gart_enable(struct amdgpu_device * adev)275 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
276 {
277 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
278 /*
279 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
280 * VF copy registers so vbios post doesn't program them, for
281 * SRIOV driver need to program them
282 */
283 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
284 adev->gmc.vram_start >> 24);
285 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
286 adev->gmc.vram_end >> 24);
287 }
288
289 /* GART Enable. */
290 gfxhub_v1_0_init_gart_aperture_regs(adev);
291 gfxhub_v1_0_init_system_aperture_regs(adev);
292 gfxhub_v1_0_init_tlb_regs(adev);
293 if (!amdgpu_sriov_vf(adev))
294 gfxhub_v1_0_init_cache_regs(adev);
295
296 gfxhub_v1_0_enable_system_domain(adev);
297 if (!amdgpu_sriov_vf(adev))
298 gfxhub_v1_0_disable_identity_aperture(adev);
299 gfxhub_v1_0_setup_vmid_config(adev);
300 gfxhub_v1_0_program_invalidation(adev);
301
302 return 0;
303 }
304
gfxhub_v1_0_gart_disable(struct amdgpu_device * adev)305 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
306 {
307 u32 tmp;
308 u32 i;
309
310 /* Disable all tables */
311 for (i = 0; i < 16; i++)
312 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
313
314 /* Setup TLB control */
315 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
316 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
317 tmp = REG_SET_FIELD(tmp,
318 MC_VM_MX_L1_TLB_CNTL,
319 ENABLE_ADVANCED_DRIVER_MODEL,
320 0);
321 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
322
323 /* Setup L2 cache */
324 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
325 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
326 }
327
328 /**
329 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
330 *
331 * @adev: amdgpu_device pointer
332 * @value: true redirects VM faults to the default page
333 */
gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)334 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
335 bool value)
336 {
337 u32 tmp;
338 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
339 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
340 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
341 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
342 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
343 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
344 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
345 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
346 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
347 tmp = REG_SET_FIELD(tmp,
348 VM_L2_PROTECTION_FAULT_CNTL,
349 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
350 value);
351 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
352 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
353 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
354 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
355 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
356 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
357 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
358 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
359 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
360 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
361 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
362 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
363 if (!value) {
364 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
365 CRASH_ON_NO_RETRY_FAULT, 1);
366 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
367 CRASH_ON_RETRY_FAULT, 1);
368 }
369 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
370 }
371
gfxhub_v1_0_init(struct amdgpu_device * adev)372 void gfxhub_v1_0_init(struct amdgpu_device *adev)
373 {
374 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
375
376 hub->ctx0_ptb_addr_lo32 =
377 SOC15_REG_OFFSET(GC, 0,
378 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
379 hub->ctx0_ptb_addr_hi32 =
380 SOC15_REG_OFFSET(GC, 0,
381 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
382 hub->vm_inv_eng0_sem =
383 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
384 hub->vm_inv_eng0_req =
385 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
386 hub->vm_inv_eng0_ack =
387 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
388 hub->vm_context0_cntl =
389 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
390 hub->vm_l2_pro_fault_status =
391 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
392 hub->vm_l2_pro_fault_cntl =
393 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
394 }
395