xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_4.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1) 
1 /*	$NetBSD: amdgpu_gfx_v9_4.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2020 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v9_4.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28 
29 #include <linux/kernel.h>
30 
31 #include "amdgpu.h"
32 #include "amdgpu_gfx.h"
33 #include "soc15.h"
34 #include "soc15d.h"
35 #include "amdgpu_atomfirmware.h"
36 #include "amdgpu_pm.h"
37 
38 #include "gc/gc_9_4_1_offset.h"
39 #include "gc/gc_9_4_1_sh_mask.h"
40 #include "soc15_common.h"
41 
42 #include "gfx_v9_4.h"
43 #include "amdgpu_ras.h"
44 
45 static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = {
46 	/* CPC */
47 	{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
48 	{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
49 	/* DC */
50 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
51 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
52 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
53 	/* CPF */
54 	{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
55 	{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
56 	/* GDS */
57 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
58 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
59 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
60 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
61 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
62 	/* SPI */
63 	{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
64 	/* SQ */
65 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16 },
66 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16 },
67 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16 },
68 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16 },
69 	/* SQC */
70 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6 },
71 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6 },
72 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6 },
73 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 },
74 	/* TA */
75 	{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16 },
76 	/* TCA */
77 	{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2 },
78 	/* TCC */
79 	{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16 },
80 	{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16 },
81 	/* TCI */
82 	{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72 },
83 	/* TCP */
84 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16 },
85 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16 },
86 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16 },
87 	/* TD */
88 	{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16 },
89 	/* GCEA */
90 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32 },
91 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32 },
92 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 1, 32 },
93 	/* RLC */
94 	{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
95 	{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2), 0, 1, 1 },
96 };
97 
gfx_v9_4_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)98 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
99 				  u32 sh_num, u32 instance)
100 {
101 	u32 data;
102 
103 	if (instance == 0xffffffff)
104 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
105 				     INSTANCE_BROADCAST_WRITES, 1);
106 	else
107 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
108 				     instance);
109 
110 	if (se_num == 0xffffffff)
111 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
112 				     1);
113 	else
114 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
115 
116 	if (sh_num == 0xffffffff)
117 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
118 				     1);
119 	else
120 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
121 
122 	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
123 }
124 
125 static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = {
126 	/* CPC */
127 	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
128 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
129 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
130 	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
131 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
132 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
133 	{ "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
134 	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
135 	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
136 	{ "CPC_DC_CSINVOC_RAM_ME1",
137 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
138 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
139 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
140 	{ "CPC_DC_RESTORE_RAM_ME1",
141 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
142 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
143 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
144 	{ "CPC_DC_CSINVOC_RAM1_ME1",
145 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
146 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
147 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
148 	{ "CPC_DC_RESTORE_RAM1_ME1",
149 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
150 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
151 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
152 
153 	/* CPF */
154 	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
155 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
156 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
157 	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
158 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
159 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
160 	{ "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
161 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
162 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
163 
164 	/* GDS */
165 	{ "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT),
166 	  SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
167 	  SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
168 	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
169 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
170 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
171 	{ "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
172 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
173 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
174 	{ "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
175 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
176 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
177 	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
178 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
179 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
180 	{ "GDS_ME1_PIPE0_PIPE_MEM",
181 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
182 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
183 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
184 	{ "GDS_ME1_PIPE1_PIPE_MEM",
185 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
186 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
187 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
188 	{ "GDS_ME1_PIPE2_PIPE_MEM",
189 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
190 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
191 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
192 	{ "GDS_ME1_PIPE3_PIPE_MEM",
193 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
194 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
195 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
196 
197 	/* SPI */
198 	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
199 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
200 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
201 	{ "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
202 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
203 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
204 	{ "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
205 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
206 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
207 	{ "SPI_WB_GRANT_61", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
208 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_SEC_COUNT),
209 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_DED_COUNT) },
210 	{ "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
211 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
212 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
213 
214 	/* SQ */
215 	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
216 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
217 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
218 	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
219 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
220 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
221 	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
222 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
223 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
224 	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
225 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
226 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
227 	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
228 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
229 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
230 	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
231 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
232 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
233 	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
234 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
235 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
236 
237 	/* SQC */
238 	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
239 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
240 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
241 	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
242 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
243 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
244 	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
245 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
246 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
247 	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
248 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
249 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
250 	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
251 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
252 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
253 	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
254 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
255 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
256 	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
257 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
258 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
259 	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
260 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
261 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
262 	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
263 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
264 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
265 			  INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
266 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
267 			  INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
268 	{ "SQC_INST_BANKA_MISS_FIFO",
269 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
270 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
271 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
272 			  INST_BANKA_MISS_FIFO_DED_COUNT) },
273 	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
274 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
275 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
276 	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
277 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
278 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
279 	{ "SQC_DATA_BANKA_HIT_FIFO",
280 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
281 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
282 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
283 	{ "SQC_DATA_BANKA_MISS_FIFO",
284 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
285 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
286 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
287 			  DATA_BANKA_MISS_FIFO_DED_COUNT) },
288 	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
289 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
290 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
291 	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
292 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
293 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
294 	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
295 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
296 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
297 			  INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
298 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
299 			  INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
300 	{ "SQC_INST_BANKB_MISS_FIFO",
301 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
302 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
303 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
304 			  INST_BANKB_MISS_FIFO_DED_COUNT) },
305 	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
306 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
307 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
308 	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
309 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
310 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
311 	{ "SQC_DATA_BANKB_HIT_FIFO",
312 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
313 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
314 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
315 	{ "SQC_DATA_BANKB_MISS_FIFO",
316 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
317 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
318 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
319 			  DATA_BANKB_MISS_FIFO_DED_COUNT) },
320 	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
321 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
322 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
323 
324 	/* TA */
325 	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
326 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
327 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
328 	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
329 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SEC_COUNT),
330 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_DED_COUNT) },
331 	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
332 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
333 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
334 	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
335 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
336 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
337 	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
338 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
339 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
340 
341 	/* TCA */
342 	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
343 	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
344 	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
345 	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
346 	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
347 	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
348 
349 	/* TCC */
350 	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
351 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
352 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
353 	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
354 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
355 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
356 	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
357 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
358 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
359 	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
360 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
361 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
362 	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
363 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
364 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
365 	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
366 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
367 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
368 	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
369 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
370 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
371 	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
372 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
373 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
374 	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
375 	  SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
376 	  SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
377 	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
378 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
379 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
380 	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
381 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
382 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
383 	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
384 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
385 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
386 	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
387 	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
388 	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
389 	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
390 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
391 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
392 	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
393 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
394 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
395 
396 	/* TCI */
397 	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
398 	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
399 	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
400 
401 	/* TCP */
402 	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
403 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
404 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
405 	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
406 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
407 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
408 	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
409 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
410 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
411 	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
412 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
413 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
414 	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
415 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0, 0 },
416 	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
417 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
418 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
419 	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
420 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
421 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
422 
423 	/* TD */
424 	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
425 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
426 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
427 	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
428 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
429 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
430 	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
431 	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
432 	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
433 
434 	/* EA */
435 	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
436 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
437 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
438 	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
439 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
440 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
441 	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
442 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
443 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
444 	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
445 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
446 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
447 	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
448 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
449 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
450 	{ "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
451 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
452 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
453 	{ "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
454 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
455 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
456 	{ "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
457 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
458 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
459 	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
460 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
461 	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
462 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
463 	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
464 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
465 	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
466 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
467 	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
468 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
469 	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
470 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
471 	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
472 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
473 	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
474 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
475 	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
476 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0, 0 },
477 	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
478 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_DATAMEM_DED_COUNT) },
479 	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
480 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
481 	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
482 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
483 	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
484 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
485 	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
486 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
487 	{ "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
488 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
489 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
490 	{ "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
491 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
492 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
493 	{ "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
494 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
495 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
496 	{ "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
497 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
498 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
499 	{ "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
500 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
501 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
502 	{ "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
503 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
504 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
505 	{ "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
506 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
507 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
508 	{ "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
509 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
510 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
511 	{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
512 	  SOC15_REG_FIELD(GCEA_EDC_CNT, MAM_AFMEM_SEC_COUNT), 0, 0 },
513 	{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
514 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
515 
516 	/* RLC */
517 	{ "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
518 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
519 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
520 	{ "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
521 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
522 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
523 	{ "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
524 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
525 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
526 	{ "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
527 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
528 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
529 	{ "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
530 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
531 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
532 	{ "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
533 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
534 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
535 	{ "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
536 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
537 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
538 	{ "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
539 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
540 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
541 	{ "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
542 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
543 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
544 	{ "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
545 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
546 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
547 	{ "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
548 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
549 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
550 	{ "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
551 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
552 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
553 	{ "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
554 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
555 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
556 	{ "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
557 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
558 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
559 	{ "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
560 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
561 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
562 	{ "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
563 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
564 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
565 };
566 
567 static const char * const vml2_mems[] = {
568 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
569 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
570 	"UTC_VML2_BANK_CACHE_0_4K_MEM0",
571 	"UTC_VML2_BANK_CACHE_0_4K_MEM1",
572 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
573 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
574 	"UTC_VML2_BANK_CACHE_1_4K_MEM0",
575 	"UTC_VML2_BANK_CACHE_1_4K_MEM1",
576 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
577 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
578 	"UTC_VML2_BANK_CACHE_2_4K_MEM0",
579 	"UTC_VML2_BANK_CACHE_2_4K_MEM1",
580 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
581 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
582 	"UTC_VML2_BANK_CACHE_3_4K_MEM0",
583 	"UTC_VML2_BANK_CACHE_3_4K_MEM1",
584 	"UTC_VML2_IFIFO_GROUP0",
585 	"UTC_VML2_IFIFO_GROUP1",
586 	"UTC_VML2_IFIFO_GROUP2",
587 	"UTC_VML2_IFIFO_GROUP3",
588 	"UTC_VML2_IFIFO_GROUP4",
589 	"UTC_VML2_IFIFO_GROUP5",
590 	"UTC_VML2_IFIFO_GROUP6",
591 	"UTC_VML2_IFIFO_GROUP7",
592 	"UTC_VML2_IFIFO_GROUP8",
593 	"UTC_VML2_IFIFO_GROUP9",
594 	"UTC_VML2_IFIFO_GROUP10",
595 	"UTC_VML2_IFIFO_GROUP11",
596 	"UTC_VML2_IFIFO_GROUP12",
597 	"UTC_VML2_IFIFO_GROUP13",
598 	"UTC_VML2_IFIFO_GROUP14",
599 	"UTC_VML2_IFIFO_GROUP15",
600 	"UTC_VML2_IFIFO_GROUP16",
601 	"UTC_VML2_IFIFO_GROUP17",
602 	"UTC_VML2_IFIFO_GROUP18",
603 	"UTC_VML2_IFIFO_GROUP19",
604 	"UTC_VML2_IFIFO_GROUP20",
605 	"UTC_VML2_IFIFO_GROUP21",
606 	"UTC_VML2_IFIFO_GROUP22",
607 	"UTC_VML2_IFIFO_GROUP23",
608 	"UTC_VML2_IFIFO_GROUP24",
609 };
610 
611 static const char * const vml2_walker_mems[] = {
612 	"UTC_VML2_CACHE_PDE0_MEM0",
613 	"UTC_VML2_CACHE_PDE0_MEM1",
614 	"UTC_VML2_CACHE_PDE1_MEM0",
615 	"UTC_VML2_CACHE_PDE1_MEM1",
616 	"UTC_VML2_CACHE_PDE2_MEM0",
617 	"UTC_VML2_CACHE_PDE2_MEM1",
618 	"UTC_VML2_RDIF_ARADDRS",
619 	"UTC_VML2_RDIF_LOG_FIFO",
620 	"UTC_VML2_QUEUE_REQ",
621 	"UTC_VML2_QUEUE_RET",
622 };
623 
624 static const char * const utcl2_router_mems[] = {
625 	"UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0",
626 	"UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1",
627 	"UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2",
628 	"UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3",
629 	"UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4",
630 	"UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5",
631 	"UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6",
632 	"UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7",
633 	"UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8",
634 	"UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9",
635 	"UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10",
636 	"UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11",
637 	"UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12",
638 	"UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13",
639 	"UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14",
640 	"UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15",
641 	"UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16",
642 	"UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17",
643 	"UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18",
644 	"UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19",
645 	"UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20",
646 	"UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21",
647 	"UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22",
648 	"UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23",
649 	"UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24",
650 };
651 
652 static const char * const atc_l2_cache_2m_mems[] = {
653 	"UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
654 	"UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
655 	"UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
656 	"UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
657 };
658 
659 static const char * const atc_l2_cache_4k_mems[] = {
660 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
661 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
662 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
663 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
664 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
665 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
666 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
667 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
668 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
669 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
670 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
671 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
672 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
673 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
674 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
675 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
676 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
677 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
678 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
679 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
680 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
681 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
682 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
683 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
684 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
685 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
686 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
687 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
688 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
689 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
690 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
691 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
692 };
693 
gfx_v9_4_query_utc_edc_status(struct amdgpu_device * adev,struct ras_err_data * err_data)694 static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
695 					 struct ras_err_data *err_data)
696 {
697 	uint32_t i, data;
698 	uint32_t sec_count, ded_count;
699 
700 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
701 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
702 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
703 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
704 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
705 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
706 
707 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
708 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
709 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
710 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
711 
712 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
713 		WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
714 		data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
715 
716 		sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
717 		if (sec_count) {
718 			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
719 				 vml2_mems[i], sec_count);
720 			err_data->ce_count += sec_count;
721 		}
722 
723 		ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
724 		if (ded_count) {
725 			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
726 				 vml2_mems[i], ded_count);
727 			err_data->ue_count += ded_count;
728 		}
729 	}
730 
731 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
732 		WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
733 		data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
734 
735 		sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
736 					  SEC_COUNT);
737 		if (sec_count) {
738 			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
739 				 vml2_walker_mems[i], sec_count);
740 			err_data->ce_count += sec_count;
741 		}
742 
743 		ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
744 					  DED_COUNT);
745 		if (ded_count) {
746 			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
747 				 vml2_walker_mems[i], ded_count);
748 			err_data->ue_count += ded_count;
749 		}
750 	}
751 
752 	for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
753 		WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
754 		data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
755 
756 		sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
757 		if (sec_count) {
758 			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
759 				 utcl2_router_mems[i], sec_count);
760 			err_data->ce_count += sec_count;
761 		}
762 
763 		ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
764 		if (ded_count) {
765 			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
766 				 utcl2_router_mems[i], ded_count);
767 			err_data->ue_count += ded_count;
768 		}
769 	}
770 
771 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
772 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
773 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
774 
775 		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
776 					  SEC_COUNT);
777 		if (sec_count) {
778 			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
779 				 atc_l2_cache_2m_mems[i], sec_count);
780 			err_data->ce_count += sec_count;
781 		}
782 
783 		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
784 					  DED_COUNT);
785 		if (ded_count) {
786 			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
787 				 atc_l2_cache_2m_mems[i], ded_count);
788 			err_data->ue_count += ded_count;
789 		}
790 	}
791 
792 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
793 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
794 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
795 
796 		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
797 					  SEC_COUNT);
798 		if (sec_count) {
799 			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
800 				 atc_l2_cache_4k_mems[i], sec_count);
801 			err_data->ce_count += sec_count;
802 		}
803 
804 		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
805 					  DED_COUNT);
806 		if (ded_count) {
807 			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
808 				 atc_l2_cache_4k_mems[i], ded_count);
809 			err_data->ue_count += ded_count;
810 		}
811 	}
812 
813 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
814 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
815 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
816 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
817 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
818 
819 	return 0;
820 }
821 
gfx_v9_4_ras_error_count(const struct soc15_reg_entry * reg,uint32_t se_id,uint32_t inst_id,uint32_t value,uint32_t * sec_count,uint32_t * ded_count)822 static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg,
823 				    uint32_t se_id, uint32_t inst_id,
824 				    uint32_t value, uint32_t *sec_count,
825 				    uint32_t *ded_count)
826 {
827 	uint32_t i;
828 	uint32_t sec_cnt, ded_cnt;
829 
830 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_ras_fields); i++) {
831 		if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
832 		    gfx_v9_4_ras_fields[i].seg != reg->seg ||
833 		    gfx_v9_4_ras_fields[i].inst != reg->inst)
834 			continue;
835 
836 		sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >>
837 			  gfx_v9_4_ras_fields[i].sec_count_shift;
838 		if (sec_cnt) {
839 			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
840 				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,
841 				 sec_cnt);
842 			*sec_count += sec_cnt;
843 		}
844 
845 		ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >>
846 			  gfx_v9_4_ras_fields[i].ded_count_shift;
847 		if (ded_cnt) {
848 			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
849 				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,
850 				 ded_cnt);
851 			*ded_count += ded_cnt;
852 		}
853 	}
854 
855 	return 0;
856 }
857 
gfx_v9_4_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)858 int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
859 				   void *ras_error_status)
860 {
861 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
862 	uint32_t sec_count = 0, ded_count = 0;
863 	uint32_t i, j, k;
864 	uint32_t reg_value;
865 
866 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
867 		return -EINVAL;
868 
869 	err_data->ue_count = 0;
870 	err_data->ce_count = 0;
871 
872 	mutex_lock(&adev->grbm_idx_mutex);
873 
874 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
875 		for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
876 			for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
877 			     k++) {
878 				gfx_v9_4_select_se_sh(adev, j, 0, k);
879 				reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
880 					gfx_v9_4_edc_counter_regs[i]));
881 				if (reg_value)
882 					gfx_v9_4_ras_error_count(
883 						&gfx_v9_4_edc_counter_regs[i],
884 						j, k, reg_value, &sec_count,
885 						&ded_count);
886 			}
887 		}
888 	}
889 
890 	err_data->ce_count += sec_count;
891 	err_data->ue_count += ded_count;
892 
893 	gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
894 	mutex_unlock(&adev->grbm_idx_mutex);
895 
896 	gfx_v9_4_query_utc_edc_status(adev, err_data);
897 
898 	return 0;
899 }
900 
gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device * adev)901 void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev)
902 {
903 	int i, j, k;
904 
905 	mutex_lock(&adev->grbm_idx_mutex);
906 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
907 		for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
908 			for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
909 			     k++) {
910 				gfx_v9_4_select_se_sh(adev, j, 0x0, k);
911 				RREG32(SOC15_REG_ENTRY_OFFSET(
912 					gfx_v9_4_edc_counter_regs[i]));
913 			}
914 		}
915 	}
916 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
917 	mutex_unlock(&adev->grbm_idx_mutex);
918 
919 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
920 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
921 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
922 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
923 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
924 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
925 
926 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
927 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
928 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
929 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
930 
931 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
932 		WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
933 		RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
934 	}
935 
936 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
937 		WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
938 		RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
939 	}
940 
941 	for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
942 		WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
943 		RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
944 	}
945 
946 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
947 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
948 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
949 	}
950 
951 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
952 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
953 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
954 	}
955 
956 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
957 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
958 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
959 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
960 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
961 }
962 
gfx_v9_4_ras_error_inject(struct amdgpu_device * adev,void * inject_if)963 int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
964 {
965 	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
966 	int ret;
967 	struct ta_ras_trigger_error_input block_info = { 0 };
968 
969 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
970 		return -EINVAL;
971 
972 	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
973 	block_info.sub_block_index = info->head.sub_block_index;
974 	block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
975 	block_info.address = info->address;
976 	block_info.value = info->value;
977 
978 	mutex_lock(&adev->grbm_idx_mutex);
979 	ret = psp_ras_trigger_error(&adev->psp, &block_info);
980 	mutex_unlock(&adev->grbm_idx_mutex);
981 
982 	return ret;
983 }
984