xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/nouveau_nvkm_engine_disp_dmacgf119.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: nouveau_nvkm_engine_disp_dmacgf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Ben Skeggs
25  */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_dmacgf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28 
29 #include "channv50.h"
30 
31 #include <core/ramht.h>
32 #include <subdev/timer.h>
33 
34 int
gf119_disp_dmac_bind(struct nv50_disp_chan * chan,struct nvkm_object * object,u32 handle)35 gf119_disp_dmac_bind(struct nv50_disp_chan *chan,
36 		     struct nvkm_object *object, u32 handle)
37 {
38 	return nvkm_ramht_insert(chan->disp->ramht, object,
39 				 chan->chid.user, -9, handle,
40 				 chan->chid.user << 27 | 0x00000001);
41 }
42 
43 void
gf119_disp_dmac_fini(struct nv50_disp_chan * chan)44 gf119_disp_dmac_fini(struct nv50_disp_chan *chan)
45 {
46 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
47 	struct nvkm_device *device = subdev->device;
48 	int ctrl = chan->chid.ctrl;
49 	int user = chan->chid.user;
50 
51 	/* deactivate channel */
52 	nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000);
53 	nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000);
54 	if (nvkm_msec(device, 2000,
55 		if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000))
56 			break;
57 	) < 0) {
58 		nvkm_error(subdev, "ch %d fini: %08x\n", user,
59 			   nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
60 	}
61 }
62 
63 static int
gf119_disp_dmac_init(struct nv50_disp_chan * chan)64 gf119_disp_dmac_init(struct nv50_disp_chan *chan)
65 {
66 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
67 	struct nvkm_device *device = subdev->device;
68 	int ctrl = chan->chid.ctrl;
69 	int user = chan->chid.user;
70 
71 	/* initialise channel for dma command submission */
72 	nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push);
73 	nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000);
74 	nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001);
75 	nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010);
76 	nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000);
77 	nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013);
78 
79 	/* wait for it to go inactive */
80 	if (nvkm_msec(device, 2000,
81 		if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000))
82 			break;
83 	) < 0) {
84 		nvkm_error(subdev, "ch %d init: %08x\n", user,
85 			   nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
86 		return -EBUSY;
87 	}
88 
89 	return 0;
90 }
91 
92 const struct nv50_disp_chan_func
93 gf119_disp_dmac_func = {
94 	.init = gf119_disp_dmac_init,
95 	.fini = gf119_disp_dmac_fini,
96 	.intr = gf119_disp_chan_intr,
97 	.user = nv50_disp_chan_user,
98 	.bind = gf119_disp_dmac_bind,
99 };
100