xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sw/nouveau_nvkm_engine_sw_gf100.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: nouveau_nvkm_engine_sw_gf100.c,v 1.3 2021/12/18 23:45:37 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Ben Skeggs
25  */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_sw_gf100.c,v 1.3 2021/12/18 23:45:37 riastradh Exp $");
28 
29 #include "nv50.h"
30 
31 #include <core/gpuobj.h>
32 #include <subdev/bar.h>
33 #include <engine/disp.h>
34 #include <engine/fifo.h>
35 
36 #include <nvif/class.h>
37 #include <nvif/event.h>
38 
39 /*******************************************************************************
40  * software context
41  ******************************************************************************/
42 
43 static int
gf100_sw_chan_vblsem_release(struct nvkm_notify * notify)44 gf100_sw_chan_vblsem_release(struct nvkm_notify *notify)
45 {
46 	struct nv50_sw_chan *chan =
47 		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
48 	struct nvkm_sw *sw = chan->base.sw;
49 	struct nvkm_device *device = sw->engine.subdev.device;
50 	u32 inst = chan->base.fifo->inst->addr >> 12;
51 
52 	nvkm_wr32(device, 0x001718, 0x80000000 | inst);
53 	nvkm_bar_flush(device->bar);
54 	nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
55 	nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
56 	nvkm_wr32(device, 0x060014, chan->vblank.value);
57 
58 	return NVKM_NOTIFY_DROP;
59 }
60 
61 static bool
gf100_sw_chan_mthd(struct nvkm_sw_chan * base,int subc,u32 mthd,u32 data)62 gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
63 {
64 	struct nv50_sw_chan *chan = nv50_sw_chan(base);
65 	struct nvkm_engine *engine = chan->base.object.engine;
66 	struct nvkm_device *device = engine->subdev.device;
67 	switch (mthd) {
68 	case 0x0400:
69 		chan->vblank.offset &= 0x00ffffffffULL;
70 		chan->vblank.offset |= (u64)data << 32;
71 		return true;
72 	case 0x0404:
73 		chan->vblank.offset &= 0xff00000000ULL;
74 		chan->vblank.offset |= data;
75 		return true;
76 	case 0x0408:
77 		chan->vblank.value = data;
78 		return true;
79 	case 0x040c:
80 		if (data < device->disp->vblank.index_nr) {
81 			nvkm_notify_get(&chan->vblank.notify[data]);
82 			return true;
83 		}
84 		break;
85 	case 0x600: /* MP.PM_UNK000 */
86 		nvkm_wr32(device, 0x419e00, data);
87 		return true;
88 	case 0x644: /* MP.TRAP_WARP_ERROR_EN */
89 		if (!(data & ~0x001ffffe)) {
90 			nvkm_wr32(device, 0x419e44, data);
91 			return true;
92 		}
93 		break;
94 	case 0x6ac: /* MP.PM_UNK0AC */
95 		nvkm_wr32(device, 0x419eac, data);
96 		return true;
97 	default:
98 		break;
99 	}
100 	return false;
101 }
102 
103 static const struct nvkm_sw_chan_func
104 gf100_sw_chan = {
105 	.dtor = nv50_sw_chan_dtor,
106 	.mthd = gf100_sw_chan_mthd,
107 };
108 
109 static int
gf100_sw_chan_new(struct nvkm_sw * sw,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)110 gf100_sw_chan_new(struct nvkm_sw *sw, struct nvkm_fifo_chan *fifoch,
111 		  const struct nvkm_oclass *oclass,
112 		  struct nvkm_object **pobject)
113 {
114 	struct nvkm_disp *disp = sw->engine.subdev.device->disp;
115 	struct nv50_sw_chan *chan;
116 	int ret, i;
117 
118 	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
119 		return -ENOMEM;
120 	*pobject = &chan->base.object;
121 
122 	ret = nvkm_sw_chan_ctor(&gf100_sw_chan, sw, fifoch, oclass,
123 				&chan->base);
124 	if (ret)
125 		return ret;
126 
127 	for (i = 0; disp && i < disp->vblank.index_nr; i++) {
128 		ret = nvkm_notify_init(NULL, &disp->vblank,
129 				       gf100_sw_chan_vblsem_release, false,
130 				       &(struct nvif_notify_head_req_v0) {
131 					.head = i,
132 				       },
133 				       sizeof(struct nvif_notify_head_req_v0),
134 				       sizeof(struct nvif_notify_head_rep_v0),
135 				       &chan->vblank.notify[i]);
136 		if (ret)
137 			return ret;
138 	}
139 
140 	return 0;
141 }
142 
143 /*******************************************************************************
144  * software engine/subdev functions
145  ******************************************************************************/
146 
147 static const struct nvkm_sw_func
148 gf100_sw = {
149 	.chan_new = gf100_sw_chan_new,
150 	.sclass = {
151 		{ nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_GF100 } },
152 		{}
153 	}
154 };
155 
156 int
gf100_sw_new(struct nvkm_device * device,int index,struct nvkm_sw ** psw)157 gf100_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw)
158 {
159 	return nvkm_sw_new_(&gf100_sw, device, index, psw);
160 }
161