xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/nouveau_nvkm_subdev_fb_ramgf100.c (revision 7649e88fcfe6a7c92de68bd5e592dec3e35224fb)
1 /*	$NetBSD: nouveau_nvkm_subdev_fb_ramgf100.c,v 1.4 2021/12/19 10:51:58 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2013 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Ben Skeggs
25  */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_fb_ramgf100.c,v 1.4 2021/12/19 10:51:58 riastradh Exp $");
28 
29 #define gf100_ram(p) container_of((p), struct gf100_ram, base)
30 #include "ram.h"
31 #include "ramfuc.h"
32 
33 #include <core/option.h>
34 #include <subdev/bios.h>
35 #include <subdev/bios/pll.h>
36 #include <subdev/bios/rammap.h>
37 #include <subdev/bios/timing.h>
38 #include <subdev/clk.h>
39 #include <subdev/clk/pll.h>
40 
41 struct gf100_ramfuc {
42 	struct ramfuc base;
43 
44 	struct ramfuc_reg r_0x10fe20;
45 	struct ramfuc_reg r_0x10fe24;
46 	struct ramfuc_reg r_0x137320;
47 	struct ramfuc_reg r_0x137330;
48 
49 	struct ramfuc_reg r_0x132000;
50 	struct ramfuc_reg r_0x132004;
51 	struct ramfuc_reg r_0x132100;
52 
53 	struct ramfuc_reg r_0x137390;
54 
55 	struct ramfuc_reg r_0x10f290;
56 	struct ramfuc_reg r_0x10f294;
57 	struct ramfuc_reg r_0x10f298;
58 	struct ramfuc_reg r_0x10f29c;
59 	struct ramfuc_reg r_0x10f2a0;
60 
61 	struct ramfuc_reg r_0x10f300;
62 	struct ramfuc_reg r_0x10f338;
63 	struct ramfuc_reg r_0x10f340;
64 	struct ramfuc_reg r_0x10f344;
65 	struct ramfuc_reg r_0x10f348;
66 
67 	struct ramfuc_reg r_0x10f910;
68 	struct ramfuc_reg r_0x10f914;
69 
70 	struct ramfuc_reg r_0x100b0c;
71 	struct ramfuc_reg r_0x10f050;
72 	struct ramfuc_reg r_0x10f090;
73 	struct ramfuc_reg r_0x10f200;
74 	struct ramfuc_reg r_0x10f210;
75 	struct ramfuc_reg r_0x10f310;
76 	struct ramfuc_reg r_0x10f314;
77 	struct ramfuc_reg r_0x10f610;
78 	struct ramfuc_reg r_0x10f614;
79 	struct ramfuc_reg r_0x10f800;
80 	struct ramfuc_reg r_0x10f808;
81 	struct ramfuc_reg r_0x10f824;
82 	struct ramfuc_reg r_0x10f830;
83 	struct ramfuc_reg r_0x10f988;
84 	struct ramfuc_reg r_0x10f98c;
85 	struct ramfuc_reg r_0x10f990;
86 	struct ramfuc_reg r_0x10f998;
87 	struct ramfuc_reg r_0x10f9b0;
88 	struct ramfuc_reg r_0x10f9b4;
89 	struct ramfuc_reg r_0x10fb04;
90 	struct ramfuc_reg r_0x10fb08;
91 	struct ramfuc_reg r_0x137300;
92 	struct ramfuc_reg r_0x137310;
93 	struct ramfuc_reg r_0x137360;
94 	struct ramfuc_reg r_0x1373ec;
95 	struct ramfuc_reg r_0x1373f0;
96 	struct ramfuc_reg r_0x1373f8;
97 
98 	struct ramfuc_reg r_0x61c140;
99 	struct ramfuc_reg r_0x611200;
100 
101 	struct ramfuc_reg r_0x13d8f4;
102 };
103 
104 struct gf100_ram {
105 	struct nvkm_ram base;
106 	struct gf100_ramfuc fuc;
107 	struct nvbios_pll refpll;
108 	struct nvbios_pll mempll;
109 };
110 
111 static void
gf100_ram_train(struct gf100_ramfuc * fuc,u32 magic)112 gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
113 {
114 	struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
115 	struct nvkm_fb *fb = ram->base.fb;
116 	struct nvkm_device *device = fb->subdev.device;
117 	u32 part = nvkm_rd32(device, 0x022438), i;
118 	u32 mask = nvkm_rd32(device, 0x022554);
119 	u32 addr = 0x110974;
120 
121 	ram_wr32(fuc, 0x10f910, magic);
122 	ram_wr32(fuc, 0x10f914, magic);
123 
124 	for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
125 		if (mask & (1 << i))
126 			continue;
127 		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
128 	}
129 }
130 
131 int
gf100_ram_calc(struct nvkm_ram * base,u32 freq)132 gf100_ram_calc(struct nvkm_ram *base, u32 freq)
133 {
134 	struct gf100_ram *ram = gf100_ram(base);
135 	struct gf100_ramfuc *fuc = &ram->fuc;
136 	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
137 	struct nvkm_device *device = subdev->device;
138 	struct nvkm_clk *clk = device->clk;
139 	struct nvkm_bios *bios = device->bios;
140 	struct nvbios_ramcfg cfg;
141 	u8  ver, cnt, len, strap;
142 	struct {
143 		u32 data;
144 		u8  size;
145 	} rammap, ramcfg, timing;
146 	int ref, div, out;
147 	int from, mode;
148 	int N1, M1, P;
149 	int ret;
150 
151 	/* lookup memory config data relevant to the target frequency */
152 	rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
153 				      &cnt, &ramcfg.size, &cfg);
154 	if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
155 		nvkm_error(subdev, "invalid/missing rammap entry\n");
156 		return -EINVAL;
157 	}
158 
159 	/* locate specific data set for the attached memory */
160 	strap = nvbios_ramcfg_index(subdev);
161 	if (strap >= cnt) {
162 		nvkm_error(subdev, "invalid ramcfg strap\n");
163 		return -EINVAL;
164 	}
165 
166 	ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
167 	if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
168 		nvkm_error(subdev, "invalid/missing ramcfg entry\n");
169 		return -EINVAL;
170 	}
171 
172 	/* lookup memory timings, if bios says they're present */
173 	strap = nvbios_rd08(bios, ramcfg.data + 0x01);
174 	if (strap != 0xff) {
175 		timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
176 					      &cnt, &len);
177 		if (!timing.data || ver != 0x10 || timing.size < 0x19) {
178 			nvkm_error(subdev, "invalid/missing timing entry\n");
179 			return -EINVAL;
180 		}
181 	} else {
182 		timing.data = 0;
183 	}
184 
185 	ret = ram_init(fuc, ram->base.fb);
186 	if (ret)
187 		return ret;
188 
189 	/* determine current mclk configuration */
190 	from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
191 
192 	/* determine target mclk configuration */
193 	if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
194 		ref = nvkm_clk_read(clk, nv_clk_src_sppll0);
195 	else
196 		ref = nvkm_clk_read(clk, nv_clk_src_sppll1);
197 	div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
198 	out = (ref * 2) / (div + 2);
199 	mode = freq != out;
200 
201 	ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
202 
203 	if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
204 		ram_nuke(fuc, 0x132000);
205 		ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
206 		ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
207 	}
208 
209 	if (mode == 1) {
210 		ram_nuke(fuc, 0x10fe20);
211 		ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
212 		ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
213 	}
214 
215 // 0x00020034 // 0x0000000a
216 	ram_wr32(fuc, 0x132100, 0x00000001);
217 
218 	if (mode == 1 && from == 0) {
219 		/* calculate refpll */
220 		ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk,
221 				     &N1, NULL, &M1, &P);
222 		if (ret <= 0) {
223 			nvkm_error(subdev, "unable to calc refpll\n");
224 			return ret ? ret : -ERANGE;
225 		}
226 
227 		ram_wr32(fuc, 0x10fe20, 0x20010000);
228 		ram_wr32(fuc, 0x137320, 0x00000003);
229 		ram_wr32(fuc, 0x137330, 0x81200006);
230 		ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
231 		ram_wr32(fuc, 0x10fe20, 0x20010001);
232 		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
233 
234 		/* calculate mempll */
235 		ret = gt215_pll_calc(subdev, &ram->mempll, freq,
236 				     &N1, NULL, &M1, &P);
237 		if (ret <= 0) {
238 			nvkm_error(subdev, "unable to calc refpll\n");
239 			return ret ? ret : -ERANGE;
240 		}
241 
242 		ram_wr32(fuc, 0x10fe20, 0x20010005);
243 		ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
244 		ram_wr32(fuc, 0x132000, 0x18010101);
245 		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
246 	} else
247 	if (mode == 0) {
248 		ram_wr32(fuc, 0x137300, 0x00000003);
249 	}
250 
251 	if (from == 0) {
252 		ram_nuke(fuc, 0x10fb04);
253 		ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
254 		ram_nuke(fuc, 0x10fb08);
255 		ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
256 		ram_wr32(fuc, 0x10f988, 0x2004ff00);
257 		ram_wr32(fuc, 0x10f98c, 0x003fc040);
258 		ram_wr32(fuc, 0x10f990, 0x20012001);
259 		ram_wr32(fuc, 0x10f998, 0x00011a00);
260 		ram_wr32(fuc, 0x13d8f4, 0x00000000);
261 	} else {
262 		ram_wr32(fuc, 0x10f988, 0x20010000);
263 		ram_wr32(fuc, 0x10f98c, 0x00000000);
264 		ram_wr32(fuc, 0x10f990, 0x20012001);
265 		ram_wr32(fuc, 0x10f998, 0x00010a00);
266 	}
267 
268 	if (from == 0) {
269 // 0x00020039 // 0x000000ba
270 	}
271 
272 // 0x0002003a // 0x00000002
273 	ram_wr32(fuc, 0x100b0c, 0x00080012);
274 // 0x00030014 // 0x00000000 // 0x02b5f070
275 // 0x00030014 // 0x00010000 // 0x02b5f070
276 	ram_wr32(fuc, 0x611200, 0x00003300);
277 // 0x00020034 // 0x0000000a
278 // 0x00030020 // 0x00000001 // 0x00000000
279 
280 	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
281 	ram_wr32(fuc, 0x10f210, 0x00000000);
282 	ram_nsec(fuc, 1000);
283 	if (mode == 0)
284 		gf100_ram_train(fuc, 0x000c1001);
285 	ram_wr32(fuc, 0x10f310, 0x00000001);
286 	ram_nsec(fuc, 1000);
287 	ram_wr32(fuc, 0x10f090, 0x00000061);
288 	ram_wr32(fuc, 0x10f090, 0xc000007f);
289 	ram_nsec(fuc, 1000);
290 
291 	if (from == 0) {
292 		ram_wr32(fuc, 0x10f824, 0x00007fd4);
293 	} else {
294 		ram_wr32(fuc, 0x1373ec, 0x00020404);
295 	}
296 
297 	if (mode == 0) {
298 		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
299 		ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
300 		ram_wr32(fuc, 0x10f830, 0x41500010);
301 		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
302 		ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
303 		ram_wr32(fuc, 0x10f050, 0xff000090);
304 		ram_wr32(fuc, 0x1373ec, 0x00020f0f);
305 		ram_wr32(fuc, 0x1373f0, 0x00000003);
306 		ram_wr32(fuc, 0x137310, 0x81201616);
307 		ram_wr32(fuc, 0x132100, 0x00000001);
308 // 0x00020039 // 0x000000ba
309 		ram_wr32(fuc, 0x10f830, 0x00300017);
310 		ram_wr32(fuc, 0x1373f0, 0x00000001);
311 		ram_wr32(fuc, 0x10f824, 0x00007e77);
312 		ram_wr32(fuc, 0x132000, 0x18030001);
313 		ram_wr32(fuc, 0x10f090, 0x4000007e);
314 		ram_nsec(fuc, 2000);
315 		ram_wr32(fuc, 0x10f314, 0x00000001);
316 		ram_wr32(fuc, 0x10f210, 0x80000000);
317 		ram_wr32(fuc, 0x10f338, 0x00300220);
318 		ram_wr32(fuc, 0x10f300, 0x0000011d);
319 		ram_nsec(fuc, 1000);
320 		ram_wr32(fuc, 0x10f290, 0x02060505);
321 		ram_wr32(fuc, 0x10f294, 0x34208288);
322 		ram_wr32(fuc, 0x10f298, 0x44050411);
323 		ram_wr32(fuc, 0x10f29c, 0x0000114c);
324 		ram_wr32(fuc, 0x10f2a0, 0x42e10069);
325 		ram_wr32(fuc, 0x10f614, 0x40044f77);
326 		ram_wr32(fuc, 0x10f610, 0x40044f77);
327 		ram_wr32(fuc, 0x10f344, 0x00600009);
328 		ram_nsec(fuc, 1000);
329 		ram_wr32(fuc, 0x10f348, 0x00700008);
330 		ram_wr32(fuc, 0x61c140, 0x19240000);
331 		ram_wr32(fuc, 0x10f830, 0x00300017);
332 		gf100_ram_train(fuc, 0x80021001);
333 		gf100_ram_train(fuc, 0x80081001);
334 		ram_wr32(fuc, 0x10f340, 0x00500004);
335 		ram_nsec(fuc, 1000);
336 		ram_wr32(fuc, 0x10f830, 0x01300017);
337 		ram_wr32(fuc, 0x10f830, 0x00300017);
338 // 0x00030020 // 0x00000000 // 0x00000000
339 // 0x00020034 // 0x0000000b
340 		ram_wr32(fuc, 0x100b0c, 0x00080028);
341 		ram_wr32(fuc, 0x611200, 0x00003330);
342 	} else {
343 		ram_wr32(fuc, 0x10f800, 0x00001800);
344 		ram_wr32(fuc, 0x13d8f4, 0x00000000);
345 		ram_wr32(fuc, 0x1373ec, 0x00020404);
346 		ram_wr32(fuc, 0x1373f0, 0x00000003);
347 		ram_wr32(fuc, 0x10f830, 0x40700010);
348 		ram_wr32(fuc, 0x10f830, 0x40500010);
349 		ram_wr32(fuc, 0x13d8f4, 0x00000000);
350 		ram_wr32(fuc, 0x1373f8, 0x00000000);
351 		ram_wr32(fuc, 0x132100, 0x00000101);
352 		ram_wr32(fuc, 0x137310, 0x89201616);
353 		ram_wr32(fuc, 0x10f050, 0xff000090);
354 		ram_wr32(fuc, 0x1373ec, 0x00030404);
355 		ram_wr32(fuc, 0x1373f0, 0x00000002);
356 	// 0x00020039 // 0x00000011
357 		ram_wr32(fuc, 0x132100, 0x00000001);
358 		ram_wr32(fuc, 0x1373f8, 0x00002000);
359 		ram_nsec(fuc, 2000);
360 		ram_wr32(fuc, 0x10f808, 0x7aaa0050);
361 		ram_wr32(fuc, 0x10f830, 0x00500010);
362 		ram_wr32(fuc, 0x10f200, 0x00ce1000);
363 		ram_wr32(fuc, 0x10f090, 0x4000007e);
364 		ram_nsec(fuc, 2000);
365 		ram_wr32(fuc, 0x10f314, 0x00000001);
366 		ram_wr32(fuc, 0x10f210, 0x80000000);
367 		ram_wr32(fuc, 0x10f338, 0x00300200);
368 		ram_wr32(fuc, 0x10f300, 0x0000084d);
369 		ram_nsec(fuc, 1000);
370 		ram_wr32(fuc, 0x10f290, 0x0b343825);
371 		ram_wr32(fuc, 0x10f294, 0x3483028e);
372 		ram_wr32(fuc, 0x10f298, 0x440c0600);
373 		ram_wr32(fuc, 0x10f29c, 0x0000214c);
374 		ram_wr32(fuc, 0x10f2a0, 0x42e20069);
375 		ram_wr32(fuc, 0x10f200, 0x00ce0000);
376 		ram_wr32(fuc, 0x10f614, 0x60044e77);
377 		ram_wr32(fuc, 0x10f610, 0x60044e77);
378 		ram_wr32(fuc, 0x10f340, 0x00500000);
379 		ram_nsec(fuc, 1000);
380 		ram_wr32(fuc, 0x10f344, 0x00600228);
381 		ram_nsec(fuc, 1000);
382 		ram_wr32(fuc, 0x10f348, 0x00700000);
383 		ram_wr32(fuc, 0x13d8f4, 0x00000000);
384 		ram_wr32(fuc, 0x61c140, 0x09a40000);
385 
386 		gf100_ram_train(fuc, 0x800e1008);
387 
388 		ram_nsec(fuc, 1000);
389 		ram_wr32(fuc, 0x10f800, 0x00001804);
390 	// 0x00030020 // 0x00000000 // 0x00000000
391 	// 0x00020034 // 0x0000000b
392 		ram_wr32(fuc, 0x13d8f4, 0x00000000);
393 		ram_wr32(fuc, 0x100b0c, 0x00080028);
394 		ram_wr32(fuc, 0x611200, 0x00003330);
395 		ram_nsec(fuc, 100000);
396 		ram_wr32(fuc, 0x10f9b0, 0x05313f41);
397 		ram_wr32(fuc, 0x10f9b4, 0x00002f50);
398 
399 		gf100_ram_train(fuc, 0x010c1001);
400 	}
401 
402 	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
403 // 0x00020016 // 0x00000000
404 
405 	if (mode == 0)
406 		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
407 
408 	return 0;
409 }
410 
411 int
gf100_ram_prog(struct nvkm_ram * base)412 gf100_ram_prog(struct nvkm_ram *base)
413 {
414 	struct gf100_ram *ram = gf100_ram(base);
415 	struct nvkm_device *device = ram->base.fb->subdev.device;
416 	ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
417 	return 0;
418 }
419 
420 void
gf100_ram_tidy(struct nvkm_ram * base)421 gf100_ram_tidy(struct nvkm_ram *base)
422 {
423 	struct gf100_ram *ram = gf100_ram(base);
424 	ram_exec(&ram->fuc, false);
425 }
426 
427 int
gf100_ram_init(struct nvkm_ram * base)428 gf100_ram_init(struct nvkm_ram *base)
429 {
430 	static const u8  train0[] = {
431 		0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
432 		0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
433 	};
434 	static const u32 train1[] = {
435 		0x00000000, 0xffffffff,
436 		0x55555555, 0xaaaaaaaa,
437 		0x33333333, 0xcccccccc,
438 		0xf0f0f0f0, 0x0f0f0f0f,
439 		0x00ff00ff, 0xff00ff00,
440 		0x0000ffff, 0xffff0000,
441 	};
442 	struct gf100_ram *ram = gf100_ram(base);
443 	struct nvkm_device *device = ram->base.fb->subdev.device;
444 	int i;
445 
446 	switch (ram->base.type) {
447 	case NVKM_RAM_TYPE_GDDR5:
448 		break;
449 	default:
450 		return 0;
451 	}
452 
453 	/* prepare for ddr link training, and load training patterns */
454 	for (i = 0; i < 0x30; i++) {
455 		nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8));
456 		nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8));
457 		nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]);
458 		nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]);
459 		nvkm_wr32(device, 0x10f918,              train1[i % 12]);
460 		nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
461 		nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]);
462 		nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]);
463 		nvkm_wr32(device, 0x10f918,              train1[i % 12]);
464 		nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
465 	}
466 
467 	return 0;
468 }
469 
470 u32
gf100_ram_probe_fbpa_amount(struct nvkm_device * device,int fbpa)471 gf100_ram_probe_fbpa_amount(struct nvkm_device *device, int fbpa)
472 {
473 	return nvkm_rd32(device, 0x11020c + (fbpa * 0x1000));
474 }
475 
476 u32
gf100_ram_probe_fbp_amount(const struct nvkm_ram_func * func,u32 fbpao,struct nvkm_device * device,int fbp,int * pltcs)477 gf100_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao,
478 			   struct nvkm_device *device, int fbp, int *pltcs)
479 {
480 	if (!(fbpao & BIT(fbp))) {
481 		*pltcs = 1;
482 		return func->probe_fbpa_amount(device, fbp);
483 	}
484 	return 0;
485 }
486 
487 u32
gf100_ram_probe_fbp(const struct nvkm_ram_func * func,struct nvkm_device * device,int fbp,int * pltcs)488 gf100_ram_probe_fbp(const struct nvkm_ram_func *func,
489 		    struct nvkm_device *device, int fbp, int *pltcs)
490 {
491 	u32 fbpao = nvkm_rd32(device, 0x022554);
492 	return func->probe_fbp_amount(func, fbpao, device, fbp, pltcs);
493 }
494 
495 int
gf100_ram_ctor(const struct nvkm_ram_func * func,struct nvkm_fb * fb,struct nvkm_ram * ram)496 gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
497 	       struct nvkm_ram *ram)
498 {
499 	struct nvkm_subdev *subdev = &fb->subdev;
500 	struct nvkm_device *device = subdev->device;
501 	struct nvkm_bios *bios = device->bios;
502 	const u32 rsvd_head = ( 256 * 1024); /* vga memory */
503 	const u32 rsvd_tail = (1024 * 1024); /* vbios etc */
504 	enum nvkm_ram_type type = nvkm_fb_bios_memtype(bios);
505 	u32 fbps = nvkm_rd32(device, 0x022438);
506 	u64 total = 0, lcomm = ~0, lower, ubase, usize;
507 	int ret, fbp, ltcs, ltcn = 0;
508 
509 	nvkm_debug(subdev, "%d FBP(s)\n", fbps);
510 	for (fbp = 0; fbp < fbps; fbp++) {
511 		u32 size = func->probe_fbp(func, device, fbp, &ltcs);
512 		if (size) {
513 			nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
514 				   fbp, size, ltcs);
515 			lcomm  = min(lcomm, (u64)(size / ltcs) << 20);
516 			total += (u64) size << 20;
517 			ltcn  += ltcs;
518 		} else {
519 			nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
520 		}
521 	}
522 
523 	lower = lcomm * ltcn;
524 	ubase = lcomm + func->upper;
525 	usize = total - lower;
526 
527 	nvkm_debug(subdev, "Lower: %4"PRId64" MiB @ %010llx\n", lower >> 20, 0ULL);
528 	nvkm_debug(subdev, "Upper: %4"PRId64" MiB @ %010"PRIx64"\n", usize >> 20, ubase);
529 	nvkm_debug(subdev, "Total: %4"PRId64" MiB\n", total >> 20);
530 
531 	ret = nvkm_ram_ctor(func, fb, type, total, ram);
532 	if (ret)
533 		return ret;
534 
535 	nvkm_mm_fini(&ram->vram);
536 
537 	/* Some GPUs are in what's known as a "mixed memory" configuration.
538 	 *
539 	 * This is either where some FBPs have more memory than the others,
540 	 * or where LTCs have been disabled on a FBP.
541 	 */
542 	if (lower != total) {
543 		/* The common memory amount is addressed normally. */
544 		ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
545 				   rsvd_head >> NVKM_RAM_MM_SHIFT,
546 				   (lower - rsvd_head) >> NVKM_RAM_MM_SHIFT, 1);
547 		if (ret)
548 			return ret;
549 
550 		/* And the rest is much higher in the physical address
551 		 * space, and may not be usable for certain operations.
552 		 */
553 		ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_MIXED,
554 				   ubase >> NVKM_RAM_MM_SHIFT,
555 				   (usize - rsvd_tail) >> NVKM_RAM_MM_SHIFT, 1);
556 		if (ret)
557 			return ret;
558 	} else {
559 		/* GPUs without mixed-memory are a lot nicer... */
560 		ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
561 				   rsvd_head >> NVKM_RAM_MM_SHIFT,
562 				   (total - rsvd_head - rsvd_tail) >>
563 				   NVKM_RAM_MM_SHIFT, 1);
564 		if (ret)
565 			return ret;
566 	}
567 
568 	return 0;
569 }
570 
571 int
gf100_ram_new_(const struct nvkm_ram_func * func,struct nvkm_fb * fb,struct nvkm_ram ** pram)572 gf100_ram_new_(const struct nvkm_ram_func *func,
573 	       struct nvkm_fb *fb, struct nvkm_ram **pram)
574 {
575 	struct nvkm_subdev *subdev = &fb->subdev;
576 	struct nvkm_bios *bios = subdev->device->bios;
577 	struct gf100_ram *ram;
578 	int ret;
579 
580 	if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
581 		return -ENOMEM;
582 	*pram = &ram->base;
583 
584 	ret = gf100_ram_ctor(func, fb, &ram->base);
585 	if (ret)
586 		return ret;
587 
588 	ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);
589 	if (ret) {
590 		nvkm_error(subdev, "mclk refpll data not found\n");
591 		return ret;
592 	}
593 
594 	ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);
595 	if (ret) {
596 		nvkm_error(subdev, "mclk pll data not found\n");
597 		return ret;
598 	}
599 
600 	ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);
601 	ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);
602 	ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
603 	ram->fuc.r_0x137330 = ramfuc_reg(0x137330);
604 
605 	ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
606 	ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
607 	ram->fuc.r_0x132100 = ramfuc_reg(0x132100);
608 
609 	ram->fuc.r_0x137390 = ramfuc_reg(0x137390);
610 
611 	ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
612 	ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
613 	ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
614 	ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
615 	ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
616 
617 	ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
618 	ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
619 	ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
620 	ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);
621 	ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);
622 
623 	ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
624 	ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
625 
626 	ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);
627 	ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);
628 	ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
629 	ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
630 	ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
631 	ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
632 	ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
633 	ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
634 	ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
635 	ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
636 	ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
637 	ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
638 	ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
639 	ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);
640 	ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);
641 	ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);
642 	ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);
643 	ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);
644 	ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);
645 	ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);
646 	ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);
647 	ram->fuc.r_0x137310 = ramfuc_reg(0x137300);
648 	ram->fuc.r_0x137310 = ramfuc_reg(0x137310);
649 	ram->fuc.r_0x137360 = ramfuc_reg(0x137360);
650 	ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
651 	ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
652 	ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);
653 
654 	ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);
655 	ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
656 
657 	ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);
658 	return 0;
659 }
660 
661 static const struct nvkm_ram_func
662 gf100_ram = {
663 	.upper = 0x0200000000ULL,
664 	.probe_fbp = gf100_ram_probe_fbp,
665 	.probe_fbp_amount = gf100_ram_probe_fbp_amount,
666 	.probe_fbpa_amount = gf100_ram_probe_fbpa_amount,
667 	.init = gf100_ram_init,
668 	.calc = gf100_ram_calc,
669 	.prog = gf100_ram_prog,
670 	.tidy = gf100_ram_tidy,
671 };
672 
673 int
gf100_ram_new(struct nvkm_fb * fb,struct nvkm_ram ** pram)674 gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
675 {
676 	return gf100_ram_new_(&gf100_ram, fb, pram);
677 }
678