1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/Support/TargetRegistry.h"
21
22 using namespace llvm;
23
24 #define DEBUG_TYPE "riscv-subtarget"
25
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "RISCVGenSubtargetInfo.inc"
29
30 static cl::opt<unsigned> RVVVectorBitsMax(
31 "riscv-v-vector-bits-max",
32 cl::desc("Assume V extension vector registers are at most this big, "
33 "with zero meaning no maximum size is assumed."),
34 cl::init(0), cl::Hidden);
35
36 static cl::opt<unsigned> RVVVectorBitsMin(
37 "riscv-v-vector-bits-min",
38 cl::desc("Assume V extension vector registers are at least this big, "
39 "with zero meaning no minimum size is assumed."),
40 cl::init(0), cl::Hidden);
41
42 static cl::opt<unsigned> RVVVectorLMULMax(
43 "riscv-v-fixed-length-vector-lmul-max",
44 cl::desc("The maximum LMUL value to use for fixed length vectors. "
45 "Fractional LMUL values are not supported."),
46 cl::init(8), cl::Hidden);
47
anchor()48 void RISCVSubtarget::anchor() {}
49
50 RISCVSubtarget &
initializeSubtargetDependencies(const Triple & TT,StringRef CPU,StringRef TuneCPU,StringRef FS,StringRef ABIName)51 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
52 StringRef TuneCPU, StringRef FS,
53 StringRef ABIName) {
54 // Determine default and user-specified characteristics
55 bool Is64Bit = TT.isArch64Bit();
56 if (CPU.empty())
57 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
58 if (CPU == "generic")
59 report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
60 (Is64Bit ? "generic-rv64" : "generic-rv32"));
61
62 if (TuneCPU.empty())
63 TuneCPU = CPU;
64
65 ParseSubtargetFeatures(CPU, TuneCPU, FS);
66 if (Is64Bit) {
67 XLenVT = MVT::i64;
68 XLen = 64;
69 }
70
71 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
72 RISCVFeatures::validate(TT, getFeatureBits());
73 return *this;
74 }
75
RISCVSubtarget(const Triple & TT,StringRef CPU,StringRef TuneCPU,StringRef FS,StringRef ABIName,const TargetMachine & TM)76 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
77 StringRef TuneCPU, StringRef FS,
78 StringRef ABIName, const TargetMachine &TM)
79 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
80 UserReservedRegister(RISCV::NUM_TARGET_REGS),
81 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
82 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
83 CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
84 Legalizer.reset(new RISCVLegalizerInfo(*this));
85
86 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
87 RegBankInfo.reset(RBI);
88 InstSelector.reset(createRISCVInstructionSelector(
89 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
90 }
91
getCallLowering() const92 const CallLowering *RISCVSubtarget::getCallLowering() const {
93 return CallLoweringInfo.get();
94 }
95
getInstructionSelector() const96 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
97 return InstSelector.get();
98 }
99
getLegalizerInfo() const100 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
101 return Legalizer.get();
102 }
103
getRegBankInfo() const104 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
105 return RegBankInfo.get();
106 }
107
getMaxRVVVectorSizeInBits() const108 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
109 assert(hasStdExtV() && "Tried to get vector length without V support!");
110 if (RVVVectorBitsMax == 0)
111 return 0;
112 assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
113 "V extension requires vector length to be at least 128 and a power of "
114 "2!");
115 assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
116 "Minimum V extension vector length should not be larger than its "
117 "maximum!");
118 unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
119 return PowerOf2Floor(Max < 128 ? 0 : Max);
120 }
121
getMinRVVVectorSizeInBits() const122 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
123 assert(hasStdExtV() &&
124 "Tried to get vector length without V extension support!");
125 assert((RVVVectorBitsMin == 0 ||
126 (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
127 "V extension requires vector length to be at least 128 and a power of "
128 "2!");
129 assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
130 "Minimum V extension vector length should not be larger than its "
131 "maximum!");
132 unsigned Min = RVVVectorBitsMin;
133 if (RVVVectorBitsMax != 0)
134 Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
135 return PowerOf2Floor(Min < 128 ? 0 : Min);
136 }
137
getMaxLMULForFixedLengthVectors() const138 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
139 assert(hasStdExtV() &&
140 "Tried to get maximum LMUL without V extension support!");
141 assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
142 "V extension requires a LMUL to be at most 8 and a power of 2!");
143 return PowerOf2Floor(std::max<unsigned>(RVVVectorLMULMax, 1));
144 }
145
useRVVForFixedLengthVectors() const146 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
147 return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
148 }
149