1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/CodeGen/ISDOpcodes.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include <vector>
22
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25
26 namespace llvm {
27 class X86Subtarget;
28
29 namespace X86 {
30
31 enum AsmComments {
32 // For instr that was compressed from EVEX to VEX.
33 AC_EVEX_2_VEX = MachineInstr::TAsmComments
34 };
35
36 /// Return a pair of condition code for the given predicate and whether
37 /// the instruction operands should be swaped to match the condition code.
38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
39
40 /// Return a setcc opcode based on whether it has a memory operand.
41 unsigned getSETOpc(bool HasMemoryOperand = false);
42
43 /// Return a cmov opcode for the given register size in bytes, and operand type.
44 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
45
46 // Turn jCC instruction into condition code.
47 CondCode getCondFromBranch(const MachineInstr &MI);
48
49 // Turn setCC instruction into condition code.
50 CondCode getCondFromSETCC(const MachineInstr &MI);
51
52 // Turn CMov instruction into condition code.
53 CondCode getCondFromCMov(const MachineInstr &MI);
54
55 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
56 /// e.g. turning COND_E to COND_NE.
57 CondCode GetOppositeBranchCondition(CondCode CC);
58
59 /// Get the VPCMP immediate for the given condition.
60 unsigned getVPCMPImmForCond(ISD::CondCode CC);
61
62 /// Get the VPCMP immediate if the opcodes are swapped.
63 unsigned getSwappedVPCMPImm(unsigned Imm);
64
65 /// Get the VPCOM immediate if the opcodes are swapped.
66 unsigned getSwappedVPCOMImm(unsigned Imm);
67
68 /// Get the VCMP immediate if the opcodes are swapped.
69 unsigned getSwappedVCMPImm(unsigned Imm);
70
71 } // namespace X86
72
73 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
74 /// a reference to a stub for a global, not the global itself.
isGlobalStubReference(unsigned char TargetFlag)75 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
76 switch (TargetFlag) {
77 case X86II::MO_DLLIMPORT: // dllimport stub.
78 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
79 case X86II::MO_GOT: // normal GOT reference.
80 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
81 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
82 case X86II::MO_COFFSTUB: // COFF .refptr stub.
83 return true;
84 default:
85 return false;
86 }
87 }
88
89 /// isGlobalRelativeToPICBase - Return true if the specified global value
90 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
91 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
isGlobalRelativeToPICBase(unsigned char TargetFlag)92 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
93 switch (TargetFlag) {
94 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
95 case X86II::MO_GOT: // isPICStyleGOT: other global.
96 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
97 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
98 case X86II::MO_TLVP: // ??? Pretty sure..
99 return true;
100 default:
101 return false;
102 }
103 }
104
isScale(const MachineOperand & MO)105 inline static bool isScale(const MachineOperand &MO) {
106 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
107 MO.getImm() == 4 || MO.getImm() == 8);
108 }
109
isLeaMem(const MachineInstr & MI,unsigned Op)110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
111 if (MI.getOperand(Op).isFI())
112 return true;
113 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
114 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
115 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
116 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
117 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
118 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
119 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
120 MI.getOperand(Op + X86::AddrDisp).isJTI());
121 }
122
isMem(const MachineInstr & MI,unsigned Op)123 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
124 if (MI.getOperand(Op).isFI())
125 return true;
126 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
127 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
128 }
129
130 class X86InstrInfo final : public X86GenInstrInfo {
131 X86Subtarget &Subtarget;
132 const X86RegisterInfo RI;
133
134 virtual void anchor();
135
136 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
137 MachineBasicBlock *&FBB,
138 SmallVectorImpl<MachineOperand> &Cond,
139 SmallVectorImpl<MachineInstr *> &CondBranches,
140 bool AllowModify) const;
141
142 public:
143 explicit X86InstrInfo(X86Subtarget &STI);
144
145 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
146 /// such, whenever a client has an instance of instruction info, it should
147 /// always be able to get register info as well (through this method).
148 ///
getRegisterInfo()149 const X86RegisterInfo &getRegisterInfo() const { return RI; }
150
151 /// Returns the stack pointer adjustment that happens inside the frame
152 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
getFrameAdjustment(const MachineInstr & I)153 int64_t getFrameAdjustment(const MachineInstr &I) const {
154 assert(isFrameInstr(I));
155 if (isFrameSetup(I))
156 return I.getOperand(2).getImm();
157 return I.getOperand(1).getImm();
158 }
159
160 /// Sets the stack pointer adjustment made inside the frame made up by this
161 /// instruction.
setFrameAdjustment(MachineInstr & I,int64_t V)162 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
163 assert(isFrameInstr(I));
164 if (isFrameSetup(I))
165 I.getOperand(2).setImm(V);
166 else
167 I.getOperand(1).setImm(V);
168 }
169
170 /// getSPAdjust - This returns the stack pointer adjustment made by
171 /// this instruction. For x86, we need to handle more complex call
172 /// sequences involving PUSHes.
173 int getSPAdjust(const MachineInstr &MI) const override;
174
175 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
176 /// extension instruction. That is, it's like a copy where it's legal for the
177 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
178 /// true, then it's expected the pre-extension value is available as a subreg
179 /// of the result register. This also returns the sub-register index in
180 /// SubIdx.
181 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
182 Register &DstReg, unsigned &SubIdx) const override;
183
184 /// Returns true if the instruction has no behavior (specified or otherwise)
185 /// that is based on the value of any of its register operands
186 ///
187 /// Instructions are considered data invariant even if they set EFLAGS.
188 ///
189 /// A classical example of something that is inherently not data invariant is
190 /// an indirect jump -- the destination is loaded into icache based on the
191 /// bits set in the jump destination register.
192 ///
193 /// FIXME: This should become part of our instruction tables.
194 static bool isDataInvariant(MachineInstr &MI);
195
196 /// Returns true if the instruction has no behavior (specified or otherwise)
197 /// that is based on the value loaded from memory or the value of any
198 /// non-address register operands.
199 ///
200 /// For example, if the latency of the instruction is dependent on the
201 /// particular bits set in any of the registers *or* any of the bits loaded
202 /// from memory.
203 ///
204 /// Instructions are considered data invariant even if they set EFLAGS.
205 ///
206 /// A classical example of something that is inherently not data invariant is
207 /// an indirect jump -- the destination is loaded into icache based on the
208 /// bits set in the jump destination register.
209 ///
210 /// FIXME: This should become part of our instruction tables.
211 static bool isDataInvariantLoad(MachineInstr &MI);
212
213 unsigned isLoadFromStackSlot(const MachineInstr &MI,
214 int &FrameIndex) const override;
215 unsigned isLoadFromStackSlot(const MachineInstr &MI,
216 int &FrameIndex,
217 unsigned &MemBytes) const override;
218 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
219 /// stack locations as well. This uses a heuristic so it isn't
220 /// reliable for correctness.
221 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
222 int &FrameIndex) const override;
223
224 unsigned isStoreToStackSlot(const MachineInstr &MI,
225 int &FrameIndex) const override;
226 unsigned isStoreToStackSlot(const MachineInstr &MI,
227 int &FrameIndex,
228 unsigned &MemBytes) const override;
229 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
230 /// stack locations as well. This uses a heuristic so it isn't
231 /// reliable for correctness.
232 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
233 int &FrameIndex) const override;
234
235 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
236 AAResults *AA) const override;
237 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
238 Register DestReg, unsigned SubIdx,
239 const MachineInstr &Orig,
240 const TargetRegisterInfo &TRI) const override;
241
242 /// Given an operand within a MachineInstr, insert preceding code to put it
243 /// into the right format for a particular kind of LEA instruction. This may
244 /// involve using an appropriate super-register instead (with an implicit use
245 /// of the original) or creating a new virtual register and inserting COPY
246 /// instructions to get the data into the right class.
247 ///
248 /// Reference parameters are set to indicate how caller should add this
249 /// operand to the LEA instruction.
250 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
251 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
252 bool &isKill, MachineOperand &ImplicitOp,
253 LiveVariables *LV) const;
254
255 /// convertToThreeAddress - This method must be implemented by targets that
256 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
257 /// may be able to convert a two-address instruction into a true
258 /// three-address instruction on demand. This allows the X86 target (for
259 /// example) to convert ADD and SHL instructions into LEA instructions if they
260 /// would require register copies due to two-addressness.
261 ///
262 /// This method returns a null pointer if the transformation cannot be
263 /// performed, otherwise it returns the new instruction.
264 ///
265 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
266 MachineInstr &MI,
267 LiveVariables *LV) const override;
268
269 /// Returns true iff the routine could find two commutable operands in the
270 /// given machine instruction.
271 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
272 /// input values can be re-defined in this method only if the input values
273 /// are not pre-defined, which is designated by the special value
274 /// 'CommuteAnyOperandIndex' assigned to it.
275 /// If both of indices are pre-defined and refer to some operands, then the
276 /// method simply returns true if the corresponding operands are commutable
277 /// and returns false otherwise.
278 ///
279 /// For example, calling this method this way:
280 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
281 /// findCommutedOpIndices(MI, Op1, Op2);
282 /// can be interpreted as a query asking to find an operand that would be
283 /// commutable with the operand#1.
284 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
285 unsigned &SrcOpIdx2) const override;
286
287 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
288 /// performs the same computations as the given \p MI but which has the
289 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
290 /// It may return 0 if it is unsafe to commute the operands.
291 /// Note that a machine instruction (instead of its opcode) is passed as the
292 /// first parameter to make it possible to analyze the instruction's uses and
293 /// commute the first operand of FMA even when it seems unsafe when you look
294 /// at the opcode. For example, it is Ok to commute the first operand of
295 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
296 ///
297 /// The returned FMA opcode may differ from the opcode in the given \p MI.
298 /// For example, commuting the operands #1 and #3 in the following FMA
299 /// FMA213 #1, #2, #3
300 /// results into instruction with adjusted opcode:
301 /// FMA231 #3, #2, #1
302 unsigned
303 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
304 unsigned SrcOpIdx2,
305 const X86InstrFMA3Group &FMA3Group) const;
306
307 // Branch analysis.
308 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
309 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
310 const MachineInstr &TailCall) const override;
311 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
312 SmallVectorImpl<MachineOperand> &Cond,
313 const MachineInstr &TailCall) const override;
314
315 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
316 MachineBasicBlock *&FBB,
317 SmallVectorImpl<MachineOperand> &Cond,
318 bool AllowModify) const override;
319
320 Optional<ExtAddrMode>
321 getAddrModeFromMemoryOp(const MachineInstr &MemI,
322 const TargetRegisterInfo *TRI) const override;
323
324 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
325 int64_t &ImmVal) const override;
326
327 bool preservesZeroValueInReg(const MachineInstr *MI,
328 const Register NullValueReg,
329 const TargetRegisterInfo *TRI) const override;
330
331 bool getMemOperandsWithOffsetWidth(
332 const MachineInstr &LdSt,
333 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
334 bool &OffsetIsScalable, unsigned &Width,
335 const TargetRegisterInfo *TRI) const override;
336 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
337 TargetInstrInfo::MachineBranchPredicate &MBP,
338 bool AllowModify = false) const override;
339
340 unsigned removeBranch(MachineBasicBlock &MBB,
341 int *BytesRemoved = nullptr) const override;
342 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
343 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
344 const DebugLoc &DL,
345 int *BytesAdded = nullptr) const override;
346 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
347 Register, Register, Register, int &, int &,
348 int &) const override;
349 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
350 const DebugLoc &DL, Register DstReg,
351 ArrayRef<MachineOperand> Cond, Register TrueReg,
352 Register FalseReg) const override;
353 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
354 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
355 bool KillSrc) const override;
356 void storeRegToStackSlot(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator MI, Register SrcReg,
358 bool isKill, int FrameIndex,
359 const TargetRegisterClass *RC,
360 const TargetRegisterInfo *TRI) const override;
361
362 void loadRegFromStackSlot(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator MI, Register DestReg,
364 int FrameIndex, const TargetRegisterClass *RC,
365 const TargetRegisterInfo *TRI) const override;
366
367 bool expandPostRAPseudo(MachineInstr &MI) const override;
368
369 /// Check whether the target can fold a load that feeds a subreg operand
370 /// (or a subreg operand that feeds a store).
isSubregFoldable()371 bool isSubregFoldable() const override { return true; }
372
373 /// foldMemoryOperand - If this target supports it, fold a load or store of
374 /// the specified stack slot into the specified machine instruction for the
375 /// specified operand(s). If this is possible, the target should perform the
376 /// folding and return true, otherwise it should return false. If it folds
377 /// the instruction, it is likely that the MachineInstruction the iterator
378 /// references has been changed.
379 MachineInstr *
380 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
381 ArrayRef<unsigned> Ops,
382 MachineBasicBlock::iterator InsertPt, int FrameIndex,
383 LiveIntervals *LIS = nullptr,
384 VirtRegMap *VRM = nullptr) const override;
385
386 /// foldMemoryOperand - Same as the previous version except it allows folding
387 /// of any load and store from / to any address, not just from a specific
388 /// stack slot.
389 MachineInstr *foldMemoryOperandImpl(
390 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
391 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
392 LiveIntervals *LIS = nullptr) const override;
393
394 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
395 /// a store or a load and a store into two or more instruction. If this is
396 /// possible, returns true as well as the new instructions by reference.
397 bool
398 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
399 bool UnfoldLoad, bool UnfoldStore,
400 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
401
402 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
403 SmallVectorImpl<SDNode *> &NewNodes) const override;
404
405 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
406 /// instruction after load / store are unfolded from an instruction of the
407 /// specified opcode. It returns zero if the specified unfolding is not
408 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
409 /// index of the operand which will hold the register holding the loaded
410 /// value.
411 unsigned
412 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
413 unsigned *LoadRegIndex = nullptr) const override;
414
415 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
416 /// to determine if two loads are loading from the same base address. It
417 /// should only return true if the base pointers are the same and the
418 /// only differences between the two addresses are the offset. It also returns
419 /// the offsets by reference.
420 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
421 int64_t &Offset2) const override;
422
423 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
424 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
425 /// intructions and prevent it from being re-scheduled.
426 bool isSchedulingBoundary(const MachineInstr &MI,
427 const MachineBasicBlock *MBB,
428 const MachineFunction &MF) const override;
429
430 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
431 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
432 /// should be scheduled togther. On some targets if two loads are loading from
433 /// addresses in the same cache line, it's better if they are scheduled
434 /// together. This function takes two integers that represent the load offsets
435 /// from the common base address. It returns true if it decides it's desirable
436 /// to schedule the two loads together. "NumLoads" is the number of loads that
437 /// have already been scheduled after Load1.
438 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
439 int64_t Offset2,
440 unsigned NumLoads) const override;
441
442 MCInst getNop() const override;
443
444 bool
445 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
446
447 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
448 /// instruction that defines the specified register class.
449 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
450
451 /// True if MI has a condition code def, e.g. EFLAGS, that is
452 /// not marked dead.
453 bool hasLiveCondCodeDef(MachineInstr &MI) const;
454
455 /// getGlobalBaseReg - Return a virtual register initialized with the
456 /// the global base register value. Output instructions required to
457 /// initialize the register in the function entry block, if necessary.
458 ///
459 unsigned getGlobalBaseReg(MachineFunction *MF) const;
460
461 std::pair<uint16_t, uint16_t>
462 getExecutionDomain(const MachineInstr &MI) const override;
463
464 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
465
466 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
467
468 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
469
470 unsigned
471 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
472 const TargetRegisterInfo *TRI) const override;
473 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
474 const TargetRegisterInfo *TRI) const override;
475 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
476 const TargetRegisterInfo *TRI) const override;
477
478 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
479 unsigned OpNum,
480 ArrayRef<MachineOperand> MOs,
481 MachineBasicBlock::iterator InsertPt,
482 unsigned Size, Align Alignment,
483 bool AllowCommute) const;
484
485 bool isHighLatencyDef(int opc) const override;
486
487 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
488 const MachineRegisterInfo *MRI,
489 const MachineInstr &DefMI, unsigned DefIdx,
490 const MachineInstr &UseMI,
491 unsigned UseIdx) const override;
492
useMachineCombiner()493 bool useMachineCombiner() const override { return true; }
494
495 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
496
497 bool hasReassociableOperands(const MachineInstr &Inst,
498 const MachineBasicBlock *MBB) const override;
499
500 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
501 MachineInstr &NewMI1,
502 MachineInstr &NewMI2) const override;
503
504 /// analyzeCompare - For a comparison instruction, return the source registers
505 /// in SrcReg and SrcReg2 if having two register operands, and the value it
506 /// compares against in CmpValue. Return true if the comparison instruction
507 /// can be analyzed.
508 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
509 Register &SrcReg2, int &CmpMask,
510 int &CmpValue) const override;
511
512 /// optimizeCompareInstr - Check if there exists an earlier instruction that
513 /// operates on the same source operands and sets flags in the same way as
514 /// Compare; remove Compare if possible.
515 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
516 Register SrcReg2, int CmpMask, int CmpValue,
517 const MachineRegisterInfo *MRI) const override;
518
519 /// optimizeLoadInstr - Try to remove the load by folding it to a register
520 /// operand at the use. We fold the load instructions if and only if the
521 /// def and use are in the same BB. We only look at one load and see
522 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
523 /// defined by the load we are trying to fold. DefMI returns the machine
524 /// instruction that defines FoldAsLoadDefReg, and the function returns
525 /// the machine instruction generated due to folding.
526 MachineInstr *optimizeLoadInstr(MachineInstr &MI,
527 const MachineRegisterInfo *MRI,
528 Register &FoldAsLoadDefReg,
529 MachineInstr *&DefMI) const override;
530
531 std::pair<unsigned, unsigned>
532 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
533
534 ArrayRef<std::pair<unsigned, const char *>>
535 getSerializableDirectMachineOperandTargetFlags() const override;
536
537 virtual outliner::OutlinedFunction getOutliningCandidateInfo(
538 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
539
540 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
541 bool OutlineFromLinkOnceODRs) const override;
542
543 outliner::InstrType
544 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
545
546 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
547 const outliner::OutlinedFunction &OF) const override;
548
549 MachineBasicBlock::iterator
550 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
551 MachineBasicBlock::iterator &It, MachineFunction &MF,
552 const outliner::Candidate &C) const override;
553
554 #define GET_INSTRINFO_HELPER_DECLS
555 #include "X86GenInstrInfo.inc"
556
hasLockPrefix(const MachineInstr & MI)557 static bool hasLockPrefix(const MachineInstr &MI) {
558 return MI.getDesc().TSFlags & X86II::LOCK;
559 }
560
561 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
562 Register Reg) const override;
563
564 protected:
565 /// Commutes the operands in the given instruction by changing the operands
566 /// order and/or changing the instruction's opcode and/or the immediate value
567 /// operand.
568 ///
569 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
570 /// to be commuted.
571 ///
572 /// Do not call this method for a non-commutable instruction or
573 /// non-commutable operands.
574 /// Even though the instruction is commutable, the method may still
575 /// fail to commute the operands, null pointer is returned in such cases.
576 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
577 unsigned CommuteOpIdx1,
578 unsigned CommuteOpIdx2) const override;
579
580 /// If the specific machine instruction is a instruction that moves/copies
581 /// value from one register to another register return destination and source
582 /// registers as machine operands.
583 Optional<DestSourcePair>
584 isCopyInstrImpl(const MachineInstr &MI) const override;
585
586 private:
587 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
588 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
589 /// super-register and then truncating back down to a 8/16-bit sub-register.
590 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
591 MachineFunction::iterator &MFI,
592 MachineInstr &MI,
593 LiveVariables *LV,
594 bool Is8BitOp) const;
595
596 /// Handles memory folding for special case instructions, for instance those
597 /// requiring custom manipulation of the address.
598 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
599 unsigned OpNum,
600 ArrayRef<MachineOperand> MOs,
601 MachineBasicBlock::iterator InsertPt,
602 unsigned Size, Align Alignment) const;
603
604 /// isFrameOperand - Return true and the FrameIndex if the specified
605 /// operand and follow operands form a reference to the stack frame.
606 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
607 int &FrameIndex) const;
608
609 /// Returns true iff the routine could find two commutable operands in the
610 /// given machine instruction with 3 vector inputs.
611 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
612 /// input values can be re-defined in this method only if the input values
613 /// are not pre-defined, which is designated by the special value
614 /// 'CommuteAnyOperandIndex' assigned to it.
615 /// If both of indices are pre-defined and refer to some operands, then the
616 /// method simply returns true if the corresponding operands are commutable
617 /// and returns false otherwise.
618 ///
619 /// For example, calling this method this way:
620 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
621 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
622 /// can be interpreted as a query asking to find an operand that would be
623 /// commutable with the operand#1.
624 ///
625 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
626 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
627 unsigned &SrcOpIdx1,
628 unsigned &SrcOpIdx2,
629 bool IsIntrinsic = false) const;
630 };
631
632 } // namespace llvm
633
634 #endif
635