1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
4 */
5
6 #include <sys/queue.h>
7 #include <stdio.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <string.h>
11 #include <rte_log.h>
12 #include <ethdev_pci.h>
13 #include <rte_alarm.h>
14
15 #include "txgbe_logs.h"
16 #include "base/txgbe.h"
17 #include "txgbe_ethdev.h"
18 #include "txgbe_rxtx.h"
19 #include "txgbe_regs_group.h"
20
21 static const struct reg_info txgbevf_regs_general[] = {
22 {TXGBE_VFRST, 1, 1, "TXGBE_VFRST"},
23 {TXGBE_VFSTATUS, 1, 1, "TXGBE_VFSTATUS"},
24 {TXGBE_VFMBCTL, 1, 1, "TXGBE_VFMAILBOX"},
25 {TXGBE_VFMBX, 16, 4, "TXGBE_VFMBX"},
26 {TXGBE_VFPBWRAP, 1, 1, "TXGBE_VFPBWRAP"},
27 {0, 0, 0, ""}
28 };
29
30 static const struct reg_info txgbevf_regs_interrupt[] = {
31 {0, 0, 0, ""}
32 };
33
34 static const struct reg_info txgbevf_regs_rxdma[] = {
35 {0, 0, 0, ""}
36 };
37
38 static const struct reg_info txgbevf_regs_tx[] = {
39 {0, 0, 0, ""}
40 };
41
42 /* VF registers */
43 static const struct reg_info *txgbevf_regs[] = {
44 txgbevf_regs_general,
45 txgbevf_regs_interrupt,
46 txgbevf_regs_rxdma,
47 txgbevf_regs_tx,
48 NULL};
49
50 static int txgbevf_dev_xstats_get(struct rte_eth_dev *dev,
51 struct rte_eth_xstat *xstats, unsigned int n);
52 static int txgbevf_dev_info_get(struct rte_eth_dev *dev,
53 struct rte_eth_dev_info *dev_info);
54 static int txgbevf_dev_configure(struct rte_eth_dev *dev);
55 static int txgbevf_dev_start(struct rte_eth_dev *dev);
56 static int txgbevf_dev_link_update(struct rte_eth_dev *dev,
57 int wait_to_complete);
58 static int txgbevf_dev_stop(struct rte_eth_dev *dev);
59 static int txgbevf_dev_close(struct rte_eth_dev *dev);
60 static void txgbevf_intr_disable(struct rte_eth_dev *dev);
61 static void txgbevf_intr_enable(struct rte_eth_dev *dev);
62 static int txgbevf_dev_stats_reset(struct rte_eth_dev *dev);
63 static int txgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
64 static void txgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
65 static void txgbevf_configure_msix(struct rte_eth_dev *dev);
66 static int txgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
67 static int txgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
68 static void txgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
69 static void txgbevf_dev_interrupt_handler(void *param);
70
71 /*
72 * The set of PCI devices this driver supports (for VF)
73 */
74 static const struct rte_pci_id pci_id_txgbevf_map[] = {
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000_VF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_VF) },
77 { .vendor_id = 0, /* sentinel */ },
78 };
79
80 static const struct rte_eth_desc_lim rx_desc_lim = {
81 .nb_max = TXGBE_RING_DESC_MAX,
82 .nb_min = TXGBE_RING_DESC_MIN,
83 .nb_align = TXGBE_RXD_ALIGN,
84 };
85
86 static const struct rte_eth_desc_lim tx_desc_lim = {
87 .nb_max = TXGBE_RING_DESC_MAX,
88 .nb_min = TXGBE_RING_DESC_MIN,
89 .nb_align = TXGBE_TXD_ALIGN,
90 .nb_seg_max = TXGBE_TX_MAX_SEG,
91 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
92 };
93
94 static const struct eth_dev_ops txgbevf_eth_dev_ops;
95
96 static const struct rte_txgbe_xstats_name_off rte_txgbevf_stats_strings[] = {
97 {"rx_multicast_packets_0",
98 offsetof(struct txgbevf_hw_stats, qp[0].vfmprc)},
99 {"rx_multicast_packets_1",
100 offsetof(struct txgbevf_hw_stats, qp[1].vfmprc)},
101 {"rx_multicast_packets_2",
102 offsetof(struct txgbevf_hw_stats, qp[2].vfmprc)},
103 {"rx_multicast_packets_3",
104 offsetof(struct txgbevf_hw_stats, qp[3].vfmprc)},
105 {"rx_multicast_packets_4",
106 offsetof(struct txgbevf_hw_stats, qp[4].vfmprc)},
107 {"rx_multicast_packets_5",
108 offsetof(struct txgbevf_hw_stats, qp[5].vfmprc)},
109 {"rx_multicast_packets_6",
110 offsetof(struct txgbevf_hw_stats, qp[6].vfmprc)},
111 {"rx_multicast_packets_7",
112 offsetof(struct txgbevf_hw_stats, qp[7].vfmprc)}
113 };
114
115 #define TXGBEVF_NB_XSTATS (sizeof(rte_txgbevf_stats_strings) / \
116 sizeof(rte_txgbevf_stats_strings[0]))
117
118 /*
119 * Negotiate mailbox API version with the PF.
120 * After reset API version is always set to the basic one (txgbe_mbox_api_10).
121 * Then we try to negotiate starting with the most recent one.
122 * If all negotiation attempts fail, then we will proceed with
123 * the default one (txgbe_mbox_api_10).
124 */
125 static void
txgbevf_negotiate_api(struct txgbe_hw * hw)126 txgbevf_negotiate_api(struct txgbe_hw *hw)
127 {
128 int32_t i;
129
130 /* start with highest supported, proceed down */
131 static const int sup_ver[] = {
132 txgbe_mbox_api_13,
133 txgbe_mbox_api_12,
134 txgbe_mbox_api_11,
135 txgbe_mbox_api_10,
136 };
137
138 for (i = 0; i < ARRAY_SIZE(sup_ver); i++) {
139 if (txgbevf_negotiate_api_version(hw, sup_ver[i]) == 0)
140 break;
141 }
142 }
143
144 static void
generate_random_mac_addr(struct rte_ether_addr * mac_addr)145 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
146 {
147 uint64_t random;
148
149 /* Set Organizationally Unique Identifier (OUI) prefix. */
150 mac_addr->addr_bytes[0] = 0x00;
151 mac_addr->addr_bytes[1] = 0x09;
152 mac_addr->addr_bytes[2] = 0xC0;
153 /* Force indication of locally assigned MAC address. */
154 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
155 /* Generate the last 3 bytes of the MAC address with a random number. */
156 random = rte_rand();
157 memcpy(&mac_addr->addr_bytes[3], &random, 3);
158 }
159
160 /*
161 * Virtual Function device init
162 */
163 static int
eth_txgbevf_dev_init(struct rte_eth_dev * eth_dev)164 eth_txgbevf_dev_init(struct rte_eth_dev *eth_dev)
165 {
166 int err;
167 uint32_t tc, tcs;
168 struct txgbe_adapter *ad = eth_dev->data->dev_private;
169 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
170 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
171 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
172 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
173 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
174 struct rte_ether_addr *perm_addr =
175 (struct rte_ether_addr *)hw->mac.perm_addr;
176
177 PMD_INIT_FUNC_TRACE();
178
179 eth_dev->dev_ops = &txgbevf_eth_dev_ops;
180 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
181 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
182 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
183 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
184
185 /* for secondary processes, we don't initialise any further as primary
186 * has already done this work. Only check we don't need a different
187 * RX function
188 */
189 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
190 struct txgbe_tx_queue *txq;
191 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
192 /* TX queue function in primary, set by last queue initialized
193 * Tx queue may not initialized by primary process
194 */
195 if (eth_dev->data->tx_queues) {
196 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
197 txgbe_set_tx_function(eth_dev, txq);
198 } else {
199 /* Use default TX function if we get here */
200 PMD_INIT_LOG(NOTICE,
201 "No TX queues configured yet. Using default TX function.");
202 }
203
204 txgbe_set_rx_function(eth_dev);
205
206 return 0;
207 }
208
209 rte_atomic_store_explicit(&ad->link_thread_running, 0, rte_memory_order_seq_cst);
210 rte_eth_copy_pci_info(eth_dev, pci_dev);
211
212 hw->device_id = pci_dev->id.device_id;
213 hw->vendor_id = pci_dev->id.vendor_id;
214 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
215 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
216 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
217
218 /* initialize the vfta */
219 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
220
221 /* initialize the hw strip bitmap*/
222 memset(hwstrip, 0, sizeof(*hwstrip));
223
224 /* Initialize the shared code (base driver) */
225 err = txgbe_init_shared_code(hw);
226 if (err != 0) {
227 PMD_INIT_LOG(ERR,
228 "Shared code init failed for txgbevf: %d", err);
229 return -EIO;
230 }
231
232 /* init_mailbox_params */
233 hw->mbx.init_params(hw);
234
235 /* Reset the hw statistics */
236 txgbevf_dev_stats_reset(eth_dev);
237
238 /* Disable the interrupts for VF */
239 txgbevf_intr_disable(eth_dev);
240
241 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
242 err = hw->mac.reset_hw(hw);
243
244 /*
245 * The VF reset operation returns the TXGBE_ERR_INVALID_MAC_ADDR when
246 * the underlying PF driver has not assigned a MAC address to the VF.
247 * In this case, assign a random MAC address.
248 */
249 if (err != 0 && err != TXGBE_ERR_INVALID_MAC_ADDR) {
250 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", err);
251 /*
252 * This error code will be propagated to the app by
253 * rte_eth_dev_reset, so use a public error code rather than
254 * the internal-only TXGBE_ERR_RESET_FAILED
255 */
256 return -EAGAIN;
257 }
258
259 /* negotiate mailbox API version to use with the PF. */
260 txgbevf_negotiate_api(hw);
261
262 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
263 txgbevf_get_queues(hw, &tcs, &tc);
264
265 /* Allocate memory for storing MAC addresses */
266 eth_dev->data->mac_addrs = rte_zmalloc("txgbevf", RTE_ETHER_ADDR_LEN *
267 hw->mac.num_rar_entries, 0);
268 if (eth_dev->data->mac_addrs == NULL) {
269 PMD_INIT_LOG(ERR,
270 "Failed to allocate %u bytes needed to store "
271 "MAC addresses",
272 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
273 return -ENOMEM;
274 }
275
276 /* Generate a random MAC address, if none was assigned by PF. */
277 if (rte_is_zero_ether_addr(perm_addr)) {
278 generate_random_mac_addr(perm_addr);
279 err = txgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
280 if (err) {
281 rte_free(eth_dev->data->mac_addrs);
282 eth_dev->data->mac_addrs = NULL;
283 return err;
284 }
285 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
286 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
287 RTE_ETHER_ADDR_PRT_FMT,
288 RTE_ETHER_ADDR_BYTES(perm_addr));
289 }
290
291 /* Copy the permanent MAC address */
292 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
293
294 /* reset the hardware with the new settings */
295 err = hw->mac.start_hw(hw);
296 if (err) {
297 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", err);
298 rte_free(eth_dev->data->mac_addrs);
299 eth_dev->data->mac_addrs = NULL;
300 return -EIO;
301 }
302
303 /* enter promiscuous mode */
304 txgbevf_dev_promiscuous_enable(eth_dev);
305
306 rte_intr_callback_register(intr_handle,
307 txgbevf_dev_interrupt_handler, eth_dev);
308 rte_intr_enable(intr_handle);
309 txgbevf_intr_enable(eth_dev);
310
311 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
312 eth_dev->data->port_id, pci_dev->id.vendor_id,
313 pci_dev->id.device_id, "txgbe_mac_raptor_vf");
314
315 return 0;
316 }
317
318 /* Virtual Function device uninit */
319 static int
eth_txgbevf_dev_uninit(struct rte_eth_dev * eth_dev)320 eth_txgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
321 {
322 PMD_INIT_FUNC_TRACE();
323
324 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
325 return 0;
326
327 txgbevf_dev_close(eth_dev);
328
329 return 0;
330 }
331
eth_txgbevf_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)332 static int eth_txgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
333 struct rte_pci_device *pci_dev)
334 {
335 return rte_eth_dev_pci_generic_probe(pci_dev,
336 sizeof(struct txgbe_adapter), eth_txgbevf_dev_init);
337 }
338
eth_txgbevf_pci_remove(struct rte_pci_device * pci_dev)339 static int eth_txgbevf_pci_remove(struct rte_pci_device *pci_dev)
340 {
341 return rte_eth_dev_pci_generic_remove(pci_dev, eth_txgbevf_dev_uninit);
342 }
343
344 /*
345 * virtual function driver struct
346 */
347 static struct rte_pci_driver rte_txgbevf_pmd = {
348 .id_table = pci_id_txgbevf_map,
349 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
350 .probe = eth_txgbevf_pci_probe,
351 .remove = eth_txgbevf_pci_remove,
352 };
353
txgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,unsigned int limit)354 static int txgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
355 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
356 {
357 unsigned int i;
358
359 if (limit < TXGBEVF_NB_XSTATS && xstats_names != NULL)
360 return -ENOMEM;
361
362 if (xstats_names != NULL)
363 for (i = 0; i < TXGBEVF_NB_XSTATS; i++)
364 snprintf(xstats_names[i].name,
365 sizeof(xstats_names[i].name),
366 "%s", rte_txgbevf_stats_strings[i].name);
367 return TXGBEVF_NB_XSTATS;
368 }
369
370 static void
txgbevf_update_stats(struct rte_eth_dev * dev)371 txgbevf_update_stats(struct rte_eth_dev *dev)
372 {
373 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
374 struct txgbevf_hw_stats *hw_stats = (struct txgbevf_hw_stats *)
375 TXGBE_DEV_STATS(dev);
376 unsigned int i;
377
378 for (i = 0; i < dev->data->nb_rx_queues; i++) {
379 /* Good Rx packet, include VF loopback */
380 TXGBE_UPDCNT32(TXGBE_QPRXPKT(i),
381 hw_stats->qp[i].last_vfgprc, hw_stats->qp[i].vfgprc);
382
383 /* Good Rx octets, include VF loopback */
384 TXGBE_UPDCNT36(TXGBE_QPRXOCTL(i),
385 hw_stats->qp[i].last_vfgorc, hw_stats->qp[i].vfgorc);
386
387 /* Rx Multicst Packet */
388 TXGBE_UPDCNT32(TXGBE_QPRXMPKT(i),
389 hw_stats->qp[i].last_vfmprc, hw_stats->qp[i].vfmprc);
390 }
391 hw->rx_loaded = 0;
392
393 for (i = 0; i < dev->data->nb_tx_queues; i++) {
394 /* Good Tx packet, include VF loopback */
395 TXGBE_UPDCNT32(TXGBE_QPTXPKT(i),
396 hw_stats->qp[i].last_vfgptc, hw_stats->qp[i].vfgptc);
397
398 /* Good Tx octets, include VF loopback */
399 TXGBE_UPDCNT36(TXGBE_QPTXOCTL(i),
400 hw_stats->qp[i].last_vfgotc, hw_stats->qp[i].vfgotc);
401 }
402 hw->offset_loaded = 0;
403 }
404
405 static int
txgbevf_dev_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned int n)406 txgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
407 unsigned int n)
408 {
409 struct txgbevf_hw_stats *hw_stats = (struct txgbevf_hw_stats *)
410 TXGBE_DEV_STATS(dev);
411 unsigned int i;
412
413 if (n < TXGBEVF_NB_XSTATS)
414 return TXGBEVF_NB_XSTATS;
415
416 txgbevf_update_stats(dev);
417
418 if (!xstats)
419 return 0;
420
421 /* Extended stats */
422 for (i = 0; i < TXGBEVF_NB_XSTATS; i++) {
423 xstats[i].id = i;
424 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
425 rte_txgbevf_stats_strings[i].offset);
426 }
427
428 return TXGBEVF_NB_XSTATS;
429 }
430
431 static int
txgbevf_dev_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * stats)432 txgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
433 {
434 struct txgbevf_hw_stats *hw_stats = (struct txgbevf_hw_stats *)
435 TXGBE_DEV_STATS(dev);
436 uint32_t i;
437
438 txgbevf_update_stats(dev);
439
440 if (stats == NULL)
441 return -EINVAL;
442
443 stats->ipackets = 0;
444 stats->ibytes = 0;
445 stats->opackets = 0;
446 stats->obytes = 0;
447
448 for (i = 0; i < 8; i++) {
449 stats->ipackets += hw_stats->qp[i].vfgprc;
450 stats->ibytes += hw_stats->qp[i].vfgorc;
451 stats->opackets += hw_stats->qp[i].vfgptc;
452 stats->obytes += hw_stats->qp[i].vfgotc;
453 }
454
455 return 0;
456 }
457
458 static int
txgbevf_dev_stats_reset(struct rte_eth_dev * dev)459 txgbevf_dev_stats_reset(struct rte_eth_dev *dev)
460 {
461 struct txgbevf_hw_stats *hw_stats = (struct txgbevf_hw_stats *)
462 TXGBE_DEV_STATS(dev);
463 uint32_t i;
464
465 /* Sync HW register to the last stats */
466 txgbevf_dev_stats_get(dev, NULL);
467
468 /* reset HW current stats*/
469 for (i = 0; i < 8; i++) {
470 hw_stats->qp[i].vfgprc = 0;
471 hw_stats->qp[i].vfgorc = 0;
472 hw_stats->qp[i].vfgptc = 0;
473 hw_stats->qp[i].vfgotc = 0;
474 }
475
476 return 0;
477 }
478
479 static int
txgbevf_dev_info_get(struct rte_eth_dev * dev,struct rte_eth_dev_info * dev_info)480 txgbevf_dev_info_get(struct rte_eth_dev *dev,
481 struct rte_eth_dev_info *dev_info)
482 {
483 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
484 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
485
486 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
487 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
488 dev_info->min_rx_bufsize = 1024;
489 dev_info->max_rx_pktlen = TXGBE_FRAME_SIZE_MAX;
490 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
491 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
492 dev_info->max_vfs = pci_dev->max_vfs;
493 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
494 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
495 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
496 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
497 dev_info->rx_queue_offload_capa);
498 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
499 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
500 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
501 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128;
502 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
503
504 dev_info->default_rxconf = (struct rte_eth_rxconf) {
505 .rx_thresh = {
506 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
507 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
508 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
509 },
510 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
511 .rx_drop_en = 0,
512 .offloads = 0,
513 };
514
515 dev_info->default_txconf = (struct rte_eth_txconf) {
516 .tx_thresh = {
517 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
518 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
519 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
520 },
521 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
522 .offloads = 0,
523 };
524
525 dev_info->rx_desc_lim = rx_desc_lim;
526 dev_info->tx_desc_lim = tx_desc_lim;
527
528 dev_info->err_handle_mode = RTE_ETH_ERROR_HANDLE_MODE_PASSIVE;
529
530 return 0;
531 }
532
533 static int
txgbevf_dev_link_update(struct rte_eth_dev * dev,int wait_to_complete)534 txgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
535 {
536 return txgbe_dev_link_update_share(dev, wait_to_complete);
537 }
538
539 /*
540 * Virtual Function operations
541 */
542 static void
txgbevf_intr_disable(struct rte_eth_dev * dev)543 txgbevf_intr_disable(struct rte_eth_dev *dev)
544 {
545 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
546 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
547
548 PMD_INIT_FUNC_TRACE();
549
550 /* Clear interrupt mask to stop from interrupts being generated */
551 wr32(hw, TXGBE_VFIMS, TXGBE_VFIMS_MASK);
552
553 txgbe_flush(hw);
554
555 /* Clear mask value. */
556 intr->mask_misc = TXGBE_VFIMS_MASK;
557 }
558
559 static void
txgbevf_intr_enable(struct rte_eth_dev * dev)560 txgbevf_intr_enable(struct rte_eth_dev *dev)
561 {
562 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
563 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
564
565 PMD_INIT_FUNC_TRACE();
566
567 /* VF enable interrupt autoclean */
568 wr32(hw, TXGBE_VFIMC, TXGBE_VFIMC_MASK);
569
570 txgbe_flush(hw);
571
572 intr->mask_misc = 0;
573 }
574
575 static int
txgbevf_dev_configure(struct rte_eth_dev * dev)576 txgbevf_dev_configure(struct rte_eth_dev *dev)
577 {
578 struct rte_eth_conf *conf = &dev->data->dev_conf;
579 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
580
581 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
582 dev->data->port_id);
583
584 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
585 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
586
587 /*
588 * VF has no ability to enable/disable HW CRC
589 * Keep the persistent behavior the same as Host PF
590 */
591 #ifndef RTE_LIBRTE_TXGBE_PF_DISABLE_STRIP_CRC
592 if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
593 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
594 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC;
595 }
596 #else
597 if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) {
598 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
599 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
600 }
601 #endif
602
603 /*
604 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
605 * allocation or vector Rx preconditions we will reset it.
606 */
607 adapter->rx_bulk_alloc_allowed = true;
608 adapter->rx_vec_allowed = true;
609
610 return 0;
611 }
612
613 static int
txgbevf_dev_start(struct rte_eth_dev * dev)614 txgbevf_dev_start(struct rte_eth_dev *dev)
615 {
616 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
617 uint32_t intr_vector = 0;
618 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
619 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
620
621 int err, mask = 0;
622
623 PMD_INIT_FUNC_TRACE();
624
625 /* Stop the link setup handler before resetting the HW. */
626 txgbe_dev_wait_setup_link_complete(dev, 0);
627
628 err = hw->mac.reset_hw(hw);
629 if (err) {
630 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
631 return err;
632 }
633 hw->mac.get_link_status = true;
634 hw->dev_start = true;
635
636 /* negotiate mailbox API version to use with the PF. */
637 txgbevf_negotiate_api(hw);
638
639 txgbevf_dev_tx_init(dev);
640
641 /* This can fail when allocating mbufs for descriptor rings */
642 err = txgbevf_dev_rx_init(dev);
643
644 /**
645 * In this case, reuses the MAC address assigned by VF
646 * initialization.
647 */
648 if (err != 0 && err != TXGBE_ERR_INVALID_MAC_ADDR) {
649 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
650 txgbe_dev_clear_queues(dev);
651 return err;
652 }
653
654 /* Set vfta */
655 txgbevf_set_vfta_all(dev, 1);
656
657 /* Set HW strip */
658 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
659 RTE_ETH_VLAN_EXTEND_MASK;
660 err = txgbevf_vlan_offload_config(dev, mask);
661 if (err) {
662 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
663 txgbe_dev_clear_queues(dev);
664 return err;
665 }
666
667 txgbevf_dev_rxtx_start(dev);
668
669 /* check and configure queue intr-vector mapping */
670 if (rte_intr_cap_multiple(intr_handle) &&
671 dev->data->dev_conf.intr_conf.rxq) {
672 /* According to datasheet, only vector 0/1/2 can be used,
673 * now only one vector is used for Rx queue
674 */
675 intr_vector = 1;
676 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
677 txgbe_dev_clear_queues(dev);
678 return -1;
679 }
680 }
681
682 if (rte_intr_dp_is_en(intr_handle)) {
683 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
684 dev->data->nb_rx_queues)) {
685 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
686 " intr_vec", dev->data->nb_rx_queues);
687 txgbe_dev_clear_queues(dev);
688 return -ENOMEM;
689 }
690 }
691 txgbevf_configure_msix(dev);
692
693 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
694 * is mapped to VFIO vector 0 in eth_txgbevf_dev_init( ).
695 * If previous VFIO interrupt mapping setting in eth_txgbevf_dev_init( )
696 * is not cleared, it will fail when following rte_intr_enable( ) tries
697 * to map Rx queue interrupt to other VFIO vectors.
698 * So clear uio/vfio intr/evevnfd first to avoid failure.
699 */
700 rte_intr_disable(intr_handle);
701
702 rte_intr_enable(intr_handle);
703
704 /* Re-enable interrupt for VF */
705 txgbevf_intr_enable(dev);
706
707 /*
708 * Update link status right before return, because it may
709 * start link configuration process in a separate thread.
710 */
711 txgbevf_dev_link_update(dev, 0);
712
713 hw->adapter_stopped = false;
714
715 return 0;
716 }
717
718 static int
txgbevf_dev_stop(struct rte_eth_dev * dev)719 txgbevf_dev_stop(struct rte_eth_dev *dev)
720 {
721 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
722 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
724 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
725
726 if (hw->adapter_stopped)
727 return 0;
728
729 PMD_INIT_FUNC_TRACE();
730
731 txgbe_dev_wait_setup_link_complete(dev, 0);
732
733 txgbevf_intr_disable(dev);
734
735 hw->adapter_stopped = 1;
736 hw->mac.stop_hw(hw);
737
738 /*
739 * Clear what we set, but we still keep shadow_vfta to
740 * restore after device starts
741 */
742 txgbevf_set_vfta_all(dev, 0);
743
744 /* Clear stored conf */
745 dev->data->scattered_rx = 0;
746
747 txgbe_dev_clear_queues(dev);
748
749 /* Clean datapath event and queue/vec mapping */
750 rte_intr_efd_disable(intr_handle);
751 rte_intr_vec_list_free(intr_handle);
752
753 adapter->rss_reta_updated = 0;
754 hw->dev_start = false;
755
756 return 0;
757 }
758
759 static int
txgbevf_dev_close(struct rte_eth_dev * dev)760 txgbevf_dev_close(struct rte_eth_dev *dev)
761 {
762 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
763 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
764 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
765 int ret;
766
767 PMD_INIT_FUNC_TRACE();
768 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
769 return 0;
770
771 hw->mac.reset_hw(hw);
772
773 ret = txgbevf_dev_stop(dev);
774
775 txgbe_dev_free_queues(dev);
776
777 /**
778 * Remove the VF MAC address ro ensure
779 * that the VF traffic goes to the PF
780 * after stop, close and detach of the VF
781 **/
782 txgbevf_remove_mac_addr(dev, 0);
783
784 dev->rx_pkt_burst = NULL;
785 dev->tx_pkt_burst = NULL;
786
787 /* Disable the interrupts for VF */
788 txgbevf_intr_disable(dev);
789
790 rte_free(dev->data->mac_addrs);
791 dev->data->mac_addrs = NULL;
792
793 rte_intr_disable(intr_handle);
794 rte_intr_callback_unregister(intr_handle,
795 txgbevf_dev_interrupt_handler, dev);
796
797 return ret;
798 }
799
800 /*
801 * Reset VF device
802 */
803 static int
txgbevf_dev_reset(struct rte_eth_dev * dev)804 txgbevf_dev_reset(struct rte_eth_dev *dev)
805 {
806 int ret;
807
808 ret = eth_txgbevf_dev_uninit(dev);
809 if (ret)
810 return ret;
811
812 ret = eth_txgbevf_dev_init(dev);
813
814 return ret;
815 }
816
txgbevf_set_vfta_all(struct rte_eth_dev * dev,bool on)817 static void txgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
818 {
819 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
820 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
821 int i = 0, j = 0, vfta = 0, mask = 1;
822
823 for (i = 0; i < TXGBE_VFTA_SIZE; i++) {
824 vfta = shadow_vfta->vfta[i];
825 if (vfta) {
826 mask = 1;
827 for (j = 0; j < 32; j++) {
828 if (vfta & mask)
829 hw->mac.set_vfta(hw, (i << 5) + j, 0,
830 on, false);
831 mask <<= 1;
832 }
833 }
834 }
835 }
836
837 static int
txgbevf_vlan_filter_set(struct rte_eth_dev * dev,uint16_t vlan_id,int on)838 txgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
839 {
840 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
841 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
842 uint32_t vid_idx = 0;
843 uint32_t vid_bit = 0;
844 int ret = 0;
845
846 PMD_INIT_FUNC_TRACE();
847
848 /* vind is not used in VF driver, set to 0, check txgbe_set_vfta_vf */
849 ret = hw->mac.set_vfta(hw, vlan_id, 0, !!on, false);
850 if (ret) {
851 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
852 return ret;
853 }
854 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
855 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
856
857 /* Save what we set and restore it after device reset */
858 if (on)
859 shadow_vfta->vfta[vid_idx] |= vid_bit;
860 else
861 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
862
863 return 0;
864 }
865
866 static void
txgbevf_vlan_strip_queue_set(struct rte_eth_dev * dev,uint16_t queue,int on)867 txgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
868 {
869 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
870 uint32_t ctrl;
871
872 PMD_INIT_FUNC_TRACE();
873
874 if (queue >= hw->mac.max_rx_queues)
875 return;
876
877 ctrl = rd32(hw, TXGBE_RXCFG(queue));
878 txgbe_dev_save_rx_queue(hw, queue);
879 if (on)
880 ctrl |= TXGBE_RXCFG_VLAN;
881 else
882 ctrl &= ~TXGBE_RXCFG_VLAN;
883 wr32(hw, TXGBE_RXCFG(queue), 0);
884 msec_delay(100);
885 txgbe_dev_store_rx_queue(hw, queue);
886 wr32m(hw, TXGBE_RXCFG(queue),
887 TXGBE_RXCFG_VLAN | TXGBE_RXCFG_ENA, ctrl);
888
889 txgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
890 }
891
892 static int
txgbevf_vlan_offload_config(struct rte_eth_dev * dev,int mask)893 txgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
894 {
895 struct txgbe_rx_queue *rxq;
896 uint16_t i;
897 int on = 0;
898
899 /* VF function only support hw strip feature, others are not support */
900 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
901 for (i = 0; i < dev->data->nb_rx_queues; i++) {
902 rxq = dev->data->rx_queues[i];
903 on = !!(rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP);
904 txgbevf_vlan_strip_queue_set(dev, i, on);
905 }
906 }
907
908 return 0;
909 }
910
911 static int
txgbevf_vlan_offload_set(struct rte_eth_dev * dev,int mask)912 txgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
913 {
914 txgbe_config_vlan_strip_on_all_queues(dev, mask);
915
916 txgbevf_vlan_offload_config(dev, mask);
917
918 return 0;
919 }
920
921 static int
txgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev * dev,uint16_t queue_id)922 txgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
923 {
924 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
925 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
926 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
927 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
928 uint32_t vec = TXGBE_MISC_VEC_ID;
929
930 if (rte_intr_allow_others(intr_handle))
931 vec = TXGBE_RX_VEC_START;
932 intr->mask_misc &= ~(1 << vec);
933 RTE_SET_USED(queue_id);
934 wr32(hw, TXGBE_VFIMC, ~intr->mask_misc);
935
936 rte_intr_enable(intr_handle);
937
938 return 0;
939 }
940
941 static int
txgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev * dev,uint16_t queue_id)942 txgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
943 {
944 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
945 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
947 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
948 uint32_t vec = TXGBE_MISC_VEC_ID;
949
950 if (rte_intr_allow_others(intr_handle))
951 vec = TXGBE_RX_VEC_START;
952 intr->mask_misc |= (1 << vec);
953 RTE_SET_USED(queue_id);
954 wr32(hw, TXGBE_VFIMS, intr->mask_misc);
955
956 return 0;
957 }
958
959 static void
txgbevf_set_ivar_map(struct txgbe_hw * hw,int8_t direction,uint8_t queue,uint8_t msix_vector)960 txgbevf_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
961 uint8_t queue, uint8_t msix_vector)
962 {
963 uint32_t tmp, idx;
964
965 if (direction == -1) {
966 /* other causes */
967 msix_vector |= TXGBE_VFIVAR_VLD;
968 tmp = rd32(hw, TXGBE_VFIVARMISC);
969 tmp &= ~0xFF;
970 tmp |= msix_vector;
971 wr32(hw, TXGBE_VFIVARMISC, tmp);
972 } else {
973 /* rx or tx cause */
974 msix_vector |= TXGBE_VFIVAR_VLD; /* Workaround for ICR lost */
975 idx = ((16 * (queue & 1)) + (8 * direction));
976 tmp = rd32(hw, TXGBE_VFIVAR(queue >> 1));
977 tmp &= ~(0xFF << idx);
978 tmp |= (msix_vector << idx);
979 wr32(hw, TXGBE_VFIVAR(queue >> 1), tmp);
980 }
981 }
982
983 static void
txgbevf_configure_msix(struct rte_eth_dev * dev)984 txgbevf_configure_msix(struct rte_eth_dev *dev)
985 {
986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
987 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
988 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
989 uint32_t q_idx;
990 uint32_t vector_idx = TXGBE_MISC_VEC_ID;
991 uint32_t base = TXGBE_MISC_VEC_ID;
992
993 /* Configure VF other cause ivar */
994 txgbevf_set_ivar_map(hw, -1, 1, vector_idx);
995
996 /* won't configure msix register if no mapping is done
997 * between intr vector and event fd.
998 */
999 if (!rte_intr_dp_is_en(intr_handle))
1000 return;
1001
1002 if (rte_intr_allow_others(intr_handle)) {
1003 base = TXGBE_RX_VEC_START;
1004 vector_idx = TXGBE_RX_VEC_START;
1005 }
1006
1007 /* Configure all RX queues of VF */
1008 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
1009 /* Force all queue use vector 0,
1010 * as TXGBE_VF_MAXMSIVECTOR = 1
1011 */
1012 txgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
1013 rte_intr_vec_list_index_set(intr_handle, q_idx,
1014 vector_idx);
1015 if (vector_idx < base + rte_intr_nb_efd_get(intr_handle)
1016 - 1)
1017 vector_idx++;
1018 }
1019
1020 /* As RX queue setting above show, all queues use the vector 0.
1021 * Set only the ITR value of TXGBE_MISC_VEC_ID.
1022 */
1023 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
1024 TXGBE_ITR_IVAL(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1025 | TXGBE_ITR_WRDSA);
1026 }
1027
1028 static int
txgbevf_add_mac_addr(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr,__rte_unused uint32_t index,__rte_unused uint32_t pool)1029 txgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1030 __rte_unused uint32_t index,
1031 __rte_unused uint32_t pool)
1032 {
1033 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1034 int err;
1035
1036 /*
1037 * On a VF, adding again the same MAC addr is not an idempotent
1038 * operation. Trap this case to avoid exhausting the [very limited]
1039 * set of PF resources used to store VF MAC addresses.
1040 */
1041 if (memcmp(hw->mac.perm_addr, mac_addr,
1042 sizeof(struct rte_ether_addr)) == 0)
1043 return -1;
1044 err = txgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
1045 if (err != 0)
1046 PMD_DRV_LOG(ERR, "Unable to add MAC address "
1047 RTE_ETHER_ADDR_PRT_FMT " - err=%d",
1048 RTE_ETHER_ADDR_BYTES(mac_addr), err);
1049 return err;
1050 }
1051
1052 static void
txgbevf_remove_mac_addr(struct rte_eth_dev * dev,uint32_t index)1053 txgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
1054 {
1055 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1056 struct rte_ether_addr *perm_addr =
1057 (struct rte_ether_addr *)hw->mac.perm_addr;
1058 struct rte_ether_addr *mac_addr;
1059 uint32_t i;
1060 int err;
1061
1062 /*
1063 * The TXGBE_VF_SET_MACVLAN command of the txgbe-pf driver does
1064 * not support the deletion of a given MAC address.
1065 * Instead, it imposes to delete all MAC addresses, then to add again
1066 * all MAC addresses with the exception of the one to be deleted.
1067 */
1068 (void)txgbevf_set_uc_addr_vf(hw, 0, NULL);
1069
1070 /*
1071 * Add again all MAC addresses, with the exception of the deleted one
1072 * and of the permanent MAC address.
1073 */
1074 for (i = 0, mac_addr = dev->data->mac_addrs;
1075 i < hw->mac.num_rar_entries; i++, mac_addr++) {
1076 /* Skip the deleted MAC address */
1077 if (i == index)
1078 continue;
1079 /* Skip NULL MAC addresses */
1080 if (rte_is_zero_ether_addr(mac_addr))
1081 continue;
1082 /* Skip the permanent MAC address */
1083 if (memcmp(perm_addr, mac_addr,
1084 sizeof(struct rte_ether_addr)) == 0)
1085 continue;
1086 err = txgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
1087 if (err != 0)
1088 PMD_DRV_LOG(ERR,
1089 "Adding again MAC address "
1090 RTE_ETHER_ADDR_PRT_FMT " failed "
1091 "err=%d",
1092 RTE_ETHER_ADDR_BYTES(mac_addr), err);
1093 }
1094 }
1095
1096 static int
txgbevf_set_default_mac_addr(struct rte_eth_dev * dev,struct rte_ether_addr * addr)1097 txgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
1098 struct rte_ether_addr *addr)
1099 {
1100 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1101
1102 hw->mac.set_rar(hw, 0, (void *)addr, 0, 0);
1103
1104 return 0;
1105 }
1106
1107 static int
txgbevf_dev_set_mtu(struct rte_eth_dev * dev,uint16_t mtu)1108 txgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1109 {
1110 struct txgbe_hw *hw;
1111 uint32_t max_frame = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
1112 struct rte_eth_dev_data *dev_data = dev->data;
1113
1114 hw = TXGBE_DEV_HW(dev);
1115
1116 if (mtu < RTE_ETHER_MIN_MTU ||
1117 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
1118 return -EINVAL;
1119
1120 /* If device is started, refuse mtu that requires the support of
1121 * scattered packets when this feature has not been enabled before.
1122 */
1123 if (dev_data->dev_started && !dev_data->scattered_rx &&
1124 (max_frame + 2 * RTE_VLAN_HLEN >
1125 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1126 PMD_INIT_LOG(ERR, "Stop port first.");
1127 return -EINVAL;
1128 }
1129
1130 /*
1131 * When supported by the underlying PF driver, use the TXGBE_VF_SET_MTU
1132 * request of the version 2.0 of the mailbox API.
1133 * For now, use the TXGBE_VF_SET_LPE request of the version 1.0
1134 * of the mailbox API.
1135 */
1136 if (txgbevf_rlpml_set_vf(hw, max_frame))
1137 return -EINVAL;
1138
1139 return 0;
1140 }
1141
1142 static int
txgbevf_get_reg_length(struct rte_eth_dev * dev __rte_unused)1143 txgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
1144 {
1145 int count = 0;
1146 int g_ind = 0;
1147 const struct reg_info *reg_group;
1148
1149 while ((reg_group = txgbevf_regs[g_ind++]))
1150 count += txgbe_regs_group_count(reg_group);
1151
1152 return count;
1153 }
1154
1155 static int
txgbevf_get_regs(struct rte_eth_dev * dev,struct rte_dev_reg_info * regs)1156 txgbevf_get_regs(struct rte_eth_dev *dev,
1157 struct rte_dev_reg_info *regs)
1158 {
1159 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1160 uint32_t *data = regs->data;
1161 int g_ind = 0;
1162 int count = 0;
1163 const struct reg_info *reg_group;
1164
1165 if (data == NULL) {
1166 regs->length = txgbevf_get_reg_length(dev);
1167 regs->width = sizeof(uint32_t);
1168 return 0;
1169 }
1170
1171 /* Support only full register dump */
1172 if (regs->length == 0 ||
1173 regs->length == (uint32_t)txgbevf_get_reg_length(dev)) {
1174 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
1175 hw->device_id;
1176 while ((reg_group = txgbevf_regs[g_ind++]))
1177 count += txgbe_read_regs_group(dev, &data[count],
1178 reg_group);
1179 return 0;
1180 }
1181
1182 return -ENOTSUP;
1183 }
1184
1185 static int
txgbevf_dev_promiscuous_enable(struct rte_eth_dev * dev)1186 txgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
1187 {
1188 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1189 int ret;
1190
1191 switch (hw->mac.update_xcast_mode(hw, TXGBEVF_XCAST_MODE_PROMISC)) {
1192 case 0:
1193 ret = 0;
1194 break;
1195 case TXGBE_ERR_FEATURE_NOT_SUPPORTED:
1196 ret = -ENOTSUP;
1197 break;
1198 default:
1199 ret = -EAGAIN;
1200 break;
1201 }
1202
1203 return ret;
1204 }
1205
1206 static int
txgbevf_dev_promiscuous_disable(struct rte_eth_dev * dev)1207 txgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
1208 {
1209 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1210 int mode = TXGBEVF_XCAST_MODE_NONE;
1211 int ret;
1212
1213 if (dev->data->all_multicast)
1214 mode = TXGBEVF_XCAST_MODE_ALLMULTI;
1215
1216 switch (hw->mac.update_xcast_mode(hw, mode)) {
1217 case 0:
1218 ret = 0;
1219 break;
1220 case TXGBE_ERR_FEATURE_NOT_SUPPORTED:
1221 ret = -ENOTSUP;
1222 break;
1223 default:
1224 ret = -EAGAIN;
1225 break;
1226 }
1227
1228 return ret;
1229 }
1230
1231 static int
txgbevf_dev_allmulticast_enable(struct rte_eth_dev * dev)1232 txgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
1233 {
1234 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1235 int ret;
1236
1237 if (dev->data->promiscuous)
1238 return 0;
1239
1240 switch (hw->mac.update_xcast_mode(hw, TXGBEVF_XCAST_MODE_ALLMULTI)) {
1241 case 0:
1242 ret = 0;
1243 break;
1244 case TXGBE_ERR_FEATURE_NOT_SUPPORTED:
1245 ret = -ENOTSUP;
1246 break;
1247 default:
1248 ret = -EAGAIN;
1249 break;
1250 }
1251
1252 return ret;
1253 }
1254
1255 static int
txgbevf_dev_allmulticast_disable(struct rte_eth_dev * dev)1256 txgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
1257 {
1258 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1259 int ret;
1260
1261 if (dev->data->promiscuous)
1262 return 0;
1263
1264 switch (hw->mac.update_xcast_mode(hw, TXGBEVF_XCAST_MODE_MULTI)) {
1265 case 0:
1266 ret = 0;
1267 break;
1268 case TXGBE_ERR_FEATURE_NOT_SUPPORTED:
1269 ret = -ENOTSUP;
1270 break;
1271 default:
1272 ret = -EAGAIN;
1273 break;
1274 }
1275
1276 return ret;
1277 }
1278
txgbevf_mbx_process(struct rte_eth_dev * dev)1279 static void txgbevf_mbx_process(struct rte_eth_dev *dev)
1280 {
1281 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1282 u32 in_msg = 0;
1283
1284 /* peek the message first */
1285 in_msg = rd32(hw, TXGBE_VFMBX);
1286
1287 /* PF reset VF event */
1288 if (in_msg == TXGBE_PF_CONTROL_MSG) {
1289 /* dummy mbx read to ack pf */
1290 if (txgbe_read_mbx(hw, &in_msg, 1, 0))
1291 return;
1292 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1293 NULL);
1294 }
1295 }
1296
1297 static int
txgbevf_dev_interrupt_get_status(struct rte_eth_dev * dev)1298 txgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
1299 {
1300 uint32_t eicr;
1301 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1302 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1303 txgbevf_intr_disable(dev);
1304
1305 /* read-on-clear nic registers here */
1306 eicr = rd32(hw, TXGBE_VFICR);
1307 intr->flags = 0;
1308
1309 /* only one misc vector supported - mailbox */
1310 eicr &= TXGBE_VFICR_MASK;
1311 /* Workaround for ICR lost */
1312 intr->flags |= TXGBE_FLAG_MAILBOX;
1313
1314 /* To avoid compiler warnings set eicr to used. */
1315 RTE_SET_USED(eicr);
1316
1317 return 0;
1318 }
1319
1320 static int
txgbevf_dev_interrupt_action(struct rte_eth_dev * dev)1321 txgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
1322 {
1323 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1324
1325 if (intr->flags & TXGBE_FLAG_MAILBOX) {
1326 txgbevf_mbx_process(dev);
1327 intr->flags &= ~TXGBE_FLAG_MAILBOX;
1328 }
1329
1330 txgbevf_intr_enable(dev);
1331
1332 return 0;
1333 }
1334
1335 static void
txgbevf_dev_interrupt_handler(void * param)1336 txgbevf_dev_interrupt_handler(void *param)
1337 {
1338 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1339
1340 txgbevf_dev_interrupt_get_status(dev);
1341 txgbevf_dev_interrupt_action(dev);
1342 }
1343
1344 /*
1345 * dev_ops for virtual function, bare necessities for basic vf
1346 * operation have been implemented
1347 */
1348 static const struct eth_dev_ops txgbevf_eth_dev_ops = {
1349 .dev_configure = txgbevf_dev_configure,
1350 .dev_start = txgbevf_dev_start,
1351 .dev_stop = txgbevf_dev_stop,
1352 .link_update = txgbevf_dev_link_update,
1353 .stats_get = txgbevf_dev_stats_get,
1354 .xstats_get = txgbevf_dev_xstats_get,
1355 .stats_reset = txgbevf_dev_stats_reset,
1356 .xstats_reset = txgbevf_dev_stats_reset,
1357 .xstats_get_names = txgbevf_dev_xstats_get_names,
1358 .dev_close = txgbevf_dev_close,
1359 .dev_reset = txgbevf_dev_reset,
1360 .promiscuous_enable = txgbevf_dev_promiscuous_enable,
1361 .promiscuous_disable = txgbevf_dev_promiscuous_disable,
1362 .allmulticast_enable = txgbevf_dev_allmulticast_enable,
1363 .allmulticast_disable = txgbevf_dev_allmulticast_disable,
1364 .dev_infos_get = txgbevf_dev_info_get,
1365 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
1366 .mtu_set = txgbevf_dev_set_mtu,
1367 .vlan_filter_set = txgbevf_vlan_filter_set,
1368 .vlan_strip_queue_set = txgbevf_vlan_strip_queue_set,
1369 .vlan_offload_set = txgbevf_vlan_offload_set,
1370 .rx_queue_setup = txgbe_dev_rx_queue_setup,
1371 .rx_queue_release = txgbe_dev_rx_queue_release,
1372 .tx_queue_setup = txgbe_dev_tx_queue_setup,
1373 .tx_queue_release = txgbe_dev_tx_queue_release,
1374 .rx_queue_intr_enable = txgbevf_dev_rx_queue_intr_enable,
1375 .rx_queue_intr_disable = txgbevf_dev_rx_queue_intr_disable,
1376 .mac_addr_add = txgbevf_add_mac_addr,
1377 .mac_addr_remove = txgbevf_remove_mac_addr,
1378 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
1379 .rxq_info_get = txgbe_rxq_info_get,
1380 .txq_info_get = txgbe_txq_info_get,
1381 .mac_addr_set = txgbevf_set_default_mac_addr,
1382 .get_reg = txgbevf_get_regs,
1383 .reta_update = txgbe_dev_rss_reta_update,
1384 .reta_query = txgbe_dev_rss_reta_query,
1385 .rss_hash_update = txgbe_dev_rss_hash_update,
1386 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
1387 .tx_done_cleanup = txgbe_dev_tx_done_cleanup,
1388 };
1389
1390 RTE_PMD_REGISTER_PCI(net_txgbe_vf, rte_txgbevf_pmd);
1391 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe_vf, pci_id_txgbevf_map);
1392 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe_vf, "* igb_uio | vfio-pci");
1393