1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2007-2013 Broadcom Corporation. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Copyright (c) 2014-2018 Cavium Inc. 9 * All rights reserved. 10 * www.cavium.com 11 */ 12 13 #ifndef ECORE_HSI_H 14 #define ECORE_HSI_H 15 16 #include "ecore_fw_defs.h" 17 #include "ecore_mfw_req.h" 18 #include "bnx2x_osal.h" 19 20 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 21 22 struct license_key { 23 uint32_t reserved[6]; 24 25 uint32_t max_iscsi_conn; 26 #define ECORE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 27 #define ECORE_MAX_ISCSI_TRGT_CONN_SHIFT 0 28 #define ECORE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 29 #define ECORE_MAX_ISCSI_INIT_CONN_SHIFT 16 30 31 uint32_t reserved_a; 32 33 uint32_t max_fcoe_conn; 34 #define ECORE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 35 #define ECORE_MAX_FCOE_TRGT_CONN_SHIFT 0 36 #define ECORE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 37 #define ECORE_MAX_FCOE_INIT_CONN_SHIFT 16 38 39 uint32_t reserved_b[4]; 40 }; 41 42 43 44 /**************************************************************************** 45 * Shared HW configuration * 46 ****************************************************************************/ 47 #define PIN_CFG_NA 0x00000000 48 #define PIN_CFG_GPIO0_P0 0x00000001 49 #define PIN_CFG_GPIO1_P0 0x00000002 50 #define PIN_CFG_GPIO2_P0 0x00000003 51 #define PIN_CFG_GPIO3_P0 0x00000004 52 #define PIN_CFG_GPIO0_P1 0x00000005 53 #define PIN_CFG_GPIO1_P1 0x00000006 54 #define PIN_CFG_GPIO2_P1 0x00000007 55 #define PIN_CFG_GPIO3_P1 0x00000008 56 #define PIN_CFG_EPIO0 0x00000009 57 #define PIN_CFG_EPIO1 0x0000000a 58 #define PIN_CFG_EPIO2 0x0000000b 59 #define PIN_CFG_EPIO3 0x0000000c 60 #define PIN_CFG_EPIO4 0x0000000d 61 #define PIN_CFG_EPIO5 0x0000000e 62 #define PIN_CFG_EPIO6 0x0000000f 63 #define PIN_CFG_EPIO7 0x00000010 64 #define PIN_CFG_EPIO8 0x00000011 65 #define PIN_CFG_EPIO9 0x00000012 66 #define PIN_CFG_EPIO10 0x00000013 67 #define PIN_CFG_EPIO11 0x00000014 68 #define PIN_CFG_EPIO12 0x00000015 69 #define PIN_CFG_EPIO13 0x00000016 70 #define PIN_CFG_EPIO14 0x00000017 71 #define PIN_CFG_EPIO15 0x00000018 72 #define PIN_CFG_EPIO16 0x00000019 73 #define PIN_CFG_EPIO17 0x0000001a 74 #define PIN_CFG_EPIO18 0x0000001b 75 #define PIN_CFG_EPIO19 0x0000001c 76 #define PIN_CFG_EPIO20 0x0000001d 77 #define PIN_CFG_EPIO21 0x0000001e 78 #define PIN_CFG_EPIO22 0x0000001f 79 #define PIN_CFG_EPIO23 0x00000020 80 #define PIN_CFG_EPIO24 0x00000021 81 #define PIN_CFG_EPIO25 0x00000022 82 #define PIN_CFG_EPIO26 0x00000023 83 #define PIN_CFG_EPIO27 0x00000024 84 #define PIN_CFG_EPIO28 0x00000025 85 #define PIN_CFG_EPIO29 0x00000026 86 #define PIN_CFG_EPIO30 0x00000027 87 #define PIN_CFG_EPIO31 0x00000028 88 89 /* EPIO definition */ 90 #define EPIO_CFG_NA 0x00000000 91 #define EPIO_CFG_EPIO0 0x00000001 92 #define EPIO_CFG_EPIO1 0x00000002 93 #define EPIO_CFG_EPIO2 0x00000003 94 #define EPIO_CFG_EPIO3 0x00000004 95 #define EPIO_CFG_EPIO4 0x00000005 96 #define EPIO_CFG_EPIO5 0x00000006 97 #define EPIO_CFG_EPIO6 0x00000007 98 #define EPIO_CFG_EPIO7 0x00000008 99 #define EPIO_CFG_EPIO8 0x00000009 100 #define EPIO_CFG_EPIO9 0x0000000a 101 #define EPIO_CFG_EPIO10 0x0000000b 102 #define EPIO_CFG_EPIO11 0x0000000c 103 #define EPIO_CFG_EPIO12 0x0000000d 104 #define EPIO_CFG_EPIO13 0x0000000e 105 #define EPIO_CFG_EPIO14 0x0000000f 106 #define EPIO_CFG_EPIO15 0x00000010 107 #define EPIO_CFG_EPIO16 0x00000011 108 #define EPIO_CFG_EPIO17 0x00000012 109 #define EPIO_CFG_EPIO18 0x00000013 110 #define EPIO_CFG_EPIO19 0x00000014 111 #define EPIO_CFG_EPIO20 0x00000015 112 #define EPIO_CFG_EPIO21 0x00000016 113 #define EPIO_CFG_EPIO22 0x00000017 114 #define EPIO_CFG_EPIO23 0x00000018 115 #define EPIO_CFG_EPIO24 0x00000019 116 #define EPIO_CFG_EPIO25 0x0000001a 117 #define EPIO_CFG_EPIO26 0x0000001b 118 #define EPIO_CFG_EPIO27 0x0000001c 119 #define EPIO_CFG_EPIO28 0x0000001d 120 #define EPIO_CFG_EPIO29 0x0000001e 121 #define EPIO_CFG_EPIO30 0x0000001f 122 #define EPIO_CFG_EPIO31 0x00000020 123 124 struct mac_addr { 125 uint32_t upper; 126 uint32_t lower; 127 }; 128 129 130 struct shared_hw_cfg { /* NVRAM Offset */ 131 /* Up to 16 bytes of NULL-terminated string */ 132 uint8_t part_num[16]; /* 0x104 */ 133 134 uint32_t config; /* 0x114 */ 135 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 136 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 137 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 138 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 139 140 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 141 142 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 143 144 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 145 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 146 147 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 148 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 149 /* Whatever MFW found in NVM 150 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 151 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 152 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 153 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 154 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 155 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 156 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 158 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 159 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 160 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 161 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 162 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 163 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 164 165 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 166 backwards compatibility, value of 0 is disabling this feature. 167 That means that though 0 is a valid value, it cannot be 168 configured. */ 169 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 170 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 171 172 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 173 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 174 #define SHARED_HW_CFG_LED_MAC1 0x00000000 175 #define SHARED_HW_CFG_LED_PHY1 0x00010000 176 #define SHARED_HW_CFG_LED_PHY2 0x00020000 177 #define SHARED_HW_CFG_LED_PHY3 0x00030000 178 #define SHARED_HW_CFG_LED_MAC2 0x00040000 179 #define SHARED_HW_CFG_LED_PHY4 0x00050000 180 #define SHARED_HW_CFG_LED_PHY5 0x00060000 181 #define SHARED_HW_CFG_LED_PHY6 0x00070000 182 #define SHARED_HW_CFG_LED_MAC3 0x00080000 183 #define SHARED_HW_CFG_LED_PHY7 0x00090000 184 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 185 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 186 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 187 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 188 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 189 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 190 191 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 192 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 193 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 194 195 #define SHARED_HW_CFG_ATC_MASK 0x80000000 196 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 197 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 198 199 uint32_t config2; /* 0x118 */ 200 201 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 202 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 203 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 204 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 205 206 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 207 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 208 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 209 210 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 211 212 213 /* Output low when PERST is asserted */ 214 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 215 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 216 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 217 218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 221 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 224 225 /* The fan failure mechanism is usually related to the PHY type 226 since the power consumption of the board is determined by the PHY. 227 Currently, fan is required for most designs with SFX7101, BNX2X8727 228 and BNX2X8481. If a fan is not required for a board which uses one 229 of those PHYs, this field should be set to "Disabled". If a fan is 230 required for a different PHY type, this option should be set to 231 "Enabled". The fan failure indication is expected on SPIO5 */ 232 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 233 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 234 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 235 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 236 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 237 238 /* ASPM Power Management support */ 239 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 240 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 242 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 243 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 245 246 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 247 tl_control_0 (register 0x2800) */ 248 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 249 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 250 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 251 252 253 /* Set the MDC/MDIO access for the first external phy */ 254 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 255 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 256 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 257 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 258 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 259 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 260 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 261 262 /* Set the MDC/MDIO access for the second external phy */ 263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 270 271 /* Max number of PF MSIX vectors */ 272 uint32_t config_3; /* 0x11C */ 273 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 274 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 275 276 /* This field extends the mf mode chosen in nvm cfg #73 (as we ran 277 * out of bits) 278 */ 279 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 280 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 281 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 282 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 283 284 uint32_t ump_nc_si_config; /* 0x120 */ 285 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 286 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 287 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 288 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 289 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 290 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 291 292 /* Reserved bits: 226-230 */ 293 294 /* The output pin template BSC_SEL which selects the I2C for this 295 port in the I2C Mux */ 296 uint32_t board; /* 0x124 */ 297 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 298 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 299 300 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 301 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 302 /* Use the PIN_CFG_XXX defines on top */ 303 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 304 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 305 306 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 307 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 308 309 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 310 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 311 312 uint32_t wc_lane_config; /* 0x128 */ 313 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 314 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 315 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 316 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 317 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 318 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 319 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 320 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 321 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 322 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 325 326 /* TX lane Polarity swap */ 327 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 328 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 329 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 330 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 331 /* TX lane Polarity swap */ 332 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 333 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 334 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 335 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 336 337 /* Selects the port layout of the board */ 338 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 339 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 340 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 341 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 342 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 343 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 344 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000 347 }; 348 349 350 /**************************************************************************** 351 * Port HW configuration * 352 ****************************************************************************/ 353 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 354 355 uint32_t pci_id; 356 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 357 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 358 359 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 360 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 361 362 uint32_t pci_sub_id; 363 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 364 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 365 366 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 367 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 368 369 uint32_t power_dissipated; 370 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 371 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 372 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 373 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 374 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 375 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 376 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 377 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 378 379 uint32_t power_consumed; 380 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 381 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 382 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 383 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 384 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 385 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 386 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 387 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 388 389 uint32_t mac_upper; 390 uint32_t mac_lower; /* 0x140 */ 391 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 392 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 393 394 395 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 396 uint32_t iscsi_mac_lower; 397 398 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 399 uint32_t rdma_mac_lower; 400 401 uint32_t serdes_config; 402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 403 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 404 405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 406 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 407 408 409 /* Default values: 2P-64, 4P-32 */ 410 uint32_t reserved; 411 412 uint32_t vf_config; /* 0x15C */ 413 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 414 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 415 416 uint32_t mf_pci_id; /* 0x160 */ 417 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 418 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 419 420 /* Controls the TX laser of the SFP+ module */ 421 uint32_t sfp_ctrl; /* 0x164 */ 422 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 423 #define PORT_HW_CFG_TX_LASER_SHIFT 0 424 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 425 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 426 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 427 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 428 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 429 430 /* Controls the fault module LED of the SFP+ */ 431 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 432 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 433 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 434 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 435 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 436 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 437 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 438 439 /* The output pin TX_DIS that controls the TX laser of the SFP+ 440 module. Use the PIN_CFG_XXX defines on top */ 441 uint32_t e3_sfp_ctrl; /* 0x168 */ 442 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 443 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 444 445 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 446 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 448 449 /* The input pin MOD_ABS that indicates whether SFP+ module is 450 present or not. Use the PIN_CFG_XXX defines on top */ 451 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 452 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 453 454 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 457 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 458 459 /* 460 * The input pin which signals module transmit fault. Use the 461 * PIN_CFG_XXX defines on top 462 */ 463 uint32_t e3_cmn_pin_cfg; /* 0x16C */ 464 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 465 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 466 467 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 468 top */ 469 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 470 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 471 472 /* 473 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 474 * defines on top 475 */ 476 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 477 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 478 479 /* The output pin values BSC_SEL which selects the I2C for this port 480 in the I2C Mux */ 481 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 482 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 483 484 485 /* 486 * The input pin I_FAULT which indicate over-current has occurred. 487 * Use the PIN_CFG_XXX defines on top 488 */ 489 uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 490 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 491 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 492 493 /* pause on host ring */ 494 uint32_t generic_features; /* 0x174 */ 495 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 496 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 497 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 498 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 499 500 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 501 * LOM recommended and tested value is 0xBEB2. Using a different 502 * value means using a value not tested by BRCM 503 */ 504 uint32_t sfi_tap_values; /* 0x178 */ 505 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 506 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 507 508 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 509 * value is 0x2. LOM recommended and tested value is 0x2. Using a 510 * different value means using a value not tested by BRCM 511 */ 512 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 513 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 514 /* Set non-default values for TXFIR in SFP mode. */ 515 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000 516 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20 517 518 /* Set non-default values for IPREDRIVER in SFP mode. */ 519 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000 520 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24 521 522 /* Set non-default values for POST2 in SFP mode. */ 523 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000 524 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28 525 526 uint32_t reserved0[5]; /* 0x17c */ 527 528 uint32_t aeu_int_mask; /* 0x190 */ 529 530 uint32_t media_type; /* 0x194 */ 531 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 532 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 533 534 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 535 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 536 537 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 538 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 539 540 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 541 (not direct mode), those values will not take effect on the 4 XGXS 542 lanes. For some external PHYs (such as 8706 and 8726) the values 543 will be used to configure the external PHY in those cases, not 544 all 4 values are needed. */ 545 uint16_t xgxs_config_rx[4]; /* 0x198 */ 546 uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 547 548 549 /* For storing FCOE mac on shared memory */ 550 uint32_t fcoe_fip_mac_upper; 551 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 552 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 553 uint32_t fcoe_fip_mac_lower; 554 555 uint32_t fcoe_wwn_port_name_upper; 556 uint32_t fcoe_wwn_port_name_lower; 557 558 uint32_t fcoe_wwn_node_name_upper; 559 uint32_t fcoe_wwn_node_name_lower; 560 561 /* wwpn for npiv enabled */ 562 uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 563 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 564 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 565 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 566 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 567 568 /* wwpn for npiv valid addresses */ 569 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 570 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 571 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 572 573 struct mac_addr wwpn_for_niv_macs[16]; 574 575 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 576 uint32_t Reserved1[14]; 577 578 uint32_t pf_allocation; /* 0x280 */ 579 /* number of vfs per PF, if 0 - sriov disabled */ 580 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 581 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 582 583 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 584 84833 only */ 585 uint32_t xgbt_phy_cfg; /* 0x284 */ 586 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 587 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 588 589 uint32_t default_cfg; /* 0x288 */ 590 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 591 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 592 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 593 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 594 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 595 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 596 597 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 598 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 599 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 600 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 601 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 602 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 603 604 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 605 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 606 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 607 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 608 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 609 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 610 611 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 612 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 613 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 614 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 615 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 616 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 617 618 /* When KR link is required to be set to force which is not 619 KR-compliant, this parameter determine what is the trigger for it. 620 When GPIO is selected, low input will force the speed. Currently 621 default speed is 1G. In the future, it may be widen to select the 622 forced speed in with another parameter. Note when force-1G is 623 enabled, it override option 56: Link Speed option. */ 624 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 625 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 626 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 627 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 628 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 629 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 630 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 631 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 632 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 633 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 634 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 635 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 636 /* Enable to determine with which GPIO to reset the external phy */ 637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 639 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 640 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 641 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 642 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 643 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 644 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 645 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 646 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 647 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 648 649 /* Enable BAM on KR */ 650 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 651 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 652 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 653 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 654 655 /* Enable Common Mode Sense */ 656 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 657 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 658 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 659 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 660 661 /* Determine the Serdes electrical interface */ 662 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 663 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 664 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 665 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 666 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 667 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 668 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 669 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 670 671 /* SFP+ main TAP and post TAP volumes */ 672 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 673 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 674 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 675 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 676 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 677 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 678 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 679 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 680 681 uint32_t speed_capability_mask2; /* 0x28C */ 682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 685 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 686 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 687 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 688 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 689 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 690 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 691 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 692 693 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 694 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 703 704 705 /* In the case where two media types (e.g. copper and fiber) are 706 present and electrically active at the same time, PHY Selection 707 will determine which of the two PHYs will be designated as the 708 Active PHY and used for a connection to the network. */ 709 uint32_t multi_phy_config; /* 0x290 */ 710 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 711 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 712 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 713 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 714 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 715 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 716 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 717 718 /* When enabled, all second phy nvram parameters will be swapped 719 with the first phy parameters */ 720 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 721 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 722 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 723 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 724 725 726 /* Address of the second external phy */ 727 uint32_t external_phy_config2; /* 0x294 */ 728 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 729 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 730 731 /* The second XGXS external PHY type */ 732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8071 0x00000100 736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8072 0x00000200 737 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8073 0x00000300 738 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8705 0x00000400 739 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8706 0x00000500 740 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8726 0x00000600 741 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8481 0x00000700 742 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 743 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727 0x00000900 744 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727_NOC 0x00000a00 745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84823 0x00000b00 746 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54640 0x00000c00 747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84833 0x00000d00 748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE 0x00000e00 749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00 750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000 751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100 752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84858 0x00001200 753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 755 756 757 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 758 8706, 8726 and 8727) not all 4 values are needed. */ 759 uint16_t xgxs_config2_rx[4]; /* 0x296 */ 760 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 761 762 uint32_t lane_config; 763 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 764 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 765 /* AN and forced */ 766 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 767 /* forced only */ 768 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 769 /* forced only */ 770 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 771 /* forced only */ 772 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 773 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 774 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 775 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 776 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 777 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 778 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 779 780 /* Indicate whether to swap the external phy polarity */ 781 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 782 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 783 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 784 785 786 uint32_t external_phy_config; 787 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 788 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 789 790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8071 0x00000100 794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8072 0x00000200 795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073 0x00000300 796 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705 0x00000400 797 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706 0x00000500 798 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726 0x00000600 799 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481 0x00000700 800 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 801 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727 0x00000900 802 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC 0x00000a00 803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823 0x00000b00 804 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54640 0x00000c00 805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833 0x00000d00 806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE 0x00000e00 807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00 808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000 809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100 810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200 811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 813 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 814 815 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 816 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 817 818 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 819 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 820 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 821 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BNX2X5482 0x01000000 822 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 823 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 824 825 uint32_t speed_capability_mask; 826 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 827 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 828 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 829 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 830 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 831 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 832 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 833 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 834 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 835 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 836 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 837 838 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 839 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 840 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 841 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 842 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 843 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 844 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 845 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 846 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 847 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 848 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 849 850 /* A place to hold the original MAC address as a backup */ 851 uint32_t backup_mac_upper; /* 0x2B4 */ 852 uint32_t backup_mac_lower; /* 0x2B8 */ 853 854 }; 855 856 857 /**************************************************************************** 858 * Shared Feature configuration * 859 ****************************************************************************/ 860 struct shared_feat_cfg { /* NVRAM Offset */ 861 862 uint32_t config; /* 0x450 */ 863 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 864 865 /* Use NVRAM values instead of HW default values */ 866 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 867 0x00000002 868 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 869 0x00000000 870 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 871 0x00000002 872 873 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 874 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 875 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 876 877 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 878 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 879 880 /* Override the OTP back to single function mode. When using GPIO, 881 high means only SF, 0 is according to CLP configuration */ 882 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 883 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 884 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 885 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 886 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 887 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 888 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 889 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 890 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 891 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 892 893 /* Act as if the FCoE license is invalid */ 894 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 895 896 /* Force FLR capability to all ports */ 897 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 898 899 /* Act as if the iSCSI license is invalid */ 900 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 901 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 902 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 903 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 904 905 /* The interval in seconds between sending LLDP packets. Set to zero 906 to disable the feature */ 907 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 908 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 909 910 /* The assigned device type ID for LLDP usage */ 911 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 912 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 913 914 }; 915 916 917 /**************************************************************************** 918 * Port Feature configuration * 919 ****************************************************************************/ 920 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 921 922 uint32_t config; 923 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 924 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 925 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 926 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 927 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 928 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 929 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 930 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 931 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 932 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 933 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 934 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 935 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 936 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 937 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 938 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 939 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 940 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 941 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 942 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 943 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 944 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 945 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 946 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 947 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 948 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 949 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 950 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 951 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 952 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 953 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 954 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 955 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 956 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 957 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 958 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 959 960 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 961 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 962 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 963 964 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 965 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 966 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 967 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 968 969 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 970 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 971 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 972 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 973 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 974 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 975 976 #define PORT_FEAT_CFG_DCBX_SEL_MASK 0x00003000 977 #define PORT_FEAT_CFG_DCBX_SEL_SHIFT 12 978 #define PORT_FEAT_CFG_DCBX_SEL_CEE 0x00000000 979 #define PORT_FEAT_CFG_DCBX_SEL_IEEE 0x00001000 980 #define PORT_FEAT_CFG_DCBX_SEL_AUTO 0x00002000 981 982 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 983 #define PORT_FEATURE_EN_SIZE_SHIFT 24 984 #define PORT_FEATURE_WOL_ENABLED 0x01000000 985 #define PORT_FEATURE_MBA_ENABLED 0x02000000 986 #define PORT_FEATURE_MFW_ENABLED 0x04000000 987 988 /* Advertise expansion ROM even if MBA is disabled */ 989 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 990 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 991 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 992 993 /* Check the optic vendor via i2c against a list of approved modules 994 in a separate nvram image */ 995 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 996 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 997 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 998 0x00000000 999 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 1000 0x20000000 1001 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 1002 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 1003 1004 uint32_t wol_config; 1005 /* Default is used when driver sets to "auto" mode */ 1006 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 1007 1008 uint32_t mba_config; 1009 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 1010 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 1011 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 1012 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 1013 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 1014 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 1015 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 1016 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1017 1018 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1019 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1020 1021 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1022 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1023 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1024 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1025 1026 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1027 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1028 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1029 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1030 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1031 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1032 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1033 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1034 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1035 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1036 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1037 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1038 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1039 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1040 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1041 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1042 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1043 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1044 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1045 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1046 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1047 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1048 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1049 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1050 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1051 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1052 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1053 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1054 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1055 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1056 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1057 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1058 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1059 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1060 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1061 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1062 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1063 1064 /* Secondary MBA configuration, 1065 * see mba_config for the fields definition. 1066 */ 1067 uint32_t mba_config2; 1068 1069 uint32_t mba_vlan_cfg; 1070 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1071 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1072 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1073 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1074 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1075 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1076 1077 /* Secondary MBA configuration, 1078 * see mba_vlan_cfg for the fields definition. 1079 */ 1080 uint32_t mba_vlan_cfg2; 1081 1082 uint32_t smbus_config; 1083 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1084 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1085 1086 uint32_t vf_config; 1087 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1088 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1089 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1090 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1091 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1092 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1093 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1094 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1095 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1096 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1097 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1098 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1099 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1100 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1101 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1102 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1103 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1104 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1105 1106 uint32_t link_config; /* Used as HW defaults for the driver */ 1107 1108 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1109 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1110 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1111 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1112 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1113 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1114 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1115 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1116 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1117 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1118 1119 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1120 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1121 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1122 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1123 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1124 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1125 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1126 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1127 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1128 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1129 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1130 1131 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1132 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1133 /* (forced) low speed switch (< 10G) */ 1134 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1135 /* (forced) high speed switch (>= 10G) */ 1136 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1137 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1138 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1139 1140 1141 /* The default for MCP link configuration, 1142 uses the same defines as link_config */ 1143 uint32_t mfw_wol_link_cfg; 1144 1145 /* The default for the driver of the second external phy, 1146 uses the same defines as link_config */ 1147 uint32_t link_config2; /* 0x47C */ 1148 1149 /* The default for MCP of the second external phy, 1150 uses the same defines as link_config */ 1151 uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1152 1153 1154 /* EEE power saving mode */ 1155 uint32_t eee_power_mode; /* 0x484 */ 1156 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1157 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1158 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1159 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1160 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1161 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1162 1163 1164 uint32_t Reserved2[16]; /* 0x48C */ 1165 }; 1166 1167 /**************************************************************************** 1168 * Device Information * 1169 ****************************************************************************/ 1170 struct shm_dev_info { /* size */ 1171 1172 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1173 1174 struct shared_hw_cfg shared_hw_config; /* 40 */ 1175 1176 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1177 1178 struct shared_feat_cfg shared_feature_config; /* 4 */ 1179 1180 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1181 1182 }; 1183 1184 struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1185 1186 /* Threshold in celcius to start using the fan */ 1187 uint32_t temperature_monitor1; /* 0x4000 */ 1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1190 1191 /* Threshold in celcius to shut down the board */ 1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1194 1195 /* EPIO of fan temperature status */ 1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1231 1232 /* EPIO of shut down temperature status */ 1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1251 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1254 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1257 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1258 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1259 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1260 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1262 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1263 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1264 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1265 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1266 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1268 1269 1270 /* EPIO of shut down temperature status */ 1271 uint32_t temperature_monitor2; /* 0x4004 */ 1272 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1273 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1274 1275 /* Sensor interface - Disabled / BSC / In the future - SMBUS */ 1276 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000 1277 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16 1278 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED \ 1279 0x00000000 1280 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000 1281 1282 /* On Board Sensor Address */ 1283 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000 1284 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18 1285 1286 /* MFW flavor to be used */ 1287 uint32_t mfw_cfg; /* 0x4008 */ 1288 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1289 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1292 1293 /* Should NIC data query remain enabled upon last drv unload */ 1294 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1295 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1296 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1297 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1298 1299 /* Prevent OCBB feature */ 1300 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200 1301 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9 1302 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200 1304 1305 /* Enable DCi support */ 1306 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400 1307 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10 1308 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000 1309 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400 1310 1311 /* Reserved bits: 75 */ 1312 1313 /* PLDM support over MCTP */ 1314 #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_MASK 0x00001000 1315 #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_SHIFT 12 1316 #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_DISABLED 0x00000000 1317 #define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_ENABLED 0x00001000 1318 1319 /* Option to Disable embedded LLDP, 0 - Off, 1 - On */ 1320 #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_MASK 0x00002000 1321 #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_SHIFT 13 1322 #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_OFF 0x00000000 1323 #define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_ON 0x00002000 1324 1325 /* Hide DCBX feature in CCM/BACS menus */ 1326 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1328 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1329 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1330 1331 uint32_t smbus_config; /* 0x400C */ 1332 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1333 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1334 1335 /* Switching regulator loop gain */ 1336 uint32_t board_cfg; /* 0x4010 */ 1337 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1338 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1339 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1340 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1341 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1343 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1344 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1345 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1346 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1348 1349 /* whether shadow swim feature is supported */ 1350 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1351 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1354 1355 /* whether to show/hide SRIOV menu in CCM */ 1356 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1357 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1358 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1359 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1360 1361 /* Override PCIE revision ID when enabled the, 1362 * revision ID will set to B1=='0x11' 1363 */ 1364 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1365 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1366 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1367 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1368 1369 /* Bypass slicer offset tuning */ 1370 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800 1371 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11 1372 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000 1373 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800 1374 /* Control Revision ID */ 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000 1376 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12 1377 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000 1378 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000 1379 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000 1380 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000 1381 /* Threshold in celcius for max continuous operation */ 1382 uint32_t temperature_report; /* 0x4014 */ 1383 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1384 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1385 1386 /* Threshold in celcius for sensor caution */ 1387 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1388 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1389 1390 /* wwn node prefix to be used (unless value is 0) */ 1391 uint32_t wwn_prefix; /* 0x4018 */ 1392 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1393 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1394 1395 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1396 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1397 1398 /* wwn port prefix to be used (unless value is 0) */ 1399 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1400 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1401 1402 /* wwn port prefix to be used (unless value is 0) */ 1403 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1404 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1405 1406 /* General debug nvm cfg */ 1407 uint32_t dbg_cfg_flags; /* 0x401C */ 1408 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1409 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1410 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1411 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1412 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1413 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1414 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1415 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1416 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1417 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1418 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1419 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1420 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1421 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1422 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1426 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1427 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1428 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1429 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1430 1431 /* Override Rx signal detect threshold when enabled the threshold 1432 * will be set statically 1433 */ 1434 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000 1435 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20 1436 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000 1437 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000 1438 1439 /* Debug signet rx threshold */ 1440 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1441 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1442 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1443 1444 /* Enable IFFE feature */ 1445 uint32_t iffe_features; /* 0x4024 */ 1446 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1447 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1448 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1449 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1450 1451 /* Allowable port enablement (bitmask for ports 3-1) */ 1452 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1453 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1454 1455 /* Allow iSCSI offload override */ 1456 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1457 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1458 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1459 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1460 1461 /* Allow FCoE offload override */ 1462 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1463 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1464 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1465 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1466 1467 /* Tie to adaptor */ 1468 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1469 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1470 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1471 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1472 1473 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1474 uint32_t current_iffe_mask; /* 0x4028 */ 1475 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1476 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1477 1478 /* Current iSCSI offload */ 1479 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1480 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1481 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1482 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1483 1484 /* Current FCoE offload */ 1485 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1486 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1487 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1488 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1489 1490 /* FW set this pin to "0" (assert) these signal if either of its MAC 1491 * or PHY specific threshold values is exceeded. 1492 * Values are standard GPIO/EPIO pins. 1493 */ 1494 uint32_t threshold_pin; /* 0x402C */ 1495 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1496 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1497 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1498 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1499 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1500 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1501 1502 /* MAC die temperature threshold in Celsius. */ 1503 uint32_t mac_threshold_val; /* 0x4030 */ 1504 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1505 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1506 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1507 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1508 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1509 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1510 1511 /* PHY die temperature threshold in Celsius. */ 1512 uint32_t phy_threshold_val; /* 0x4034 */ 1513 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1514 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1515 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1516 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1517 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1518 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1519 1520 /* External pins to communicate with host. 1521 * Values are standard GPIO/EPIO pins. 1522 */ 1523 uint32_t host_pin; /* 0x4038 */ 1524 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1525 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1526 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1527 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1528 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1529 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1530 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1531 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1532 1533 /* Manufacture kit version */ 1534 uint32_t manufacture_ver; /* 0x403C */ 1535 1536 /* Manufacture timestamp */ 1537 uint32_t manufacture_data; /* 0x4040 */ 1538 1539 /* Number of ISCSI/FCOE cfg images */ 1540 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000 1541 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18 1542 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000 1543 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000 1544 1545 /* MCP crash dump trigger */ 1546 uint32_t mcp_crash_dump; /* 0x4044 */ 1547 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF 1548 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0 1549 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000 1550 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001 1551 1552 /* MBI version */ 1553 uint32_t mbi_version; /* 0x4048 */ 1554 1555 /* MBI date */ 1556 uint32_t mbi_date; /* 0x404C */ 1557 }; 1558 1559 1560 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1561 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1562 #endif 1563 1564 #define FUNC_0 0 1565 #define FUNC_1 1 1566 #define FUNC_2 2 1567 #define FUNC_3 3 1568 #define FUNC_4 4 1569 #define FUNC_5 5 1570 #define FUNC_6 6 1571 #define FUNC_7 7 1572 #define E1_FUNC_MAX 2 1573 #define E1H_FUNC_MAX 8 1574 #define E2_FUNC_MAX 4 /* per path */ 1575 1576 #define VN_0 0 1577 #define VN_1 1 1578 #define VN_2 2 1579 #define VN_3 3 1580 #define E1VN_MAX 1 1581 #define E1HVN_MAX 4 1582 1583 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1584 /* This value (in milliseconds) determines the frequency of the driver 1585 * issuing the PULSE message code. The firmware monitors this periodic 1586 * pulse to determine when to switch to an OS-absent mode. */ 1587 #define DRV_PULSE_PERIOD_MS 250 1588 1589 /* This value (in milliseconds) determines how long the driver should 1590 * wait for an acknowledgement from the firmware before timing out. Once 1591 * the firmware has timed out, the driver will assume there is no firmware 1592 * running and there won't be any firmware-driver synchronization during a 1593 * driver reset. */ 1594 #define FW_ACK_TIME_OUT_MS 5000 1595 1596 #define FW_ACK_POLL_TIME_MS 1 1597 1598 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1599 1600 #define MFW_TRACE_SIGNATURE 0x54524342 1601 1602 /**************************************************************************** 1603 * Driver <-> FW Mailbox * 1604 ****************************************************************************/ 1605 struct drv_port_mb { 1606 1607 uint32_t link_status; 1608 /* Driver should update this field on any link change event */ 1609 1610 #define LINK_STATUS_NONE (0<<0) 1611 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1612 #define LINK_STATUS_LINK_UP 0x00000001 1613 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1614 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1615 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1616 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1617 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1618 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1619 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1620 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1621 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1622 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1623 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1624 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1625 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1626 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1627 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1628 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1629 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1630 1631 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1632 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1633 1634 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1635 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1636 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1637 1638 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1639 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1640 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1641 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1642 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1643 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1644 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1645 1646 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1647 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1648 1649 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1650 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1651 1652 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1653 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1654 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1655 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1656 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1657 1658 #define LINK_STATUS_SERDES_LINK 0x00100000 1659 1660 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1661 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1662 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1663 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1664 1665 #define LINK_STATUS_PFC_ENABLED 0x20000000 1666 1667 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1668 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1669 1670 uint32_t port_stx; 1671 1672 uint32_t stat_nig_timer; 1673 1674 /* MCP firmware does not use this field */ 1675 uint32_t ext_phy_fw_version; 1676 1677 }; 1678 1679 1680 struct drv_func_mb { 1681 1682 uint32_t drv_mb_header; 1683 #define DRV_MSG_CODE_MASK 0xffff0000 1684 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1685 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1686 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1687 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1688 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1689 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1690 #define DRV_MSG_CODE_DCC_OK 0x30000000 1691 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1692 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1693 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1694 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1695 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1696 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1697 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1698 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1699 #define DRV_MSG_CODE_OEM_OK 0x00010000 1700 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000 1701 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 1702 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 1703 1704 /* 1705 * The optic module verification command requires bootcode 1706 * v5.0.6 or later, te specific optic module verification command 1707 * requires bootcode v5.2.12 or later 1708 */ 1709 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1710 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1711 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1712 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1713 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1714 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1715 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1716 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1717 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1718 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1719 1720 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1721 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1722 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1723 1724 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1725 1726 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1727 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1728 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1729 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1730 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1731 1732 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1733 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1734 1735 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1736 1737 #define DRV_MSG_CODE_RMMOD 0xdb000000 1738 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1739 1740 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1741 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1742 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1743 1744 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1745 1746 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1747 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1748 1749 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1750 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1751 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1752 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1753 1754 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1755 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1756 1757 #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000 1758 1759 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1760 1761 #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000 1762 1763 #define DRV_MSG_CODE_UPDATE_DRIVER_STATE 0xC2000000 1764 #define REQ_BC_VER_4_UPDATE_DRIVER_STATE 0x00070f35 1765 1766 uint32_t drv_mb_param; 1767 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1768 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1769 1770 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1771 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1772 1773 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1774 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1775 1776 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1777 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 1778 #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003 1779 #define DRV_MSG_CODE_VLAN_TABLE_IMAGE_REQ 0x00000004 1780 1781 #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001 1782 #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002 1783 #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003 1784 #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004 1785 #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005 1786 #define DRV_MSG_CODE_CONFIG_CHANGE_RST2DFT 0x00000006 1787 1788 #define DRV_MSG_CODE_DRIVER_STATE_UNKNOWN 0x00000001 1789 #define DRV_MSG_CODE_DRIVER_STATE_NOT_LOADED 0x00000002 1790 #define DRV_MSG_CODE_DRIVER_STATE_LOADING 0x00000003 1791 #define DRV_MSG_CODE_DRIVER_STATE_DISABLED 0x00000004 1792 #define DRV_MSG_CODE_DRIVER_STATE_ACTIVE 0x00000005 1793 1794 uint32_t fw_mb_header; 1795 #define FW_MSG_CODE_MASK 0xffff0000 1796 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1797 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1798 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1799 /* Load common chip is supported from bc 6.0.0 */ 1800 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1801 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1802 1803 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1804 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1805 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1806 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1807 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1808 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1809 #define FW_MSG_CODE_DCC_DONE 0x30100000 1810 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1811 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1812 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1813 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1814 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1815 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1816 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1817 #define FW_MSG_CODE_NO_KEY 0x80f00000 1818 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1819 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1820 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1821 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1822 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1823 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1824 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1825 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1826 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1827 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1828 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1829 1830 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1831 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1832 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1833 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1834 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1835 1836 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1837 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1838 1839 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1840 1841 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1842 1843 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1844 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1845 1846 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1847 1848 #define FW_MSG_CODE_FLR_ACK 0x02000000 1849 #define FW_MSG_CODE_FLR_NACK 0x02100000 1850 1851 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1852 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1853 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1854 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1855 1856 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1857 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1858 1859 #define FW_MSG_CODE_OEM_ACK 0x00010000 1860 #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000 1861 1862 #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000 1863 1864 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0xC3000000 1865 1866 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1867 1868 uint32_t fw_mb_param; 1869 1870 #define FW_PARAM_INVALID_IMG 0xffffffff 1871 1872 uint32_t drv_pulse_mb; 1873 #define DRV_PULSE_SEQ_MASK 0x00007fff 1874 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1875 /* 1876 * The system time is in the format of 1877 * (year-2001)*12*32 + month*32 + day. 1878 */ 1879 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1880 /* 1881 * Indicate to the firmware not to go into the 1882 * OS-absent when it is not getting driver pulse. 1883 * This is used for debugging as well for PXE(MBA). 1884 */ 1885 1886 uint32_t mcp_pulse_mb; 1887 #define MCP_PULSE_SEQ_MASK 0x00007fff 1888 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1889 /* Indicates to the driver not to assert due to lack 1890 * of MCP response */ 1891 #define MCP_EVENT_MASK 0xffff0000 1892 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1893 1894 uint32_t iscsi_boot_signature; 1895 uint32_t iscsi_boot_block_offset; 1896 1897 uint32_t drv_status; 1898 #define DRV_STATUS_PMF 0x00000001 1899 #define DRV_STATUS_VF_DISABLED 0x00000002 1900 #define DRV_STATUS_SET_MF_BW 0x00000004 1901 #define DRV_STATUS_LINK_EVENT 0x00000008 1902 1903 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070 1904 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 1905 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 1906 #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040 1907 1908 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080 1909 1910 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1911 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1912 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1913 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1914 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1915 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1916 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1917 1918 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1919 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1920 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1921 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1922 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1923 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1924 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1925 1926 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1927 1928 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1929 1930 uint32_t virt_mac_upper; 1931 #define VIRT_MAC_SIGN_MASK 0xffff0000 1932 #define VIRT_MAC_SIGNATURE 0x564d0000 1933 uint32_t virt_mac_lower; 1934 1935 }; 1936 1937 1938 /**************************************************************************** 1939 * Management firmware state * 1940 ****************************************************************************/ 1941 /* Allocate 440 bytes for management firmware */ 1942 #define MGMTFW_STATE_WORD_SIZE 110 1943 1944 struct mgmtfw_state { 1945 uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1946 }; 1947 1948 1949 /**************************************************************************** 1950 * Multi-Function configuration * 1951 ****************************************************************************/ 1952 struct shared_mf_cfg { 1953 1954 uint32_t clp_mb; 1955 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1956 /* set by CLP */ 1957 #define SHARED_MF_CLP_EXIT 0x00000001 1958 /* set by MCP */ 1959 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1960 1961 }; 1962 1963 struct port_mf_cfg { 1964 1965 uint32_t dynamic_cfg; /* device control channel */ 1966 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1967 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1968 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1969 1970 uint32_t reserved[1]; 1971 1972 }; 1973 1974 struct func_mf_cfg { 1975 1976 uint32_t config; 1977 /* E/R/I/D */ 1978 /* function 0 of each port cannot be hidden */ 1979 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1980 1981 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1982 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1983 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1984 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1985 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1986 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1987 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1988 1989 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1990 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1991 1992 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1993 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1994 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1995 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1996 1997 /* PRI */ 1998 /* 0 - low priority, 3 - high priority */ 1999 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 2000 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 2001 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 2002 2003 /* MINBW, MAXBW */ 2004 /* value range - 0..100, increments in 100Mbps */ 2005 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 2006 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 2007 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 2008 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 2009 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 2010 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 2011 2012 uint32_t mac_upper; /* MAC */ 2013 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 2014 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 2015 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 2016 uint32_t mac_lower; 2017 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 2018 2019 uint32_t e1hov_tag; /* VNI */ 2020 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 2021 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 2022 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 2023 2024 /* afex default VLAN ID - 12 bits */ 2025 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 2026 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 2027 2028 uint32_t afex_config; 2029 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 2030 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 2031 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 2032 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 2033 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 2034 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 2035 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 2036 2037 uint32_t pf_allocation; 2038 /* number of vfs in function, if 0 - sriov disabled */ 2039 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 2040 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 2041 }; 2042 2043 enum mf_cfg_afex_vlan_mode { 2044 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 2045 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 2046 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 2047 }; 2048 2049 /* This structure is not applicable and should not be accessed on 57711 */ 2050 struct func_ext_cfg { 2051 uint32_t func_cfg; 2052 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 2053 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 2054 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 2055 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 2056 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 2057 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 2058 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 2059 2060 uint32_t iscsi_mac_addr_upper; 2061 uint32_t iscsi_mac_addr_lower; 2062 2063 uint32_t fcoe_mac_addr_upper; 2064 uint32_t fcoe_mac_addr_lower; 2065 2066 uint32_t fcoe_wwn_port_name_upper; 2067 uint32_t fcoe_wwn_port_name_lower; 2068 2069 uint32_t fcoe_wwn_node_name_upper; 2070 uint32_t fcoe_wwn_node_name_lower; 2071 2072 uint32_t preserve_data; 2073 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 2074 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 2075 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 2076 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 2077 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 2078 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 2079 }; 2080 2081 struct mf_cfg { 2082 2083 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 2084 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 2085 /* 0x10*2=0x20 */ 2086 /* for all chips, there are 8 mf functions */ 2087 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 2088 /* 2089 * Extended configuration per function - this array does not exist and 2090 * should not be accessed on 57711 2091 */ 2092 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 2093 }; /* 0x224 */ 2094 2095 /**************************************************************************** 2096 * Shared Memory Region * 2097 ****************************************************************************/ 2098 struct shmem_region { /* SharedMem Offset (size) */ 2099 2100 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 2101 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 2102 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 2103 /* validity bits */ 2104 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 2105 #define SHR_MEM_VALIDITY_MB 0x00200000 2106 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 2107 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 2108 /* One licensing bit should be set */ 2109 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 2110 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 2111 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 2112 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 2113 /* Active MFW */ 2114 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 2115 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 2116 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 2117 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 2118 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 2119 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 2120 2121 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 2122 2123 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52 * 2 = 0x68) */ 2124 2125 /* FW information (for internal FW use) */ 2126 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 2127 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 2128 2129 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 2130 2131 2132 #ifdef BMAPI 2133 /* This is a variable length array */ 2134 /* the number of function depends on the chip type */ 2135 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 2136 #else 2137 /* the number of function depends on the chip type */ 2138 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 2139 #endif /* BMAPI */ 2140 2141 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 2142 2143 /**************************************************************************** 2144 * Shared Memory 2 Region * 2145 ****************************************************************************/ 2146 /* The fw_flr_ack is actually built in the following way: */ 2147 /* 8 bit: PF ack */ 2148 /* 64 bit: VF ack */ 2149 /* 8 bit: ios_dis_ack */ 2150 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2151 /* uint32_t. The fw must have the VF right after the PF since this is how it */ 2152 /* access arrays(it expects always the VF to reside after the PF, and that */ 2153 /* makes the calculation much easier for it. ) */ 2154 /* In order to answer both limitations, and keep the struct small, the code */ 2155 /* will abuse the structure defined here to achieve the actual partition */ 2156 /* above */ 2157 /****************************************************************************/ 2158 struct fw_flr_ack { 2159 uint32_t pf_ack; 2160 uint32_t vf_ack; 2161 uint32_t iov_dis_ack; 2162 }; 2163 2164 struct fw_flr_mb { 2165 uint32_t aggint; 2166 uint32_t opgen_addr; 2167 struct fw_flr_ack ack; 2168 }; 2169 2170 struct eee_remote_vals { 2171 uint32_t tx_tw; 2172 uint32_t rx_tw; 2173 }; 2174 2175 /**** SUPPORT FOR SHMEM ARRRAYS *** 2176 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2177 * define arrays with storage types smaller then unsigned dwords. 2178 * The macros below add generic support for SHMEM arrays with numeric elements 2179 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2180 * array with individual bit-filed elements accessed using shifts and masks. 2181 * 2182 */ 2183 2184 /* eb is the bitwidth of a single element */ 2185 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2186 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2187 2188 /* the bit-position macro allows the used to flip the order of the arrays 2189 * elements on a per byte or word boundary. 2190 * 2191 * example: an array with 8 entries each 4 bit wide. This array will fit into 2192 * a single dword. The diagrams below show the array order of the nibbles. 2193 * 2194 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the standard ordering: 2195 * 2196 * | | | | 2197 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2198 * | | | | 2199 * 2200 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2201 * 2202 * | | | | 2203 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2204 * | | | | 2205 * 2206 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2207 * 2208 * | | | | 2209 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2210 * | | | | 2211 */ 2212 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2213 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2214 (((i)%((fb)/(eb))) * (eb))) 2215 2216 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2217 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2218 SHMEM_ARRAY_MASK(eb)) 2219 2220 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2221 do { \ 2222 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2223 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2224 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2225 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2226 } while (0) 2227 2228 2229 /****START OF DCBX STRUCTURES DECLARATIONS****/ 2230 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2231 #define DCBX_PRI_PG_BITWIDTH 4 2232 #define DCBX_PRI_PG_FBITS 8 2233 #define DCBX_PRI_PG_GET(a, i) \ 2234 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2235 #define DCBX_PRI_PG_SET(a, i, val) \ 2236 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2237 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2238 #define DCBX_BW_PG_BITWIDTH 8 2239 #define DCBX_PG_BW_GET(a, i) \ 2240 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2241 #define DCBX_PG_BW_SET(a, i, val) \ 2242 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2243 #define DCBX_STRICT_PRI_PG 15 2244 #define DCBX_MAX_APP_PROTOCOL 16 2245 #define DCBX_MAX_APP_LOCAL 32 2246 #define FCOE_APP_IDX 0 2247 #define ISCSI_APP_IDX 1 2248 #define PREDEFINED_APP_IDX_MAX 2 2249 2250 2251 /* Big/Little endian have the same representation. */ 2252 struct dcbx_ets_feature { 2253 /* 2254 * For Admin MIB - is this feature supported by the 2255 * driver | For Local MIB - should this feature be enabled. 2256 */ 2257 uint32_t enabled; 2258 uint32_t pg_bw_tbl[2]; 2259 uint32_t pri_pg_tbl[1]; 2260 }; 2261 2262 /* Driver structure in LE */ 2263 struct dcbx_pfc_feature { 2264 #ifdef __BIG_ENDIAN 2265 uint8_t pri_en_bitmap; 2266 #define DCBX_PFC_PRI_0 0x01 2267 #define DCBX_PFC_PRI_1 0x02 2268 #define DCBX_PFC_PRI_2 0x04 2269 #define DCBX_PFC_PRI_3 0x08 2270 #define DCBX_PFC_PRI_4 0x10 2271 #define DCBX_PFC_PRI_5 0x20 2272 #define DCBX_PFC_PRI_6 0x40 2273 #define DCBX_PFC_PRI_7 0x80 2274 uint8_t pfc_caps; 2275 uint8_t reserved; 2276 uint8_t enabled; 2277 #elif defined(__LITTLE_ENDIAN) 2278 uint8_t enabled; 2279 uint8_t reserved; 2280 uint8_t pfc_caps; 2281 uint8_t pri_en_bitmap; 2282 #define DCBX_PFC_PRI_0 0x01 2283 #define DCBX_PFC_PRI_1 0x02 2284 #define DCBX_PFC_PRI_2 0x04 2285 #define DCBX_PFC_PRI_3 0x08 2286 #define DCBX_PFC_PRI_4 0x10 2287 #define DCBX_PFC_PRI_5 0x20 2288 #define DCBX_PFC_PRI_6 0x40 2289 #define DCBX_PFC_PRI_7 0x80 2290 #endif 2291 }; 2292 2293 struct dcbx_app_priority_entry { 2294 #ifdef __BIG_ENDIAN 2295 uint16_t app_id; 2296 uint8_t pri_bitmap; 2297 uint8_t appBitfield; 2298 #define DCBX_APP_ENTRY_VALID 0x01 2299 #define DCBX_APP_ENTRY_SF_MASK 0xF0 2300 #define DCBX_APP_ENTRY_SF_SHIFT 4 2301 #define DCBX_APP_SF_ETH_TYPE 0x10 2302 #define DCBX_APP_SF_PORT 0x20 /* TCP */ 2303 #define DCBX_APP_SF_UDP 0x40 /* UDP */ 2304 #define DCBX_APP_SF_DEFAULT 0x80 2305 #define DCBX_APP_PRI_0 0x01 2306 #define DCBX_APP_PRI_1 0x02 2307 #define DCBX_APP_PRI_2 0x04 2308 #define DCBX_APP_PRI_3 0x08 2309 #define DCBX_APP_PRI_4 0x10 2310 #define DCBX_APP_PRI_5 0x20 2311 #define DCBX_APP_PRI_6 0x40 2312 #define DCBX_APP_PRI_7 0x80 2313 #elif defined(__LITTLE_ENDIAN) 2314 uint8_t appBitfield; 2315 #define DCBX_APP_ENTRY_VALID 0x01 2316 #define DCBX_APP_ENTRY_SF_MASK 0xF0 2317 #define DCBX_APP_ENTRY_SF_SHIFT 4 2318 #define DCBX_APP_ENTRY_VALID 0x01 2319 #define DCBX_APP_SF_ETH_TYPE 0x10 2320 #define DCBX_APP_SF_PORT 0x20 /* TCP */ 2321 #define DCBX_APP_SF_UDP 0x40 /* UDP */ 2322 #define DCBX_APP_SF_DEFAULT 0x80 2323 uint8_t pri_bitmap; 2324 uint16_t app_id; 2325 #endif 2326 }; 2327 2328 2329 /* FW structure in BE */ 2330 struct dcbx_app_priority_feature { 2331 #ifdef __BIG_ENDIAN 2332 uint8_t reserved; 2333 uint8_t default_pri; 2334 uint8_t tc_supported; 2335 uint8_t enabled; 2336 #elif defined(__LITTLE_ENDIAN) 2337 uint8_t enabled; 2338 uint8_t tc_supported; 2339 uint8_t default_pri; 2340 uint8_t reserved; 2341 #endif 2342 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2343 }; 2344 2345 /* FW structure in BE */ 2346 struct dcbx_features { 2347 /* PG feature */ 2348 struct dcbx_ets_feature ets; 2349 /* PFC feature */ 2350 struct dcbx_pfc_feature pfc; 2351 /* APP feature */ 2352 struct dcbx_app_priority_feature app; 2353 }; 2354 2355 /* LLDP protocol parameters */ 2356 /* FW structure in BE */ 2357 struct lldp_params { 2358 #ifdef __BIG_ENDIAN 2359 uint8_t msg_fast_tx_interval; 2360 uint8_t msg_tx_hold; 2361 uint8_t msg_tx_interval; 2362 uint8_t admin_status; 2363 #define LLDP_TX_ONLY 0x01 2364 #define LLDP_RX_ONLY 0x02 2365 #define LLDP_TX_RX 0x03 2366 #define LLDP_DISABLED 0x04 2367 uint8_t reserved1; 2368 uint8_t tx_fast; 2369 uint8_t tx_crd_max; 2370 uint8_t tx_crd; 2371 #elif defined(__LITTLE_ENDIAN) 2372 uint8_t admin_status; 2373 #define LLDP_TX_ONLY 0x01 2374 #define LLDP_RX_ONLY 0x02 2375 #define LLDP_TX_RX 0x03 2376 #define LLDP_DISABLED 0x04 2377 uint8_t msg_tx_interval; 2378 uint8_t msg_tx_hold; 2379 uint8_t msg_fast_tx_interval; 2380 uint8_t tx_crd; 2381 uint8_t tx_crd_max; 2382 uint8_t tx_fast; 2383 uint8_t reserved1; 2384 #endif 2385 #define REM_CHASSIS_ID_STAT_LEN 4 2386 #define REM_PORT_ID_STAT_LEN 4 2387 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2388 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2389 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2390 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2391 }; 2392 2393 struct lldp_dcbx_stat { 2394 #define LOCAL_CHASSIS_ID_STAT_LEN 2 2395 #define LOCAL_PORT_ID_STAT_LEN 2 2396 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2397 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2398 /* Holds local Port ID 8B payload of constant subtype 3. */ 2399 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2400 /* Number of DCBX frames transmitted. */ 2401 uint32_t num_tx_dcbx_pkts; 2402 /* Number of DCBX frames received. */ 2403 uint32_t num_rx_dcbx_pkts; 2404 }; 2405 2406 /* ADMIN MIB - DCBX local machine default configuration. */ 2407 struct lldp_admin_mib { 2408 uint32_t ver_cfg_flags; 2409 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2410 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2411 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2412 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2413 #define DCBX_ETS_RECO_VALID 0x00000010 2414 #define DCBX_ETS_WILLING 0x00000020 2415 #define DCBX_PFC_WILLING 0x00000040 2416 #define DCBX_APP_WILLING 0x00000080 2417 #define DCBX_VERSION_CEE 0x00000100 2418 #define DCBX_VERSION_IEEE 0x00000200 2419 #define DCBX_DCBX_ENABLED 0x00000400 2420 #define DCBX_CEE_VERSION_MASK 0x0000f000 2421 #define DCBX_CEE_VERSION_SHIFT 12 2422 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2423 #define DCBX_CEE_MAX_VERSION_SHIFT 16 2424 struct dcbx_features features; 2425 }; 2426 2427 /* REMOTE MIB - remote machine DCBX configuration. */ 2428 struct lldp_remote_mib { 2429 uint32_t prefix_seq_num; 2430 uint32_t flags; 2431 #define DCBX_ETS_TLV_RX 0x00000001 2432 #define DCBX_PFC_TLV_RX 0x00000002 2433 #define DCBX_APP_TLV_RX 0x00000004 2434 #define DCBX_ETS_RX_ERROR 0x00000010 2435 #define DCBX_PFC_RX_ERROR 0x00000020 2436 #define DCBX_APP_RX_ERROR 0x00000040 2437 #define DCBX_ETS_REM_WILLING 0x00000100 2438 #define DCBX_PFC_REM_WILLING 0x00000200 2439 #define DCBX_APP_REM_WILLING 0x00000400 2440 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2441 #define DCBX_REMOTE_MIB_VALID 0x00002000 2442 struct dcbx_features features; 2443 uint32_t suffix_seq_num; 2444 }; 2445 2446 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2447 struct lldp_local_mib { 2448 uint32_t prefix_seq_num; 2449 /* Indicates if there is mismatch with negotiation results. */ 2450 uint32_t error; 2451 #define DCBX_LOCAL_ETS_ERROR 0x00000001 2452 #define DCBX_LOCAL_PFC_ERROR 0x00000002 2453 #define DCBX_LOCAL_APP_ERROR 0x00000004 2454 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2455 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2456 #define DCBX_REMOTE_MIB_ERROR 0x00000040 2457 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2458 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2459 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2460 struct dcbx_features features; 2461 uint32_t suffix_seq_num; 2462 }; 2463 2464 struct lldp_local_mib_ext { 2465 uint32_t prefix_seq_num; 2466 /* APP TLV extension - 16 more entries for negotiation results*/ 2467 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2468 uint32_t suffix_seq_num; 2469 }; 2470 /***END OF DCBX STRUCTURES DECLARATIONS***/ 2471 2472 /***********************************************************/ 2473 /* Elink section */ 2474 /***********************************************************/ 2475 #define SHMEM_LINK_CONFIG_SIZE 2 2476 struct shmem_lfa { 2477 uint32_t req_duplex; 2478 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2479 #define REQ_DUPLEX_PHY0_SHIFT 0 2480 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2481 #define REQ_DUPLEX_PHY1_SHIFT 16 2482 uint32_t req_flow_ctrl; 2483 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2484 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2485 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2486 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2487 uint32_t req_line_speed; /* Also determine AutoNeg */ 2488 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2489 #define REQ_LINE_SPD_PHY0_SHIFT 0 2490 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2491 #define REQ_LINE_SPD_PHY1_SHIFT 16 2492 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2493 uint32_t additional_config; 2494 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2495 #define REQ_FC_AUTO_ADV0_SHIFT 0 2496 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2497 uint32_t lfa_sts; 2498 #define LFA_LINK_FLAP_REASON_OFFSET 0 2499 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2500 #define LFA_LINK_DOWN 0x1 2501 #define LFA_LOOPBACK_ENABLED 0x2 2502 #define LFA_DUPLEX_MISMATCH 0x3 2503 #define LFA_MFW_IS_TOO_OLD 0x4 2504 #define LFA_LINK_SPEED_MISMATCH 0x5 2505 #define LFA_FLOW_CTRL_MISMATCH 0x6 2506 #define LFA_SPEED_CAP_MISMATCH 0x7 2507 #define LFA_DCC_LFA_DISABLED 0x8 2508 #define LFA_EEE_MISMATCH 0x9 2509 2510 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2511 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2512 2513 #define LINK_FLAP_COUNT_OFFSET 16 2514 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2515 2516 #define LFA_FLAGS_MASK 0xff000000 2517 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2518 2519 }; 2520 2521 /* 2522 * Used to support NSCI get OS driver version 2523 * On driver load the version value will be set 2524 * On driver unload driver value of 0x0 will be set 2525 */ 2526 struct os_drv_ver { 2527 #define DRV_VER_NOT_LOADED 0 2528 /* personalities order is important */ 2529 #define DRV_PERS_ETHERNET 0 2530 #define DRV_PERS_ISCSI 1 2531 #define DRV_PERS_FCOE 2 2532 /* shmem2 struct is constant can't add more personalities here */ 2533 #define MAX_DRV_PERS 3 2534 uint32_t versions[MAX_DRV_PERS]; 2535 }; 2536 2537 #define OEM_I2C_UUID_STR_ADDR 0x9f 2538 #define OEM_I2C_CARD_SKU_STR_ADDR 0x3c 2539 #define OEM_I2C_CARD_FN_STR_ADDR 0x48 2540 #define OEM_I2C_CARD_NAME_STR_ADDR 0x10e 2541 2542 #define OEM_I2C_UUID_STR_LEN 16 2543 #define OEM_I2C_CARD_SKU_STR_LEN 12 2544 #define OEM_I2C_CARD_FN_STR_LEN 12 2545 #define OEM_I2C_CARD_NAME_STR_LEN 128 2546 #define OEM_I2C_CARD_VERSION_STR_LEN 36 2547 2548 struct oem_i2c_data_t { 2549 uint32_t size; 2550 uint8_t uuid[OEM_I2C_UUID_STR_LEN]; 2551 uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN]; 2552 uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN]; 2553 uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN]; 2554 uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN]; 2555 }; 2556 2557 enum curr_cfg_method_e { 2558 CURR_CFG_MET_NONE = 0, /* default config */ 2559 CURR_CFG_MET_OS = 1, 2560 CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */ 2561 CURR_CFG_MET_HP_OTHER = 3, 2562 CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */ 2563 CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */ 2564 CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */ 2565 }; 2566 2567 #define FC_NPIV_WWPN_SIZE 8 2568 #define FC_NPIV_WWNN_SIZE 8 2569 struct bdn_npiv_settings { 2570 uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE]; 2571 uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE]; 2572 }; 2573 2574 struct bdn_fc_npiv_cfg { 2575 /* hdr used internally by the MFW */ 2576 uint32_t hdr; 2577 uint32_t num_of_npiv; 2578 }; 2579 2580 #define MAX_NUMBER_NPIV 64 2581 struct bdn_fc_npiv_tbl { 2582 struct bdn_fc_npiv_cfg fc_npiv_cfg; 2583 struct bdn_npiv_settings settings[MAX_NUMBER_NPIV]; 2584 }; 2585 2586 struct mdump_driver_info { 2587 uint32_t epoc; 2588 uint32_t drv_ver; 2589 uint32_t fw_ver; 2590 2591 uint32_t valid_dump; 2592 #define FIRST_DUMP_VALID (1 << 0) 2593 #define SECOND_DUMP_VALID (1 << 1) 2594 2595 uint32_t flags; 2596 #define ENABLE_ALL_TRIGGERS (0x7fffffff) 2597 #define TRIGGER_MDUMP_ONCE (1 << 31) 2598 }; 2599 2600 struct shmem2_region { 2601 2602 uint32_t size; /* 0x0000 */ 2603 2604 uint32_t dcc_support; /* 0x0004 */ 2605 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2606 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2607 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2608 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2609 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2610 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2611 2612 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2613 /* 2614 * For backwards compatibility, if the mf_cfg_addr does not exist 2615 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2616 * end of struct shmem_region 2617 */ 2618 uint32_t mf_cfg_addr; /* 0x0010 */ 2619 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2620 2621 struct fw_flr_mb flr_mb; /* 0x0014 */ 2622 uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2623 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2624 uint32_t dcbx_neg_res_offset; /* 0x002c */ 2625 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2626 uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2627 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2628 /* 2629 * The other shmemX_base_addr holds the other path's shmem address 2630 * required for example in case of common phy init, or for path1 to know 2631 * the address of mcp debug trace which is located in offset from shmem 2632 * of path0 2633 */ 2634 uint32_t other_shmem_base_addr; /* 0x0034 */ 2635 uint32_t other_shmem2_base_addr; /* 0x0038 */ 2636 /* 2637 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2638 * which were disabled/flred 2639 */ 2640 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2641 2642 /* 2643 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2644 * VFs 2645 */ 2646 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2647 2648 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2649 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2650 2651 /* 2652 * edebug_driver_if field is used to transfer messages between edebug 2653 * app to the driver through shmem2. 2654 * 2655 * message format: 2656 * bits 0-2 - function number / instance of driver to perform request 2657 * bits 3-5 - op code / is_ack? 2658 * bits 6-63 - data 2659 */ 2660 uint32_t edebug_driver_if[2]; /* 0x0068 */ 2661 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2662 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2663 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2664 2665 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2666 2667 /* afex support of that driver */ 2668 uint32_t afex_driver_support; /* 0x0074 */ 2669 #define SHMEM_AFEX_VERSION_MASK 0x100f 2670 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2671 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2672 2673 /* driver receives addr in scratchpad to which it should respond */ 2674 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2675 2676 /* 2677 * generic params from MCP to driver (value depends on the msg sent 2678 * to driver 2679 */ 2680 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2681 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2682 2683 uint32_t swim_base_addr; /* 0x00a8 */ 2684 uint32_t swim_funcs; /* 0x00ac */ 2685 uint32_t swim_main_cb; /* 0x00b0 */ 2686 2687 /* 2688 * bitmap notifying which VIF profiles stored in nvram are enabled by 2689 * switch 2690 */ 2691 uint32_t afex_profiles_enabled[2]; /* 0x00b4 */ 2692 2693 /* generic flags controlled by the driver */ 2694 uint32_t drv_flags; /* 0x00bc */ 2695 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2696 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2697 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2698 2699 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2700 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2701 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2702 /* Port offset*/ 2703 #define DRV_FLAGS_P0_OFFSET 0 2704 #define DRV_FLAGS_P1_OFFSET 16 2705 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2706 DRV_FLAGS_P0_OFFSET : \ 2707 DRV_FLAGS_P1_OFFSET) 2708 2709 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2710 DRV_FLAGS_GET_PORT_OFFSET(_port)) 2711 2712 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2713 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2714 2715 /* pointer to extended dev_info shared data copied from nvm image */ 2716 uint32_t extended_dev_info_shared_addr; /* 0x00c0 */ 2717 uint32_t ncsi_oem_data_addr; /* 0x00c4 */ 2718 2719 uint32_t sensor_data_addr; /* 0x00c8 */ 2720 uint32_t buffer_block_addr; /* 0x00cc */ 2721 uint32_t sensor_data_req_update_interval; /* 0x00d0 */ 2722 uint32_t temperature_in_half_celsius; /* 0x00d4 */ 2723 uint32_t glob_struct_in_host; /* 0x00d8 */ 2724 2725 uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */ 2726 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2727 2728 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */ 2729 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2730 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2731 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2732 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2733 #define DRV_FLAGS_MTU_MASK 0xffff0000 2734 #define DRV_FLAGS_MTU_SHIFT 16 2735 2736 uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */ 2737 2738 uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */ 2739 2740 /* The offset points to the multi threaded meta structure */ 2741 uint32_t multi_thread_data_offset; /* 0x00fc */ 2742 2743 /* address of DMAable host address holding values from the drivers */ 2744 uint32_t drv_info_host_addr_lo; /* 0x0100 */ 2745 uint32_t drv_info_host_addr_hi; /* 0x0104 */ 2746 2747 /* general values written by the MFW (such as current version) */ 2748 uint32_t drv_info_control; /* 0x0108 */ 2749 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2750 #define DRV_INFO_CONTROL_VER_SHIFT 0 2751 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2752 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2753 uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */ 2754 2755 struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */ 2756 uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */ 2757 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2758 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2759 2760 /* the status of EEE auto-negotiation 2761 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2762 * bits 19:16 the supported modes for EEE. 2763 * bits 23:20 the speeds advertised for EEE. 2764 * bits 27:24 the speeds the Link partner advertised for EEE. 2765 * The supported/adv. modes in bits 27:19 originate from the 2766 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2767 * bit 28 when 1'b1 EEE was requested. 2768 * bit 29 when 1'b1 tx lpi was requested. 2769 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted if 2770 * 30:29 are 2'b11. 2771 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2772 * value. When 1'b1 those bits contains a value times 16 microseconds. 2773 */ 2774 uint32_t eee_status[PORT_MAX]; /* 0x0130 */ 2775 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2776 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2777 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2778 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2779 #define SHMEM_EEE_100M_ADV (1<<0) 2780 #define SHMEM_EEE_1G_ADV (1 << 1) 2781 #define SHMEM_EEE_10G_ADV (1<<2) 2782 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2783 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2784 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2785 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2786 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2787 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2788 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2789 2790 uint32_t sizeof_port_stats; /* 0x0138 */ 2791 2792 /* Link Flap Avoidance */ 2793 uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */ 2794 2795 /* External PHY temperature in deg C. */ 2796 uint32_t extphy_temps_in_celsius; /* 0x0144 */ 2797 #define EXTPHY1_TEMP_MASK 0x0000ffff 2798 #define EXTPHY1_TEMP_SHIFT 0 2799 #define ON_BOARD_TEMP_MASK 0xffff0000 2800 #define ON_BOARD_TEMP_SHIFT 16 2801 2802 uint32_t ocdata_info_addr; /* Offset 0x148 */ 2803 uint32_t drv_func_info_addr; /* Offset 0x14C */ 2804 uint32_t drv_func_info_size; /* Offset 0x150 */ 2805 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2806 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 2807 #define LINK_ATTR_84858 0x00000002 2808 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 2809 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 2810 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 2811 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 2812 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 2813 2814 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */ 2815 uint32_t fcode_ver; /* Offset 0x15c */ 2816 uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */ 2817 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */ 2818 /* driver version for each personality*/ 2819 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ 2820 2821 /* Flag to the driver that PF's drv_info_host_addr buffer was read */ 2822 uint32_t mfw_drv_indication; /* Offset 0x19c */ 2823 2824 /* We use indication for each PF (0..3) */ 2825 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_)) 2826 2827 union { /* For various OEMs */ /* Offset 0x1a0 */ 2828 uint8_t storage_boot_prog[E2_FUNC_MAX]; 2829 #define STORAGE_BOOT_PROG_MASK 0x000000FF 2830 #define STORAGE_BOOT_PROG_NONE 0x00000000 2831 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002 2832 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002 2833 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004 2834 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008 2835 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008 2836 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010 2837 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020 2838 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040 2839 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080 2840 2841 uint32_t oem_i2c_data_addr; 2842 }; 2843 2844 /* 9 entries for the C2S PCP map for each inner VLAN PCP + 1 default */ 2845 /* For PCP values 0-3 use the map lower */ 2846 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 2847 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 2848 */ 2849 uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */ 2850 2851 /* For PCP values 4-7 use the map upper */ 2852 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 2853 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 2854 */ 2855 uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */ 2856 2857 /* For PCP default value get the MSB byte of the map default */ 2858 uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */ 2859 2860 /* FC_NPIV table offset in NVRAM */ 2861 uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */ 2862 2863 /* Shows last method that changed configuration of this device */ 2864 enum curr_cfg_method_e curr_cfg; /* 0x1dc */ 2865 2866 /* Storm FW version, shold be kept in the format 0xMMmmbbdd: 2867 * MM - Major, mm - Minor, bb - Build ,dd - Drop 2868 */ 2869 uint32_t netproc_fw_ver; /* 0x1e0 */ 2870 2871 /* Option ROM SMASH CLP version */ 2872 uint32_t clp_ver; /* 0x1e4 */ 2873 2874 uint32_t pcie_bus_num; /* 0x1e8 */ 2875 2876 uint32_t sriov_switch_mode; /* 0x1ec */ 2877 #define SRIOV_SWITCH_MODE_NONE 0x0 2878 #define SRIOV_SWITCH_MODE_VEB 0x1 2879 #define SRIOV_SWITCH_MODE_VEPA 0x2 2880 2881 uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */ 2882 2883 uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */ 2884 2885 uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */ 2886 2887 uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */ 2888 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */ 2889 #define OS_DRIVER_STATE_LOADING 1 /* transition state */ 2890 #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */ 2891 #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */ 2892 2893 /* mini dump driver info */ 2894 struct mdump_driver_info drv_info; /* 0x218 */ 2895 2896 /* written by mfw, read by driver, eg. feature capability support */ 2897 uint32_t mfw_flags; /* 0x22c */ 2898 #define DISABLE_EMBEDDED_LLDP_SUPPORT 0x00000001 2899 }; 2900 2901 #define VLAN_BITMAP_SIZE 512 2902 #define VLAN_PF_NUM_MAX 8 2903 2904 struct pf_vlan_table { 2905 uint16_t pvid; 2906 uint8_t pcp; 2907 uint8_t rsvd; 2908 uint8_t trunk_vlan_bitmap[VLAN_BITMAP_SIZE]; 2909 uint32_t rsvd1[4]; 2910 }; 2911 2912 struct vlan_table_s { 2913 uint32_t version; 2914 #define VLAN_TABLE_IMAGE_VERSION_1 1 2915 uint8_t vlan_mode[NVM_PATH_MAX][PORT_MAX]; 2916 #define VLAN_MODE_NORMAL 0 2917 #define VLAN_MODE_FILTER 1 2918 #define VLAN_MODE_QINQ 2 2919 struct pf_vlan_table pf_vlans[VLAN_PF_NUM_MAX]; 2920 uint32_t rsvd2[8]; 2921 }; 2922 2923 /* The VLAN table Image is stored in Big Endian format */ 2924 struct nvm_vlan_table_image { 2925 struct vlan_table_s vlan_table; 2926 uint32_t crc; 2927 }; 2928 2929 2930 struct emac_stats { 2931 uint32_t rx_stat_ifhcinoctets; 2932 uint32_t rx_stat_ifhcinbadoctets; 2933 uint32_t rx_stat_etherstatsfragments; 2934 uint32_t rx_stat_ifhcinucastpkts; 2935 uint32_t rx_stat_ifhcinmulticastpkts; 2936 uint32_t rx_stat_ifhcinbroadcastpkts; 2937 uint32_t rx_stat_dot3statsfcserrors; 2938 uint32_t rx_stat_dot3statsalignmenterrors; 2939 uint32_t rx_stat_dot3statscarriersenseerrors; 2940 uint32_t rx_stat_xonpauseframesreceived; 2941 uint32_t rx_stat_xoffpauseframesreceived; 2942 uint32_t rx_stat_maccontrolframesreceived; 2943 uint32_t rx_stat_xoffstateentered; 2944 uint32_t rx_stat_dot3statsframestoolong; 2945 uint32_t rx_stat_etherstatsjabbers; 2946 uint32_t rx_stat_etherstatsundersizepkts; 2947 uint32_t rx_stat_etherstatspkts64octets; 2948 uint32_t rx_stat_etherstatspkts65octetsto127octets; 2949 uint32_t rx_stat_etherstatspkts128octetsto255octets; 2950 uint32_t rx_stat_etherstatspkts256octetsto511octets; 2951 uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2952 uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2953 uint32_t rx_stat_etherstatspktsover1522octets; 2954 2955 uint32_t rx_stat_falsecarriererrors; 2956 2957 uint32_t tx_stat_ifhcoutoctets; 2958 uint32_t tx_stat_ifhcoutbadoctets; 2959 uint32_t tx_stat_etherstatscollisions; 2960 uint32_t tx_stat_outxonsent; 2961 uint32_t tx_stat_outxoffsent; 2962 uint32_t tx_stat_flowcontroldone; 2963 uint32_t tx_stat_dot3statssinglecollisionframes; 2964 uint32_t tx_stat_dot3statsmultiplecollisionframes; 2965 uint32_t tx_stat_dot3statsdeferredtransmissions; 2966 uint32_t tx_stat_dot3statsexcessivecollisions; 2967 uint32_t tx_stat_dot3statslatecollisions; 2968 uint32_t tx_stat_ifhcoutucastpkts; 2969 uint32_t tx_stat_ifhcoutmulticastpkts; 2970 uint32_t tx_stat_ifhcoutbroadcastpkts; 2971 uint32_t tx_stat_etherstatspkts64octets; 2972 uint32_t tx_stat_etherstatspkts65octetsto127octets; 2973 uint32_t tx_stat_etherstatspkts128octetsto255octets; 2974 uint32_t tx_stat_etherstatspkts256octetsto511octets; 2975 uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2976 uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2977 uint32_t tx_stat_etherstatspktsover1522octets; 2978 uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2979 }; 2980 2981 2982 struct bmac1_stats { 2983 uint32_t tx_stat_gtpkt_lo; 2984 uint32_t tx_stat_gtpkt_hi; 2985 uint32_t tx_stat_gtxpf_lo; 2986 uint32_t tx_stat_gtxpf_hi; 2987 uint32_t tx_stat_gtfcs_lo; 2988 uint32_t tx_stat_gtfcs_hi; 2989 uint32_t tx_stat_gtmca_lo; 2990 uint32_t tx_stat_gtmca_hi; 2991 uint32_t tx_stat_gtbca_lo; 2992 uint32_t tx_stat_gtbca_hi; 2993 uint32_t tx_stat_gtfrg_lo; 2994 uint32_t tx_stat_gtfrg_hi; 2995 uint32_t tx_stat_gtovr_lo; 2996 uint32_t tx_stat_gtovr_hi; 2997 uint32_t tx_stat_gt64_lo; 2998 uint32_t tx_stat_gt64_hi; 2999 uint32_t tx_stat_gt127_lo; 3000 uint32_t tx_stat_gt127_hi; 3001 uint32_t tx_stat_gt255_lo; 3002 uint32_t tx_stat_gt255_hi; 3003 uint32_t tx_stat_gt511_lo; 3004 uint32_t tx_stat_gt511_hi; 3005 uint32_t tx_stat_gt1023_lo; 3006 uint32_t tx_stat_gt1023_hi; 3007 uint32_t tx_stat_gt1518_lo; 3008 uint32_t tx_stat_gt1518_hi; 3009 uint32_t tx_stat_gt2047_lo; 3010 uint32_t tx_stat_gt2047_hi; 3011 uint32_t tx_stat_gt4095_lo; 3012 uint32_t tx_stat_gt4095_hi; 3013 uint32_t tx_stat_gt9216_lo; 3014 uint32_t tx_stat_gt9216_hi; 3015 uint32_t tx_stat_gt16383_lo; 3016 uint32_t tx_stat_gt16383_hi; 3017 uint32_t tx_stat_gtmax_lo; 3018 uint32_t tx_stat_gtmax_hi; 3019 uint32_t tx_stat_gtufl_lo; 3020 uint32_t tx_stat_gtufl_hi; 3021 uint32_t tx_stat_gterr_lo; 3022 uint32_t tx_stat_gterr_hi; 3023 uint32_t tx_stat_gtbyt_lo; 3024 uint32_t tx_stat_gtbyt_hi; 3025 3026 uint32_t rx_stat_gr64_lo; 3027 uint32_t rx_stat_gr64_hi; 3028 uint32_t rx_stat_gr127_lo; 3029 uint32_t rx_stat_gr127_hi; 3030 uint32_t rx_stat_gr255_lo; 3031 uint32_t rx_stat_gr255_hi; 3032 uint32_t rx_stat_gr511_lo; 3033 uint32_t rx_stat_gr511_hi; 3034 uint32_t rx_stat_gr1023_lo; 3035 uint32_t rx_stat_gr1023_hi; 3036 uint32_t rx_stat_gr1518_lo; 3037 uint32_t rx_stat_gr1518_hi; 3038 uint32_t rx_stat_gr2047_lo; 3039 uint32_t rx_stat_gr2047_hi; 3040 uint32_t rx_stat_gr4095_lo; 3041 uint32_t rx_stat_gr4095_hi; 3042 uint32_t rx_stat_gr9216_lo; 3043 uint32_t rx_stat_gr9216_hi; 3044 uint32_t rx_stat_gr16383_lo; 3045 uint32_t rx_stat_gr16383_hi; 3046 uint32_t rx_stat_grmax_lo; 3047 uint32_t rx_stat_grmax_hi; 3048 uint32_t rx_stat_grpkt_lo; 3049 uint32_t rx_stat_grpkt_hi; 3050 uint32_t rx_stat_grfcs_lo; 3051 uint32_t rx_stat_grfcs_hi; 3052 uint32_t rx_stat_grmca_lo; 3053 uint32_t rx_stat_grmca_hi; 3054 uint32_t rx_stat_grbca_lo; 3055 uint32_t rx_stat_grbca_hi; 3056 uint32_t rx_stat_grxcf_lo; 3057 uint32_t rx_stat_grxcf_hi; 3058 uint32_t rx_stat_grxpf_lo; 3059 uint32_t rx_stat_grxpf_hi; 3060 uint32_t rx_stat_grxuo_lo; 3061 uint32_t rx_stat_grxuo_hi; 3062 uint32_t rx_stat_grjbr_lo; 3063 uint32_t rx_stat_grjbr_hi; 3064 uint32_t rx_stat_grovr_lo; 3065 uint32_t rx_stat_grovr_hi; 3066 uint32_t rx_stat_grflr_lo; 3067 uint32_t rx_stat_grflr_hi; 3068 uint32_t rx_stat_grmeg_lo; 3069 uint32_t rx_stat_grmeg_hi; 3070 uint32_t rx_stat_grmeb_lo; 3071 uint32_t rx_stat_grmeb_hi; 3072 uint32_t rx_stat_grbyt_lo; 3073 uint32_t rx_stat_grbyt_hi; 3074 uint32_t rx_stat_grund_lo; 3075 uint32_t rx_stat_grund_hi; 3076 uint32_t rx_stat_grfrg_lo; 3077 uint32_t rx_stat_grfrg_hi; 3078 uint32_t rx_stat_grerb_lo; 3079 uint32_t rx_stat_grerb_hi; 3080 uint32_t rx_stat_grfre_lo; 3081 uint32_t rx_stat_grfre_hi; 3082 uint32_t rx_stat_gripj_lo; 3083 uint32_t rx_stat_gripj_hi; 3084 }; 3085 3086 struct bmac2_stats { 3087 uint32_t tx_stat_gtpk_lo; /* gtpok */ 3088 uint32_t tx_stat_gtpk_hi; /* gtpok */ 3089 uint32_t tx_stat_gtxpf_lo; /* gtpf */ 3090 uint32_t tx_stat_gtxpf_hi; /* gtpf */ 3091 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 3092 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 3093 uint32_t tx_stat_gtfcs_lo; 3094 uint32_t tx_stat_gtfcs_hi; 3095 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 3096 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 3097 uint32_t tx_stat_gtmca_lo; 3098 uint32_t tx_stat_gtmca_hi; 3099 uint32_t tx_stat_gtbca_lo; 3100 uint32_t tx_stat_gtbca_hi; 3101 uint32_t tx_stat_gtovr_lo; 3102 uint32_t tx_stat_gtovr_hi; 3103 uint32_t tx_stat_gtfrg_lo; 3104 uint32_t tx_stat_gtfrg_hi; 3105 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 3106 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 3107 uint32_t tx_stat_gt64_lo; 3108 uint32_t tx_stat_gt64_hi; 3109 uint32_t tx_stat_gt127_lo; 3110 uint32_t tx_stat_gt127_hi; 3111 uint32_t tx_stat_gt255_lo; 3112 uint32_t tx_stat_gt255_hi; 3113 uint32_t tx_stat_gt511_lo; 3114 uint32_t tx_stat_gt511_hi; 3115 uint32_t tx_stat_gt1023_lo; 3116 uint32_t tx_stat_gt1023_hi; 3117 uint32_t tx_stat_gt1518_lo; 3118 uint32_t tx_stat_gt1518_hi; 3119 uint32_t tx_stat_gt2047_lo; 3120 uint32_t tx_stat_gt2047_hi; 3121 uint32_t tx_stat_gt4095_lo; 3122 uint32_t tx_stat_gt4095_hi; 3123 uint32_t tx_stat_gt9216_lo; 3124 uint32_t tx_stat_gt9216_hi; 3125 uint32_t tx_stat_gt16383_lo; 3126 uint32_t tx_stat_gt16383_hi; 3127 uint32_t tx_stat_gtmax_lo; 3128 uint32_t tx_stat_gtmax_hi; 3129 uint32_t tx_stat_gtufl_lo; 3130 uint32_t tx_stat_gtufl_hi; 3131 uint32_t tx_stat_gterr_lo; 3132 uint32_t tx_stat_gterr_hi; 3133 uint32_t tx_stat_gtbyt_lo; 3134 uint32_t tx_stat_gtbyt_hi; 3135 3136 uint32_t rx_stat_gr64_lo; 3137 uint32_t rx_stat_gr64_hi; 3138 uint32_t rx_stat_gr127_lo; 3139 uint32_t rx_stat_gr127_hi; 3140 uint32_t rx_stat_gr255_lo; 3141 uint32_t rx_stat_gr255_hi; 3142 uint32_t rx_stat_gr511_lo; 3143 uint32_t rx_stat_gr511_hi; 3144 uint32_t rx_stat_gr1023_lo; 3145 uint32_t rx_stat_gr1023_hi; 3146 uint32_t rx_stat_gr1518_lo; 3147 uint32_t rx_stat_gr1518_hi; 3148 uint32_t rx_stat_gr2047_lo; 3149 uint32_t rx_stat_gr2047_hi; 3150 uint32_t rx_stat_gr4095_lo; 3151 uint32_t rx_stat_gr4095_hi; 3152 uint32_t rx_stat_gr9216_lo; 3153 uint32_t rx_stat_gr9216_hi; 3154 uint32_t rx_stat_gr16383_lo; 3155 uint32_t rx_stat_gr16383_hi; 3156 uint32_t rx_stat_grmax_lo; 3157 uint32_t rx_stat_grmax_hi; 3158 uint32_t rx_stat_grpkt_lo; 3159 uint32_t rx_stat_grpkt_hi; 3160 uint32_t rx_stat_grfcs_lo; 3161 uint32_t rx_stat_grfcs_hi; 3162 uint32_t rx_stat_gruca_lo; 3163 uint32_t rx_stat_gruca_hi; 3164 uint32_t rx_stat_grmca_lo; 3165 uint32_t rx_stat_grmca_hi; 3166 uint32_t rx_stat_grbca_lo; 3167 uint32_t rx_stat_grbca_hi; 3168 uint32_t rx_stat_grxpf_lo; /* grpf */ 3169 uint32_t rx_stat_grxpf_hi; /* grpf */ 3170 uint32_t rx_stat_grpp_lo; 3171 uint32_t rx_stat_grpp_hi; 3172 uint32_t rx_stat_grxuo_lo; /* gruo */ 3173 uint32_t rx_stat_grxuo_hi; /* gruo */ 3174 uint32_t rx_stat_grjbr_lo; 3175 uint32_t rx_stat_grjbr_hi; 3176 uint32_t rx_stat_grovr_lo; 3177 uint32_t rx_stat_grovr_hi; 3178 uint32_t rx_stat_grxcf_lo; /* grcf */ 3179 uint32_t rx_stat_grxcf_hi; /* grcf */ 3180 uint32_t rx_stat_grflr_lo; 3181 uint32_t rx_stat_grflr_hi; 3182 uint32_t rx_stat_grpok_lo; 3183 uint32_t rx_stat_grpok_hi; 3184 uint32_t rx_stat_grmeg_lo; 3185 uint32_t rx_stat_grmeg_hi; 3186 uint32_t rx_stat_grmeb_lo; 3187 uint32_t rx_stat_grmeb_hi; 3188 uint32_t rx_stat_grbyt_lo; 3189 uint32_t rx_stat_grbyt_hi; 3190 uint32_t rx_stat_grund_lo; 3191 uint32_t rx_stat_grund_hi; 3192 uint32_t rx_stat_grfrg_lo; 3193 uint32_t rx_stat_grfrg_hi; 3194 uint32_t rx_stat_grerb_lo; /* grerrbyt */ 3195 uint32_t rx_stat_grerb_hi; /* grerrbyt */ 3196 uint32_t rx_stat_grfre_lo; /* grfrerr */ 3197 uint32_t rx_stat_grfre_hi; /* grfrerr */ 3198 uint32_t rx_stat_gripj_lo; 3199 uint32_t rx_stat_gripj_hi; 3200 }; 3201 3202 struct mstat_stats { 3203 struct { 3204 /* OTE MSTAT on E3 has a bug where this register's contents are 3205 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 3206 */ 3207 uint32_t tx_gtxpok_lo; 3208 uint32_t tx_gtxpok_hi; 3209 uint32_t tx_gtxpf_lo; 3210 uint32_t tx_gtxpf_hi; 3211 uint32_t tx_gtxpp_lo; 3212 uint32_t tx_gtxpp_hi; 3213 uint32_t tx_gtfcs_lo; 3214 uint32_t tx_gtfcs_hi; 3215 uint32_t tx_gtuca_lo; 3216 uint32_t tx_gtuca_hi; 3217 uint32_t tx_gtmca_lo; 3218 uint32_t tx_gtmca_hi; 3219 uint32_t tx_gtgca_lo; 3220 uint32_t tx_gtgca_hi; 3221 uint32_t tx_gtpkt_lo; 3222 uint32_t tx_gtpkt_hi; 3223 uint32_t tx_gt64_lo; 3224 uint32_t tx_gt64_hi; 3225 uint32_t tx_gt127_lo; 3226 uint32_t tx_gt127_hi; 3227 uint32_t tx_gt255_lo; 3228 uint32_t tx_gt255_hi; 3229 uint32_t tx_gt511_lo; 3230 uint32_t tx_gt511_hi; 3231 uint32_t tx_gt1023_lo; 3232 uint32_t tx_gt1023_hi; 3233 uint32_t tx_gt1518_lo; 3234 uint32_t tx_gt1518_hi; 3235 uint32_t tx_gt2047_lo; 3236 uint32_t tx_gt2047_hi; 3237 uint32_t tx_gt4095_lo; 3238 uint32_t tx_gt4095_hi; 3239 uint32_t tx_gt9216_lo; 3240 uint32_t tx_gt9216_hi; 3241 uint32_t tx_gt16383_lo; 3242 uint32_t tx_gt16383_hi; 3243 uint32_t tx_gtufl_lo; 3244 uint32_t tx_gtufl_hi; 3245 uint32_t tx_gterr_lo; 3246 uint32_t tx_gterr_hi; 3247 uint32_t tx_gtbyt_lo; 3248 uint32_t tx_gtbyt_hi; 3249 uint32_t tx_collisions_lo; 3250 uint32_t tx_collisions_hi; 3251 uint32_t tx_singlecollision_lo; 3252 uint32_t tx_singlecollision_hi; 3253 uint32_t tx_multiplecollisions_lo; 3254 uint32_t tx_multiplecollisions_hi; 3255 uint32_t tx_deferred_lo; 3256 uint32_t tx_deferred_hi; 3257 uint32_t tx_excessivecollisions_lo; 3258 uint32_t tx_excessivecollisions_hi; 3259 uint32_t tx_latecollisions_lo; 3260 uint32_t tx_latecollisions_hi; 3261 } stats_tx; 3262 3263 struct { 3264 uint32_t rx_gr64_lo; 3265 uint32_t rx_gr64_hi; 3266 uint32_t rx_gr127_lo; 3267 uint32_t rx_gr127_hi; 3268 uint32_t rx_gr255_lo; 3269 uint32_t rx_gr255_hi; 3270 uint32_t rx_gr511_lo; 3271 uint32_t rx_gr511_hi; 3272 uint32_t rx_gr1023_lo; 3273 uint32_t rx_gr1023_hi; 3274 uint32_t rx_gr1518_lo; 3275 uint32_t rx_gr1518_hi; 3276 uint32_t rx_gr2047_lo; 3277 uint32_t rx_gr2047_hi; 3278 uint32_t rx_gr4095_lo; 3279 uint32_t rx_gr4095_hi; 3280 uint32_t rx_gr9216_lo; 3281 uint32_t rx_gr9216_hi; 3282 uint32_t rx_gr16383_lo; 3283 uint32_t rx_gr16383_hi; 3284 uint32_t rx_grpkt_lo; 3285 uint32_t rx_grpkt_hi; 3286 uint32_t rx_grfcs_lo; 3287 uint32_t rx_grfcs_hi; 3288 uint32_t rx_gruca_lo; 3289 uint32_t rx_gruca_hi; 3290 uint32_t rx_grmca_lo; 3291 uint32_t rx_grmca_hi; 3292 uint32_t rx_grbca_lo; 3293 uint32_t rx_grbca_hi; 3294 uint32_t rx_grxpf_lo; 3295 uint32_t rx_grxpf_hi; 3296 uint32_t rx_grxpp_lo; 3297 uint32_t rx_grxpp_hi; 3298 uint32_t rx_grxuo_lo; 3299 uint32_t rx_grxuo_hi; 3300 uint32_t rx_grovr_lo; 3301 uint32_t rx_grovr_hi; 3302 uint32_t rx_grxcf_lo; 3303 uint32_t rx_grxcf_hi; 3304 uint32_t rx_grflr_lo; 3305 uint32_t rx_grflr_hi; 3306 uint32_t rx_grpok_lo; 3307 uint32_t rx_grpok_hi; 3308 uint32_t rx_grbyt_lo; 3309 uint32_t rx_grbyt_hi; 3310 uint32_t rx_grund_lo; 3311 uint32_t rx_grund_hi; 3312 uint32_t rx_grfrg_lo; 3313 uint32_t rx_grfrg_hi; 3314 uint32_t rx_grerb_lo; 3315 uint32_t rx_grerb_hi; 3316 uint32_t rx_grfre_lo; 3317 uint32_t rx_grfre_hi; 3318 3319 uint32_t rx_alignmenterrors_lo; 3320 uint32_t rx_alignmenterrors_hi; 3321 uint32_t rx_falsecarrier_lo; 3322 uint32_t rx_falsecarrier_hi; 3323 uint32_t rx_llfcmsgcnt_lo; 3324 uint32_t rx_llfcmsgcnt_hi; 3325 } stats_rx; 3326 }; 3327 3328 union mac_stats { 3329 struct emac_stats emac_stats; 3330 struct bmac1_stats bmac1_stats; 3331 struct bmac2_stats bmac2_stats; 3332 struct mstat_stats mstat_stats; 3333 }; 3334 3335 3336 struct mac_stx { 3337 /* in_bad_octets */ 3338 uint32_t rx_stat_ifhcinbadoctets_hi; 3339 uint32_t rx_stat_ifhcinbadoctets_lo; 3340 3341 /* out_bad_octets */ 3342 uint32_t tx_stat_ifhcoutbadoctets_hi; 3343 uint32_t tx_stat_ifhcoutbadoctets_lo; 3344 3345 /* crc_receive_errors */ 3346 uint32_t rx_stat_dot3statsfcserrors_hi; 3347 uint32_t rx_stat_dot3statsfcserrors_lo; 3348 /* alignment_errors */ 3349 uint32_t rx_stat_dot3statsalignmenterrors_hi; 3350 uint32_t rx_stat_dot3statsalignmenterrors_lo; 3351 /* carrier_sense_errors */ 3352 uint32_t rx_stat_dot3statscarriersenseerrors_hi; 3353 uint32_t rx_stat_dot3statscarriersenseerrors_lo; 3354 /* false_carrier_detections */ 3355 uint32_t rx_stat_falsecarriererrors_hi; 3356 uint32_t rx_stat_falsecarriererrors_lo; 3357 3358 /* runt_packets_received */ 3359 uint32_t rx_stat_etherstatsundersizepkts_hi; 3360 uint32_t rx_stat_etherstatsundersizepkts_lo; 3361 /* jabber_packets_received */ 3362 uint32_t rx_stat_dot3statsframestoolong_hi; 3363 uint32_t rx_stat_dot3statsframestoolong_lo; 3364 3365 /* error_runt_packets_received */ 3366 uint32_t rx_stat_etherstatsfragments_hi; 3367 uint32_t rx_stat_etherstatsfragments_lo; 3368 /* error_jabber_packets_received */ 3369 uint32_t rx_stat_etherstatsjabbers_hi; 3370 uint32_t rx_stat_etherstatsjabbers_lo; 3371 3372 /* control_frames_received */ 3373 uint32_t rx_stat_maccontrolframesreceived_hi; 3374 uint32_t rx_stat_maccontrolframesreceived_lo; 3375 uint32_t rx_stat_mac_xpf_hi; 3376 uint32_t rx_stat_mac_xpf_lo; 3377 uint32_t rx_stat_mac_xcf_hi; 3378 uint32_t rx_stat_mac_xcf_lo; 3379 3380 /* xoff_state_entered */ 3381 uint32_t rx_stat_xoffstateentered_hi; 3382 uint32_t rx_stat_xoffstateentered_lo; 3383 /* pause_xon_frames_received */ 3384 uint32_t rx_stat_xonpauseframesreceived_hi; 3385 uint32_t rx_stat_xonpauseframesreceived_lo; 3386 /* pause_xoff_frames_received */ 3387 uint32_t rx_stat_xoffpauseframesreceived_hi; 3388 uint32_t rx_stat_xoffpauseframesreceived_lo; 3389 /* pause_xon_frames_transmitted */ 3390 uint32_t tx_stat_outxonsent_hi; 3391 uint32_t tx_stat_outxonsent_lo; 3392 /* pause_xoff_frames_transmitted */ 3393 uint32_t tx_stat_outxoffsent_hi; 3394 uint32_t tx_stat_outxoffsent_lo; 3395 /* flow_control_done */ 3396 uint32_t tx_stat_flowcontroldone_hi; 3397 uint32_t tx_stat_flowcontroldone_lo; 3398 3399 /* ether_stats_collisions */ 3400 uint32_t tx_stat_etherstatscollisions_hi; 3401 uint32_t tx_stat_etherstatscollisions_lo; 3402 /* single_collision_transmit_frames */ 3403 uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3404 uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3405 /* multiple_collision_transmit_frames */ 3406 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3407 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3408 /* deferred_transmissions */ 3409 uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3410 uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3411 /* excessive_collision_frames */ 3412 uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3413 uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3414 /* late_collision_frames */ 3415 uint32_t tx_stat_dot3statslatecollisions_hi; 3416 uint32_t tx_stat_dot3statslatecollisions_lo; 3417 3418 /* frames_transmitted_64_bytes */ 3419 uint32_t tx_stat_etherstatspkts64octets_hi; 3420 uint32_t tx_stat_etherstatspkts64octets_lo; 3421 /* frames_transmitted_65_127_bytes */ 3422 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3423 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3424 /* frames_transmitted_128_255_bytes */ 3425 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3426 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3427 /* frames_transmitted_256_511_bytes */ 3428 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3429 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3430 /* frames_transmitted_512_1023_bytes */ 3431 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3432 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3433 /* frames_transmitted_1024_1522_bytes */ 3434 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3435 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3436 /* frames_transmitted_1523_9022_bytes */ 3437 uint32_t tx_stat_etherstatspktsover1522octets_hi; 3438 uint32_t tx_stat_etherstatspktsover1522octets_lo; 3439 uint32_t tx_stat_mac_2047_hi; 3440 uint32_t tx_stat_mac_2047_lo; 3441 uint32_t tx_stat_mac_4095_hi; 3442 uint32_t tx_stat_mac_4095_lo; 3443 uint32_t tx_stat_mac_9216_hi; 3444 uint32_t tx_stat_mac_9216_lo; 3445 uint32_t tx_stat_mac_16383_hi; 3446 uint32_t tx_stat_mac_16383_lo; 3447 3448 /* internal_mac_transmit_errors */ 3449 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3450 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3451 3452 /* if_out_discards */ 3453 uint32_t tx_stat_mac_ufl_hi; 3454 uint32_t tx_stat_mac_ufl_lo; 3455 }; 3456 3457 3458 #define MAC_STX_IDX_MAX 2 3459 3460 struct host_port_stats { 3461 uint32_t host_port_stats_counter; 3462 3463 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3464 3465 uint32_t brb_drop_hi; 3466 uint32_t brb_drop_lo; 3467 3468 uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3469 3470 uint32_t pfc_frames_tx_hi; 3471 uint32_t pfc_frames_tx_lo; 3472 uint32_t pfc_frames_rx_hi; 3473 uint32_t pfc_frames_rx_lo; 3474 3475 uint32_t eee_lpi_count_hi; 3476 uint32_t eee_lpi_count_lo; 3477 }; 3478 3479 3480 struct host_func_stats { 3481 uint32_t host_func_stats_start; 3482 3483 uint32_t total_bytes_received_hi; 3484 uint32_t total_bytes_received_lo; 3485 3486 uint32_t total_bytes_transmitted_hi; 3487 uint32_t total_bytes_transmitted_lo; 3488 3489 uint32_t total_unicast_packets_received_hi; 3490 uint32_t total_unicast_packets_received_lo; 3491 3492 uint32_t total_multicast_packets_received_hi; 3493 uint32_t total_multicast_packets_received_lo; 3494 3495 uint32_t total_broadcast_packets_received_hi; 3496 uint32_t total_broadcast_packets_received_lo; 3497 3498 uint32_t total_unicast_packets_transmitted_hi; 3499 uint32_t total_unicast_packets_transmitted_lo; 3500 3501 uint32_t total_multicast_packets_transmitted_hi; 3502 uint32_t total_multicast_packets_transmitted_lo; 3503 3504 uint32_t total_broadcast_packets_transmitted_hi; 3505 uint32_t total_broadcast_packets_transmitted_lo; 3506 3507 uint32_t valid_bytes_received_hi; 3508 uint32_t valid_bytes_received_lo; 3509 3510 uint32_t host_func_stats_end; 3511 }; 3512 3513 /* VIC definitions */ 3514 #define VICSTATST_UIF_INDEX 2 3515 3516 /* 3517 * stats collected for afex. 3518 * NOTE: structure is exactly as expected to be received by the switch. 3519 * order must remain exactly as is unless protocol changes ! 3520 */ 3521 struct afex_stats { 3522 uint32_t tx_unicast_frames_hi; 3523 uint32_t tx_unicast_frames_lo; 3524 uint32_t tx_unicast_bytes_hi; 3525 uint32_t tx_unicast_bytes_lo; 3526 uint32_t tx_multicast_frames_hi; 3527 uint32_t tx_multicast_frames_lo; 3528 uint32_t tx_multicast_bytes_hi; 3529 uint32_t tx_multicast_bytes_lo; 3530 uint32_t tx_broadcast_frames_hi; 3531 uint32_t tx_broadcast_frames_lo; 3532 uint32_t tx_broadcast_bytes_hi; 3533 uint32_t tx_broadcast_bytes_lo; 3534 uint32_t tx_frames_discarded_hi; 3535 uint32_t tx_frames_discarded_lo; 3536 uint32_t tx_frames_dropped_hi; 3537 uint32_t tx_frames_dropped_lo; 3538 3539 uint32_t rx_unicast_frames_hi; 3540 uint32_t rx_unicast_frames_lo; 3541 uint32_t rx_unicast_bytes_hi; 3542 uint32_t rx_unicast_bytes_lo; 3543 uint32_t rx_multicast_frames_hi; 3544 uint32_t rx_multicast_frames_lo; 3545 uint32_t rx_multicast_bytes_hi; 3546 uint32_t rx_multicast_bytes_lo; 3547 uint32_t rx_broadcast_frames_hi; 3548 uint32_t rx_broadcast_frames_lo; 3549 uint32_t rx_broadcast_bytes_hi; 3550 uint32_t rx_broadcast_bytes_lo; 3551 uint32_t rx_frames_discarded_hi; 3552 uint32_t rx_frames_discarded_lo; 3553 uint32_t rx_frames_dropped_hi; 3554 uint32_t rx_frames_dropped_lo; 3555 }; 3556 3557 /* To maintain backward compatibility between FW and drivers, new elements */ 3558 /* should be added to the end of the structure. */ 3559 3560 /* Per Port Statistics */ 3561 struct port_info { 3562 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3563 uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3564 uint32_t link_speed; /* multiplier of 100Mb */ 3565 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3566 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3567 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3568 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3569 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3570 This is flagged by Consumer as an error. */ 3571 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3572 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3573 uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3574 uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3575 uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3576 uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3577 uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3578 uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3579 uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3580 uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3581 uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3582 uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3583 uint32_t tx_errors; /* TX Errors */ 3584 uint32_t tx_discards; /* TX Discards */ 3585 uint32_t rx_frames_lo; /* RX Frames received */ 3586 uint32_t rx_frames_hi; /* RX Frames received */ 3587 uint32_t rx_bytes_lo; /* RX Bytes received */ 3588 uint32_t rx_bytes_hi; /* RX Bytes received */ 3589 uint32_t tx_frames_lo; /* TX Frames sent */ 3590 uint32_t tx_frames_hi; /* TX Frames sent */ 3591 uint32_t tx_bytes_lo; /* TX Bytes sent */ 3592 uint32_t tx_bytes_hi; /* TX Bytes sent */ 3593 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3594 1:1 bit for link good, 3595 2:1 Set if link changed between last poll. */ 3596 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3597 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3598 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3599 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3600 }; 3601 3602 3603 #define BNX2X_5710_FW_MAJOR_VERSION 7 3604 #define BNX2X_5710_FW_MINOR_VERSION 13 3605 #define BNX2X_5710_FW_REVISION_VERSION 11 3606 #define BNX2X_5710_FW_ENGINEERING_VERSION 0 3607 #define BNX2X_5710_FW_COMPILE_FLAGS 1 3608 3609 3610 /* 3611 * attention bits 3612 */ 3613 struct atten_sp_status_block { 3614 __le32 attn_bits; 3615 __le32 attn_bits_ack; 3616 uint8_t status_block_id; 3617 uint8_t reserved0; 3618 __le16 attn_bits_index; 3619 __le32 reserved1; 3620 }; 3621 3622 3623 /* 3624 * The eth aggregative context of Cstorm 3625 */ 3626 struct cstorm_eth_ag_context { 3627 uint32_t __reserved0[10]; 3628 }; 3629 3630 3631 /* 3632 * dmae command structure 3633 */ 3634 struct dmae_command { 3635 uint32_t opcode; 3636 #define DMAE_COMMAND_SRC (0x1 << 0) 3637 #define DMAE_COMMAND_SRC_SHIFT 0 3638 #define DMAE_COMMAND_DST (0x3 << 1) 3639 #define DMAE_COMMAND_DST_SHIFT 1 3640 #define DMAE_COMMAND_C_DST (0x1 << 3) 3641 #define DMAE_COMMAND_C_DST_SHIFT 3 3642 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1 << 4) 3643 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3644 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1 << 5) 3645 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3646 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7 << 6) 3647 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3648 #define DMAE_COMMAND_ENDIANITY (0x3 << 9) 3649 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 3650 #define DMAE_COMMAND_PORT (0x1 << 11) 3651 #define DMAE_COMMAND_PORT_SHIFT 11 3652 #define DMAE_COMMAND_CRC_RESET (0x1 << 12) 3653 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 3654 #define DMAE_COMMAND_SRC_RESET (0x1 << 13) 3655 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 3656 #define DMAE_COMMAND_DST_RESET (0x1 << 14) 3657 #define DMAE_COMMAND_DST_RESET_SHIFT 14 3658 #define DMAE_COMMAND_E1HVN (0x3 << 15) 3659 #define DMAE_COMMAND_E1HVN_SHIFT 15 3660 #define DMAE_COMMAND_DST_VN (0x3 << 17) 3661 #define DMAE_COMMAND_DST_VN_SHIFT 17 3662 #define DMAE_COMMAND_C_FUNC (0x1 << 19) 3663 #define DMAE_COMMAND_C_FUNC_SHIFT 19 3664 #define DMAE_COMMAND_ERR_POLICY (0x3 << 20) 3665 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3666 #define DMAE_COMMAND_RESERVED0 (0x3FF << 22) 3667 #define DMAE_COMMAND_RESERVED0_SHIFT 22 3668 uint32_t src_addr_lo; 3669 uint32_t src_addr_hi; 3670 uint32_t dst_addr_lo; 3671 uint32_t dst_addr_hi; 3672 #if defined(__BIG_ENDIAN) 3673 uint16_t opcode_iov; 3674 #define DMAE_COMMAND_SRC_VFID (0x3F << 0) 3675 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 3676 #define DMAE_COMMAND_SRC_VFPF (0x1 << 6) 3677 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3678 #define DMAE_COMMAND_RESERVED1 (0x1 << 7) 3679 #define DMAE_COMMAND_RESERVED1_SHIFT 7 3680 #define DMAE_COMMAND_DST_VFID (0x3F << 8) 3681 #define DMAE_COMMAND_DST_VFID_SHIFT 8 3682 #define DMAE_COMMAND_DST_VFPF (0x1 << 14) 3683 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 3684 #define DMAE_COMMAND_RESERVED2 (0x1 << 15) 3685 #define DMAE_COMMAND_RESERVED2_SHIFT 15 3686 uint16_t len; 3687 #elif defined(__LITTLE_ENDIAN) 3688 uint16_t len; 3689 uint16_t opcode_iov; 3690 #define DMAE_COMMAND_SRC_VFID (0x3F << 0) 3691 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 3692 #define DMAE_COMMAND_SRC_VFPF (0x1 << 6) 3693 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3694 #define DMAE_COMMAND_RESERVED1 (0x1 << 7) 3695 #define DMAE_COMMAND_RESERVED1_SHIFT 7 3696 #define DMAE_COMMAND_DST_VFID (0x3F << 8) 3697 #define DMAE_COMMAND_DST_VFID_SHIFT 8 3698 #define DMAE_COMMAND_DST_VFPF (0x1 << 14) 3699 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 3700 #define DMAE_COMMAND_RESERVED2 (0x1 << 15) 3701 #define DMAE_COMMAND_RESERVED2_SHIFT 15 3702 #endif 3703 uint32_t comp_addr_lo; 3704 uint32_t comp_addr_hi; 3705 uint32_t comp_val; 3706 uint32_t crc32; 3707 uint32_t crc32_c; 3708 #if defined(__BIG_ENDIAN) 3709 uint16_t crc16_c; 3710 uint16_t crc16; 3711 #elif defined(__LITTLE_ENDIAN) 3712 uint16_t crc16; 3713 uint16_t crc16_c; 3714 #endif 3715 #if defined(__BIG_ENDIAN) 3716 uint16_t reserved3; 3717 uint16_t crc_t10; 3718 #elif defined(__LITTLE_ENDIAN) 3719 uint16_t crc_t10; 3720 uint16_t reserved3; 3721 #endif 3722 #if defined(__BIG_ENDIAN) 3723 uint16_t xsum8; 3724 uint16_t xsum16; 3725 #elif defined(__LITTLE_ENDIAN) 3726 uint16_t xsum16; 3727 uint16_t xsum8; 3728 #endif 3729 }; 3730 3731 3732 /* 3733 * common data for all protocols 3734 */ 3735 struct doorbell_hdr { 3736 uint8_t header; 3737 #define DOORBELL_HDR_RX (0x1 << 0) 3738 #define DOORBELL_HDR_RX_SHIFT 0 3739 #define DOORBELL_HDR_DB_TYPE (0x1 << 1) 3740 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 3741 #define DOORBELL_HDR_DPM_SIZE (0x3 << 2) 3742 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3743 #define DOORBELL_HDR_CONN_TYPE (0xF << 4) 3744 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3745 }; 3746 3747 /* 3748 * Ethernet doorbell 3749 */ 3750 struct eth_tx_doorbell { 3751 #if defined(__BIG_ENDIAN) 3752 uint16_t npackets; 3753 uint8_t params; 3754 #define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0) 3755 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3756 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6) 3757 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3758 #define ETH_TX_DOORBELL_SPARE (0x1 << 7) 3759 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3760 struct doorbell_hdr hdr; 3761 #elif defined(__LITTLE_ENDIAN) 3762 struct doorbell_hdr hdr; 3763 uint8_t params; 3764 #define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0) 3765 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3766 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6) 3767 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3768 #define ETH_TX_DOORBELL_SPARE (0x1 << 7) 3769 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3770 uint16_t npackets; 3771 #endif 3772 }; 3773 3774 3775 /* 3776 * 3 lines. status block 3777 */ 3778 struct hc_status_block_e1x { 3779 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3780 __le16 running_index[HC_SB_MAX_SM]; 3781 __le32 rsrv[11]; 3782 }; 3783 3784 /* 3785 * host status block 3786 */ 3787 struct host_hc_status_block_e1x { 3788 struct hc_status_block_e1x sb; 3789 }; 3790 3791 3792 /* 3793 * 3 lines. status block 3794 */ 3795 struct hc_status_block_e2 { 3796 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3797 __le16 running_index[HC_SB_MAX_SM]; 3798 __le32 reserved[11]; 3799 }; 3800 3801 /* 3802 * host status block 3803 */ 3804 struct host_hc_status_block_e2 { 3805 struct hc_status_block_e2 sb; 3806 }; 3807 3808 3809 /* 3810 * 5 lines. slow-path status block 3811 */ 3812 struct hc_sp_status_block { 3813 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3814 __le16 running_index; 3815 __le16 rsrv; 3816 uint32_t rsrv1; 3817 }; 3818 3819 /* 3820 * host status block 3821 */ 3822 struct host_sp_status_block { 3823 struct atten_sp_status_block atten_status_block; 3824 struct hc_sp_status_block sp_sb; 3825 }; 3826 3827 3828 /* 3829 * IGU driver acknowledgment register 3830 */ 3831 struct igu_ack_register { 3832 #if defined(__BIG_ENDIAN) 3833 uint16_t sb_id_and_flags; 3834 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0) 3835 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3836 #define IGU_ACK_REGISTER_STORM_ID (0x7 << 5) 3837 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3838 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8) 3839 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3840 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9) 3841 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3842 #define IGU_ACK_REGISTER_RESERVED (0x1F << 11) 3843 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3844 uint16_t status_block_index; 3845 #elif defined(__LITTLE_ENDIAN) 3846 uint16_t status_block_index; 3847 uint16_t sb_id_and_flags; 3848 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0) 3849 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3850 #define IGU_ACK_REGISTER_STORM_ID (0x7 << 5) 3851 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3852 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8) 3853 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3854 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9) 3855 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3856 #define IGU_ACK_REGISTER_RESERVED (0x1F << 11) 3857 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3858 #endif 3859 }; 3860 3861 3862 /* 3863 * IGU driver acknowledgement register 3864 */ 3865 struct igu_backward_compatible { 3866 uint32_t sb_id_and_flags; 3867 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF << 0) 3868 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3869 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F << 16) 3870 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3871 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7 << 21) 3872 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3873 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1 << 24) 3874 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3875 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3 << 25) 3876 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3877 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F << 27) 3878 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3879 uint32_t reserved_2; 3880 }; 3881 3882 3883 /* 3884 * IGU driver acknowledgement register 3885 */ 3886 struct igu_regular { 3887 uint32_t sb_id_and_flags; 3888 #define IGU_REGULAR_SB_INDEX (0xFFFFF << 0) 3889 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3890 #define IGU_REGULAR_RESERVED0 (0x1 << 20) 3891 #define IGU_REGULAR_RESERVED0_SHIFT 20 3892 #define IGU_REGULAR_SEGMENT_ACCESS (0x7 << 21) 3893 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3894 #define IGU_REGULAR_BUPDATE (0x1 << 24) 3895 #define IGU_REGULAR_BUPDATE_SHIFT 24 3896 #define IGU_REGULAR_ENABLE_INT (0x3 << 25) 3897 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3898 #define IGU_REGULAR_RESERVED_1 (0x1 << 27) 3899 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3900 #define IGU_REGULAR_CLEANUP_TYPE (0x3 << 28) 3901 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3902 #define IGU_REGULAR_CLEANUP_SET (0x1 << 30) 3903 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3904 #define IGU_REGULAR_BCLEANUP (0x1 << 31) 3905 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3906 uint32_t reserved_2; 3907 }; 3908 3909 /* 3910 * IGU driver acknowledgement register 3911 */ 3912 union igu_consprod_reg { 3913 struct igu_regular regular; 3914 struct igu_backward_compatible backward_compatible; 3915 }; 3916 3917 3918 /* 3919 * Igu control commands 3920 */ 3921 enum igu_ctrl_cmd { 3922 IGU_CTRL_CMD_TYPE_RD, 3923 IGU_CTRL_CMD_TYPE_WR, 3924 MAX_IGU_CTRL_CMD}; 3925 3926 3927 /* 3928 * Control register for the IGU command register 3929 */ 3930 struct igu_ctrl_reg { 3931 uint32_t ctrl_data; 3932 #define IGU_CTRL_REG_ADDRESS (0xFFF << 0) 3933 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3934 #define IGU_CTRL_REG_FID (0x7F << 12) 3935 #define IGU_CTRL_REG_FID_SHIFT 12 3936 #define IGU_CTRL_REG_RESERVED (0x1 << 19) 3937 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3938 #define IGU_CTRL_REG_TYPE (0x1 << 20) 3939 #define IGU_CTRL_REG_TYPE_SHIFT 20 3940 #define IGU_CTRL_REG_UNUSED (0x7FF << 21) 3941 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3942 }; 3943 3944 3945 /* 3946 * Igu interrupt command 3947 */ 3948 enum igu_int_cmd { 3949 IGU_INT_ENABLE, 3950 IGU_INT_DISABLE, 3951 IGU_INT_NOP, 3952 IGU_INT_NOP2, 3953 MAX_IGU_INT_CMD}; 3954 3955 3956 /* 3957 * Igu segments 3958 */ 3959 enum igu_seg_access { 3960 IGU_SEG_ACCESS_NORM, 3961 IGU_SEG_ACCESS_DEF, 3962 IGU_SEG_ACCESS_ATTN, 3963 MAX_IGU_SEG_ACCESS}; 3964 3965 3966 /* 3967 * Parser parsing flags field 3968 */ 3969 struct parsing_flags { 3970 __le16 flags; 3971 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1 << 0) 3972 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3973 #define PARSING_FLAGS_VLAN (0x1 << 1) 3974 #define PARSING_FLAGS_VLAN_SHIFT 1 3975 #define PARSING_FLAGS_EXTRA_VLAN (0x1 << 2) 3976 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3977 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3 << 3) 3978 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3979 #define PARSING_FLAGS_IP_OPTIONS (0x1 << 5) 3980 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3981 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1 << 6) 3982 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3983 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3 << 7) 3984 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3985 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1 << 9) 3986 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3987 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1 << 10) 3988 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3989 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1 << 11) 3990 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3991 #define PARSING_FLAGS_CONNECTION_MATCH (0x1 << 12) 3992 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3993 #define PARSING_FLAGS_LLC_SNAP (0x1 << 13) 3994 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3995 #define PARSING_FLAGS_RESERVED0 (0x3 << 14) 3996 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3997 }; 3998 3999 4000 /* 4001 * Parsing flags for TCP ACK type 4002 */ 4003 enum prs_flags_ack_type { 4004 PRS_FLAG_PUREACK_PIGGY, 4005 PRS_FLAG_PUREACK_PURE, 4006 MAX_PRS_FLAGS_ACK_TYPE}; 4007 4008 4009 /* 4010 * Parsing flags for Ethernet address type 4011 */ 4012 enum prs_flags_eth_addr_type { 4013 PRS_FLAG_ETHTYPE_NON_UNICAST, 4014 PRS_FLAG_ETHTYPE_UNICAST, 4015 MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 4016 4017 4018 /* 4019 * Parsing flags for over-ethernet protocol 4020 */ 4021 enum prs_flags_over_eth { 4022 PRS_FLAG_OVERETH_UNKNOWN, 4023 PRS_FLAG_OVERETH_IPV4, 4024 PRS_FLAG_OVERETH_IPV6, 4025 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 4026 MAX_PRS_FLAGS_OVER_ETH}; 4027 4028 4029 /* 4030 * Parsing flags for over-IP protocol 4031 */ 4032 enum prs_flags_over_ip { 4033 PRS_FLAG_OVERIP_UNKNOWN, 4034 PRS_FLAG_OVERIP_TCP, 4035 PRS_FLAG_OVERIP_UDP, 4036 MAX_PRS_FLAGS_OVER_IP}; 4037 4038 4039 /* 4040 * SDM operation gen command (generate aggregative interrupt) 4041 */ 4042 struct sdm_op_gen { 4043 __le32 command; 4044 #define SDM_OP_GEN_COMP_PARAM (0x1F << 0) 4045 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 4046 #define SDM_OP_GEN_COMP_TYPE (0x7 << 5) 4047 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 4048 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF << 8) 4049 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 4050 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1 << 16) 4051 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 4052 #define SDM_OP_GEN_RESERVED (0x7FFF << 17) 4053 #define SDM_OP_GEN_RESERVED_SHIFT 17 4054 }; 4055 4056 4057 /* 4058 * Timers connection context 4059 */ 4060 struct timers_block_context { 4061 uint32_t __reserved_0; 4062 uint32_t __reserved_1; 4063 uint32_t __reserved_2; 4064 uint32_t flags; 4065 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3 << 0) 4066 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 4067 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1 << 2) 4068 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 4069 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF << 3) 4070 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 4071 }; 4072 4073 4074 /* 4075 * The eth aggregative context of Tstorm 4076 */ 4077 struct tstorm_eth_ag_context { 4078 uint32_t __reserved0[14]; 4079 }; 4080 4081 4082 /* 4083 * The eth aggregative context of Ustorm 4084 */ 4085 struct ustorm_eth_ag_context { 4086 uint32_t __reserved0; 4087 #if defined(__BIG_ENDIAN) 4088 uint8_t cdu_usage; 4089 uint8_t __reserved2; 4090 uint16_t __reserved1; 4091 #elif defined(__LITTLE_ENDIAN) 4092 uint16_t __reserved1; 4093 uint8_t __reserved2; 4094 uint8_t cdu_usage; 4095 #endif 4096 uint32_t __reserved3[6]; 4097 }; 4098 4099 4100 /* 4101 * The eth aggregative context of Xstorm 4102 */ 4103 struct xstorm_eth_ag_context { 4104 uint32_t reserved0; 4105 #if defined(__BIG_ENDIAN) 4106 uint8_t cdu_reserved; 4107 uint8_t reserved2; 4108 uint16_t reserved1; 4109 #elif defined(__LITTLE_ENDIAN) 4110 uint16_t reserved1; 4111 uint8_t reserved2; 4112 uint8_t cdu_reserved; 4113 #endif 4114 uint32_t reserved3[30]; 4115 }; 4116 4117 4118 /* 4119 * doorbell message sent to the chip 4120 */ 4121 struct doorbell { 4122 #if defined(__BIG_ENDIAN) 4123 uint16_t zero_fill2; 4124 uint8_t zero_fill1; 4125 struct doorbell_hdr header; 4126 #elif defined(__LITTLE_ENDIAN) 4127 struct doorbell_hdr header; 4128 uint8_t zero_fill1; 4129 uint16_t zero_fill2; 4130 #endif 4131 }; 4132 4133 4134 /* 4135 * doorbell message sent to the chip 4136 */ 4137 struct doorbell_set_prod { 4138 #if defined(__BIG_ENDIAN) 4139 uint16_t prod; 4140 uint8_t zero_fill1; 4141 struct doorbell_hdr header; 4142 #elif defined(__LITTLE_ENDIAN) 4143 struct doorbell_hdr header; 4144 uint8_t zero_fill1; 4145 uint16_t prod; 4146 #endif 4147 }; 4148 4149 4150 struct regpair { 4151 __le32 lo; 4152 __le32 hi; 4153 }; 4154 4155 4156 struct regpair_native { 4157 uint32_t lo; 4158 uint32_t hi; 4159 }; 4160 4161 4162 /* 4163 * Classify rule opcodes in E2/E3 4164 */ 4165 enum classify_rule { 4166 CLASSIFY_RULE_OPCODE_MAC, 4167 CLASSIFY_RULE_OPCODE_VLAN, 4168 CLASSIFY_RULE_OPCODE_PAIR, 4169 CLASSIFY_RULE_OPCODE_IMAC_VNI, 4170 MAX_CLASSIFY_RULE}; 4171 4172 4173 /* 4174 * Classify rule types in E2/E3 4175 */ 4176 enum classify_rule_action_type { 4177 CLASSIFY_RULE_REMOVE, 4178 CLASSIFY_RULE_ADD, 4179 MAX_CLASSIFY_RULE_ACTION_TYPE}; 4180 4181 4182 /* 4183 * client init ramrod data 4184 */ 4185 struct client_init_general_data { 4186 uint8_t client_id; 4187 uint8_t statistics_counter_id; 4188 uint8_t statistics_en_flg; 4189 uint8_t is_fcoe_flg; 4190 uint8_t activate_flg; 4191 uint8_t sp_client_id; 4192 __le16 mtu; 4193 uint8_t statistics_zero_flg; 4194 uint8_t func_id; 4195 uint8_t cos; 4196 uint8_t traffic_type; 4197 uint8_t fp_hsi_ver; 4198 uint8_t reserved0[3]; 4199 }; 4200 4201 4202 /* 4203 * client init rx data 4204 */ 4205 struct client_init_rx_data { 4206 uint8_t tpa_en; 4207 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1 << 0) 4208 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 4209 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1 << 1) 4210 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 4211 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1 << 2) 4212 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 4213 #define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1 << 3) 4214 #define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3 4215 #define CLIENT_INIT_RX_DATA_RESERVED5 (0xF << 4) 4216 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4 4217 uint8_t vmqueue_mode_en_flg; 4218 uint8_t extra_data_over_sgl_en_flg; 4219 uint8_t cache_line_alignment_log_size; 4220 uint8_t enable_dynamic_hc; 4221 uint8_t max_sges_for_packet; 4222 uint8_t client_qzone_id; 4223 uint8_t drop_ip_cs_err_flg; 4224 uint8_t drop_tcp_cs_err_flg; 4225 uint8_t drop_ttl0_flg; 4226 uint8_t drop_udp_cs_err_flg; 4227 uint8_t inner_vlan_removal_enable_flg; 4228 uint8_t outer_vlan_removal_enable_flg; 4229 uint8_t status_block_id; 4230 uint8_t rx_sb_index_number; 4231 uint8_t dont_verify_rings_pause_thr_flg; 4232 uint8_t max_tpa_queues; 4233 uint8_t silent_vlan_removal_flg; 4234 __le16 max_bytes_on_bd; 4235 __le16 sge_buff_size; 4236 uint8_t approx_mcast_engine_id; 4237 uint8_t rss_engine_id; 4238 struct regpair bd_page_base; 4239 struct regpair sge_page_base; 4240 struct regpair cqe_page_base; 4241 uint8_t is_leading_rss; 4242 uint8_t is_approx_mcast; 4243 __le16 max_agg_size; 4244 __le16 state; 4245 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1 << 0) 4246 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 4247 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1 << 1) 4248 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 4249 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1 << 2) 4250 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4251 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1 << 3) 4252 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 4253 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1 << 4) 4254 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 4255 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1 << 5) 4256 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 4257 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1 << 6) 4258 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 4259 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF << 7) 4260 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 4261 __le16 cqe_pause_thr_low; 4262 __le16 cqe_pause_thr_high; 4263 __le16 bd_pause_thr_low; 4264 __le16 bd_pause_thr_high; 4265 __le16 sge_pause_thr_low; 4266 __le16 sge_pause_thr_high; 4267 __le16 rx_cos_mask; 4268 __le16 silent_vlan_value; 4269 __le16 silent_vlan_mask; 4270 uint8_t handle_ptp_pkts_flg; 4271 uint8_t reserved6[3]; 4272 __le32 reserved7; 4273 }; 4274 4275 /* 4276 * client init tx data 4277 */ 4278 struct client_init_tx_data { 4279 uint8_t enforce_security_flg; 4280 uint8_t tx_status_block_id; 4281 uint8_t tx_sb_index_number; 4282 uint8_t tss_leading_client_id; 4283 uint8_t tx_switching_flg; 4284 uint8_t anti_spoofing_flg; 4285 __le16 default_vlan; 4286 struct regpair tx_bd_page_base; 4287 __le16 state; 4288 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1 << 0) 4289 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 4290 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1 << 1) 4291 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 4292 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1 << 2) 4293 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 4294 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1 << 3) 4295 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 4296 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF << 4) 4297 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 4298 uint8_t default_vlan_flg; 4299 uint8_t force_default_pri_flg; 4300 uint8_t tunnel_lso_inc_ip_id; 4301 uint8_t refuse_outband_vlan_flg; 4302 uint8_t tunnel_non_lso_pcsum_location; 4303 uint8_t tunnel_non_lso_outer_ip_csum_location; 4304 }; 4305 4306 /* 4307 * client init ramrod data 4308 */ 4309 struct client_init_ramrod_data { 4310 struct client_init_general_data general; 4311 struct client_init_rx_data rx; 4312 struct client_init_tx_data tx; 4313 }; 4314 4315 4316 /* 4317 * client update ramrod data 4318 */ 4319 struct client_update_ramrod_data { 4320 uint8_t client_id; 4321 uint8_t func_id; 4322 uint8_t inner_vlan_removal_enable_flg; 4323 uint8_t inner_vlan_removal_change_flg; 4324 uint8_t outer_vlan_removal_enable_flg; 4325 uint8_t outer_vlan_removal_change_flg; 4326 uint8_t anti_spoofing_enable_flg; 4327 uint8_t anti_spoofing_change_flg; 4328 uint8_t activate_flg; 4329 uint8_t activate_change_flg; 4330 __le16 default_vlan; 4331 uint8_t default_vlan_enable_flg; 4332 uint8_t default_vlan_change_flg; 4333 __le16 silent_vlan_value; 4334 __le16 silent_vlan_mask; 4335 uint8_t silent_vlan_removal_flg; 4336 uint8_t silent_vlan_change_flg; 4337 uint8_t refuse_outband_vlan_flg; 4338 uint8_t refuse_outband_vlan_change_flg; 4339 uint8_t tx_switching_flg; 4340 uint8_t tx_switching_change_flg; 4341 uint8_t handle_ptp_pkts_flg; 4342 uint8_t handle_ptp_pkts_change_flg; 4343 __le16 reserved1; 4344 __le32 echo; 4345 }; 4346 4347 4348 /* 4349 * The eth storm context of Cstorm 4350 */ 4351 struct cstorm_eth_st_context { 4352 uint32_t __reserved0[4]; 4353 }; 4354 4355 4356 struct double_regpair { 4357 uint32_t regpair0_lo; 4358 uint32_t regpair0_hi; 4359 uint32_t regpair1_lo; 4360 uint32_t regpair1_hi; 4361 }; 4362 4363 4364 /* 4365 * 2nd parse bd type used in ethernet tx BDs 4366 */ 4367 enum eth_2nd_parse_bd_type { 4368 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL, 4369 MAX_ETH_2ND_PARSE_BD_TYPE}; 4370 4371 4372 /* 4373 * Ethernet address typesm used in ethernet tx BDs 4374 */ 4375 enum eth_addr_type { 4376 UNKNOWN_ADDRESS, 4377 UNICAST_ADDRESS, 4378 MULTICAST_ADDRESS, 4379 BROADCAST_ADDRESS, 4380 MAX_ETH_ADDR_TYPE}; 4381 4382 4383 /* 4384 * 4385 */ 4386 struct eth_classify_cmd_header { 4387 uint8_t cmd_general_data; 4388 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1 << 0) 4389 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 4390 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1 << 1) 4391 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 4392 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3 << 2) 4393 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 4394 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1 << 4) 4395 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 4396 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7 << 5) 4397 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 4398 uint8_t func_id; 4399 uint8_t client_id; 4400 uint8_t reserved1; 4401 }; 4402 4403 4404 /* 4405 * header for eth classification config ramrod 4406 */ 4407 struct eth_classify_header { 4408 uint8_t rule_cnt; 4409 uint8_t warning_on_error; 4410 __le16 reserved1; 4411 __le32 echo; 4412 }; 4413 4414 4415 /* 4416 * Command for adding/removing a Inner-MAC/VNI classification rule 4417 */ 4418 struct eth_classify_imac_vni_cmd { 4419 struct eth_classify_cmd_header header; 4420 __le32 vni; 4421 __le16 imac_lsb; 4422 __le16 imac_mid; 4423 __le16 imac_msb; 4424 __le16 reserved1; 4425 }; 4426 4427 4428 /* 4429 * Command for adding/removing a MAC classification rule 4430 */ 4431 struct eth_classify_mac_cmd { 4432 struct eth_classify_cmd_header header; 4433 __le16 reserved0; 4434 __le16 inner_mac; 4435 __le16 mac_lsb; 4436 __le16 mac_mid; 4437 __le16 mac_msb; 4438 __le16 reserved1; 4439 }; 4440 4441 4442 /* 4443 * Command for adding/removing a MAC-VLAN pair classification rule 4444 */ 4445 struct eth_classify_pair_cmd { 4446 struct eth_classify_cmd_header header; 4447 __le16 reserved0; 4448 __le16 inner_mac; 4449 __le16 mac_lsb; 4450 __le16 mac_mid; 4451 __le16 mac_msb; 4452 __le16 vlan; 4453 }; 4454 4455 4456 /* 4457 * Command for adding/removing a VLAN classification rule 4458 */ 4459 struct eth_classify_vlan_cmd { 4460 struct eth_classify_cmd_header header; 4461 __le32 reserved0; 4462 __le32 reserved1; 4463 __le16 reserved2; 4464 __le16 vlan; 4465 }; 4466 4467 /* 4468 * union for eth classification rule 4469 */ 4470 union eth_classify_rule_cmd { 4471 struct eth_classify_mac_cmd mac; 4472 struct eth_classify_vlan_cmd vlan; 4473 struct eth_classify_pair_cmd pair; 4474 struct eth_classify_imac_vni_cmd imac_vni; 4475 }; 4476 4477 /* 4478 * parameters for eth classification configuration ramrod 4479 */ 4480 struct eth_classify_rules_ramrod_data { 4481 struct eth_classify_header header; 4482 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4483 }; 4484 4485 4486 /* 4487 * The data contain client ID need to the ramrod 4488 */ 4489 struct eth_common_ramrod_data { 4490 __le32 client_id; 4491 __le32 reserved1; 4492 }; 4493 4494 4495 /* 4496 * The eth storm context of Ustorm 4497 */ 4498 struct ustorm_eth_st_context { 4499 uint32_t reserved0[52]; 4500 }; 4501 4502 /* 4503 * The eth storm context of Tstorm 4504 */ 4505 struct tstorm_eth_st_context { 4506 uint32_t __reserved0[28]; 4507 }; 4508 4509 /* 4510 * The eth storm context of Xstorm 4511 */ 4512 struct xstorm_eth_st_context { 4513 uint32_t reserved0[60]; 4514 }; 4515 4516 /* 4517 * Ethernet connection context 4518 */ 4519 struct eth_context { 4520 struct ustorm_eth_st_context ustorm_st_context; 4521 struct tstorm_eth_st_context tstorm_st_context; 4522 struct xstorm_eth_ag_context xstorm_ag_context; 4523 struct tstorm_eth_ag_context tstorm_ag_context; 4524 struct cstorm_eth_ag_context cstorm_ag_context; 4525 struct ustorm_eth_ag_context ustorm_ag_context; 4526 struct timers_block_context timers_context; 4527 struct xstorm_eth_st_context xstorm_st_context; 4528 struct cstorm_eth_st_context cstorm_st_context; 4529 }; 4530 4531 4532 /* 4533 * union for sgl and raw data. 4534 */ 4535 union eth_sgl_or_raw_data { 4536 __le16 sgl[8]; 4537 uint32_t raw_data[4]; 4538 }; 4539 4540 /* 4541 * eth FP end aggregation CQE parameters struct 4542 */ 4543 struct eth_end_agg_rx_cqe { 4544 uint8_t type_error_flags; 4545 #define ETH_END_AGG_RX_CQE_TYPE (0x3 << 0) 4546 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 4547 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1 << 2) 4548 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 4549 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F << 3) 4550 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 4551 uint8_t reserved1; 4552 uint8_t queue_index; 4553 uint8_t reserved2; 4554 __le32 timestamp_delta; 4555 __le16 num_of_coalesced_segs; 4556 __le16 pkt_len; 4557 uint8_t pure_ack_count; 4558 uint8_t reserved3; 4559 __le16 reserved4; 4560 union eth_sgl_or_raw_data sgl_or_raw_data; 4561 __le32 padding[8]; 4562 }; 4563 4564 /* 4565 * Ethernet error code 4566 */ 4567 enum eth_error_code { 4568 ETH_OK = 0x00, 4569 ETH_RAMROD_DATA_READ_ERROR = 0x01, 4570 ETH_FILTERS_FUNC_NOT_ENABLED, 4571 ETH_FILTERS_MAC_ADD_FAIL_CAM_FULL, 4572 ETH_FILTERS_MAC_DEL_FAIL_NOF, 4573 ETH_FILTERS_PAIR_ADD_FAIL_CAM_FULL, 4574 ETH_FILTERS_PAIR_DEL_FAIL_NOF, 4575 ETH_FILTERS_VLAN_ADD_FAIL_CAM_FULL, 4576 ETH_FILTERS_VLAN_ADD_FAIL_DUP_TT, 4577 ETH_FILTERS_VLAN_DEL_FAIL_NOF, 4578 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT, 4579 ETH_FILTERS_VLAN_DEL_FAIL_NO_VLAN, 4580 ETH_FILTERS_IMAC_VNI_ADD_UNALLOWED_IN_TX, 4581 ETH_FILTERS_IMAC_VNI_DEL_UNALLOWED_IN_TX, 4582 ETH_FILTERS_IMAC_VNI_ADD_FAIL_CAM_FULL, 4583 ETH_FILTERS_IMAC_VNI_DEL_FAIL_NOF, 4584 MAX_ETH_ERROR_CODE}; 4585 4586 /* 4587 * regular eth FP CQE parameters struct 4588 */ 4589 struct eth_fast_path_rx_cqe { 4590 uint8_t type_error_flags; 4591 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3 << 0) 4592 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 4593 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1 << 2) 4594 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 4595 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1 << 3) 4596 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 4597 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1 << 4) 4598 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 4599 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1 << 5) 4600 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 4601 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1 << 6) 4602 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6 4603 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1 << 7) 4604 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7 4605 uint8_t status_flags; 4606 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7 << 0) 4607 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4608 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1 << 3) 4609 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4610 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1 << 4) 4611 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4612 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1 << 5) 4613 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4614 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1 << 6) 4615 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4616 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1 << 7) 4617 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4618 uint8_t queue_index; 4619 uint8_t placement_offset; 4620 __le32 rss_hash_result; 4621 __le16 vlan_tag; 4622 __le16 pkt_len_or_gro_seg_len; 4623 __le16 len_on_bd; 4624 struct parsing_flags pars_flags; 4625 union eth_sgl_or_raw_data sgl_or_raw_data; 4626 uint8_t tunn_type; 4627 uint8_t tunn_inner_hdrs_offset; 4628 __le16 reserved1; 4629 __le32 tunn_tenant_id; 4630 __le32 padding[5]; 4631 __le32 marker; 4632 }; 4633 4634 4635 /* 4636 * Command for setting classification flags for a client 4637 */ 4638 struct eth_filter_rules_cmd { 4639 uint8_t cmd_general_data; 4640 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1 << 0) 4641 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4642 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1 << 1) 4643 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4644 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F << 2) 4645 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4646 uint8_t func_id; 4647 uint8_t client_id; 4648 uint8_t reserved1; 4649 __le16 state; 4650 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1 << 0) 4651 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4652 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1 << 1) 4653 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4654 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1 << 2) 4655 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4656 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1 << 3) 4657 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4658 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1 << 4) 4659 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4660 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1 << 5) 4661 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4662 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1 << 6) 4663 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4664 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF << 7) 4665 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4666 __le16 reserved3; 4667 struct regpair reserved4; 4668 }; 4669 4670 4671 /* 4672 * parameters for eth classification filters ramrod 4673 */ 4674 struct eth_filter_rules_ramrod_data { 4675 struct eth_classify_header header; 4676 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4677 }; 4678 4679 4680 /* 4681 * Hsi version 4682 */ 4683 enum eth_fp_hsi_ver { 4684 ETH_FP_HSI_VER_0, 4685 ETH_FP_HSI_VER_1, 4686 ETH_FP_HSI_VER_2, 4687 MAX_ETH_FP_HSI_VER}; 4688 4689 4690 /* 4691 * parameters for eth classification configuration ramrod 4692 */ 4693 struct eth_general_rules_ramrod_data { 4694 struct eth_classify_header header; 4695 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4696 }; 4697 4698 4699 /* 4700 * The data for Halt ramrod 4701 */ 4702 struct eth_halt_ramrod_data { 4703 __le32 client_id; 4704 __le32 reserved0; 4705 }; 4706 4707 4708 /* 4709 * destination and source mac address. 4710 */ 4711 struct eth_mac_addresses { 4712 #if defined(__BIG_ENDIAN) 4713 __le16 dst_mid; 4714 __le16 dst_lo; 4715 #elif defined(__LITTLE_ENDIAN) 4716 __le16 dst_lo; 4717 __le16 dst_mid; 4718 #endif 4719 #if defined(__BIG_ENDIAN) 4720 __le16 src_lo; 4721 __le16 dst_hi; 4722 #elif defined(__LITTLE_ENDIAN) 4723 __le16 dst_hi; 4724 __le16 src_lo; 4725 #endif 4726 #if defined(__BIG_ENDIAN) 4727 __le16 src_hi; 4728 __le16 src_mid; 4729 #elif defined(__LITTLE_ENDIAN) 4730 __le16 src_mid; 4731 __le16 src_hi; 4732 #endif 4733 }; 4734 4735 4736 /* 4737 * tunneling related data. 4738 */ 4739 struct eth_tunnel_data { 4740 __le16 dst_lo; 4741 __le16 dst_mid; 4742 __le16 dst_hi; 4743 __le16 fw_ip_hdr_csum; 4744 __le16 pseudo_csum; 4745 uint8_t ip_hdr_start_inner_w; 4746 uint8_t flags; 4747 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1 << 0) 4748 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0 4749 #define ETH_TUNNEL_DATA_RESERVED (0x7F << 1) 4750 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4751 }; 4752 4753 /* 4754 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 4755 */ 4756 union eth_mac_addr_or_tunnel_data { 4757 struct eth_mac_addresses mac_addr; 4758 struct eth_tunnel_data tunnel_data; 4759 }; 4760 4761 4762 /* 4763 * Command for setting multicast classification for a client 4764 */ 4765 struct eth_multicast_rules_cmd { 4766 uint8_t cmd_general_data; 4767 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1 << 0) 4768 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4769 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1 << 1) 4770 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4771 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1 << 2) 4772 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4773 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F << 3) 4774 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4775 uint8_t func_id; 4776 uint8_t bin_id; 4777 uint8_t engine_id; 4778 __le32 reserved2; 4779 struct regpair reserved3; 4780 }; 4781 4782 4783 /* 4784 * parameters for multicast classification ramrod 4785 */ 4786 struct eth_multicast_rules_ramrod_data { 4787 struct eth_classify_header header; 4788 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4789 }; 4790 4791 4792 /* 4793 * Place holder for ramrods protocol specific data 4794 */ 4795 struct ramrod_data { 4796 __le32 data_lo; 4797 __le32 data_hi; 4798 }; 4799 4800 /* 4801 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4802 */ 4803 union eth_ramrod_data { 4804 struct ramrod_data general; 4805 }; 4806 4807 4808 /* 4809 * RSS toeplitz hash type, as reported in CQE 4810 */ 4811 enum eth_rss_hash_type { 4812 DEFAULT_HASH_TYPE, 4813 IPV4_HASH_TYPE, 4814 TCP_IPV4_HASH_TYPE, 4815 IPV6_HASH_TYPE, 4816 TCP_IPV6_HASH_TYPE, 4817 VLAN_PRI_HASH_TYPE, 4818 E1HOV_PRI_HASH_TYPE, 4819 DSCP_HASH_TYPE, 4820 MAX_ETH_RSS_HASH_TYPE}; 4821 4822 4823 /* 4824 * Ethernet RSS mode 4825 */ 4826 enum eth_rss_mode { 4827 ETH_RSS_MODE_DISABLED, 4828 ETH_RSS_MODE_REGULAR, 4829 ETH_RSS_MODE_ESX51, 4830 ETH_RSS_MODE_VLAN_PRI, 4831 ETH_RSS_MODE_E1HOV_PRI, 4832 ETH_RSS_MODE_IP_DSCP, 4833 MAX_ETH_RSS_MODE}; 4834 4835 4836 /* 4837 * parameters for RSS update ramrod (E2) 4838 */ 4839 struct eth_rss_update_ramrod_data { 4840 uint8_t rss_engine_id; 4841 uint8_t rss_mode; 4842 __le16 capabilities; 4843 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1 << 0) 4844 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4845 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1 << 1) 4846 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4847 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1 << 2) 4848 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4849 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1 << 3) 4850 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3 4851 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1 << 4) 4852 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4 4853 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1 << 5) 4854 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5 4855 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1 << 6) 4856 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6 4857 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1 << 7) 4858 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7 4859 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1 << 8) 4860 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8 4861 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1 << 9) 4862 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9 4863 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F << 10) 4864 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10 4865 uint8_t rss_result_mask; 4866 uint8_t reserved3; 4867 __le16 reserved4; 4868 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4869 __le32 rss_key[T_ETH_RSS_KEY]; 4870 __le32 echo; 4871 __le32 reserved5; 4872 }; 4873 4874 4875 /* 4876 * The eth Rx Buffer Descriptor 4877 */ 4878 struct eth_rx_bd { 4879 __le32 addr_lo; 4880 __le32 addr_hi; 4881 }; 4882 4883 4884 /* 4885 * Eth Rx Cqe structure- general structure for ramrods 4886 */ 4887 struct common_ramrod_eth_rx_cqe { 4888 uint8_t ramrod_type; 4889 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3 << 0) 4890 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4891 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1 << 2) 4892 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4893 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F << 3) 4894 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4895 uint8_t conn_type; 4896 __le16 reserved1; 4897 __le32 conn_and_cmd_data; 4898 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF << 0) 4899 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4900 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF << 24) 4901 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4902 struct ramrod_data protocol_data; 4903 __le32 echo; 4904 __le32 reserved2[11]; 4905 }; 4906 4907 /* 4908 * Rx Last CQE in page (in ETH) 4909 */ 4910 struct eth_rx_cqe_next_page { 4911 __le32 addr_lo; 4912 __le32 addr_hi; 4913 __le32 reserved[14]; 4914 }; 4915 4916 /* 4917 * union for all eth rx cqe types (fix their sizes) 4918 */ 4919 union eth_rx_cqe { 4920 struct eth_fast_path_rx_cqe fast_path_cqe; 4921 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4922 struct eth_rx_cqe_next_page next_page_cqe; 4923 struct eth_end_agg_rx_cqe end_agg_cqe; 4924 }; 4925 4926 4927 /* 4928 * Values for RX ETH CQE type field 4929 */ 4930 enum eth_rx_cqe_type { 4931 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4932 RX_ETH_CQE_TYPE_ETH_RAMROD, 4933 RX_ETH_CQE_TYPE_ETH_START_AGG, 4934 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4935 MAX_ETH_RX_CQE_TYPE}; 4936 4937 4938 /* 4939 * Type of SGL/Raw field in ETH RX fast path CQE 4940 */ 4941 enum eth_rx_fp_sel { 4942 ETH_FP_CQE_REGULAR, 4943 ETH_FP_CQE_RAW, 4944 MAX_ETH_RX_FP_SEL}; 4945 4946 4947 /* 4948 * The eth Rx SGE Descriptor 4949 */ 4950 struct eth_rx_sge { 4951 __le32 addr_lo; 4952 __le32 addr_hi; 4953 }; 4954 4955 4956 /* 4957 * common data for all protocols 4958 */ 4959 struct spe_hdr { 4960 __le32 conn_and_cmd_data; 4961 #define SPE_HDR_CID (0xFFFFFF << 0) 4962 #define SPE_HDR_CID_SHIFT 0 4963 #define SPE_HDR_CMD_ID (0xFF << 24) 4964 #define SPE_HDR_CMD_ID_SHIFT 24 4965 __le16 type; 4966 #define SPE_HDR_CONN_TYPE (0xFF << 0) 4967 #define SPE_HDR_CONN_TYPE_SHIFT 0 4968 #define SPE_HDR_FUNCTION_ID (0xFF << 8) 4969 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4970 __le16 reserved1; 4971 }; 4972 4973 /* 4974 * specific data for ethernet slow path element 4975 */ 4976 union eth_specific_data { 4977 uint8_t protocol_data[8]; 4978 struct regpair client_update_ramrod_data; 4979 struct regpair client_init_ramrod_init_data; 4980 struct eth_halt_ramrod_data halt_ramrod_data; 4981 struct regpair update_data_addr; 4982 struct eth_common_ramrod_data common_ramrod_data; 4983 struct regpair classify_cfg_addr; 4984 struct regpair filter_cfg_addr; 4985 struct regpair mcast_cfg_addr; 4986 }; 4987 4988 /* 4989 * Ethernet slow path element 4990 */ 4991 struct eth_spe { 4992 struct spe_hdr hdr; 4993 union eth_specific_data data; 4994 }; 4995 4996 4997 /* 4998 * Ethernet command ID for slow path elements 4999 */ 5000 enum eth_spqe_cmd_id { 5001 RAMROD_CMD_ID_ETH_UNUSED, 5002 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 5003 RAMROD_CMD_ID_ETH_HALT, 5004 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 5005 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 5006 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 5007 RAMROD_CMD_ID_ETH_EMPTY, 5008 RAMROD_CMD_ID_ETH_TERMINATE, 5009 RAMROD_CMD_ID_ETH_TPA_UPDATE, 5010 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 5011 RAMROD_CMD_ID_ETH_FILTER_RULES, 5012 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 5013 RAMROD_CMD_ID_ETH_RSS_UPDATE, 5014 RAMROD_CMD_ID_ETH_SET_MAC, 5015 MAX_ETH_SPQE_CMD_ID}; 5016 5017 5018 /* 5019 * eth tpa update command 5020 */ 5021 enum eth_tpa_update_command { 5022 TPA_UPDATE_NONE_COMMAND, 5023 TPA_UPDATE_ENABLE_COMMAND, 5024 TPA_UPDATE_DISABLE_COMMAND, 5025 MAX_ETH_TPA_UPDATE_COMMAND}; 5026 5027 5028 /* 5029 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 5030 */ 5031 enum eth_tunnel_lso_inc_ip_id { 5032 EXT_HEADER, 5033 INT_HEADER, 5034 MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 5035 5036 5037 /* 5038 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 5039 */ 5040 enum eth_tunnel_non_lso_csum_location { 5041 CSUM_ON_PKT, 5042 CSUM_ON_BD, 5043 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 5044 5045 5046 /* 5047 * Packet Tunneling Type 5048 */ 5049 enum eth_tunn_type { 5050 TUNN_TYPE_NONE, 5051 TUNN_TYPE_VXLAN, 5052 TUNN_TYPE_L2_GRE, 5053 TUNN_TYPE_IPV4_GRE, 5054 TUNN_TYPE_IPV6_GRE, 5055 TUNN_TYPE_L2_GENEVE, 5056 TUNN_TYPE_IPV4_GENEVE, 5057 TUNN_TYPE_IPV6_GENEVE, 5058 MAX_ETH_TUNN_TYPE}; 5059 5060 5061 /* 5062 * Tx regular BD structure 5063 */ 5064 struct eth_tx_bd { 5065 __le32 addr_lo; 5066 __le32 addr_hi; 5067 __le16 total_pkt_bytes; 5068 __le16 nbytes; 5069 uint8_t reserved[4]; 5070 }; 5071 5072 5073 /* 5074 * structure for easy accessibility to assembler 5075 */ 5076 struct eth_tx_bd_flags { 5077 uint8_t as_bitfield; 5078 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1 << 0) 5079 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 5080 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1 << 1) 5081 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 5082 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3 << 2) 5083 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 5084 #define ETH_TX_BD_FLAGS_START_BD (0x1 << 4) 5085 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 5086 #define ETH_TX_BD_FLAGS_IS_UDP (0x1 << 5) 5087 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 5088 #define ETH_TX_BD_FLAGS_SW_LSO (0x1 << 6) 5089 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 5090 #define ETH_TX_BD_FLAGS_IPV6 (0x1 << 7) 5091 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 5092 }; 5093 5094 /* 5095 * The eth Tx Buffer Descriptor 5096 */ 5097 struct eth_tx_start_bd { 5098 __le32 addr_lo; 5099 __le32 addr_hi; 5100 __le16 nbd; 5101 __le16 nbytes; 5102 __le16 vlan_or_ethertype; 5103 struct eth_tx_bd_flags bd_flags; 5104 uint8_t general_data; 5105 #define ETH_TX_START_BD_HDR_NBDS (0x7 << 0) 5106 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 5107 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1 << 3) 5108 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3 5109 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1 << 4) 5110 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 5111 #define ETH_TX_START_BD_PARSE_NBDS (0x3 << 5) 5112 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 5113 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1 << 7) 5114 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 5115 }; 5116 5117 /* 5118 * Tx parsing BD structure for ETH E1/E1h 5119 */ 5120 struct eth_tx_parse_bd_e1x { 5121 __le16 global_data; 5122 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF << 0) 5123 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 5124 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3 << 4) 5125 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 5126 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1 << 6) 5127 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 5128 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1 << 7) 5129 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 5130 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1 << 8) 5131 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 5132 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F << 9) 5133 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 5134 uint8_t tcp_flags; 5135 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1 << 0) 5136 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 5137 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1 << 1) 5138 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 5139 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1 << 2) 5140 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 5141 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1 << 3) 5142 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 5143 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1 << 4) 5144 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 5145 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1 << 5) 5146 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 5147 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1 << 6) 5148 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 5149 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1 << 7) 5150 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 5151 uint8_t ip_hlen_w; 5152 __le16 total_hlen_w; 5153 __le16 tcp_pseudo_csum; 5154 __le16 lso_mss; 5155 __le16 ip_id; 5156 __le32 tcp_send_seq; 5157 }; 5158 5159 /* 5160 * Tx parsing BD structure for ETH E2 5161 */ 5162 struct eth_tx_parse_bd_e2 { 5163 union eth_mac_addr_or_tunnel_data data; 5164 __le32 parsing_data; 5165 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF << 0) 5166 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 5167 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF << 11) 5168 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 5169 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1 << 15) 5170 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 5171 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF << 16) 5172 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 5173 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3 << 30) 5174 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 5175 }; 5176 5177 /* 5178 * Tx 2nd parsing BD structure for ETH packet 5179 */ 5180 struct eth_tx_parse_2nd_bd { 5181 __le16 global_data; 5182 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF << 0) 5183 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 5184 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1 << 4) 5185 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 5186 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1 << 5) 5187 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 5188 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1 << 6) 5189 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 5190 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1 << 7) 5191 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 5192 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F << 8) 5193 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 5194 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7 << 13) 5195 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 5196 uint8_t bd_type; 5197 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF << 0) 5198 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0 5199 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF << 4) 5200 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4 5201 uint8_t reserved3; 5202 uint8_t tcp_flags; 5203 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1 << 0) 5204 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 5205 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1 << 1) 5206 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 5207 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1 << 2) 5208 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 5209 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1 << 3) 5210 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 5211 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1 << 4) 5212 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 5213 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1 << 5) 5214 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 5215 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1 << 6) 5216 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 5217 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1 << 7) 5218 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 5219 uint8_t reserved4; 5220 uint8_t tunnel_udp_hdr_start_w; 5221 uint8_t fw_ip_hdr_to_payload_w; 5222 __le16 fw_ip_csum_wo_len_flags_frag; 5223 __le16 hw_ip_id; 5224 __le32 tcp_send_seq; 5225 }; 5226 5227 /* 5228 * The last BD in the BD memory will hold a pointer to the next BD memory 5229 */ 5230 struct eth_tx_next_bd { 5231 __le32 addr_lo; 5232 __le32 addr_hi; 5233 uint8_t reserved[8]; 5234 }; 5235 5236 /* 5237 * union for 4 Bd types 5238 */ 5239 union eth_tx_bd_types { 5240 struct eth_tx_start_bd start_bd; 5241 struct eth_tx_bd reg_bd; 5242 struct eth_tx_parse_bd_e1x parse_bd_e1x; 5243 struct eth_tx_parse_bd_e2 parse_bd_e2; 5244 struct eth_tx_parse_2nd_bd parse_2nd_bd; 5245 struct eth_tx_next_bd next_bd; 5246 }; 5247 5248 /* 5249 * array of 13 bds as appears in the eth xstorm context 5250 */ 5251 struct eth_tx_bds_array { 5252 union eth_tx_bd_types bds[13]; 5253 }; 5254 5255 5256 /* 5257 * VLAN mode on TX BDs 5258 */ 5259 enum eth_tx_vlan_type { 5260 X_ETH_NO_VLAN, 5261 X_ETH_OUTBAND_VLAN, 5262 X_ETH_INBAND_VLAN, 5263 X_ETH_FW_ADDED_VLAN, 5264 MAX_ETH_TX_VLAN_TYPE}; 5265 5266 5267 /* 5268 * Ethernet VLAN filtering mode in E1x 5269 */ 5270 enum eth_vlan_filter_mode { 5271 ETH_VLAN_FILTER_ANY_VLAN, 5272 ETH_VLAN_FILTER_SPECIFIC_VLAN, 5273 ETH_VLAN_FILTER_CLASSIFY, 5274 MAX_ETH_VLAN_FILTER_MODE}; 5275 5276 5277 /* 5278 * MAC filtering configuration command header 5279 */ 5280 struct mac_configuration_hdr { 5281 uint8_t length; 5282 uint8_t offset; 5283 __le16 client_id; 5284 __le32 echo; 5285 }; 5286 5287 /* 5288 * MAC address in list for ramrod 5289 */ 5290 struct mac_configuration_entry { 5291 __le16 lsb_mac_addr; 5292 __le16 middle_mac_addr; 5293 __le16 msb_mac_addr; 5294 __le16 vlan_id; 5295 uint8_t pf_id; 5296 uint8_t flags; 5297 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1 << 0) 5298 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 5299 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1 << 1) 5300 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 5301 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3 << 2) 5302 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 5303 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1 << 4) 5304 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 5305 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1 << 5) 5306 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 5307 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3 << 6) 5308 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 5309 __le16 reserved0; 5310 __le32 clients_bit_vector; 5311 }; 5312 5313 /* 5314 * MAC filtering configuration command 5315 */ 5316 struct mac_configuration_cmd { 5317 struct mac_configuration_hdr hdr; 5318 struct mac_configuration_entry config_table[64]; 5319 }; 5320 5321 5322 /* 5323 * Set-MAC command type (in E1x) 5324 */ 5325 enum set_mac_action_type { 5326 T_ETH_MAC_COMMAND_INVALIDATE, 5327 T_ETH_MAC_COMMAND_SET, 5328 MAX_SET_MAC_ACTION_TYPE}; 5329 5330 5331 /* 5332 * Ethernet TPA Modes 5333 */ 5334 enum tpa_mode { 5335 TPA_LRO, 5336 TPA_GRO, 5337 MAX_TPA_MODE}; 5338 5339 5340 /* 5341 * tpa update ramrod data 5342 */ 5343 struct tpa_update_ramrod_data { 5344 uint8_t update_ipv4; 5345 uint8_t update_ipv6; 5346 uint8_t client_id; 5347 uint8_t max_tpa_queues; 5348 uint8_t max_sges_for_packet; 5349 uint8_t complete_on_both_clients; 5350 uint8_t dont_verify_rings_pause_thr_flg; 5351 uint8_t tpa_mode; 5352 __le16 sge_buff_size; 5353 __le16 max_agg_size; 5354 __le32 sge_page_base_lo; 5355 __le32 sge_page_base_hi; 5356 __le16 sge_pause_thr_low; 5357 __le16 sge_pause_thr_high; 5358 uint8_t tpa_over_vlan_disable; 5359 uint8_t reserved[7]; 5360 }; 5361 5362 5363 /* 5364 * approximate-match multicast filtering for E1H per function in Tstorm 5365 */ 5366 struct tstorm_eth_approximate_match_multicast_filtering { 5367 uint32_t mcast_add_hash_bit_array[8]; 5368 }; 5369 5370 5371 /* 5372 * Common configuration parameters per function in Tstorm 5373 */ 5374 struct tstorm_eth_function_common_config { 5375 __le16 config_flags; 5376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0) 5377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 5378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1) 5379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 5380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2) 5381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 5382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3) 5383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 5384 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4) 5385 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 5386 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1 << 7) 5387 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 5388 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF << 8) 5389 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 5390 uint8_t rss_result_mask; 5391 uint8_t reserved1; 5392 __le16 vlan_id[2]; 5393 }; 5394 5395 5396 /* 5397 * MAC filtering configuration parameters per port in Tstorm 5398 */ 5399 struct tstorm_eth_mac_filter_config { 5400 uint32_t ucast_drop_all; 5401 uint32_t ucast_accept_all; 5402 uint32_t mcast_drop_all; 5403 uint32_t mcast_accept_all; 5404 uint32_t bcast_accept_all; 5405 uint32_t vlan_filter[2]; 5406 uint32_t unmatched_unicast; 5407 }; 5408 5409 5410 /* 5411 * tx only queue init ramrod data 5412 */ 5413 struct tx_queue_init_ramrod_data { 5414 struct client_init_general_data general; 5415 struct client_init_tx_data tx; 5416 }; 5417 5418 5419 /* 5420 * Three RX producers for ETH 5421 */ 5422 struct ustorm_eth_rx_producers { 5423 #if defined(__BIG_ENDIAN) 5424 uint16_t bd_prod; 5425 uint16_t cqe_prod; 5426 #elif defined(__LITTLE_ENDIAN) 5427 uint16_t cqe_prod; 5428 uint16_t bd_prod; 5429 #endif 5430 #if defined(__BIG_ENDIAN) 5431 uint16_t reserved; 5432 uint16_t sge_prod; 5433 #elif defined(__LITTLE_ENDIAN) 5434 uint16_t sge_prod; 5435 uint16_t reserved; 5436 #endif 5437 }; 5438 5439 5440 /* 5441 * FCoE RX statistics parameters section#0 5442 */ 5443 struct fcoe_rx_stat_params_section0 { 5444 __le32 fcoe_rx_pkt_cnt; 5445 __le32 fcoe_rx_byte_cnt; 5446 }; 5447 5448 5449 /* 5450 * FCoE RX statistics parameters section#1 5451 */ 5452 struct fcoe_rx_stat_params_section1 { 5453 __le32 fcoe_ver_cnt; 5454 __le32 fcoe_rx_drop_pkt_cnt; 5455 }; 5456 5457 5458 /* 5459 * FCoE RX statistics parameters section#2 5460 */ 5461 struct fcoe_rx_stat_params_section2 { 5462 __le32 fc_crc_cnt; 5463 __le32 eofa_del_cnt; 5464 __le32 miss_frame_cnt; 5465 __le32 seq_timeout_cnt; 5466 __le32 drop_seq_cnt; 5467 __le32 fcoe_rx_drop_pkt_cnt; 5468 __le32 fcp_rx_pkt_cnt; 5469 __le32 reserved0; 5470 }; 5471 5472 5473 /* 5474 * FCoE TX statistics parameters 5475 */ 5476 struct fcoe_tx_stat_params { 5477 __le32 fcoe_tx_pkt_cnt; 5478 __le32 fcoe_tx_byte_cnt; 5479 __le32 fcp_tx_pkt_cnt; 5480 __le32 reserved0; 5481 }; 5482 5483 /* 5484 * FCoE statistics parameters 5485 */ 5486 struct fcoe_statistics_params { 5487 struct fcoe_tx_stat_params tx_stat; 5488 struct fcoe_rx_stat_params_section0 rx_stat0; 5489 struct fcoe_rx_stat_params_section1 rx_stat1; 5490 struct fcoe_rx_stat_params_section2 rx_stat2; 5491 }; 5492 5493 5494 /* 5495 * The data afex vif list ramrod need 5496 */ 5497 struct afex_vif_list_ramrod_data { 5498 uint8_t afex_vif_list_command; 5499 uint8_t func_bit_map; 5500 __le16 vif_list_index; 5501 uint8_t func_to_clear; 5502 uint8_t echo; 5503 __le16 reserved1; 5504 }; 5505 5506 5507 /* 5508 * 5509 */ 5510 struct c2s_pri_trans_table_entry { 5511 uint8_t val[MAX_VLAN_PRIORITIES]; 5512 }; 5513 5514 5515 /* 5516 * cfc delete event data 5517 */ 5518 struct cfc_del_event_data { 5519 __le32 cid; 5520 __le32 reserved0; 5521 __le32 reserved1; 5522 }; 5523 5524 5525 /* 5526 * per-port SAFC demo variables 5527 */ 5528 struct cmng_flags_per_port { 5529 uint32_t cmng_enables; 5530 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1 << 0) 5531 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 5532 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1 << 1) 5533 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 5534 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1 << 2) 5535 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 5536 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1 << 3) 5537 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 5538 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF << 4) 5539 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 5540 uint32_t __reserved1; 5541 }; 5542 5543 5544 /* 5545 * per-port rate shaping variables 5546 */ 5547 struct rate_shaping_vars_per_port { 5548 uint32_t rs_periodic_timeout; 5549 uint32_t rs_threshold; 5550 }; 5551 5552 /* 5553 * per-port fairness variables 5554 */ 5555 struct fairness_vars_per_port { 5556 uint32_t upper_bound; 5557 uint32_t fair_threshold; 5558 uint32_t fairness_timeout; 5559 uint32_t size_thr; 5560 }; 5561 5562 /* 5563 * per-port SAFC variables 5564 */ 5565 struct safc_struct_per_port { 5566 #if defined(__BIG_ENDIAN) 5567 uint16_t __reserved1; 5568 uint8_t __reserved0; 5569 uint8_t safc_timeout_usec; 5570 #elif defined(__LITTLE_ENDIAN) 5571 uint8_t safc_timeout_usec; 5572 uint8_t __reserved0; 5573 uint16_t __reserved1; 5574 #endif 5575 uint8_t cos_to_traffic_types[MAX_COS_NUMBER]; 5576 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS]; 5577 }; 5578 5579 /* 5580 * Per-port congestion management variables 5581 */ 5582 struct cmng_struct_per_port { 5583 struct rate_shaping_vars_per_port rs_vars; 5584 struct fairness_vars_per_port fair_vars; 5585 struct safc_struct_per_port safc_vars; 5586 struct cmng_flags_per_port flags; 5587 }; 5588 5589 /* 5590 * a single rate shaping counter. can be used as protocol or vnic counter 5591 */ 5592 struct rate_shaping_counter { 5593 uint32_t quota; 5594 #if defined(__BIG_ENDIAN) 5595 uint16_t __reserved0; 5596 uint16_t rate; 5597 #elif defined(__LITTLE_ENDIAN) 5598 uint16_t rate; 5599 uint16_t __reserved0; 5600 #endif 5601 }; 5602 5603 /* 5604 * per-vnic rate shaping variables 5605 */ 5606 struct rate_shaping_vars_per_vn { 5607 struct rate_shaping_counter vn_counter; 5608 }; 5609 5610 /* 5611 * per-vnic fairness variables 5612 */ 5613 struct fairness_vars_per_vn { 5614 uint32_t cos_credit_delta[MAX_COS_NUMBER]; 5615 uint32_t vn_credit_delta; 5616 uint32_t __reserved0; 5617 }; 5618 5619 /* 5620 * cmng port init state 5621 */ 5622 struct cmng_vnic { 5623 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5624 struct fairness_vars_per_vn vnic_min_rate[4]; 5625 }; 5626 5627 /* 5628 * cmng port init state 5629 */ 5630 struct cmng_init { 5631 struct cmng_struct_per_port port; 5632 struct cmng_vnic vnic; 5633 }; 5634 5635 5636 /* 5637 * driver parameters for congestion management init, all rates are in Mbps 5638 */ 5639 struct cmng_init_input { 5640 uint32_t port_rate; 5641 uint32_t size_thr; 5642 uint32_t fairness_thr; 5643 uint16_t vnic_min_rate[4]; 5644 uint16_t vnic_max_rate[4]; 5645 uint16_t cos_min_rate[MAX_COS_NUMBER]; 5646 uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 5647 struct cmng_flags_per_port flags; 5648 }; 5649 5650 5651 /* 5652 * Protocol-common command ID for slow path elements 5653 */ 5654 enum common_spqe_cmd_id { 5655 RAMROD_CMD_ID_COMMON_UNUSED, 5656 RAMROD_CMD_ID_COMMON_FUNCTION_START, 5657 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 5658 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 5659 RAMROD_CMD_ID_COMMON_CFC_DEL, 5660 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 5661 RAMROD_CMD_ID_COMMON_STAT_QUERY, 5662 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 5663 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 5664 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 5665 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 5666 MAX_COMMON_SPQE_CMD_ID}; 5667 5668 5669 /* 5670 * Per-protocol connection types 5671 */ 5672 enum connection_type { 5673 ETH_CONNECTION_TYPE, 5674 TOE_CONNECTION_TYPE, 5675 RDMA_CONNECTION_TYPE, 5676 ISCSI_CONNECTION_TYPE, 5677 FCOE_CONNECTION_TYPE, 5678 RESERVED_CONNECTION_TYPE_0, 5679 RESERVED_CONNECTION_TYPE_1, 5680 RESERVED_CONNECTION_TYPE_2, 5681 NONE_CONNECTION_TYPE, 5682 MAX_CONNECTION_TYPE}; 5683 5684 5685 /* 5686 * Cos modes 5687 */ 5688 enum cos_mode { 5689 OVERRIDE_COS, 5690 STATIC_COS, 5691 FW_WRR, 5692 MAX_COS_MODE}; 5693 5694 5695 /* 5696 * Dynamic HC counters set by the driver 5697 */ 5698 struct hc_dynamic_drv_counter { 5699 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES]; 5700 }; 5701 5702 /* 5703 * zone A per-queue data 5704 */ 5705 struct cstorm_queue_zone_data { 5706 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 5707 struct regpair reserved[2]; 5708 }; 5709 5710 5711 /* 5712 * Vf-PF channel data in cstorm ram (non-triggered zone) 5713 */ 5714 struct vf_pf_channel_zone_data { 5715 uint32_t msg_addr_lo; 5716 uint32_t msg_addr_hi; 5717 }; 5718 5719 /* 5720 * zone for VF non-triggered data 5721 */ 5722 struct non_trigger_vf_zone { 5723 struct vf_pf_channel_zone_data vf_pf_channel; 5724 }; 5725 5726 /* 5727 * Vf-PF channel trigger zone in cstorm ram 5728 */ 5729 struct vf_pf_channel_zone_trigger { 5730 uint8_t addr_valid; 5731 }; 5732 5733 /* 5734 * zone that triggers the in-bound interrupt 5735 */ 5736 struct trigger_vf_zone { 5737 struct vf_pf_channel_zone_trigger vf_pf_channel; 5738 uint8_t reserved0; 5739 uint16_t reserved1; 5740 uint32_t reserved2; 5741 }; 5742 5743 /* 5744 * zone B per-VF data 5745 */ 5746 struct cstorm_vf_zone_data { 5747 struct non_trigger_vf_zone non_trigger; 5748 struct trigger_vf_zone trigger; 5749 }; 5750 5751 5752 /* 5753 * Dynamic host coalescing init parameters, per state machine 5754 */ 5755 struct dynamic_hc_sm_config { 5756 uint32_t threshold[3]; 5757 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 5758 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 5759 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 5760 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 5761 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 5762 }; 5763 5764 /* 5765 * Dynamic host coalescing init parameters 5766 */ 5767 struct dynamic_hc_config { 5768 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 5769 }; 5770 5771 5772 struct e2_integ_data { 5773 #if defined(__BIG_ENDIAN) 5774 uint8_t flags; 5775 #define E2_INTEG_DATA_TESTING_EN (0x1 << 0) 5776 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5777 #define E2_INTEG_DATA_LB_TX (0x1 << 1) 5778 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5779 #define E2_INTEG_DATA_COS_TX (0x1 << 2) 5780 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5781 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3) 5782 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5783 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4) 5784 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5785 #define E2_INTEG_DATA_RESERVED (0x7 << 5) 5786 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5787 uint8_t cos; 5788 uint8_t voq; 5789 uint8_t pbf_queue; 5790 #elif defined(__LITTLE_ENDIAN) 5791 uint8_t pbf_queue; 5792 uint8_t voq; 5793 uint8_t cos; 5794 uint8_t flags; 5795 #define E2_INTEG_DATA_TESTING_EN (0x1 << 0) 5796 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5797 #define E2_INTEG_DATA_LB_TX (0x1 << 1) 5798 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5799 #define E2_INTEG_DATA_COS_TX (0x1 << 2) 5800 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5801 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3) 5802 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5803 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4) 5804 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5805 #define E2_INTEG_DATA_RESERVED (0x7 << 5) 5806 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5807 #endif 5808 #if defined(__BIG_ENDIAN) 5809 uint16_t reserved3; 5810 uint8_t reserved2; 5811 uint8_t ramEn; 5812 #elif defined(__LITTLE_ENDIAN) 5813 uint8_t ramEn; 5814 uint8_t reserved2; 5815 uint16_t reserved3; 5816 #endif 5817 }; 5818 5819 5820 /* 5821 * set mac event data 5822 */ 5823 struct eth_event_data { 5824 __le32 echo; 5825 __le32 reserved0; 5826 __le32 reserved1; 5827 }; 5828 5829 5830 /* 5831 * pf-vf event data 5832 */ 5833 struct vf_pf_event_data { 5834 uint8_t vf_id; 5835 uint8_t reserved0; 5836 __le16 reserved1; 5837 __le32 msg_addr_lo; 5838 __le32 msg_addr_hi; 5839 }; 5840 5841 /* 5842 * VF FLR event data 5843 */ 5844 struct vf_flr_event_data { 5845 uint8_t vf_id; 5846 uint8_t reserved0; 5847 __le16 reserved1; 5848 __le32 reserved2; 5849 __le32 reserved3; 5850 }; 5851 5852 /* 5853 * malicious VF event data 5854 */ 5855 struct malicious_vf_event_data { 5856 uint8_t vf_id; 5857 uint8_t err_id; 5858 __le16 reserved1; 5859 __le32 reserved2; 5860 __le32 reserved3; 5861 }; 5862 5863 /* 5864 * vif list event data 5865 */ 5866 struct vif_list_event_data { 5867 uint8_t func_bit_map; 5868 uint8_t echo; 5869 __le16 reserved0; 5870 __le32 reserved1; 5871 __le32 reserved2; 5872 }; 5873 5874 /* 5875 * function update event data 5876 */ 5877 struct function_update_event_data { 5878 uint8_t echo; 5879 uint8_t reserved; 5880 __le16 reserved0; 5881 __le32 reserved1; 5882 __le32 reserved2; 5883 }; 5884 5885 /* 5886 * union for all event ring message types 5887 */ 5888 union event_data { 5889 struct vf_pf_event_data vf_pf_event; 5890 struct eth_event_data eth_event; 5891 struct cfc_del_event_data cfc_del_event; 5892 struct vf_flr_event_data vf_flr_event; 5893 struct malicious_vf_event_data malicious_vf_event; 5894 struct vif_list_event_data vif_list_event; 5895 struct function_update_event_data function_update_event; 5896 }; 5897 5898 5899 /* 5900 * per PF event ring data 5901 */ 5902 struct event_ring_data { 5903 struct regpair_native base_addr; 5904 #if defined(__BIG_ENDIAN) 5905 uint8_t index_id; 5906 uint8_t sb_id; 5907 uint16_t producer; 5908 #elif defined(__LITTLE_ENDIAN) 5909 uint16_t producer; 5910 uint8_t sb_id; 5911 uint8_t index_id; 5912 #endif 5913 uint32_t reserved0; 5914 }; 5915 5916 5917 /* 5918 * event ring message element (each element is 128 bits) 5919 */ 5920 struct event_ring_msg { 5921 uint8_t opcode; 5922 uint8_t error; 5923 uint16_t reserved1; 5924 union event_data data; 5925 }; 5926 5927 /* 5928 * event ring next page element (128 bits) 5929 */ 5930 struct event_ring_next { 5931 struct regpair addr; 5932 uint32_t reserved[2]; 5933 }; 5934 5935 /* 5936 * union for event ring element types (each element is 128 bits) 5937 */ 5938 union event_ring_elem { 5939 struct event_ring_msg message; 5940 struct event_ring_next next_page; 5941 }; 5942 5943 5944 /* 5945 * Common event ring opcodes 5946 */ 5947 enum event_ring_opcode { 5948 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5949 EVENT_RING_OPCODE_FUNCTION_START, 5950 EVENT_RING_OPCODE_FUNCTION_STOP, 5951 EVENT_RING_OPCODE_CFC_DEL, 5952 EVENT_RING_OPCODE_CFC_DEL_WB, 5953 EVENT_RING_OPCODE_STAT_QUERY, 5954 EVENT_RING_OPCODE_STOP_TRAFFIC, 5955 EVENT_RING_OPCODE_START_TRAFFIC, 5956 EVENT_RING_OPCODE_VF_FLR, 5957 EVENT_RING_OPCODE_MALICIOUS_VF, 5958 EVENT_RING_OPCODE_FORWARD_SETUP, 5959 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5960 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5961 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5962 EVENT_RING_OPCODE_SET_MAC, 5963 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5964 EVENT_RING_OPCODE_FILTERS_RULES, 5965 EVENT_RING_OPCODE_MULTICAST_RULES, 5966 EVENT_RING_OPCODE_SET_TIMESYNC, 5967 MAX_EVENT_RING_OPCODE}; 5968 5969 5970 /* 5971 * Modes for fairness algorithm 5972 */ 5973 enum fairness_mode { 5974 FAIRNESS_COS_WRR_MODE, 5975 FAIRNESS_COS_ETS_MODE, 5976 MAX_FAIRNESS_MODE}; 5977 5978 5979 /* 5980 * Priority and cos 5981 */ 5982 struct priority_cos { 5983 uint8_t priority; 5984 uint8_t cos; 5985 __le16 reserved1; 5986 }; 5987 5988 /* 5989 * The data for flow control configuration 5990 */ 5991 struct flow_control_configuration { 5992 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5993 uint8_t dcb_enabled; 5994 uint8_t dcb_version; 5995 uint8_t dont_add_pri_0_en; 5996 uint8_t reserved1; 5997 __le32 reserved2; 5998 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES]; 5999 }; 6000 6001 6002 /* 6003 * 6004 */ 6005 struct function_start_data { 6006 uint8_t function_mode; 6007 uint8_t allow_npar_tx_switching; 6008 __le16 sd_vlan_tag; 6009 __le16 vif_id; 6010 uint8_t path_id; 6011 uint8_t network_cos_mode; 6012 uint8_t dmae_cmd_id; 6013 uint8_t no_added_tags; 6014 __le16 reserved0; 6015 __le32 reserved1; 6016 uint8_t inner_clss_vxlan; 6017 uint8_t inner_clss_l2gre; 6018 uint8_t inner_clss_l2geneve; 6019 uint8_t inner_rss; 6020 __le16 vxlan_dst_port; 6021 __le16 geneve_dst_port; 6022 uint8_t sd_accept_mf_clss_fail; 6023 uint8_t sd_accept_mf_clss_fail_match_ethtype; 6024 __le16 sd_accept_mf_clss_fail_ethtype; 6025 __le16 sd_vlan_eth_type; 6026 uint8_t sd_vlan_force_pri_flg; 6027 uint8_t sd_vlan_force_pri_val; 6028 uint8_t c2s_pri_tt_valid; 6029 uint8_t c2s_pri_default; 6030 uint8_t tx_vlan_filtering_enable; 6031 uint8_t tx_vlan_filtering_use_pvid; 6032 uint8_t reserved2[4]; 6033 struct c2s_pri_trans_table_entry c2s_pri_trans_table; 6034 }; 6035 6036 6037 /* 6038 * 6039 */ 6040 struct function_update_data { 6041 uint8_t vif_id_change_flg; 6042 uint8_t afex_default_vlan_change_flg; 6043 uint8_t allowed_priorities_change_flg; 6044 uint8_t network_cos_mode_change_flg; 6045 __le16 vif_id; 6046 __le16 afex_default_vlan; 6047 uint8_t allowed_priorities; 6048 uint8_t network_cos_mode; 6049 uint8_t lb_mode_en_change_flg; 6050 uint8_t lb_mode_en; 6051 uint8_t tx_switch_suspend_change_flg; 6052 uint8_t tx_switch_suspend; 6053 uint8_t echo; 6054 uint8_t update_tunn_cfg_flg; 6055 uint8_t inner_clss_vxlan; 6056 uint8_t inner_clss_l2gre; 6057 uint8_t inner_clss_l2geneve; 6058 uint8_t inner_rss; 6059 __le16 vxlan_dst_port; 6060 __le16 geneve_dst_port; 6061 uint8_t sd_vlan_force_pri_change_flg; 6062 uint8_t sd_vlan_force_pri_flg; 6063 uint8_t sd_vlan_force_pri_val; 6064 uint8_t sd_vlan_tag_change_flg; 6065 uint8_t sd_vlan_eth_type_change_flg; 6066 uint8_t reserved1; 6067 __le16 sd_vlan_tag; 6068 __le16 sd_vlan_eth_type; 6069 uint8_t tx_vlan_filtering_pvid_change_flg; 6070 uint8_t reserved0; 6071 __le32 reserved2; 6072 }; 6073 6074 6075 /* 6076 * FW version stored in the Xstorm RAM 6077 */ 6078 struct fw_version { 6079 #if defined(__BIG_ENDIAN) 6080 uint8_t engineering; 6081 uint8_t revision; 6082 uint8_t minor; 6083 uint8_t major; 6084 #elif defined(__LITTLE_ENDIAN) 6085 uint8_t major; 6086 uint8_t minor; 6087 uint8_t revision; 6088 uint8_t engineering; 6089 #endif 6090 uint32_t flags; 6091 #define FW_VERSION_OPTIMIZED (0x1 << 0) 6092 #define FW_VERSION_OPTIMIZED_SHIFT 0 6093 #define FW_VERSION_BIG_ENDIEN (0x1 << 1) 6094 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 6095 #define FW_VERSION_CHIP_VERSION (0x3 << 2) 6096 #define FW_VERSION_CHIP_VERSION_SHIFT 2 6097 #define __FW_VERSION_RESERVED (0xFFFFFFF << 4) 6098 #define __FW_VERSION_RESERVED_SHIFT 4 6099 }; 6100 6101 6102 /* 6103 * Dynamic Host-Coalescing - Driver(host) counters 6104 */ 6105 struct hc_dynamic_sb_drv_counters { 6106 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 6107 }; 6108 6109 6110 /* 6111 * 2 bytes. configuration/state parameters for a single protocol index 6112 */ 6113 struct hc_index_data { 6114 #if defined(__BIG_ENDIAN) 6115 uint8_t flags; 6116 #define HC_INDEX_DATA_SM_ID (0x1 << 0) 6117 #define HC_INDEX_DATA_SM_ID_SHIFT 0 6118 #define HC_INDEX_DATA_HC_ENABLED (0x1 << 1) 6119 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 6120 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2) 6121 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 6122 #define HC_INDEX_DATA_RESERVE (0x1F << 3) 6123 #define HC_INDEX_DATA_RESERVE_SHIFT 3 6124 uint8_t timeout; 6125 #elif defined(__LITTLE_ENDIAN) 6126 uint8_t timeout; 6127 uint8_t flags; 6128 #define HC_INDEX_DATA_SM_ID (0x1 << 0) 6129 #define HC_INDEX_DATA_SM_ID_SHIFT 0 6130 #define HC_INDEX_DATA_HC_ENABLED (0x1 << 1) 6131 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 6132 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2) 6133 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 6134 #define HC_INDEX_DATA_RESERVE (0x1F << 3) 6135 #define HC_INDEX_DATA_RESERVE_SHIFT 3 6136 #endif 6137 }; 6138 6139 6140 /* 6141 * HC state-machine 6142 */ 6143 struct hc_status_block_sm { 6144 #if defined(__BIG_ENDIAN) 6145 uint8_t igu_seg_id; 6146 uint8_t igu_sb_id; 6147 uint8_t timer_value; 6148 uint8_t __flags; 6149 #elif defined(__LITTLE_ENDIAN) 6150 uint8_t __flags; 6151 uint8_t timer_value; 6152 uint8_t igu_sb_id; 6153 uint8_t igu_seg_id; 6154 #endif 6155 uint32_t time_to_expire; 6156 }; 6157 6158 /* 6159 * hold PCI identification variables- used in various places in firmware 6160 */ 6161 struct pci_entity { 6162 #if defined(__BIG_ENDIAN) 6163 uint8_t vf_valid; 6164 uint8_t vf_id; 6165 uint8_t vnic_id; 6166 uint8_t pf_id; 6167 #elif defined(__LITTLE_ENDIAN) 6168 uint8_t pf_id; 6169 uint8_t vnic_id; 6170 uint8_t vf_id; 6171 uint8_t vf_valid; 6172 #endif 6173 }; 6174 6175 /* 6176 * The fast-path status block meta-data, common to all chips 6177 */ 6178 struct hc_sb_data { 6179 struct regpair_native host_sb_addr; 6180 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 6181 struct pci_entity p_func; 6182 #if defined(__BIG_ENDIAN) 6183 uint8_t rsrv0; 6184 uint8_t state; 6185 uint8_t dhc_qzone_id; 6186 uint8_t same_igu_sb_1b; 6187 #elif defined(__LITTLE_ENDIAN) 6188 uint8_t same_igu_sb_1b; 6189 uint8_t dhc_qzone_id; 6190 uint8_t state; 6191 uint8_t rsrv0; 6192 #endif 6193 struct regpair_native rsrv1[2]; 6194 }; 6195 6196 6197 /* 6198 * Segment types for host coalescing 6199 */ 6200 enum hc_segment { 6201 HC_REGULAR_SEGMENT, 6202 HC_DEFAULT_SEGMENT, 6203 MAX_HC_SEGMENT}; 6204 6205 6206 /* 6207 * The fast-path status block meta-data 6208 */ 6209 struct hc_sp_status_block_data { 6210 struct regpair_native host_sb_addr; 6211 #if defined(__BIG_ENDIAN) 6212 uint8_t rsrv1; 6213 uint8_t state; 6214 uint8_t igu_seg_id; 6215 uint8_t igu_sb_id; 6216 #elif defined(__LITTLE_ENDIAN) 6217 uint8_t igu_sb_id; 6218 uint8_t igu_seg_id; 6219 uint8_t state; 6220 uint8_t rsrv1; 6221 #endif 6222 struct pci_entity p_func; 6223 }; 6224 6225 6226 /* 6227 * The fast-path status block meta-data 6228 */ 6229 struct hc_status_block_data_e1x { 6230 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 6231 struct hc_sb_data common; 6232 }; 6233 6234 6235 /* 6236 * The fast-path status block meta-data 6237 */ 6238 struct hc_status_block_data_e2 { 6239 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 6240 struct hc_sb_data common; 6241 }; 6242 6243 6244 /* 6245 * IGU block operation modes (in Everest2) 6246 */ 6247 enum igu_mode { 6248 HC_IGU_BC_MODE, 6249 HC_IGU_NBC_MODE, 6250 MAX_IGU_MODE}; 6251 6252 6253 /* 6254 * Inner Headers Classification Type 6255 */ 6256 enum inner_clss_type { 6257 INNER_CLSS_DISABLED, 6258 INNER_CLSS_USE_VLAN, 6259 INNER_CLSS_USE_VNI, 6260 MAX_INNER_CLSS_TYPE}; 6261 6262 6263 /* 6264 * IP versions 6265 */ 6266 enum ip_ver { 6267 IP_V4, 6268 IP_V6, 6269 MAX_IP_VER}; 6270 6271 6272 /* 6273 * Malicious VF error ID 6274 */ 6275 enum malicious_vf_error_id { 6276 MALICIOUS_VF_NO_ERROR, 6277 VF_PF_CHANNEL_NOT_READY, 6278 ETH_ILLEGAL_BD_LENGTHS, 6279 ETH_PACKET_TOO_SHORT, 6280 ETH_PAYLOAD_TOO_BIG, 6281 ETH_ILLEGAL_ETH_TYPE, 6282 ETH_ILLEGAL_LSO_HDR_LEN, 6283 ETH_TOO_MANY_BDS, 6284 ETH_ZERO_HDR_NBDS, 6285 ETH_START_BD_NOT_SET, 6286 ETH_ILLEGAL_PARSE_NBDS, 6287 ETH_IPV6_AND_CHECKSUM, 6288 ETH_VLAN_FLG_INCORRECT, 6289 ETH_ILLEGAL_LSO_MSS, 6290 ETH_TUNNEL_NOT_SUPPORTED, 6291 MAX_MALICIOUS_VF_ERROR_ID}; 6292 6293 6294 /* 6295 * Multi-function modes 6296 */ 6297 enum mf_mode { 6298 SINGLE_FUNCTION, 6299 MULTI_FUNCTION_SD, 6300 MULTI_FUNCTION_SI, 6301 MULTI_FUNCTION_AFEX, 6302 MAX_MF_MODE}; 6303 6304 6305 /* 6306 * Protocol-common statistics collected by the Tstorm (per pf) 6307 */ 6308 struct tstorm_per_pf_stats { 6309 struct regpair rcv_error_bytes; 6310 }; 6311 6312 /* 6313 * 6314 */ 6315 struct per_pf_stats { 6316 struct tstorm_per_pf_stats tstorm_pf_statistics; 6317 }; 6318 6319 6320 /* 6321 * Protocol-common statistics collected by the Tstorm (per port) 6322 */ 6323 struct tstorm_per_port_stats { 6324 __le32 mac_discard; 6325 __le32 mac_filter_discard; 6326 __le32 brb_truncate_discard; 6327 __le32 mf_tag_discard; 6328 __le32 packet_drop; 6329 __le32 reserved; 6330 }; 6331 6332 /* 6333 * 6334 */ 6335 struct per_port_stats { 6336 struct tstorm_per_port_stats tstorm_port_statistics; 6337 }; 6338 6339 6340 /* 6341 * Protocol-common statistics collected by the Tstorm (per client) 6342 */ 6343 struct tstorm_per_queue_stats { 6344 struct regpair rcv_ucast_bytes; 6345 __le32 rcv_ucast_pkts; 6346 __le32 checksum_discard; 6347 struct regpair rcv_bcast_bytes; 6348 __le32 rcv_bcast_pkts; 6349 __le32 pkts_too_big_discard; 6350 struct regpair rcv_mcast_bytes; 6351 __le32 rcv_mcast_pkts; 6352 __le32 ttl0_discard; 6353 __le16 no_buff_discard; 6354 __le16 reserved0; 6355 __le32 reserved1; 6356 }; 6357 6358 /* 6359 * Protocol-common statistics collected by the Ustorm (per client) 6360 */ 6361 struct ustorm_per_queue_stats { 6362 struct regpair ucast_no_buff_bytes; 6363 struct regpair mcast_no_buff_bytes; 6364 struct regpair bcast_no_buff_bytes; 6365 __le32 ucast_no_buff_pkts; 6366 __le32 mcast_no_buff_pkts; 6367 __le32 bcast_no_buff_pkts; 6368 __le32 coalesced_pkts; 6369 struct regpair coalesced_bytes; 6370 __le32 coalesced_events; 6371 __le32 coalesced_aborts; 6372 }; 6373 6374 /* 6375 * Protocol-common statistics collected by the Xstorm (per client) 6376 */ 6377 struct xstorm_per_queue_stats { 6378 struct regpair ucast_bytes_sent; 6379 struct regpair mcast_bytes_sent; 6380 struct regpair bcast_bytes_sent; 6381 __le32 ucast_pkts_sent; 6382 __le32 mcast_pkts_sent; 6383 __le32 bcast_pkts_sent; 6384 __le32 error_drop_pkts; 6385 }; 6386 6387 /* 6388 * 6389 */ 6390 struct per_queue_stats { 6391 struct tstorm_per_queue_stats tstorm_queue_statistics; 6392 struct ustorm_per_queue_stats ustorm_queue_statistics; 6393 struct xstorm_per_queue_stats xstorm_queue_statistics; 6394 }; 6395 6396 6397 /* 6398 * FW version stored in first line of pram 6399 */ 6400 struct pram_fw_version { 6401 uint8_t major; 6402 uint8_t minor; 6403 uint8_t revision; 6404 uint8_t engineering; 6405 uint8_t flags; 6406 #define PRAM_FW_VERSION_OPTIMIZED (0x1 << 0) 6407 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 6408 #define PRAM_FW_VERSION_STORM_ID (0x3 << 1) 6409 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 6410 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1 << 3) 6411 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 6412 #define PRAM_FW_VERSION_CHIP_VERSION (0x3 << 4) 6413 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 6414 #define __PRAM_FW_VERSION_RESERVED0 (0x3 << 6) 6415 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 6416 }; 6417 6418 6419 /* 6420 * Ethernet slow path element 6421 */ 6422 union protocol_common_specific_data { 6423 uint8_t protocol_data[8]; 6424 struct regpair phy_address; 6425 struct regpair mac_config_addr; 6426 struct afex_vif_list_ramrod_data afex_vif_list_data; 6427 }; 6428 6429 /* 6430 * The send queue element 6431 */ 6432 struct protocol_common_spe { 6433 struct spe_hdr hdr; 6434 union protocol_common_specific_data data; 6435 }; 6436 6437 6438 /* 6439 * The data for the Set Timesync Ramrod 6440 */ 6441 struct set_timesync_ramrod_data { 6442 uint8_t drift_adjust_cmd; 6443 uint8_t offset_cmd; 6444 uint8_t add_sub_drift_adjust_value; 6445 uint8_t drift_adjust_value; 6446 uint32_t drift_adjust_period; 6447 struct regpair offset_delta; 6448 }; 6449 6450 6451 /* 6452 * The send queue element 6453 */ 6454 struct slow_path_element { 6455 struct spe_hdr hdr; 6456 struct regpair protocol_data; 6457 }; 6458 6459 6460 /* 6461 * Protocol-common statistics counter 6462 */ 6463 struct stats_counter { 6464 __le16 xstats_counter; 6465 __le16 reserved0; 6466 __le32 reserved1; 6467 __le16 tstats_counter; 6468 __le16 reserved2; 6469 __le32 reserved3; 6470 __le16 ustats_counter; 6471 __le16 reserved4; 6472 __le32 reserved5; 6473 __le16 cstats_counter; 6474 __le16 reserved6; 6475 __le32 reserved7; 6476 }; 6477 6478 6479 /* 6480 * 6481 */ 6482 struct stats_query_entry { 6483 uint8_t kind; 6484 uint8_t index; 6485 __le16 funcID; 6486 __le32 reserved; 6487 struct regpair address; 6488 }; 6489 6490 /* 6491 * statistic command 6492 */ 6493 struct stats_query_cmd_group { 6494 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 6495 }; 6496 6497 6498 /* 6499 * statistic command header 6500 */ 6501 struct stats_query_header { 6502 uint8_t cmd_num; 6503 uint8_t reserved0; 6504 __le16 drv_stats_counter; 6505 __le32 reserved1; 6506 struct regpair stats_counters_addrs; 6507 }; 6508 6509 6510 /* 6511 * Types of statistics query entry 6512 */ 6513 enum stats_query_type { 6514 STATS_TYPE_QUEUE, 6515 STATS_TYPE_PORT, 6516 STATS_TYPE_PF, 6517 STATS_TYPE_TOE, 6518 STATS_TYPE_FCOE, 6519 MAX_STATS_QUERY_TYPE}; 6520 6521 6522 /* 6523 * Indicate of the function status block state 6524 */ 6525 enum status_block_state { 6526 SB_DISABLED, 6527 SB_ENABLED, 6528 SB_CLEANED, 6529 MAX_STATUS_BLOCK_STATE}; 6530 6531 6532 /* 6533 * Storm IDs (including attentions for IGU related enums) 6534 */ 6535 enum storm_id { 6536 USTORM_ID, 6537 CSTORM_ID, 6538 XSTORM_ID, 6539 TSTORM_ID, 6540 ATTENTION_ID, 6541 MAX_STORM_ID}; 6542 6543 6544 /* 6545 * Traffic types used in ETS and flow control algorithms 6546 */ 6547 enum traffic_type { 6548 LLFC_TRAFFIC_TYPE_NW, 6549 LLFC_TRAFFIC_TYPE_FCOE, 6550 LLFC_TRAFFIC_TYPE_ISCSI, 6551 MAX_TRAFFIC_TYPE}; 6552 6553 6554 /* 6555 * zone A per-queue data 6556 */ 6557 struct tstorm_queue_zone_data { 6558 struct regpair reserved[4]; 6559 }; 6560 6561 6562 /* 6563 * zone B per-VF data 6564 */ 6565 struct tstorm_vf_zone_data { 6566 struct regpair reserved; 6567 }; 6568 6569 6570 /* 6571 * Add or Subtract Value for Set Timesync Ramrod 6572 */ 6573 enum ts_add_sub_value { 6574 TS_SUB_VALUE, 6575 TS_ADD_VALUE, 6576 MAX_TS_ADD_SUB_VALUE}; 6577 6578 6579 /* 6580 * Drift-Adjust Commands for Set Timesync Ramrod 6581 */ 6582 enum ts_drift_adjust_cmd { 6583 TS_DRIFT_ADJUST_KEEP, 6584 TS_DRIFT_ADJUST_SET, 6585 TS_DRIFT_ADJUST_RESET, 6586 MAX_TS_DRIFT_ADJUST_CMD}; 6587 6588 6589 /* 6590 * Offset Commands for Set Timesync Ramrod 6591 */ 6592 enum ts_offset_cmd { 6593 TS_OFFSET_KEEP, 6594 TS_OFFSET_INC, 6595 TS_OFFSET_DEC, 6596 MAX_TS_OFFSET_CMD}; 6597 6598 6599 /* 6600 * Input for measuring Pci Latency 6601 */ 6602 struct t_measure_pci_latency_ctrl { 6603 struct regpair read_addr; 6604 #if defined(__BIG_ENDIAN) 6605 uint8_t sleep; 6606 uint8_t enable; 6607 uint8_t func_id; 6608 uint8_t read_size; 6609 #elif defined(__LITTLE_ENDIAN) 6610 uint8_t read_size; 6611 uint8_t func_id; 6612 uint8_t enable; 6613 uint8_t sleep; 6614 #endif 6615 #if defined(__BIG_ENDIAN) 6616 uint16_t num_meas; 6617 uint8_t reserved; 6618 uint8_t period_10us; 6619 #elif defined(__LITTLE_ENDIAN) 6620 uint8_t period_10us; 6621 uint8_t reserved; 6622 uint16_t num_meas; 6623 #endif 6624 }; 6625 6626 6627 /* 6628 * Input for measuring Pci Latency 6629 */ 6630 struct t_measure_pci_latency_data { 6631 #if defined(__BIG_ENDIAN) 6632 uint16_t max_time_ns; 6633 uint16_t min_time_ns; 6634 #elif defined(__LITTLE_ENDIAN) 6635 uint16_t min_time_ns; 6636 uint16_t max_time_ns; 6637 #endif 6638 #if defined(__BIG_ENDIAN) 6639 uint16_t reserved; 6640 uint16_t num_reads; 6641 #elif defined(__LITTLE_ENDIAN) 6642 uint16_t num_reads; 6643 uint16_t reserved; 6644 #endif 6645 struct regpair sum_time_ns; 6646 }; 6647 6648 6649 /* 6650 * zone A per-queue data 6651 */ 6652 struct ustorm_queue_zone_data { 6653 struct ustorm_eth_rx_producers eth_rx_producers; 6654 struct regpair reserved[3]; 6655 }; 6656 6657 6658 /* 6659 * zone B per-VF data 6660 */ 6661 struct ustorm_vf_zone_data { 6662 struct regpair reserved; 6663 }; 6664 6665 6666 /* 6667 * data per VF-PF channel 6668 */ 6669 struct vf_pf_channel_data { 6670 #if defined(__BIG_ENDIAN) 6671 uint16_t reserved0; 6672 uint8_t valid; 6673 uint8_t state; 6674 #elif defined(__LITTLE_ENDIAN) 6675 uint8_t state; 6676 uint8_t valid; 6677 uint16_t reserved0; 6678 #endif 6679 uint32_t reserved1; 6680 }; 6681 6682 6683 /* 6684 * State of VF-PF channel 6685 */ 6686 enum vf_pf_channel_state { 6687 VF_PF_CHANNEL_STATE_READY, 6688 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 6689 MAX_VF_PF_CHANNEL_STATE}; 6690 6691 6692 /* 6693 * vif_list_rule_kind 6694 */ 6695 enum vif_list_rule_kind { 6696 VIF_LIST_RULE_SET, 6697 VIF_LIST_RULE_GET, 6698 VIF_LIST_RULE_CLEAR_ALL, 6699 VIF_LIST_RULE_CLEAR_FUNC, 6700 MAX_VIF_LIST_RULE_KIND}; 6701 6702 6703 /* 6704 * zone A per-queue data 6705 */ 6706 struct xstorm_queue_zone_data { 6707 struct regpair reserved[4]; 6708 }; 6709 6710 6711 /* 6712 * zone B per-VF data 6713 */ 6714 struct xstorm_vf_zone_data { 6715 struct regpair reserved; 6716 }; 6717 6718 #endif /* ECORE_HSI_H */ 6719