1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" 2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s 3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV 4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +mte -target-feature +bti -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-MTE-BTI 5 6 int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; } 7 int __attribute__((target_clones("sha2", "sha2+memtag", " default "))) ftc_def(void) { return 1; } 8 int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; } 9 int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; } 10 int __attribute__((target_clones("memtag", "bti"))) ftc_dup3(void) { return 4; } 11 int foo() { 12 return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3(); 13 } 14 15 inline int __attribute__((target_clones("rng+simd", "rcpc", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; } 16 inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void); 17 inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; } 18 19 int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; } 20 21 int __attribute__((target_clones("default"))) main() { 22 return ftc_inline1() + ftc_inline2() + ftc_inline3() + ftc_direct(); 23 } 24 inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))) ftc_inline2(void) { return 2; }; 25 26 27 28 //. 29 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } 30 // CHECK: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver 31 // CHECK: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver 32 // CHECK: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver 33 // CHECK: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver 34 // CHECK: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver 35 // CHECK: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver 36 // CHECK: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver 37 // CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver 38 //. 39 // CHECK-MTE-BTI: @__aarch64_cpu_features = external dso_local global { i64 } 40 // CHECK-MTE-BTI: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver 41 // CHECK-MTE-BTI: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver 42 // CHECK-MTE-BTI: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver 43 // CHECK-MTE-BTI: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver 44 // CHECK-MTE-BTI: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver 45 // CHECK-MTE-BTI: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver 46 // CHECK-MTE-BTI: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver 47 // CHECK-MTE-BTI: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver 48 //. 49 // CHECK: Function Attrs: noinline nounwind optnone 50 // CHECK-LABEL: define {{[^@]+}}@ftc._MaesMlse 51 // CHECK-SAME: () #[[ATTR0:[0-9]+]] { 52 // CHECK-NEXT: entry: 53 // CHECK-NEXT: ret i32 0 54 // 55 // 56 // CHECK: Function Attrs: noinline nounwind optnone 57 // CHECK-LABEL: define {{[^@]+}}@ftc._Msve2 58 // CHECK-SAME: () #[[ATTR1:[0-9]+]] { 59 // CHECK-NEXT: entry: 60 // CHECK-NEXT: ret i32 0 61 // 62 // 63 // CHECK-LABEL: define {{[^@]+}}@ftc.resolver() comdat { 64 // CHECK-NEXT: resolver_entry: 65 // CHECK-NEXT: call void @__init_cpu_features_resolver() 66 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 67 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352 68 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352 69 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 70 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 71 // CHECK: resolver_return: 72 // CHECK-NEXT: ret ptr @ftc._Msve2 73 // CHECK: resolver_else: 74 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 75 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664 76 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664 77 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 78 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 79 // CHECK: resolver_return1: 80 // CHECK-NEXT: ret ptr @ftc._MaesMlse 81 // CHECK: resolver_else2: 82 // CHECK-NEXT: ret ptr @ftc.default 83 // 84 // 85 // CHECK: Function Attrs: noinline nounwind optnone 86 // CHECK-LABEL: define {{[^@]+}}@ftc_def._Msha2 87 // CHECK-SAME: () #[[ATTR2:[0-9]+]] { 88 // CHECK-NEXT: entry: 89 // CHECK-NEXT: ret i32 1 90 // 91 // 92 // CHECK: Function Attrs: noinline nounwind optnone 93 // CHECK-LABEL: define {{[^@]+}}@ftc_def._MmemtagMsha2 94 // CHECK-SAME: () #[[ATTR3:[0-9]+]] { 95 // CHECK-NEXT: entry: 96 // CHECK-NEXT: ret i32 1 97 // 98 // 99 // CHECK-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { 100 // CHECK-NEXT: resolver_entry: 101 // CHECK-NEXT: call void @__init_cpu_features_resolver() 102 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 103 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 104 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 105 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 106 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 107 // CHECK: resolver_return: 108 // CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2 109 // CHECK: resolver_else: 110 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 111 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 112 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 113 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 114 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 115 // CHECK: resolver_return1: 116 // CHECK-NEXT: ret ptr @ftc_def._Msha2 117 // CHECK: resolver_else2: 118 // CHECK-NEXT: ret ptr @ftc_def.default 119 // 120 // 121 // CHECK: Function Attrs: noinline nounwind optnone 122 // CHECK-LABEL: define {{[^@]+}}@ftc_dup1._Msha2 123 // CHECK-SAME: () #[[ATTR2]] { 124 // CHECK-NEXT: entry: 125 // CHECK-NEXT: ret i32 2 126 // 127 // 128 // CHECK-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { 129 // CHECK-NEXT: resolver_entry: 130 // CHECK-NEXT: call void @__init_cpu_features_resolver() 131 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 132 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 133 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 134 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 135 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 136 // CHECK: resolver_return: 137 // CHECK-NEXT: ret ptr @ftc_dup1._Msha2 138 // CHECK: resolver_else: 139 // CHECK-NEXT: ret ptr @ftc_dup1.default 140 // 141 // 142 // CHECK: Function Attrs: noinline nounwind optnone 143 // CHECK-LABEL: define {{[^@]+}}@ftc_dup2._Mfp 144 // CHECK-SAME: () #[[ATTR4:[0-9]+]] { 145 // CHECK-NEXT: entry: 146 // CHECK-NEXT: ret i32 3 147 // 148 // 149 // CHECK: Function Attrs: noinline nounwind optnone 150 // CHECK-LABEL: define {{[^@]+}}@ftc_dup2._McrcMdotprod 151 // CHECK-SAME: () #[[ATTR5:[0-9]+]] { 152 // CHECK-NEXT: entry: 153 // CHECK-NEXT: ret i32 3 154 // 155 // 156 // CHECK-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { 157 // CHECK-NEXT: resolver_entry: 158 // CHECK-NEXT: call void @__init_cpu_features_resolver() 159 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 160 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 161 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 162 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 163 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 164 // CHECK: resolver_return: 165 // CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod 166 // CHECK: resolver_else: 167 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 168 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 169 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 170 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 171 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 172 // CHECK: resolver_return1: 173 // CHECK-NEXT: ret ptr @ftc_dup2._Mfp 174 // CHECK: resolver_else2: 175 // CHECK-NEXT: ret ptr @ftc_dup2.default 176 // 177 // 178 // CHECK: Function Attrs: noinline nounwind optnone 179 // CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag 180 // CHECK-SAME: () #[[ATTR6:[0-9]+]] { 181 // CHECK-NEXT: entry: 182 // CHECK-NEXT: ret i32 4 183 // 184 // 185 // CHECK: Function Attrs: noinline nounwind optnone 186 // CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mbti 187 // CHECK-SAME: () #[[ATTR7:[0-9]+]] { 188 // CHECK-NEXT: entry: 189 // CHECK-NEXT: ret i32 4 190 // 191 // 192 // CHECK-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { 193 // CHECK-NEXT: resolver_entry: 194 // CHECK-NEXT: call void @__init_cpu_features_resolver() 195 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 196 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 197 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 198 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 199 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 200 // CHECK: resolver_return: 201 // CHECK-NEXT: ret ptr @ftc_dup3._Mbti 202 // CHECK: resolver_else: 203 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 204 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 205 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 206 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 207 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 208 // CHECK: resolver_return1: 209 // CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag 210 // CHECK: resolver_else2: 211 // CHECK-NEXT: ret ptr @ftc_dup3.default 212 // 213 // 214 // CHECK: Function Attrs: noinline nounwind optnone 215 // CHECK-LABEL: define {{[^@]+}}@foo 216 // CHECK-SAME: () #[[ATTR8:[0-9]+]] { 217 // CHECK-NEXT: entry: 218 // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc() 219 // CHECK-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() 220 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 221 // CHECK-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1() 222 // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 223 // CHECK-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() 224 // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 225 // CHECK-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() 226 // CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] 227 // CHECK-NEXT: ret i32 [[ADD7]] 228 // 229 // 230 // CHECK: Function Attrs: noinline nounwind optnone 231 // CHECK-LABEL: define {{[^@]+}}@ftc_direct 232 // CHECK-SAME: () #[[ATTR8]] { 233 // CHECK-NEXT: entry: 234 // CHECK-NEXT: ret i32 4 235 // 236 // 237 // CHECK: Function Attrs: noinline nounwind optnone 238 // CHECK-LABEL: define {{[^@]+}}@main 239 // CHECK-SAME: () #[[ATTR8]] { 240 // CHECK-NEXT: entry: 241 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 242 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 243 // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1() 244 // CHECK-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2() 245 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 246 // CHECK-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3() 247 // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 248 // CHECK-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() 249 // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 250 // CHECK-NEXT: ret i32 [[ADD5]] 251 // 252 // 253 // CHECK: Function Attrs: noinline nounwind optnone 254 // CHECK-LABEL: define {{[^@]+}}@ftc.default 255 // CHECK-SAME: () #[[ATTR9:[0-9]+]] { 256 // CHECK-NEXT: entry: 257 // CHECK-NEXT: ret i32 0 258 // 259 // 260 // CHECK: Function Attrs: noinline nounwind optnone 261 // CHECK-LABEL: define {{[^@]+}}@ftc_def.default 262 // CHECK-SAME: () #[[ATTR9]] { 263 // CHECK-NEXT: entry: 264 // CHECK-NEXT: ret i32 1 265 // 266 // 267 // CHECK: Function Attrs: noinline nounwind optnone 268 // CHECK-LABEL: define {{[^@]+}}@ftc_dup1.default 269 // CHECK-SAME: () #[[ATTR9]] { 270 // CHECK-NEXT: entry: 271 // CHECK-NEXT: ret i32 2 272 // 273 // 274 // CHECK: Function Attrs: noinline nounwind optnone 275 // CHECK-LABEL: define {{[^@]+}}@ftc_dup2.default 276 // CHECK-SAME: () #[[ATTR9]] { 277 // CHECK-NEXT: entry: 278 // CHECK-NEXT: ret i32 3 279 // 280 // 281 // CHECK: Function Attrs: noinline nounwind optnone 282 // CHECK-LABEL: define {{[^@]+}}@ftc_dup3.default 283 // CHECK-SAME: () #[[ATTR9]] { 284 // CHECK-NEXT: entry: 285 // CHECK-NEXT: ret i32 4 286 // 287 // 288 // CHECK: Function Attrs: noinline nounwind optnone 289 // CHECK-LABEL: define {{[^@]+}}@ftc_inline2._Mfp16 290 // CHECK-SAME: () #[[ATTR10:[0-9]+]] { 291 // CHECK-NEXT: entry: 292 // CHECK-NEXT: ret i32 2 293 // 294 // 295 // CHECK: Function Attrs: noinline nounwind optnone 296 // CHECK-LABEL: define {{[^@]+}}@ftc_inline2._MfcmaMsve2-bitperm 297 // CHECK-SAME: () #[[ATTR11:[0-9]+]] { 298 // CHECK-NEXT: entry: 299 // CHECK-NEXT: ret i32 2 300 // 301 // 302 // CHECK: Function Attrs: noinline nounwind optnone 303 // CHECK-LABEL: define {{[^@]+}}@ftc_inline2.default 304 // CHECK-SAME: () #[[ATTR9]] { 305 // CHECK-NEXT: entry: 306 // CHECK-NEXT: ret i32 2 307 // 308 // 309 // CHECK-LABEL: define {{[^@]+}}@ftc_inline2.resolver() comdat { 310 // CHECK-NEXT: resolver_entry: 311 // CHECK-NEXT: call void @__init_cpu_features_resolver() 312 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 313 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 619551195904 314 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 619551195904 315 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 316 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 317 // CHECK: resolver_return: 318 // CHECK-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm 319 // CHECK: resolver_else: 320 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 321 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65792 322 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65792 323 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 324 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 325 // CHECK: resolver_return1: 326 // CHECK-NEXT: ret ptr @ftc_inline2._Mfp16 327 // CHECK: resolver_else2: 328 // CHECK-NEXT: ret ptr @ftc_inline2.default 329 // 330 // 331 // CHECK: Function Attrs: noinline nounwind optnone 332 // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._MrngMsimd 333 // CHECK-SAME: () #[[ATTR12:[0-9]+]] { 334 // CHECK-NEXT: entry: 335 // CHECK-NEXT: ret i32 1 336 // 337 // 338 // CHECK: Function Attrs: noinline nounwind optnone 339 // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc 340 // CHECK-SAME: () #[[ATTR13:[0-9]+]] { 341 // CHECK-NEXT: entry: 342 // CHECK-NEXT: ret i32 1 343 // 344 // 345 // CHECK: Function Attrs: noinline nounwind optnone 346 // CHECK-LABEL: define {{[^@]+}}@ftc_inline1._Msve2-aesMwfxt 347 // CHECK-SAME: () #[[ATTR14:[0-9]+]] { 348 // CHECK-NEXT: entry: 349 // CHECK-NEXT: ret i32 1 350 // 351 // 352 // CHECK: Function Attrs: noinline nounwind optnone 353 // CHECK-LABEL: define {{[^@]+}}@ftc_inline1.default 354 // CHECK-SAME: () #[[ATTR9]] { 355 // CHECK-NEXT: entry: 356 // CHECK-NEXT: ret i32 1 357 // 358 // 359 // CHECK-LABEL: define {{[^@]+}}@ftc_inline1.resolver() comdat { 360 // CHECK-NEXT: resolver_entry: 361 // CHECK-NEXT: call void @__init_cpu_features_resolver() 362 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 363 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014743180706560 364 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014743180706560 365 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 366 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 367 // CHECK: resolver_return: 368 // CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt 369 // CHECK: resolver_else: 370 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 371 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304 372 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304 373 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 374 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 375 // CHECK: resolver_return1: 376 // CHECK-NEXT: ret ptr @ftc_inline1._Mrcpc 377 // CHECK: resolver_else2: 378 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 379 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769 380 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 769 381 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] 382 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 383 // CHECK: resolver_return3: 384 // CHECK-NEXT: ret ptr @ftc_inline1._MrngMsimd 385 // CHECK: resolver_else4: 386 // CHECK-NEXT: ret ptr @ftc_inline1.default 387 // 388 // 389 // CHECK: Function Attrs: noinline nounwind optnone 390 // CHECK-LABEL: define {{[^@]+}}@ftc_inline3._Mbti 391 // CHECK-SAME: () #[[ATTR7]] { 392 // CHECK-NEXT: entry: 393 // CHECK-NEXT: ret i32 3 394 // 395 // 396 // CHECK: Function Attrs: noinline nounwind optnone 397 // CHECK-LABEL: define {{[^@]+}}@ftc_inline3._MsbMsve 398 // CHECK-SAME: () #[[ATTR15:[0-9]+]] { 399 // CHECK-NEXT: entry: 400 // CHECK-NEXT: ret i32 3 401 // 402 // 403 // CHECK: Function Attrs: noinline nounwind optnone 404 // CHECK-LABEL: define {{[^@]+}}@ftc_inline3.default 405 // CHECK-SAME: () #[[ATTR9]] { 406 // CHECK-NEXT: entry: 407 // CHECK-NEXT: ret i32 3 408 // 409 // 410 // CHECK-LABEL: define {{[^@]+}}@ftc_inline3.resolver() comdat { 411 // CHECK-NEXT: resolver_entry: 412 // CHECK-NEXT: call void @__init_cpu_features_resolver() 413 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 414 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 415 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 416 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 417 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 418 // CHECK: resolver_return: 419 // CHECK-NEXT: ret ptr @ftc_inline3._Mbti 420 // CHECK: resolver_else: 421 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 422 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280 423 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280 424 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 425 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 426 // CHECK: resolver_return1: 427 // CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve 428 // CHECK: resolver_else2: 429 // CHECK-NEXT: ret ptr @ftc_inline3.default 430 // 431 // 432 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 433 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc 434 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { 435 // CHECK-NOFMV-NEXT: entry: 436 // CHECK-NOFMV-NEXT: ret i32 0 437 // 438 // 439 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 440 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc_def 441 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 442 // CHECK-NOFMV-NEXT: entry: 443 // CHECK-NOFMV-NEXT: ret i32 1 444 // 445 // 446 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 447 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc_dup1 448 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 449 // CHECK-NOFMV-NEXT: entry: 450 // CHECK-NOFMV-NEXT: ret i32 2 451 // 452 // 453 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 454 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc_dup2 455 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 456 // CHECK-NOFMV-NEXT: entry: 457 // CHECK-NOFMV-NEXT: ret i32 3 458 // 459 // 460 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 461 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc_dup3 462 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 463 // CHECK-NOFMV-NEXT: entry: 464 // CHECK-NOFMV-NEXT: ret i32 4 465 // 466 // 467 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 468 // CHECK-NOFMV-LABEL: define {{[^@]+}}@foo 469 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 470 // CHECK-NOFMV-NEXT: entry: 471 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @ftc() 472 // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() 473 // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 474 // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1() 475 // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 476 // CHECK-NOFMV-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() 477 // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 478 // CHECK-NOFMV-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() 479 // CHECK-NOFMV-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] 480 // CHECK-NOFMV-NEXT: ret i32 [[ADD7]] 481 // 482 // 483 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 484 // CHECK-NOFMV-LABEL: define {{[^@]+}}@ftc_direct 485 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 486 // CHECK-NOFMV-NEXT: entry: 487 // CHECK-NOFMV-NEXT: ret i32 4 488 // 489 // 490 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 491 // CHECK-NOFMV-LABEL: define {{[^@]+}}@main 492 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 493 // CHECK-NOFMV-NEXT: entry: 494 // CHECK-NOFMV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 495 // CHECK-NOFMV-NEXT: store i32 0, ptr [[RETVAL]], align 4 496 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1() 497 // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2() 498 // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 499 // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3() 500 // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 501 // CHECK-NOFMV-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() 502 // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 503 // CHECK-NOFMV-NEXT: ret i32 [[ADD5]] 504 // 505 // 506 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 507 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc._MaesMlse 508 // CHECK-MTE-BTI-SAME: () #[[ATTR0:[0-9]+]] { 509 // CHECK-MTE-BTI-NEXT: entry: 510 // CHECK-MTE-BTI-NEXT: ret i32 0 511 // 512 // 513 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 514 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc._Msve2 515 // CHECK-MTE-BTI-SAME: () #[[ATTR1:[0-9]+]] { 516 // CHECK-MTE-BTI-NEXT: entry: 517 // CHECK-MTE-BTI-NEXT: ret i32 0 518 // 519 // 520 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc.resolver() comdat { 521 // CHECK-MTE-BTI-NEXT: resolver_entry: 522 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 523 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 524 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352 525 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352 526 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 527 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 528 // CHECK-MTE-BTI: resolver_return: 529 // CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2 530 // CHECK-MTE-BTI: resolver_else: 531 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 532 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664 533 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664 534 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 535 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 536 // CHECK-MTE-BTI: resolver_return1: 537 // CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse 538 // CHECK-MTE-BTI: resolver_else2: 539 // CHECK-MTE-BTI-NEXT: ret ptr @ftc.default 540 // 541 // 542 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 543 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def._Msha2 544 // CHECK-MTE-BTI-SAME: () #[[ATTR2:[0-9]+]] { 545 // CHECK-MTE-BTI-NEXT: entry: 546 // CHECK-MTE-BTI-NEXT: ret i32 1 547 // 548 // 549 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 550 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def._MmemtagMsha2 551 // CHECK-MTE-BTI-SAME: () #[[ATTR3:[0-9]+]] { 552 // CHECK-MTE-BTI-NEXT: entry: 553 // CHECK-MTE-BTI-NEXT: ret i32 1 554 // 555 // 556 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.resolver() comdat { 557 // CHECK-MTE-BTI-NEXT: resolver_entry: 558 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 559 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 560 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186049280 561 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186049280 562 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 563 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 564 // CHECK-MTE-BTI: resolver_return: 565 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._MmemtagMsha2 566 // CHECK-MTE-BTI: resolver_else: 567 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 568 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4864 569 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4864 570 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 571 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 572 // CHECK-MTE-BTI: resolver_return1: 573 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Msha2 574 // CHECK-MTE-BTI: resolver_else2: 575 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_def.default 576 // 577 // 578 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 579 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1._Msha2 580 // CHECK-MTE-BTI-SAME: () #[[ATTR2]] { 581 // CHECK-MTE-BTI-NEXT: entry: 582 // CHECK-MTE-BTI-NEXT: ret i32 2 583 // 584 // 585 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.resolver() comdat { 586 // CHECK-MTE-BTI-NEXT: resolver_entry: 587 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 588 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 589 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4864 590 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4864 591 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 592 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 593 // CHECK-MTE-BTI: resolver_return: 594 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1._Msha2 595 // CHECK-MTE-BTI: resolver_else: 596 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup1.default 597 // 598 // 599 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 600 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2._Mfp 601 // CHECK-MTE-BTI-SAME: () #[[ATTR4:[0-9]+]] { 602 // CHECK-MTE-BTI-NEXT: entry: 603 // CHECK-MTE-BTI-NEXT: ret i32 3 604 // 605 // 606 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 607 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2._McrcMdotprod 608 // CHECK-MTE-BTI-SAME: () #[[ATTR5:[0-9]+]] { 609 // CHECK-MTE-BTI-NEXT: entry: 610 // CHECK-MTE-BTI-NEXT: ret i32 3 611 // 612 // 613 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.resolver() comdat { 614 // CHECK-MTE-BTI-NEXT: resolver_entry: 615 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 616 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 617 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1808 618 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1808 619 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 620 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 621 // CHECK-MTE-BTI: resolver_return: 622 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._McrcMdotprod 623 // CHECK-MTE-BTI: resolver_else: 624 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 625 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 626 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 627 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 628 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 629 // CHECK-MTE-BTI: resolver_return1: 630 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2._Mfp 631 // CHECK-MTE-BTI: resolver_else2: 632 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup2.default 633 // 634 // 635 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 636 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag 637 // CHECK-MTE-BTI-SAME: () #[[ATTR6:[0-9]+]] { 638 // CHECK-MTE-BTI-NEXT: entry: 639 // CHECK-MTE-BTI-NEXT: ret i32 4 640 // 641 // 642 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 643 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mbti 644 // CHECK-MTE-BTI-SAME: () #[[ATTR7:[0-9]+]] { 645 // CHECK-MTE-BTI-NEXT: entry: 646 // CHECK-MTE-BTI-NEXT: ret i32 4 647 // 648 // 649 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.resolver() comdat { 650 // CHECK-MTE-BTI-NEXT: resolver_entry: 651 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 652 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 653 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 654 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 655 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 656 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 657 // CHECK-MTE-BTI: resolver_return: 658 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mbti 659 // CHECK-MTE-BTI: resolver_else: 660 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 661 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416 662 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416 663 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 664 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 665 // CHECK-MTE-BTI: resolver_return1: 666 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mmemtag 667 // CHECK-MTE-BTI: resolver_else2: 668 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3.default 669 // 670 // 671 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 672 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@foo 673 // CHECK-MTE-BTI-SAME: () #[[ATTR8:[0-9]+]] { 674 // CHECK-MTE-BTI-NEXT: entry: 675 // CHECK-MTE-BTI-NEXT: [[CALL:%.*]] = call i32 @ftc() 676 // CHECK-MTE-BTI-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() 677 // CHECK-MTE-BTI-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 678 // CHECK-MTE-BTI-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1() 679 // CHECK-MTE-BTI-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 680 // CHECK-MTE-BTI-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() 681 // CHECK-MTE-BTI-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 682 // CHECK-MTE-BTI-NEXT: [[CALL6:%.*]] = call i32 @ftc_dup3() 683 // CHECK-MTE-BTI-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] 684 // CHECK-MTE-BTI-NEXT: ret i32 [[ADD7]] 685 // 686 // 687 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 688 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_direct 689 // CHECK-MTE-BTI-SAME: () #[[ATTR8]] { 690 // CHECK-MTE-BTI-NEXT: entry: 691 // CHECK-MTE-BTI-NEXT: ret i32 4 692 // 693 // 694 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 695 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@main 696 // CHECK-MTE-BTI-SAME: () #[[ATTR8]] { 697 // CHECK-MTE-BTI-NEXT: entry: 698 // CHECK-MTE-BTI-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 699 // CHECK-MTE-BTI-NEXT: store i32 0, ptr [[RETVAL]], align 4 700 // CHECK-MTE-BTI-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1() 701 // CHECK-MTE-BTI-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2() 702 // CHECK-MTE-BTI-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 703 // CHECK-MTE-BTI-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3() 704 // CHECK-MTE-BTI-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 705 // CHECK-MTE-BTI-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() 706 // CHECK-MTE-BTI-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] 707 // CHECK-MTE-BTI-NEXT: ret i32 [[ADD5]] 708 // 709 // 710 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 711 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc.default 712 // CHECK-MTE-BTI-SAME: () #[[ATTR9:[0-9]+]] { 713 // CHECK-MTE-BTI-NEXT: entry: 714 // CHECK-MTE-BTI-NEXT: ret i32 0 715 // 716 // 717 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 718 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def.default 719 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 720 // CHECK-MTE-BTI-NEXT: entry: 721 // CHECK-MTE-BTI-NEXT: ret i32 1 722 // 723 // 724 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 725 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup1.default 726 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 727 // CHECK-MTE-BTI-NEXT: entry: 728 // CHECK-MTE-BTI-NEXT: ret i32 2 729 // 730 // 731 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 732 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup2.default 733 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 734 // CHECK-MTE-BTI-NEXT: entry: 735 // CHECK-MTE-BTI-NEXT: ret i32 3 736 // 737 // 738 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 739 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3.default 740 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 741 // CHECK-MTE-BTI-NEXT: entry: 742 // CHECK-MTE-BTI-NEXT: ret i32 4 743 // 744 // 745 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 746 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2._Mfp16 747 // CHECK-MTE-BTI-SAME: () #[[ATTR10:[0-9]+]] { 748 // CHECK-MTE-BTI-NEXT: entry: 749 // CHECK-MTE-BTI-NEXT: ret i32 2 750 // 751 // 752 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 753 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2._MfcmaMsve2-bitperm 754 // CHECK-MTE-BTI-SAME: () #[[ATTR11:[0-9]+]] { 755 // CHECK-MTE-BTI-NEXT: entry: 756 // CHECK-MTE-BTI-NEXT: ret i32 2 757 // 758 // 759 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 760 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2.default 761 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 762 // CHECK-MTE-BTI-NEXT: entry: 763 // CHECK-MTE-BTI-NEXT: ret i32 2 764 // 765 // 766 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline2.resolver() comdat { 767 // CHECK-MTE-BTI-NEXT: resolver_entry: 768 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 769 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 770 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 619551195904 771 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 619551195904 772 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 773 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 774 // CHECK-MTE-BTI: resolver_return: 775 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm 776 // CHECK-MTE-BTI: resolver_else: 777 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 778 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65792 779 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65792 780 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 781 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 782 // CHECK-MTE-BTI: resolver_return1: 783 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2._Mfp16 784 // CHECK-MTE-BTI: resolver_else2: 785 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline2.default 786 // 787 // 788 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 789 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._MrngMsimd 790 // CHECK-MTE-BTI-SAME: () #[[ATTR12:[0-9]+]] { 791 // CHECK-MTE-BTI-NEXT: entry: 792 // CHECK-MTE-BTI-NEXT: ret i32 1 793 // 794 // 795 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 796 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc 797 // CHECK-MTE-BTI-SAME: () #[[ATTR13:[0-9]+]] { 798 // CHECK-MTE-BTI-NEXT: entry: 799 // CHECK-MTE-BTI-NEXT: ret i32 1 800 // 801 // 802 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 803 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._Msve2-aesMwfxt 804 // CHECK-MTE-BTI-SAME: () #[[ATTR14:[0-9]+]] { 805 // CHECK-MTE-BTI-NEXT: entry: 806 // CHECK-MTE-BTI-NEXT: ret i32 1 807 // 808 // 809 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 810 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1.default 811 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 812 // CHECK-MTE-BTI-NEXT: entry: 813 // CHECK-MTE-BTI-NEXT: ret i32 1 814 // 815 // 816 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1.resolver() comdat { 817 // CHECK-MTE-BTI-NEXT: resolver_entry: 818 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 819 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 820 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014743180706560 821 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014743180706560 822 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 823 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 824 // CHECK-MTE-BTI: resolver_return: 825 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt 826 // CHECK-MTE-BTI: resolver_else: 827 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 828 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304 829 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304 830 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 831 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 832 // CHECK-MTE-BTI: resolver_return1: 833 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Mrcpc 834 // CHECK-MTE-BTI: resolver_else2: 835 // CHECK-MTE-BTI-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 836 // CHECK-MTE-BTI-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769 837 // CHECK-MTE-BTI-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 769 838 // CHECK-MTE-BTI-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] 839 // CHECK-MTE-BTI-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 840 // CHECK-MTE-BTI: resolver_return3: 841 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._MrngMsimd 842 // CHECK-MTE-BTI: resolver_else4: 843 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1.default 844 // 845 // 846 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 847 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3._Mbti 848 // CHECK-MTE-BTI-SAME: () #[[ATTR7]] { 849 // CHECK-MTE-BTI-NEXT: entry: 850 // CHECK-MTE-BTI-NEXT: ret i32 3 851 // 852 // 853 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 854 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3._MsbMsve 855 // CHECK-MTE-BTI-SAME: () #[[ATTR15:[0-9]+]] { 856 // CHECK-MTE-BTI-NEXT: entry: 857 // CHECK-MTE-BTI-NEXT: ret i32 3 858 // 859 // 860 // CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone 861 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3.default 862 // CHECK-MTE-BTI-SAME: () #[[ATTR9]] { 863 // CHECK-MTE-BTI-NEXT: entry: 864 // CHECK-MTE-BTI-NEXT: ret i32 3 865 // 866 // 867 // CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline3.resolver() comdat { 868 // CHECK-MTE-BTI-NEXT: resolver_entry: 869 // CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver() 870 // CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 871 // CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624 872 // CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624 873 // CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 874 // CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 875 // CHECK-MTE-BTI: resolver_return: 876 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti 877 // CHECK-MTE-BTI: resolver_else: 878 // CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 879 // CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280 880 // CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280 881 // CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 882 // CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 883 // CHECK-MTE-BTI: resolver_return1: 884 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve 885 // CHECK-MTE-BTI: resolver_else2: 886 // CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3.default 887 // 888 //. 889 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 890 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 891 //. 892 // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 893 // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 894 //. 895 // CHECK-MTE-BTI: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 896 // CHECK-MTE-BTI: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 897 //. 898