1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #ifndef __ECORE_HSI_ETH__ 8 #define __ECORE_HSI_ETH__ 9 /************************************************************************/ 10 /* Add include to common eth target for both eCore and protocol driver */ 11 /************************************************************************/ 12 #include "eth_common.h" 13 14 /* 15 * The eth storm context for the Tstorm 16 */ 17 struct tstorm_eth_conn_st_ctx { 18 __le32 reserved[4]; 19 }; 20 21 /* 22 * The eth storm context for the Pstorm 23 */ 24 struct pstorm_eth_conn_st_ctx { 25 __le32 reserved[8]; 26 }; 27 28 /* 29 * The eth storm context for the Xstorm 30 */ 31 struct xstorm_eth_conn_st_ctx { 32 __le32 reserved[60]; 33 }; 34 35 struct xstorm_eth_conn_ag_ctx { 36 u8 reserved0 /* cdu_validation */; 37 u8 state /* state */; 38 u8 flags0; 39 /* exist_in_qm0 */ 40 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 41 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 42 /* exist_in_qm1 */ 43 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 44 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 45 /* exist_in_qm2 */ 46 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 47 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 48 /* exist_in_qm3 */ 49 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 50 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 51 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 52 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 53 /* cf_array_active */ 54 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 55 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 56 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 57 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 58 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 59 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 60 u8 flags1; 61 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 62 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 63 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 64 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 65 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 66 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 67 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 68 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 69 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 70 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 71 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 72 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 73 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 74 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 75 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 76 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 77 u8 flags2; 78 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 79 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 80 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 81 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 82 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 83 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 84 /* timer_stop_all */ 85 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 86 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 87 u8 flags3; 88 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 89 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 90 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 91 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 92 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 93 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 94 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 95 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 96 u8 flags4; 97 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 98 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 99 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 100 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 101 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 102 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 103 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 104 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 105 u8 flags5; 106 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 107 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 108 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 109 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 110 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 111 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 112 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 113 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 114 u8 flags6; 115 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 116 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 117 /* cf_array_cf */ 118 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 119 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 120 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 121 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 122 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 123 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 124 u8 flags7; 125 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 126 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 127 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 128 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 129 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 130 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 131 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 132 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 133 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 134 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 135 u8 flags8; 136 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 137 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 138 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 139 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 140 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 141 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 142 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 143 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 144 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 145 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 146 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 147 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 148 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 149 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 150 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 151 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 152 u8 flags9; 153 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 154 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 155 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 156 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 157 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 158 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 159 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 160 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 161 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 162 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 163 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 164 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 165 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 166 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 167 /* cf_array_cf_en */ 168 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 169 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 170 u8 flags10; 171 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 172 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 173 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 174 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 175 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 176 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 177 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 178 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 179 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 180 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 181 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 182 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 183 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 184 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 185 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 186 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 187 u8 flags11; 188 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 189 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 190 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 191 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 192 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 193 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 194 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 195 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 196 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 197 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 198 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 199 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 200 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 201 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 202 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 203 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 204 u8 flags12; 205 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 206 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 207 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 208 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 209 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 210 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 211 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 212 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 213 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 214 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 215 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 216 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 217 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 218 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 219 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 220 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 221 u8 flags13; 222 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 223 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 224 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 225 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 226 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 227 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 228 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 229 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 230 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 231 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 232 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 233 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 234 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 235 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 236 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 237 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 238 u8 flags14; 239 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 240 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 241 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 242 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 243 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 244 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 245 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 246 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 247 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 248 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 249 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 250 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 251 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 252 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 253 u8 edpm_event_id /* byte2 */; 254 __le16 physical_q0 /* physical_q0 */; 255 __le16 e5_reserved1 /* physical_q1 */; 256 __le16 edpm_num_bds /* physical_q2 */; 257 __le16 tx_bd_cons /* word3 */; 258 __le16 tx_bd_prod /* word4 */; 259 __le16 updated_qm_pq_id /* word5 */; 260 __le16 conn_dpi /* conn_dpi */; 261 u8 byte3 /* byte3 */; 262 u8 byte4 /* byte4 */; 263 u8 byte5 /* byte5 */; 264 u8 byte6 /* byte6 */; 265 __le32 reg0 /* reg0 */; 266 __le32 reg1 /* reg1 */; 267 __le32 reg2 /* reg2 */; 268 __le32 reg3 /* reg3 */; 269 __le32 reg4 /* reg4 */; 270 __le32 reg5 /* cf_array0 */; 271 __le32 reg6 /* cf_array1 */; 272 __le16 word7 /* word7 */; 273 __le16 word8 /* word8 */; 274 __le16 word9 /* word9 */; 275 __le16 word10 /* word10 */; 276 __le32 reg7 /* reg7 */; 277 __le32 reg8 /* reg8 */; 278 __le32 reg9 /* reg9 */; 279 u8 byte7 /* byte7 */; 280 u8 byte8 /* byte8 */; 281 u8 byte9 /* byte9 */; 282 u8 byte10 /* byte10 */; 283 u8 byte11 /* byte11 */; 284 u8 byte12 /* byte12 */; 285 u8 byte13 /* byte13 */; 286 u8 byte14 /* byte14 */; 287 u8 byte15 /* byte15 */; 288 u8 e5_reserved /* e5_reserved */; 289 __le16 word11 /* word11 */; 290 __le32 reg10 /* reg10 */; 291 __le32 reg11 /* reg11 */; 292 __le32 reg12 /* reg12 */; 293 __le32 reg13 /* reg13 */; 294 __le32 reg14 /* reg14 */; 295 __le32 reg15 /* reg15 */; 296 __le32 reg16 /* reg16 */; 297 __le32 reg17 /* reg17 */; 298 __le32 reg18 /* reg18 */; 299 __le32 reg19 /* reg19 */; 300 __le16 word12 /* word12 */; 301 __le16 word13 /* word13 */; 302 __le16 word14 /* word14 */; 303 __le16 word15 /* word15 */; 304 }; 305 306 struct tstorm_eth_conn_ag_ctx { 307 u8 byte0 /* cdu_validation */; 308 u8 byte1 /* state */; 309 u8 flags0; 310 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 311 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 312 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 313 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 314 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 315 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 316 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 317 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 318 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 319 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 320 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 321 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 322 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 323 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 324 u8 flags1; 325 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 326 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 327 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 328 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 329 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 330 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 331 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 332 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 333 u8 flags2; 334 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 335 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 336 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 337 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 338 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 339 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 340 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 341 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 342 u8 flags3; 343 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 344 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 345 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 346 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 347 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 348 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 349 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 350 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 351 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 352 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 353 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 354 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 355 u8 flags4; 356 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 357 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 358 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 359 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 360 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 361 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 362 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 363 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 364 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 365 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 366 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 367 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 368 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 369 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 370 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 371 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 372 u8 flags5; 373 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 374 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 375 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 376 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 377 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 378 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 379 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 380 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 381 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 382 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 383 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 384 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 385 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 386 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 387 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 388 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 389 __le32 reg0 /* reg0 */; 390 __le32 reg1 /* reg1 */; 391 __le32 reg2 /* reg2 */; 392 __le32 reg3 /* reg3 */; 393 __le32 reg4 /* reg4 */; 394 __le32 reg5 /* reg5 */; 395 __le32 reg6 /* reg6 */; 396 __le32 reg7 /* reg7 */; 397 __le32 reg8 /* reg8 */; 398 u8 byte2 /* byte2 */; 399 u8 byte3 /* byte3 */; 400 __le16 rx_bd_cons /* word0 */; 401 u8 byte4 /* byte4 */; 402 u8 byte5 /* byte5 */; 403 __le16 rx_bd_prod /* word1 */; 404 __le16 word2 /* conn_dpi */; 405 __le16 word3 /* word3 */; 406 __le32 reg9 /* reg9 */; 407 __le32 reg10 /* reg10 */; 408 }; 409 410 /* 411 * The eth storm context for the Ystorm 412 */ 413 struct ystorm_eth_conn_st_ctx { 414 __le32 reserved[8]; 415 }; 416 417 struct ystorm_eth_conn_ag_ctx { 418 u8 byte0 /* cdu_validation */; 419 u8 state /* state */; 420 u8 flags0; 421 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 422 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 423 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 424 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 425 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 426 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 427 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 428 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 429 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 430 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 431 u8 flags1; 432 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 433 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 434 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 435 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 436 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 437 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 438 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 439 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 440 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 441 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 442 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 443 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 444 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 445 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 446 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 447 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 448 u8 tx_q0_int_coallecing_timeset /* byte2 */; 449 u8 byte3 /* byte3 */; 450 __le16 word0 /* word0 */; 451 __le32 terminate_spqe /* reg0 */; 452 __le32 reg1 /* reg1 */; 453 __le16 tx_bd_cons_upd /* word1 */; 454 __le16 word2 /* word2 */; 455 __le16 word3 /* word3 */; 456 __le16 word4 /* word4 */; 457 __le32 reg2 /* reg2 */; 458 __le32 reg3 /* reg3 */; 459 }; 460 461 struct ustorm_eth_conn_ag_ctx { 462 u8 byte0 /* cdu_validation */; 463 u8 byte1 /* state */; 464 u8 flags0; 465 /* exist_in_qm0 */ 466 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 467 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 468 /* exist_in_qm1 */ 469 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 470 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 471 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 472 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 473 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 474 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 475 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 476 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 477 u8 flags1; 478 /* timer_stop_all */ 479 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 480 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 481 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 482 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 483 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 484 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 485 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 486 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 487 u8 flags2; 488 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 489 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 490 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 491 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 492 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 493 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 494 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 495 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 496 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 497 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 498 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 499 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 500 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 501 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 502 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 503 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 504 u8 flags3; 505 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 506 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 507 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 508 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 509 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 510 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 511 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 512 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 513 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 514 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 515 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 516 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 517 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 518 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 519 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 520 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 521 u8 byte2 /* byte2 */; 522 u8 byte3 /* byte3 */; 523 __le16 word0 /* conn_dpi */; 524 __le16 tx_bd_cons /* word1 */; 525 __le32 reg0 /* reg0 */; 526 __le32 reg1 /* reg1 */; 527 __le32 reg2 /* reg2 */; 528 __le32 tx_int_coallecing_timeset /* reg3 */; 529 __le16 tx_drv_bd_cons /* word2 */; 530 __le16 rx_drv_cqe_cons /* word3 */; 531 }; 532 533 /* 534 * The eth storm context for the Ustorm 535 */ 536 struct ustorm_eth_conn_st_ctx { 537 __le32 reserved[40]; 538 }; 539 540 /* 541 * The eth storm context for the Mstorm 542 */ 543 struct mstorm_eth_conn_st_ctx { 544 __le32 reserved[8]; 545 }; 546 547 /* 548 * eth connection context 549 */ 550 struct eth_conn_context { 551 /* tstorm storm context */ 552 struct tstorm_eth_conn_st_ctx tstorm_st_context; 553 struct regpair tstorm_st_padding[2] /* padding */; 554 /* pstorm storm context */ 555 struct pstorm_eth_conn_st_ctx pstorm_st_context; 556 /* xstorm storm context */ 557 struct xstorm_eth_conn_st_ctx xstorm_st_context; 558 /* xstorm aggregative context */ 559 struct xstorm_eth_conn_ag_ctx xstorm_ag_context; 560 /* tstorm aggregative context */ 561 struct tstorm_eth_conn_ag_ctx tstorm_ag_context; 562 /* ystorm storm context */ 563 struct ystorm_eth_conn_st_ctx ystorm_st_context; 564 /* ystorm aggregative context */ 565 struct ystorm_eth_conn_ag_ctx ystorm_ag_context; 566 /* ustorm aggregative context */ 567 struct ustorm_eth_conn_ag_ctx ustorm_ag_context; 568 /* ustorm storm context */ 569 struct ustorm_eth_conn_st_ctx ustorm_st_context; 570 /* mstorm storm context */ 571 struct mstorm_eth_conn_st_ctx mstorm_st_context; 572 }; 573 574 575 /* 576 * Ethernet filter types: mac/vlan/pair 577 */ 578 enum eth_error_code { 579 ETH_OK = 0x00 /* command succeeded */, 580 /* mac add filters command failed due to cam full state */ 581 ETH_FILTERS_MAC_ADD_FAIL_FULL, 582 /* mac add filters command failed due to mtt2 full state */ 583 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, 584 /* mac add filters command failed due to duplicate mac address */ 585 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, 586 /* mac add filters command failed due to duplicate mac address */ 587 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, 588 /* mac delete filters command failed due to not found state */ 589 ETH_FILTERS_MAC_DEL_FAIL_NOF, 590 /* mac delete filters command failed due to not found state */ 591 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, 592 /* mac delete filters command failed due to not found state */ 593 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, 594 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */ 595 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, 596 /* vlan add filters command failed due to cam full state */ 597 ETH_FILTERS_VLAN_ADD_FAIL_FULL, 598 /* vlan add filters command failed due to duplicate VLAN filter */ 599 ETH_FILTERS_VLAN_ADD_FAIL_DUP, 600 /* vlan delete filters command failed due to not found state */ 601 ETH_FILTERS_VLAN_DEL_FAIL_NOF, 602 /* vlan delete filters command failed due to not found state */ 603 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, 604 /* pair add filters command failed due to duplicate request */ 605 ETH_FILTERS_PAIR_ADD_FAIL_DUP, 606 /* pair add filters command failed due to full state */ 607 ETH_FILTERS_PAIR_ADD_FAIL_FULL, 608 /* pair add filters command failed due to full state */ 609 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, 610 /* pair add filters command failed due not found state */ 611 ETH_FILTERS_PAIR_DEL_FAIL_NOF, 612 /* pair add filters command failed due not found state */ 613 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, 614 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */ 615 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, 616 /* vni add filters command failed due to cam full state */ 617 ETH_FILTERS_VNI_ADD_FAIL_FULL, 618 /* vni add filters command failed due to duplicate VNI filter */ 619 ETH_FILTERS_VNI_ADD_FAIL_DUP, 620 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, 621 MAX_ETH_ERROR_CODE 622 }; 623 624 625 /* 626 * opcodes for the event ring 627 */ 628 enum eth_event_opcode { 629 ETH_EVENT_UNUSED, 630 ETH_EVENT_VPORT_START, 631 ETH_EVENT_VPORT_UPDATE, 632 ETH_EVENT_VPORT_STOP, 633 ETH_EVENT_TX_QUEUE_START, 634 ETH_EVENT_TX_QUEUE_STOP, 635 ETH_EVENT_RX_QUEUE_START, 636 ETH_EVENT_RX_QUEUE_UPDATE, 637 ETH_EVENT_RX_QUEUE_STOP, 638 ETH_EVENT_FILTERS_UPDATE, 639 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 640 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 641 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 642 ETH_EVENT_RX_ADD_UDP_FILTER, 643 ETH_EVENT_RX_DELETE_UDP_FILTER, 644 ETH_EVENT_RX_CREATE_GFT_ACTION, 645 ETH_EVENT_RX_GFT_UPDATE_FILTER, 646 ETH_EVENT_TX_QUEUE_UPDATE, 647 MAX_ETH_EVENT_OPCODE 648 }; 649 650 651 /* 652 * Classify rule types in E2/E3 653 */ 654 enum eth_filter_action { 655 ETH_FILTER_ACTION_UNUSED, 656 ETH_FILTER_ACTION_REMOVE, 657 ETH_FILTER_ACTION_ADD, 658 /* Remove all filters of given type and vport ID. */ 659 ETH_FILTER_ACTION_REMOVE_ALL, 660 MAX_ETH_FILTER_ACTION 661 }; 662 663 664 /* 665 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ 666 */ 667 struct eth_filter_cmd { 668 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */; 669 u8 vport_id /* the vport id */; 670 u8 action /* filter command action: add/remove/replace */; 671 u8 reserved0; 672 __le32 vni; 673 __le16 mac_lsb; 674 __le16 mac_mid; 675 __le16 mac_msb; 676 __le16 vlan_id; 677 }; 678 679 680 /* 681 * $$KEEP_ENDIANNESS$$ 682 */ 683 struct eth_filter_cmd_header { 684 u8 rx /* If set, apply these commands to the RX path */; 685 u8 tx /* If set, apply these commands to the TX path */; 686 u8 cmd_cnt /* Number of filter commands */; 687 /* 0 - dont assert in case of filter configuration error. Just return an error 688 * code. 1 - assert in case of filter configuration error. 689 */ 690 u8 assert_on_error; 691 u8 reserved1[4]; 692 }; 693 694 695 /* 696 * Ethernet filter types: mac/vlan/pair 697 */ 698 enum eth_filter_type { 699 ETH_FILTER_TYPE_UNUSED, 700 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, 701 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, 702 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, 703 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, 704 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, 705 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, 706 /* Add/remove a inner MAC-VNI pair */ 707 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, 708 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, 709 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, 710 MAX_ETH_FILTER_TYPE 711 }; 712 713 714 /* 715 * inner to inner vlan priority translation configurations 716 */ 717 struct eth_in_to_in_pri_map_cfg { 718 /* If set, non_rdma_in_to_in_pri_map or rdma_in_to_in_pri_map will be used for 719 * inner to inner priority mapping depending on protocol type 720 */ 721 u8 inner_vlan_pri_remap_en; 722 u8 reserved[7]; 723 /* Map for inner to inner vlan priority translation for Non RDMA protocols, used 724 * for TenantDcb. Set inner_vlan_pri_remap_en, when init the map. 725 */ 726 u8 non_rdma_in_to_in_pri_map[8]; 727 /* Map for inner to inner vlan priority translation for RDMA protocols, used for 728 * TenantDcb. Set inner_vlan_pri_remap_en, when init the map. 729 */ 730 u8 rdma_in_to_in_pri_map[8]; 731 }; 732 733 734 /* 735 * eth IPv4 Fragment Type 736 */ 737 enum eth_ipv4_frag_type { 738 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, 739 /* First Fragment of IPv4 Packet (contains headers) */ 740 ETH_IPV4_FIRST_FRAG, 741 /* Non-First Fragment of IPv4 Packet (does not contain headers) */ 742 ETH_IPV4_NON_FIRST_FRAG, 743 MAX_ETH_IPV4_FRAG_TYPE 744 }; 745 746 747 /* 748 * eth IPv4 Fragment Type 749 */ 750 enum eth_ip_type { 751 ETH_IPV4 /* IPv4 */, 752 ETH_IPV6 /* IPv6 */, 753 MAX_ETH_IP_TYPE 754 }; 755 756 757 /* 758 * Ethernet Ramrod Command IDs 759 */ 760 enum eth_ramrod_cmd_id { 761 ETH_RAMROD_UNUSED, 762 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, 763 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, 764 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, 765 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 766 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 767 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 768 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 769 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, 770 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, 771 /* RX - Create an Openflow Action */ 772 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, 773 /* RX - Add an Openflow Filter to the Searcher */ 774 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, 775 /* RX - Delete an Openflow Filter to the Searcher */ 776 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, 777 /* RX - Add a UDP Filter to the Searcher */ 778 ETH_RAMROD_RX_ADD_UDP_FILTER, 779 /* RX - Delete a UDP Filter to the Searcher */ 780 ETH_RAMROD_RX_DELETE_UDP_FILTER, 781 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, 782 /* RX - Add/Delete a GFT Filter to the Searcher */ 783 ETH_RAMROD_GFT_UPDATE_FILTER, 784 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 785 MAX_ETH_RAMROD_CMD_ID 786 }; 787 788 789 /* 790 * return code from eth sp ramrods 791 */ 792 struct eth_return_code { 793 u8 value; 794 /* error code (use enum eth_error_code) */ 795 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F 796 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 797 #define ETH_RETURN_CODE_RESERVED_MASK 0x1 798 #define ETH_RETURN_CODE_RESERVED_SHIFT 6 799 /* rx path - 0, tx path - 1 */ 800 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 801 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 802 }; 803 804 805 /* 806 * tx destination enum 807 */ 808 enum eth_tx_dst_mode_config_enum { 809 /* tx destination configuration override is disabled */ 810 ETH_TX_DST_MODE_CONFIG_DISABLE, 811 /* tx destination configuration override is enabled, vport and tx dst will be 812 * taken from from 4th bd 813 */ 814 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD, 815 /* tx destination configuration override is enabled, vport and tx dst will be 816 * taken from from vport data 817 */ 818 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT, 819 MAX_ETH_TX_DST_MODE_CONFIG_ENUM 820 }; 821 822 823 /* 824 * What to do in case an error occurs 825 */ 826 enum eth_tx_err { 827 ETH_TX_ERR_DROP /* Drop erroneous packet. */, 828 /* Assert an interrupt for PF, declare as malicious for VF */ 829 ETH_TX_ERR_ASSERT_MALICIOUS, 830 MAX_ETH_TX_ERR 831 }; 832 833 834 /* 835 * Array of the different error type behaviors 836 */ 837 struct eth_tx_err_vals { 838 __le16 values; 839 /* Wrong VLAN insertion mode (use enum eth_tx_err) */ 840 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 841 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 842 /* Packet is below minimal size (use enum eth_tx_err) */ 843 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 844 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 845 /* Vport has sent spoofed packet (use enum eth_tx_err) */ 846 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 847 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 848 /* Packet with illegal type of inband tag (use enum eth_tx_err) */ 849 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 850 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 851 /* Packet marked for VLAN insertion when inband tag is present 852 * (use enum eth_tx_err) 853 */ 854 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 855 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 856 /* Non LSO packet larger than MTU (use enum eth_tx_err) */ 857 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 858 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 859 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not 860 * allowed to (use enum eth_tx_err) 861 */ 862 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 863 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 864 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 865 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 866 }; 867 868 869 /* 870 * vport rss configuration data 871 */ 872 struct eth_vport_rss_config { 873 __le16 capabilities; 874 /* configuration of the IpV4 2-tuple capability */ 875 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 876 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 877 /* configuration of the IpV6 2-tuple capability */ 878 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 879 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 880 /* configuration of the IpV4 4-tuple capability for TCP */ 881 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 882 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 883 /* configuration of the IpV6 4-tuple capability for TCP */ 884 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 885 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 886 /* configuration of the IpV4 4-tuple capability for UDP */ 887 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 888 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 889 /* configuration of the IpV6 4-tuple capability for UDP */ 890 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 891 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 892 /* configuration of the 5-tuple capability */ 893 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 894 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 895 /* if set update the rss keys */ 896 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF 897 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 898 /* The RSS engine ID. Must be allocated to each vport with RSS enabled. 899 * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. 900 */ 901 u8 rss_id; 902 u8 rss_mode /* The RSS mode for this function */; 903 u8 update_rss_key /* if set update the rss key */; 904 /* if set update the indirection table values */ 905 u8 update_rss_ind_table; 906 /* if set update the capabilities and indirection table size. */ 907 u8 update_rss_capabilities; 908 u8 tbl_size /* rss mask (Tbl size) */; 909 __le32 reserved2[2]; 910 /* RSS indirection table */ 911 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; 912 /* RSS key supplied to us by OS */ 913 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; 914 __le32 reserved3[2]; 915 }; 916 917 918 /* 919 * eth vport RSS mode 920 */ 921 enum eth_vport_rss_mode { 922 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, 923 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 924 MAX_ETH_VPORT_RSS_MODE 925 }; 926 927 928 /* 929 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 930 */ 931 struct eth_vport_rx_mode { 932 __le16 state; 933 /* drop all unicast packets */ 934 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 935 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 936 /* accept all unicast packets (subject to vlan) */ 937 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 938 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 939 /* accept all unmatched unicast packets */ 940 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 941 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 942 /* drop all multicast packets */ 943 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 944 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 945 /* accept all multicast packets (subject to vlan) */ 946 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 947 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 948 /* accept all broadcast packets (subject to vlan) */ 949 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 950 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 951 /* accept any VNI in tunnel VNI classification. Used for default queue. */ 952 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1 953 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6 954 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF 955 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7 956 }; 957 958 959 /* 960 * Command for setting tpa parameters 961 */ 962 struct eth_vport_tpa_param { 963 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; 964 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; 965 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; 966 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; 967 /* If set, start each TPA segment on new BD (GRO mode). One BD per segment 968 * allowed. 969 */ 970 u8 tpa_pkt_split_flg; 971 /* If set, put header of first TPA segment on first BD and data on second BD. */ 972 u8 tpa_hdr_data_split_flg; 973 /* If set, GRO data consistent will checked for TPA continue */ 974 u8 tpa_gro_consistent_flg; 975 /* maximum number of opened aggregations per v-port */ 976 u8 tpa_max_aggs_num; 977 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; 978 /* minimum TCP payload size for a packet to start aggregation */ 979 __le16 tpa_min_size_to_start; 980 /* minimum TCP payload size for a packet to continue aggregation */ 981 __le16 tpa_min_size_to_cont; 982 /* maximal number of buffers that can be used for one aggregation */ 983 u8 max_buff_num; 984 u8 reserved; 985 }; 986 987 988 /* 989 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 990 */ 991 struct eth_vport_tx_mode { 992 __le16 state; 993 /* drop all unicast packets */ 994 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 995 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 996 /* accept all unicast packets (subject to vlan) */ 997 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 998 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 999 /* drop all multicast packets */ 1000 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 1001 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 1002 /* accept all multicast packets (subject to vlan) */ 1003 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 1004 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 1005 /* accept all broadcast packets (subject to vlan) */ 1006 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 1007 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 1008 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 1009 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 1010 }; 1011 1012 1013 /* 1014 * GFT filter update action type. 1015 */ 1016 enum gft_filter_update_action { 1017 GFT_ADD_FILTER, 1018 GFT_DELETE_FILTER, 1019 MAX_GFT_FILTER_UPDATE_ACTION 1020 }; 1021 1022 1023 1024 1025 /* 1026 * Ramrod data for rx add openflow filter 1027 */ 1028 struct rx_add_openflow_filter_data { 1029 __le16 action_icid /* CID of Action to run for this filter */; 1030 u8 priority /* Searcher String - Packet priority */; 1031 u8 reserved0; 1032 __le32 tenant_id /* Searcher String - Tenant ID */; 1033 /* Searcher String - Destination Mac Bytes 0 to 1 */ 1034 __le16 dst_mac_hi; 1035 /* Searcher String - Destination Mac Bytes 2 to 3 */ 1036 __le16 dst_mac_mid; 1037 /* Searcher String - Destination Mac Bytes 4 to 5 */ 1038 __le16 dst_mac_lo; 1039 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; 1040 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; 1041 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; 1042 __le16 vlan_id /* Searcher String - Vlan ID */; 1043 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; 1044 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; 1045 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */; 1046 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; 1047 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1048 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; 1049 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; 1050 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; 1051 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; 1052 }; 1053 1054 1055 /* 1056 * Ramrod data for rx create gft action 1057 */ 1058 struct rx_create_gft_action_data { 1059 u8 vport_id /* Vport Id of GFT Action */; 1060 u8 reserved[7]; 1061 }; 1062 1063 1064 /* 1065 * Ramrod data for rx create openflow action 1066 */ 1067 struct rx_create_openflow_action_data { 1068 u8 vport_id /* ID of RX queue */; 1069 u8 reserved[7]; 1070 }; 1071 1072 1073 /* 1074 * Ramrod data for rx queue start ramrod 1075 */ 1076 struct rx_queue_start_ramrod_data { 1077 __le16 rx_queue_id /* ID of RX queue */; 1078 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */; 1079 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; 1080 __le16 sb_id /* Status block ID */; 1081 u8 sb_index /* index of the protocol index */; 1082 u8 vport_id /* ID of virtual port */; 1083 u8 default_rss_queue_flg /* set queue as default rss queue if set */; 1084 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1085 u8 complete_event_flg /* post completion to the event ring if set */; 1086 u8 stats_counter_id /* Statistics counter ID */; 1087 u8 pin_context /* Pin context in CCFC to improve performance */; 1088 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; 1089 /* PXP command TPH Valid - for packet placement */ 1090 u8 pxp_tph_valid_pkt; 1091 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */ 1092 u8 pxp_st_hint; 1093 __le16 pxp_st_index /* PXP command Steering tag index */; 1094 /* Indicates that current queue belongs to poll-mode driver */ 1095 u8 pmd_mode; 1096 /* Indicates that the current queue is using the TX notification queue 1097 * mechanism - should be set only for PMD queue 1098 */ 1099 u8 notify_en; 1100 /* Initial value for the toggle valid bit - used in PMD mode */ 1101 u8 toggle_val; 1102 /* Index of RX producers in VF zone. Used for VF only. */ 1103 u8 vf_rx_prod_index; 1104 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used 1105 * for VF RX producers instead of VF zone. 1106 */ 1107 u8 vf_rx_prod_use_zone_a; 1108 u8 reserved[5]; 1109 __le16 reserved1 /* FW reserved. */; 1110 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 1111 struct regpair bd_base /* bd address of the first bd page */; 1112 struct regpair reserved2 /* FW reserved. */; 1113 }; 1114 1115 1116 /* 1117 * Ramrod data for rx queue stop ramrod 1118 */ 1119 struct rx_queue_stop_ramrod_data { 1120 __le16 rx_queue_id /* ID of RX queue */; 1121 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1122 u8 complete_event_flg /* post completion to the event ring if set */; 1123 u8 vport_id /* ID of virtual port */; 1124 u8 reserved[3]; 1125 }; 1126 1127 1128 /* 1129 * Ramrod data for rx queue update ramrod 1130 */ 1131 struct rx_queue_update_ramrod_data { 1132 __le16 rx_queue_id /* ID of RX queue */; 1133 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1134 u8 complete_event_flg /* post completion to the event ring if set */; 1135 u8 vport_id /* ID of virtual port */; 1136 /* If set, update default rss queue to this RX queue. */ 1137 u8 set_default_rss_queue; 1138 u8 reserved[3]; 1139 u8 reserved1 /* FW reserved. */; 1140 u8 reserved2 /* FW reserved. */; 1141 u8 reserved3 /* FW reserved. */; 1142 __le16 reserved4 /* FW reserved. */; 1143 __le16 reserved5 /* FW reserved. */; 1144 struct regpair reserved6 /* FW reserved. */; 1145 }; 1146 1147 1148 /* 1149 * Ramrod data for rx Add UDP Filter 1150 */ 1151 struct rx_udp_filter_data { 1152 __le16 action_icid /* CID of Action to run for this filter */; 1153 __le16 vlan_id /* Searcher String - Vlan ID */; 1154 u8 ip_type /* Searcher String - IP Type */; 1155 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1156 __le16 reserved1; 1157 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */ 1158 __le32 ip_dst_addr[4]; 1159 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */ 1160 __le32 ip_src_addr[4]; 1161 __le16 udp_dst_port /* Searcher String - UDP Destination Port */; 1162 __le16 udp_src_port /* Searcher String - UDP Source Port */; 1163 __le32 tenant_id /* Searcher String - Tenant ID */; 1164 }; 1165 1166 1167 /* 1168 * add or delete GFT filter - filter is packet header of type of packet wished 1169 * to pass certain FW flow 1170 */ 1171 struct rx_update_gft_filter_data { 1172 /* Pointer to Packet Header That Defines GFT Filter */ 1173 struct regpair pkt_hdr_addr; 1174 __le16 pkt_hdr_length /* Packet Header Length */; 1175 /* Action icid. Valid if action_icid_valid flag set. */ 1176 __le16 action_icid; 1177 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; 1178 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; 1179 /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */ 1180 __le16 vport_id; 1181 /* If set, action_icid will used for GFT filter update. */ 1182 u8 action_icid_valid; 1183 /* If set, rx_qid will used for traffic steering, in additional to vport_id. 1184 * flow_id_valid must be cleared. If cleared, queue ID will selected by RSS. 1185 */ 1186 u8 rx_qid_valid; 1187 /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If 1188 * cleared, flow_id 0 will reported by CQE. 1189 */ 1190 u8 flow_id_valid; 1191 u8 filter_action /* Use to set type of action on filter */; 1192 /* 0 - dont assert in case of error. Just return an error code. 1 - assert in 1193 * case of error. 1194 */ 1195 u8 assert_on_error; 1196 /* If set, inner VLAN will be removed regardless to VPORT configuration. 1197 * Supported by E4 only. 1198 */ 1199 u8 inner_vlan_removal_en; 1200 }; 1201 1202 1203 1204 /* 1205 * Ramrod data for tx queue start ramrod 1206 */ 1207 struct tx_queue_start_ramrod_data { 1208 __le16 sb_id /* Status block ID */; 1209 u8 sb_index /* Status block protocol index */; 1210 u8 vport_id /* VPort ID */; 1211 u8 reserved0 /* FW reserved. (qcn_rl_en) */; 1212 u8 stats_counter_id /* Statistics counter ID to use */; 1213 __le16 qm_pq_id /* QM PQ ID */; 1214 u8 flags; 1215 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ 1216 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 1217 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 1218 /* If set, Test Mode - packets will be duplicated by Xstorm handler */ 1219 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 1220 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 1221 /* If set, Test Mode - packets destination will be determined by dest_port_mode 1222 * field from Tx BD 1223 */ 1224 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 1225 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 1226 /* Indicates that current queue belongs to poll-mode driver */ 1227 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 1228 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 1229 /* Indicates that the current queue is using the TX notification queue 1230 * mechanism - should be set only for PMD queue 1231 */ 1232 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 1233 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 1234 /* Pin context in CCFC to improve performance */ 1235 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 1236 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 1237 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 1238 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 1239 u8 pxp_st_hint /* PXP command Steering tag hint */; 1240 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; 1241 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; 1242 __le16 pxp_st_index /* PXP command Steering tag index */; 1243 /* TX completion min agg size - for PMD queues */ 1244 __le16 comp_agg_size; 1245 __le16 queue_zone_id /* queue zone ID to use */; 1246 __le16 reserved2 /* FW reserved. (test_dup_count) */; 1247 __le16 pbl_size /* Number of BD pages pointed by PBL */; 1248 /* unique Queue ID - currently used only by PMD flow */ 1249 __le16 tx_queue_id; 1250 /* Unique Same-As-Last Resource ID - improves performance for same-as-last 1251 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs 1252 * available) 1253 */ 1254 __le16 same_as_last_id; 1255 __le16 reserved[3]; 1256 struct regpair pbl_base_addr /* address of the pbl page */; 1257 /* BD consumer address in host - for PMD queues */ 1258 struct regpair bd_cons_address; 1259 }; 1260 1261 1262 /* 1263 * Ramrod data for tx queue stop ramrod 1264 */ 1265 struct tx_queue_stop_ramrod_data { 1266 __le16 reserved[4]; 1267 }; 1268 1269 1270 /* 1271 * Ramrod data for tx queue update ramrod 1272 */ 1273 struct tx_queue_update_ramrod_data { 1274 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 1275 __le16 qm_pq_id /* Updated QM PQ ID */; 1276 __le32 reserved0; 1277 struct regpair reserved1[5]; 1278 }; 1279 1280 1281 /* 1282 * Inner to Inner VLAN priority map update mode 1283 */ 1284 enum update_in_to_in_pri_map_mode_enum { 1285 /* Inner to Inner VLAN priority map update Disabled */ 1286 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED, 1287 /* Update Inner to Inner VLAN priority map for non RDMA protocols */ 1288 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL, 1289 /* Update Inner to Inner VLAN priority map for RDMA protocols */ 1290 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL, 1291 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM 1292 }; 1293 1294 1295 1296 /* 1297 * Ramrod data for vport update ramrod 1298 */ 1299 struct vport_filter_update_ramrod_data { 1300 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */ 1301 struct eth_filter_cmd_header filter_cmd_hdr; 1302 /* Filter Commands */ 1303 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; 1304 }; 1305 1306 1307 /* 1308 * Ramrod data for vport start ramrod 1309 */ 1310 struct vport_start_ramrod_data { 1311 u8 vport_id; 1312 u8 sw_fid; 1313 __le16 mtu; 1314 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; 1315 u8 inner_vlan_removal_en; 1316 struct eth_vport_rx_mode rx_mode /* Rx filter data */; 1317 struct eth_vport_tx_mode tx_mode /* Tx filter data */; 1318 /* TPA configuration parameters */ 1319 struct eth_vport_tpa_param tpa_param; 1320 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1321 u8 tx_switching_en /* Tx switching is enabled for current Vport */; 1322 /* Anti-spoofing verification is set for current Vport */ 1323 u8 anti_spoofing_en; 1324 /* If set, the default Vlan value is forced by the FW */ 1325 u8 default_vlan_en; 1326 /* If set, the vport handles PTP Timesync Packets */ 1327 u8 handle_ptp_pkts; 1328 /* If enable then innerVlan will be striped and not written to cqe */ 1329 u8 silent_vlan_removal_en; 1330 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is 1331 * marked as any-vlan 1332 */ 1333 u8 untagged; 1334 /* Desired behavior per TX error type */ 1335 struct eth_tx_err_vals tx_err_behav; 1336 /* If set, ETH header padding will not inserted. placement_offset will be zero. 1337 */ 1338 u8 zero_placement_offset; 1339 /* If set, control frames will be filtered according to MAC check. */ 1340 u8 ctl_frame_mac_check_en; 1341 /* If set, control frames will be filtered according to ethtype check. */ 1342 u8 ctl_frame_ethtype_check_en; 1343 /* If set, the inner vlan (802.1q tag) priority that is written to cqe will be 1344 * zero out, used for TenantDcb 1345 */ 1346 u8 wipe_inner_vlan_pri_en; 1347 /* inner to inner vlan priority translation configurations */ 1348 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg; 1349 }; 1350 1351 1352 /* 1353 * Ramrod data for vport stop ramrod 1354 */ 1355 struct vport_stop_ramrod_data { 1356 u8 vport_id; 1357 u8 reserved[7]; 1358 }; 1359 1360 1361 /* 1362 * Ramrod data for vport update ramrod 1363 */ 1364 struct vport_update_ramrod_data_cmn { 1365 u8 vport_id; 1366 u8 update_rx_active_flg /* set if rx active flag should be handled */; 1367 u8 rx_active_flg /* rx active flag value */; 1368 u8 update_tx_active_flg /* set if tx active flag should be handled */; 1369 u8 tx_active_flg /* tx active flag value */; 1370 u8 update_rx_mode_flg /* set if rx state data should be handled */; 1371 u8 update_tx_mode_flg /* set if tx state data should be handled */; 1372 /* set if approx. mcast data should be handled */ 1373 u8 update_approx_mcast_flg; 1374 u8 update_rss_flg /* set if rss data should be handled */; 1375 /* set if inner_vlan_removal_en should be handled */ 1376 u8 update_inner_vlan_removal_en_flg; 1377 u8 inner_vlan_removal_en; 1378 /* set if tpa parameters should be handled, TPA must be disable before */ 1379 u8 update_tpa_param_flg; 1380 u8 update_tpa_en_flg /* set if tpa enable changes */; 1381 /* set if tx switching en flag should be handled */ 1382 u8 update_tx_switching_en_flg; 1383 u8 tx_switching_en /* tx switching en value */; 1384 /* set if anti spoofing flag should be handled */ 1385 u8 update_anti_spoofing_en_flg; 1386 u8 anti_spoofing_en /* Anti-spoofing verification en value */; 1387 /* set if handle_ptp_pkts should be handled. */ 1388 u8 update_handle_ptp_pkts; 1389 /* If set, the vport handles PTP Timesync Packets */ 1390 u8 handle_ptp_pkts; 1391 /* If set, the default Vlan enable flag is updated */ 1392 u8 update_default_vlan_en_flg; 1393 /* If set, the default Vlan value is forced by the FW */ 1394 u8 default_vlan_en; 1395 /* If set, the default Vlan value is updated */ 1396 u8 update_default_vlan_flg; 1397 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1398 /* set if accept_any_vlan should be handled */ 1399 u8 update_accept_any_vlan_flg; 1400 u8 accept_any_vlan /* accept_any_vlan updated value */; 1401 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled 1402 * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data 1403 */ 1404 u8 silent_vlan_removal_en; 1405 /* If set, MTU will be updated. Vport must be not active. */ 1406 u8 update_mtu_flg; 1407 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; 1408 /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be 1409 * updated 1410 */ 1411 u8 update_ctl_frame_checks_en_flg; 1412 /* If set, control frames will be filtered according to MAC check. */ 1413 u8 ctl_frame_mac_check_en; 1414 /* If set, control frames will be filtered according to ethtype check. */ 1415 u8 ctl_frame_ethtype_check_en; 1416 /* Indicates to update RDMA or NON-RDMA vlan remapping priority table according 1417 * to update_in_to_in_pri_map_mode_enum, used for TenantDcb (use enum 1418 * update_in_to_in_pri_map_mode_enum) 1419 */ 1420 u8 update_in_to_in_pri_map_mode; 1421 /* Map for inner to inner vlan priority translation, used for TenantDcb. */ 1422 u8 in_to_in_pri_map[8]; 1423 u8 reserved[6]; 1424 }; 1425 1426 struct vport_update_ramrod_mcast { 1427 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; 1428 }; 1429 1430 /* 1431 * Ramrod data for vport update ramrod 1432 */ 1433 struct vport_update_ramrod_data { 1434 /* Common data for all vport update ramrods */ 1435 struct vport_update_ramrod_data_cmn common; 1436 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; 1437 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; 1438 __le32 reserved[3]; 1439 /* TPA configuration parameters */ 1440 struct eth_vport_tpa_param tpa_param; 1441 struct vport_update_ramrod_mcast approx_mcast; 1442 struct eth_vport_rss_config rss_config /* rss config data */; 1443 }; 1444 1445 1446 1447 1448 1449 1450 struct E4XstormEthConnAgCtxDqExtLdPart { 1451 u8 reserved0 /* cdu_validation */; 1452 u8 state /* state */; 1453 u8 flags0; 1454 /* exist_in_qm0 */ 1455 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 1456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1457 /* exist_in_qm1 */ 1458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 1459 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1460 /* exist_in_qm2 */ 1461 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 1462 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1463 /* exist_in_qm3 */ 1464 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 1465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1466 /* bit4 */ 1467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 1468 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1469 /* cf_array_active */ 1470 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 1471 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1472 /* bit6 */ 1473 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 1474 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1475 /* bit7 */ 1476 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 1477 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1478 u8 flags1; 1479 /* bit8 */ 1480 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 1481 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1482 /* bit9 */ 1483 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 1484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1485 /* bit10 */ 1486 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 1487 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1488 /* bit11 */ 1489 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 1490 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1491 /* bit12 */ 1492 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 1493 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1494 /* bit13 */ 1495 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 1496 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1497 /* bit14 */ 1498 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 1499 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1500 /* bit15 */ 1501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 1502 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1503 u8 flags2; 1504 /* timer0cf */ 1505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 1506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1507 /* timer1cf */ 1508 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 1509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1510 /* timer2cf */ 1511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 1512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1513 /* timer_stop_all */ 1514 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 1515 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1516 u8 flags3; 1517 /* cf4 */ 1518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 1519 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1520 /* cf5 */ 1521 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 1522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1523 /* cf6 */ 1524 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 1525 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1526 /* cf7 */ 1527 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 1528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1529 u8 flags4; 1530 /* cf8 */ 1531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 1532 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1533 /* cf9 */ 1534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 1535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1536 /* cf10 */ 1537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 1538 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1539 /* cf11 */ 1540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 1541 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1542 u8 flags5; 1543 /* cf12 */ 1544 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 1545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1546 /* cf13 */ 1547 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 1548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1549 /* cf14 */ 1550 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 1551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1552 /* cf15 */ 1553 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 1554 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1555 u8 flags6; 1556 /* cf16 */ 1557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 1558 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1559 /* cf_array_cf */ 1560 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 1561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1562 /* cf18 */ 1563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 1564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1565 /* cf19 */ 1566 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 1567 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1568 u8 flags7; 1569 /* cf20 */ 1570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 1571 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1572 /* cf21 */ 1573 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 1574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1575 /* cf22 */ 1576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 1577 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1578 /* cf0en */ 1579 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 1580 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1581 /* cf1en */ 1582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 1583 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1584 u8 flags8; 1585 /* cf2en */ 1586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 1587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1588 /* cf3en */ 1589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 1590 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1591 /* cf4en */ 1592 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 1593 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1594 /* cf5en */ 1595 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 1596 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1597 /* cf6en */ 1598 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 1599 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1600 /* cf7en */ 1601 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 1602 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1603 /* cf8en */ 1604 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 1605 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1606 /* cf9en */ 1607 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 1608 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1609 u8 flags9; 1610 /* cf10en */ 1611 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 1612 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1613 /* cf11en */ 1614 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 1615 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1616 /* cf12en */ 1617 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 1618 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1619 /* cf13en */ 1620 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 1621 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1622 /* cf14en */ 1623 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 1624 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1625 /* cf15en */ 1626 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 1627 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1628 /* cf16en */ 1629 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 1630 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1631 /* cf_array_cf_en */ 1632 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 1633 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1634 u8 flags10; 1635 /* cf18en */ 1636 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 1637 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1638 /* cf19en */ 1639 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 1640 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1641 /* cf20en */ 1642 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 1643 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1644 /* cf21en */ 1645 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 1646 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1647 /* cf22en */ 1648 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 1649 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1650 /* cf23en */ 1651 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 1652 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1653 /* rule0en */ 1654 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 1655 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1656 /* rule1en */ 1657 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 1658 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1659 u8 flags11; 1660 /* rule2en */ 1661 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 1662 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1663 /* rule3en */ 1664 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 1665 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1666 /* rule4en */ 1667 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 1668 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1669 /* rule5en */ 1670 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 1671 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1672 /* rule6en */ 1673 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 1674 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1675 /* rule7en */ 1676 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 1677 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1678 /* rule8en */ 1679 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 1680 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1681 /* rule9en */ 1682 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 1683 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1684 u8 flags12; 1685 /* rule10en */ 1686 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 1687 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1688 /* rule11en */ 1689 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 1690 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1691 /* rule12en */ 1692 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 1693 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1694 /* rule13en */ 1695 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 1696 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1697 /* rule14en */ 1698 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 1699 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1700 /* rule15en */ 1701 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 1702 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1703 /* rule16en */ 1704 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 1705 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1706 /* rule17en */ 1707 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 1708 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1709 u8 flags13; 1710 /* rule18en */ 1711 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 1712 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1713 /* rule19en */ 1714 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 1715 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1716 /* rule20en */ 1717 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 1718 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1719 /* rule21en */ 1720 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 1721 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1722 /* rule22en */ 1723 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 1724 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1725 /* rule23en */ 1726 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 1727 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1728 /* rule24en */ 1729 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 1730 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1731 /* rule25en */ 1732 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 1733 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1734 u8 flags14; 1735 /* bit16 */ 1736 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 1737 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 1738 /* bit17 */ 1739 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 1740 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 1741 /* bit18 */ 1742 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 1743 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 1744 /* bit19 */ 1745 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 1746 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1747 /* bit20 */ 1748 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 1749 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 1750 /* bit21 */ 1751 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 1752 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1753 /* cf23 */ 1754 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 1755 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 1756 u8 edpm_event_id /* byte2 */; 1757 __le16 physical_q0 /* physical_q0 */; 1758 __le16 e5_reserved1 /* physical_q1 */; 1759 __le16 edpm_num_bds /* physical_q2 */; 1760 __le16 tx_bd_cons /* word3 */; 1761 __le16 tx_bd_prod /* word4 */; 1762 __le16 updated_qm_pq_id /* word5 */; 1763 __le16 conn_dpi /* conn_dpi */; 1764 u8 byte3 /* byte3 */; 1765 u8 byte4 /* byte4 */; 1766 u8 byte5 /* byte5 */; 1767 u8 byte6 /* byte6 */; 1768 __le32 reg0 /* reg0 */; 1769 __le32 reg1 /* reg1 */; 1770 __le32 reg2 /* reg2 */; 1771 __le32 reg3 /* reg3 */; 1772 __le32 reg4 /* reg4 */; 1773 }; 1774 1775 1776 struct mstorm_eth_conn_ag_ctx { 1777 u8 byte0 /* cdu_validation */; 1778 u8 byte1 /* state */; 1779 u8 flags0; 1780 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1781 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1782 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1783 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1784 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1785 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 1786 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1787 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 1788 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1789 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1790 u8 flags1; 1791 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1792 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 1793 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1794 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 1795 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1796 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1797 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1798 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 1799 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1800 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 1801 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1802 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 1803 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1804 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 1805 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1806 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 1807 __le16 word0 /* word0 */; 1808 __le16 word1 /* word1 */; 1809 __le32 reg0 /* reg0 */; 1810 __le32 reg1 /* reg1 */; 1811 }; 1812 1813 1814 1815 1816 1817 struct xstorm_eth_hw_conn_ag_ctx { 1818 u8 reserved0 /* cdu_validation */; 1819 u8 eth_state /* state */; 1820 u8 flags0; 1821 /* exist_in_qm0 */ 1822 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 1823 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1824 /* exist_in_qm1 */ 1825 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 1826 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 1827 /* exist_in_qm2 */ 1828 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 1829 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 1830 /* exist_in_qm3 */ 1831 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 1832 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1833 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1834 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 1835 /* cf_array_active */ 1836 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 1837 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 1838 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1839 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 1840 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1841 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 1842 u8 flags1; 1843 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1844 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 1845 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1846 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 1847 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 1848 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 1849 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1850 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 1851 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 1852 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 1853 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 1854 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 1855 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1856 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 1857 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1858 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 1859 u8 flags2; 1860 /* timer0cf */ 1861 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 1862 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 1863 /* timer1cf */ 1864 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 1865 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 1866 /* timer2cf */ 1867 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 1868 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 1869 /* timer_stop_all */ 1870 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 1871 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 1872 u8 flags3; 1873 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1874 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 1875 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1876 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 1877 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1878 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 1879 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1880 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 1881 u8 flags4; 1882 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1883 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 1884 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1885 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 1886 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1887 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 1888 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1889 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 1890 u8 flags5; 1891 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1892 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 1893 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1894 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 1895 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1896 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 1897 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1898 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 1899 u8 flags6; 1900 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1901 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 1902 /* cf_array_cf */ 1903 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 1904 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 1905 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 1906 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 1907 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 1908 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 1909 u8 flags7; 1910 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1911 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1912 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 1913 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 1914 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1915 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1916 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1917 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 1918 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1919 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 1920 u8 flags8; 1921 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1922 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 1923 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1924 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 1925 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1926 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 1927 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1928 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 1929 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1930 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 1931 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1932 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 1933 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1934 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 1935 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1936 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 1937 u8 flags9; 1938 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1939 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 1940 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1941 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 1942 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1943 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 1944 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1945 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 1946 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1947 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 1948 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1949 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 1950 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1951 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 1952 /* cf_array_cf_en */ 1953 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 1954 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 1955 u8 flags10; 1956 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 1957 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 1958 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1959 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 1960 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1961 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1962 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 1963 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 1964 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1965 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1966 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1967 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 1968 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 1969 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 1970 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 1971 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 1972 u8 flags11; 1973 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 1974 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 1975 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 1976 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 1977 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1978 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 1979 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1980 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 1981 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1982 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 1983 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1984 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 1985 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1986 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1987 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1988 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 1989 u8 flags12; 1990 /* rule10en */ 1991 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 1992 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 1993 /* rule11en */ 1994 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 1995 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 1996 /* rule12en */ 1997 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 1998 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1999 /* rule13en */ 2000 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 2001 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2002 /* rule14en */ 2003 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 2004 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2005 /* rule15en */ 2006 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 2007 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2008 /* rule16en */ 2009 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 2010 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2011 /* rule17en */ 2012 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 2013 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2014 u8 flags13; 2015 /* rule18en */ 2016 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 2017 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2018 /* rule19en */ 2019 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 2020 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2021 /* rule20en */ 2022 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 2023 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2024 /* rule21en */ 2025 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 2026 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2027 /* rule22en */ 2028 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 2029 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2030 /* rule23en */ 2031 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 2032 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2033 /* rule24en */ 2034 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 2035 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2036 /* rule25en */ 2037 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 2038 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2039 u8 flags14; 2040 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2041 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2042 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2043 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2044 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2045 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2046 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2047 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2048 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2049 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2050 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2051 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2052 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2053 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2054 u8 edpm_event_id /* byte2 */; 2055 __le16 physical_q0 /* physical_q0 */; 2056 __le16 e5_reserved1 /* physical_q1 */; 2057 __le16 edpm_num_bds /* physical_q2 */; 2058 __le16 tx_bd_cons /* word3 */; 2059 __le16 tx_bd_prod /* word4 */; 2060 __le16 updated_qm_pq_id /* word5 */; 2061 __le16 conn_dpi /* conn_dpi */; 2062 }; 2063 2064 2065 2066 /* 2067 * GFT CAM line struct 2068 */ 2069 struct gft_cam_line { 2070 __le32 camline; 2071 /* Indication if the line is valid. */ 2072 #define GFT_CAM_LINE_VALID_MASK 0x1 2073 #define GFT_CAM_LINE_VALID_SHIFT 0 2074 /* Data bits, the word that compared with the profile key */ 2075 #define GFT_CAM_LINE_DATA_MASK 0x3FFF 2076 #define GFT_CAM_LINE_DATA_SHIFT 1 2077 /* Mask bits, indicate the bits in the data that are Dont-Care */ 2078 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF 2079 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 2080 #define GFT_CAM_LINE_RESERVED1_MASK 0x7 2081 #define GFT_CAM_LINE_RESERVED1_SHIFT 29 2082 }; 2083 2084 2085 /* 2086 * GFT CAM line struct (for driversim use) 2087 */ 2088 struct gft_cam_line_mapped { 2089 __le32 camline; 2090 /* Indication if the line is valid. */ 2091 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 2092 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 2093 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2094 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 2095 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 2096 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2097 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 2098 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 2099 /* use enum gft_profile_upper_protocol_type 2100 * (use enum gft_profile_upper_protocol_type) 2101 */ 2102 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF 2103 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 2104 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2105 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF 2106 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 2107 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 2108 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 2109 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2110 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 2111 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 2112 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2113 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 2114 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 2115 /* use enum gft_profile_upper_protocol_type 2116 * (use enum gft_profile_upper_protocol_type) 2117 */ 2118 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 2119 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 2120 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2121 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 2122 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 2123 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 2124 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 2125 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 2126 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 2127 }; 2128 2129 2130 union gft_cam_line_union { 2131 struct gft_cam_line cam_line; 2132 struct gft_cam_line_mapped cam_line_mapped; 2133 }; 2134 2135 2136 /* 2137 * Used in gft_profile_key: Indication for ip version 2138 */ 2139 enum gft_profile_ip_version { 2140 GFT_PROFILE_IPV4 = 0, 2141 GFT_PROFILE_IPV6 = 1, 2142 MAX_GFT_PROFILE_IP_VERSION 2143 }; 2144 2145 2146 /* 2147 * Profile key stucr fot GFT logic in Prs 2148 */ 2149 struct gft_profile_key { 2150 __le16 profile_key; 2151 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2152 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 2153 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 2154 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2155 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 2156 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 2157 /* use enum gft_profile_upper_protocol_type 2158 * (use enum gft_profile_upper_protocol_type) 2159 */ 2160 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 2161 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 2162 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2163 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 2164 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 2165 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 2166 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 2167 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 2168 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 2169 }; 2170 2171 2172 /* 2173 * Used in gft_profile_key: Indication for tunnel type 2174 */ 2175 enum gft_profile_tunnel_type { 2176 GFT_PROFILE_NO_TUNNEL = 0, 2177 GFT_PROFILE_VXLAN_TUNNEL = 1, 2178 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, 2179 GFT_PROFILE_GRE_IP_TUNNEL = 3, 2180 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, 2181 GFT_PROFILE_GENEVE_IP_TUNNEL = 5, 2182 MAX_GFT_PROFILE_TUNNEL_TYPE 2183 }; 2184 2185 2186 /* 2187 * Used in gft_profile_key: Indication for protocol type 2188 */ 2189 enum gft_profile_upper_protocol_type { 2190 GFT_PROFILE_ROCE_PROTOCOL = 0, 2191 GFT_PROFILE_RROCE_PROTOCOL = 1, 2192 GFT_PROFILE_FCOE_PROTOCOL = 2, 2193 GFT_PROFILE_ICMP_PROTOCOL = 3, 2194 GFT_PROFILE_ARP_PROTOCOL = 4, 2195 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, 2196 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, 2197 GFT_PROFILE_TCP_PROTOCOL = 7, 2198 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, 2199 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, 2200 GFT_PROFILE_UDP_PROTOCOL = 10, 2201 GFT_PROFILE_USER_IP_1_INNER = 11, 2202 GFT_PROFILE_USER_IP_2_OUTER = 12, 2203 GFT_PROFILE_USER_ETH_1_INNER = 13, 2204 GFT_PROFILE_USER_ETH_2_OUTER = 14, 2205 GFT_PROFILE_RAW = 15, 2206 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 2207 }; 2208 2209 2210 /* 2211 * GFT RAM line struct 2212 */ 2213 struct gft_ram_line { 2214 __le32 lo; 2215 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 2216 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 2217 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 2218 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 2219 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 2220 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 2221 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 2222 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 2223 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 2224 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 2225 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 2226 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 2227 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 2228 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 2229 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 2230 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 2231 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 2232 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 2233 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 2234 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 2235 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 2236 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 2237 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 2238 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 2239 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 2240 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 2241 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 2242 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 2243 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 2244 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 2245 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 2246 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 2247 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 2248 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 2249 #define GFT_RAM_LINE_TTL_MASK 0x1 2250 #define GFT_RAM_LINE_TTL_SHIFT 18 2251 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 2252 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 2253 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 2254 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 2255 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 2256 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 2257 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 2258 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 2259 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 2260 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 2261 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 2262 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 2263 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 2264 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 2265 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 2266 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 2267 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 2268 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 2269 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 2270 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 2271 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 2272 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 2273 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 2274 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 2275 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1U 2276 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 2277 __le32 hi; 2278 #define GFT_RAM_LINE_DSCP_MASK 0x1 2279 #define GFT_RAM_LINE_DSCP_SHIFT 0 2280 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 2281 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 2282 #define GFT_RAM_LINE_DST_IP_MASK 0x1 2283 #define GFT_RAM_LINE_DST_IP_SHIFT 2 2284 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 2285 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 2286 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 2287 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 2288 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 2289 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 2290 #define GFT_RAM_LINE_VLAN_MASK 0x1 2291 #define GFT_RAM_LINE_VLAN_SHIFT 6 2292 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 2293 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 2294 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 2295 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 2296 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 2297 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 2298 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 2299 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 2300 }; 2301 2302 2303 /* 2304 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask 2305 */ 2306 enum gft_vlan_select { 2307 INNER_PROVIDER_VLAN = 0, 2308 INNER_VLAN = 1, 2309 OUTER_PROVIDER_VLAN = 2, 2310 OUTER_VLAN = 3, 2311 MAX_GFT_VLAN_SELECT 2312 }; 2313 2314 2315 #endif /* __ECORE_HSI_ETH__ */ 2316