1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2018 Intel Corporation 3 */ 4 5 #ifndef _IFPGA_DEFINES_H_ 6 #define _IFPGA_DEFINES_H_ 7 8 #include "ifpga_compat.h" 9 10 #define MAX_FPGA_PORT_NUM 4 11 12 #define FME_FEATURE_HEADER "fme_hdr" 13 #define FME_FEATURE_THERMAL_MGMT "fme_thermal" 14 #define FME_FEATURE_POWER_MGMT "fme_power" 15 #define FME_FEATURE_GLOBAL_IPERF "fme_iperf" 16 #define FME_FEATURE_GLOBAL_ERR "fme_error" 17 #define FME_FEATURE_PR_MGMT "fme_pr" 18 #define FME_FEATURE_EMIF_MGMT "fme_emif" 19 #define FME_FEATURE_HSSI_ETH "fme_hssi" 20 #define FME_FEATURE_GLOBAL_DPERF "fme_dperf" 21 #define FME_FEATURE_QSPI_FLASH "fme_qspi_flash" 22 #define FME_FEATURE_MAX10_SPI "fme_max10_spi" 23 #define FME_FEATURE_NIOS_SPI "fme_nios_spi" 24 #define FME_FEATURE_I2C_MASTER "fme_i2c_master" 25 #define FME_FEATURE_ETH_GROUP "fme_eth_group" 26 #define FME_FEATURE_PMCI "fme_pmci" 27 28 #define PORT_FEATURE_HEADER "port_hdr" 29 #define PORT_FEATURE_UAFU "port_uafu" 30 #define PORT_FEATURE_ERR "port_err" 31 #define PORT_FEATURE_UMSG "port_umsg" 32 #define PORT_FEATURE_PR "port_pr" 33 #define PORT_FEATURE_UINT "port_uint" 34 #define PORT_FEATURE_STP "port_stp" 35 36 /* 37 * do not check the revision id as id may be dynamic under 38 * some cases, e.g, UAFU. 39 */ 40 #define SKIP_REVISION_CHECK 0xff 41 42 #define FME_HEADER_REVISION 1 43 #define FME_THERMAL_MGMT_REVISION 0 44 #define FME_POWER_MGMT_REVISION 1 45 #define FME_GLOBAL_IPERF_REVISION 1 46 #define FME_GLOBAL_ERR_REVISION 1 47 #define FME_PR_MGMT_REVISION 2 48 #define FME_HSSI_ETH_REVISION 0 49 #define FME_GLOBAL_DPERF_REVISION 0 50 #define FME_QSPI_REVISION 0 51 #define FME_MAX10_SPI 0 52 #define FME_I2C_MASTER 0 53 54 #define PORT_HEADER_REVISION 0 55 /* UAFU's header info depends on the downloaded GBS */ 56 #define PORT_UAFU_REVISION SKIP_REVISION_CHECK 57 #define PORT_ERR_REVISION 1 58 #define PORT_UMSG_REVISION 0 59 #define PORT_UINT_REVISION 0 60 #define PORT_STP_REVISION 1 61 62 #define FEATURE_TYPE_AFU 0x1 63 #define FEATURE_TYPE_BBB 0x2 64 #define FEATURE_TYPE_PRIVATE 0x3 65 #define FEATURE_TYPE_FIU 0x4 66 67 #define FEATURE_FIU_ID_FME 0x0 68 #define FEATURE_FIU_ID_PORT 0x1 69 70 /* Reserved 0xfe for Header, 0xff for AFU*/ 71 #define FEATURE_ID_FIU_HEADER 0xfe 72 #define FEATURE_ID_AFU 0xff 73 74 enum fpga_id_type { 75 FME_ID, 76 PORT_ID, 77 AFU_ID, 78 FPGA_ID_MAX, 79 }; 80 81 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 82 #define FME_FEATURE_ID_THERMAL_MGMT 0x1 83 #define FME_FEATURE_ID_POWER_MGMT 0x2 84 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3 85 #define FME_FEATURE_ID_GLOBAL_ERR 0x4 86 #define FME_FEATURE_ID_PR_MGMT 0x5 87 #define FME_FEATURE_ID_HSSI_ETH 0x6 88 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7 89 #define FME_FEATURE_ID_QSPI_FLASH 0x8 90 #define FME_FEATURE_ID_EMIF_MGMT 0x9 91 #define FME_FEATURE_ID_MAX10_SPI 0xe 92 #define FME_FEATURE_ID_NIOS_SPI 0xd 93 #define FME_FEATURE_ID_I2C_MASTER 0xf 94 #define FME_FEATURE_ID_ETH_GROUP 0x10 95 #define FME_FEATURE_ID_PMCI 0x12 96 97 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 98 #define PORT_FEATURE_ID_ERROR 0x10 99 #define PORT_FEATURE_ID_UMSG 0x11 100 #define PORT_FEATURE_ID_UINT 0x12 101 #define PORT_FEATURE_ID_STP 0x13 102 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU 103 104 /* 105 * All headers and structures must be byte-packed to match the spec. 106 */ 107 #pragma pack(push, 1) 108 109 struct feature_header { 110 union { 111 u64 csr; 112 struct { 113 u16 id:12; 114 u8 revision:4; 115 u32 next_header_offset:24; 116 u8 end_of_list:1; 117 u32 reserved:19; 118 u8 type:4; 119 }; 120 }; 121 }; 122 123 struct feature_bbb_header { 124 struct uuid guid; 125 }; 126 127 struct feature_afu_header { 128 struct uuid guid; 129 union { 130 u64 csr; 131 struct { 132 u64 next_afu:24; 133 u64 reserved:40; 134 }; 135 }; 136 }; 137 138 struct feature_fiu_header { 139 struct uuid guid; 140 union { 141 u64 csr; 142 struct { 143 u64 next_afu:24; 144 u64 reserved:40; 145 }; 146 }; 147 }; 148 149 struct feature_fme_capability { 150 union { 151 u64 csr; 152 struct { 153 u8 fabric_verid; /* Fabric version ID */ 154 u8 socket_id:1; /* Socket id */ 155 u8 rsvd1:3; /* Reserved */ 156 /* pci0 link available yes /no */ 157 u8 pci0_link_avile:1; 158 /* pci1 link available yes /no */ 159 u8 pci1_link_avile:1; 160 /* Coherent (QPI/UPI) link available yes /no */ 161 u8 qpi_link_avile:1; 162 u8 rsvd2:1; /* Reserved */ 163 /* IOMMU or VT-d supported yes/no */ 164 u8 iommu_support:1; 165 u8 num_ports:3; /* Number of ports */ 166 u8 sf_fab_ctl:1; /* Internal validation bit */ 167 u8 rsvd3:3; /* Reserved */ 168 /* 169 * Address width supported in bits 170 * BXT -0x26 , SKX -0x30 171 */ 172 u8 address_width_bits:6; 173 u8 rsvd4:2; /* Reserved */ 174 /* Size of cache supported in kb */ 175 u16 cache_size:12; 176 u8 cache_assoc:4; /* Cache Associativity */ 177 u16 rsvd5:15; /* Reserved */ 178 u8 lock_bit:1; /* Lock bit */ 179 }; 180 }; 181 }; 182 183 #define FME_AFU_ACCESS_PF 0 184 #define FME_AFU_ACCESS_VF 1 185 186 struct feature_fme_port { 187 union { 188 u64 csr; 189 struct { 190 u32 port_offset:24; 191 u8 reserved1; 192 u8 port_bar:3; 193 u32 reserved2:20; 194 u8 afu_access_control:1; 195 u8 reserved3:4; 196 u8 port_implemented:1; 197 u8 reserved4:3; 198 }; 199 }; 200 }; 201 202 struct feature_fme_fab_status { 203 union { 204 u64 csr; 205 struct { 206 u8 upilink_status:4; /* UPI Link Status */ 207 u8 rsvd1:4; /* Reserved */ 208 u8 pci0link_status:1; /* pci0 link status */ 209 u8 rsvd2:3; /* Reserved */ 210 u8 pci1link_status:1; /* pci1 link status */ 211 u64 rsvd3:51; /* Reserved */ 212 }; 213 }; 214 }; 215 216 struct feature_fme_genprotrange2_base { 217 union { 218 u64 csr; 219 struct { 220 u16 rsvd1; /* Reserved */ 221 /* Base Address of memory range */ 222 u8 protected_base_addrss:4; 223 u64 rsvd2:44; /* Reserved */ 224 }; 225 }; 226 }; 227 228 struct feature_fme_genprotrange2_limit { 229 union { 230 u64 csr; 231 struct { 232 u16 rsvd1; /* Reserved */ 233 /* Limit Address of memory range */ 234 u8 protected_limit_addrss:4; 235 u16 rsvd2:11; /* Reserved */ 236 u8 enable:1; /* Enable GENPROTRANGE check */ 237 u32 rsvd3; /* Reserved */ 238 }; 239 }; 240 }; 241 242 struct feature_fme_dxe_lock { 243 union { 244 u64 csr; 245 struct { 246 /* 247 * Determines write access to the DXE region CSRs 248 * 1 - CSR region is locked; 249 * 0 - it is open for write access. 250 */ 251 u8 dxe_early_lock:1; 252 /* 253 * Determines write access to the HSSI CSR 254 * 1 - CSR region is locked; 255 * 0 - it is open for write access. 256 */ 257 u8 dxe_late_lock:1; 258 u64 rsvd:62; 259 }; 260 }; 261 }; 262 263 #define HSSI_ID_NO_HASSI 0 264 #define HSSI_ID_PCIE_RP 1 265 #define HSSI_ID_ETHERNET 2 266 267 struct feature_fme_bitstream_id { 268 union { 269 u64 csr; 270 struct { 271 u8 build_patch:8; 272 u8 build_minor:8; 273 u8 build_major:8; 274 u8 fvl_bypass:1; 275 u8 mac_lightweight:1; 276 u8 disagregate:1; 277 u8 lightweiht:1; 278 u8 seu:1; 279 u8 ptp:1; 280 u8 reserve:2; 281 u8 interface:4; 282 u32 afu_revision:12; 283 u8 patch:4; 284 u8 minor:4; 285 u8 major:4; 286 u8 reserved:4; 287 } v1; 288 struct { 289 u32 gitrepo_hash:32; /* GIT repository hash */ 290 /* 291 * HSSI configuration identifier: 292 * 0 - No HSSI 293 * 1 - PCIe-RP 294 * 2 - Ethernet 295 */ 296 u8 hssi_id:4; 297 u8 rsvd1:4; 298 u8 fim_type:8; 299 /* Bitstream version patch number */ 300 u8 bs_verpatch:4; 301 /* Bitstream version minor number */ 302 u8 bs_verminor:4; 303 /* Bitstream version major number */ 304 u8 bs_vermajor:4; 305 /* Bitstream version debug number */ 306 u8 bs_verdebug:4; 307 } v2; 308 }; 309 }; 310 311 struct feature_fme_bitstream_md { 312 union { 313 u64 csr; 314 struct { 315 /* Seed number userd for synthesis flow */ 316 u8 synth_seed:4; 317 /* Synthesis date(day number - 2 digits) */ 318 u8 synth_day:8; 319 /* Synthesis date(month number - 2 digits) */ 320 u8 synth_month:8; 321 /* Synthesis date(year number - 2 digits) */ 322 u8 synth_year:8; 323 u64 rsvd:36; /* Reserved */ 324 }; 325 }; 326 }; 327 328 struct feature_fme_iommu_ctrl { 329 union { 330 u64 csr; 331 struct { 332 /* Disables IOMMU prefetcher for C0 channel */ 333 u8 prefetch_disableC0:1; 334 /* Disables IOMMU prefetcher for C1 channel */ 335 u8 prefetch_disableC1:1; 336 /* Disables IOMMU partial cache line writes */ 337 u8 prefetch_wrdisable:1; 338 u8 rsvd1:1; /* Reserved */ 339 /* 340 * Select counter and read value from register 341 * iommu_stat.dbg_counters 342 * 0 - Number of 4K page translation response 343 * 1 - Number of 2M page translation response 344 * 2 - Number of 1G page translation response 345 */ 346 u8 counter_sel:2; 347 u32 rsvd2:26; /* Reserved */ 348 /* Connected to IOMMU SIP Capabilities */ 349 u32 capecap_defeature; 350 }; 351 }; 352 }; 353 354 struct feature_fme_iommu_stat { 355 union { 356 u64 csr; 357 struct { 358 /* Translation Enable bit from IOMMU SIP */ 359 u8 translation_enable:1; 360 /* Drain request in progress */ 361 u8 drain_req_inprog:1; 362 /* Invalidation current state */ 363 u8 inv_state:3; 364 /* C0 Response Buffer current state */ 365 u8 respbuffer_stateC0:3; 366 /* C1 Response Buffer current state */ 367 u8 respbuffer_stateC1:3; 368 /* Last request ID to IOMMU SIP */ 369 u8 last_reqID:4; 370 /* Last IOMMU SIP response ID value */ 371 u8 last_respID:4; 372 /* Last IOMMU SIP response status value */ 373 u8 last_respstatus:3; 374 /* C0 Transaction Buffer is not empty */ 375 u8 transbuf_notEmptyC0:1; 376 /* C1 Transaction Buffer is not empty */ 377 u8 transbuf_notEmptyC1:1; 378 /* C0 Request FIFO is not empty */ 379 u8 reqFIFO_notemptyC0:1; 380 /* C1 Request FIFO is not empty */ 381 u8 reqFIFO_notemptyC1:1; 382 /* C0 Response FIFO is not empty */ 383 u8 respFIFO_notemptyC0:1; 384 /* C1 Response FIFO is not empty */ 385 u8 respFIFO_notemptyC1:1; 386 /* C0 Response FIFO overflow detected */ 387 u8 respFIFO_overflowC0:1; 388 /* C1 Response FIFO overflow detected */ 389 u8 respFIFO_overflowC1:1; 390 /* C0 Transaction Buffer overflow detected */ 391 u8 tranbuf_overflowC0:1; 392 /* C1 Transaction Buffer overflow detected */ 393 u8 tranbuf_overflowC1:1; 394 /* Request FIFO overflow detected */ 395 u8 reqFIFO_overflow:1; 396 /* IOMMU memory read in progress */ 397 u8 memrd_inprog:1; 398 /* IOMMU memory write in progress */ 399 u8 memwr_inprog:1; 400 u8 rsvd1:1; /* Reserved */ 401 /* Value of counter selected by iommu_ctl.counter_sel */ 402 u16 dbg_counters:16; 403 u16 rsvd2:12; /* Reserved */ 404 }; 405 }; 406 }; 407 408 struct feature_fme_pcie0_ctrl { 409 union { 410 u64 csr; 411 struct { 412 u64 vtd_bar_lock:1; /* Lock VT-D BAR register */ 413 u64 rsvd1:3; 414 u64 rciep:1; /* Configure PCIE0 as RCiEP */ 415 u64 rsvd2:59; 416 }; 417 }; 418 }; 419 420 struct feature_fme_llpr_smrr_base { 421 union { 422 u64 csr; 423 struct { 424 u64 rsvd1:12; 425 u64 base:20; /* SMRR2 memory range base address */ 426 u64 rsvd2:32; 427 }; 428 }; 429 }; 430 431 struct feature_fme_llpr_smrr_mask { 432 union { 433 u64 csr; 434 struct { 435 u64 rsvd1:11; 436 u64 valid:1; /* LLPR_SMRR rule is valid or not */ 437 /* 438 * SMRR memory range mask which determines the range 439 * of region being mapped 440 */ 441 u64 phys_mask:20; 442 u64 rsvd2:32; 443 }; 444 }; 445 }; 446 447 struct feature_fme_llpr_smrr2_base { 448 union { 449 u64 csr; 450 struct { 451 u64 rsvd1:12; 452 u64 base:20; /* SMRR2 memory range base address */ 453 u64 rsvd2:32; 454 }; 455 }; 456 }; 457 458 struct feature_fme_llpr_smrr2_mask { 459 union { 460 u64 csr; 461 struct { 462 u64 rsvd1:11; 463 u64 valid:1; /* LLPR_SMRR2 rule is valid or not */ 464 /* 465 * SMRR2 memory range mask which determines the range 466 * of region being mapped 467 */ 468 u64 phys_mask:20; 469 u64 rsvd2:32; 470 }; 471 }; 472 }; 473 474 struct feature_fme_llpr_meseg_base { 475 union { 476 u64 csr; 477 struct { 478 /* A[45:19] of base address memory range */ 479 u64 me_base:27; 480 u64 rsvd:37; 481 }; 482 }; 483 }; 484 485 struct feature_fme_llpr_meseg_limit { 486 union { 487 u64 csr; 488 struct { 489 /* A[45:19] of limit address memory range */ 490 u64 me_limit:27; 491 u64 rsvd1:4; 492 u64 enable:1; /* Enable LLPR MESEG rule */ 493 u64 rsvd2:32; 494 }; 495 }; 496 }; 497 498 struct feature_fme_header { 499 struct feature_header header; 500 struct feature_afu_header afu_header; 501 u64 reserved; 502 u64 scratchpad; 503 struct feature_fme_capability capability; 504 struct feature_fme_port port[MAX_FPGA_PORT_NUM]; 505 struct feature_fme_fab_status fab_status; 506 struct feature_fme_bitstream_id bitstream_id; 507 struct feature_fme_bitstream_md bitstream_md; 508 struct feature_fme_genprotrange2_base genprotrange2_base; 509 struct feature_fme_genprotrange2_limit genprotrange2_limit; 510 struct feature_fme_dxe_lock dxe_lock; 511 struct feature_fme_iommu_ctrl iommu_ctrl; 512 struct feature_fme_iommu_stat iommu_stat; 513 struct feature_fme_pcie0_ctrl pcie0_control; 514 struct feature_fme_llpr_smrr_base smrr_base; 515 struct feature_fme_llpr_smrr_mask smrr_mask; 516 struct feature_fme_llpr_smrr2_base smrr2_base; 517 struct feature_fme_llpr_smrr2_mask smrr2_mask; 518 struct feature_fme_llpr_meseg_base meseg_base; 519 struct feature_fme_llpr_meseg_limit meseg_limit; 520 }; 521 522 struct feature_port_capability { 523 union { 524 u64 csr; 525 struct { 526 u8 port_number:2; /* Port Number 0-3 */ 527 u8 rsvd1:6; /* Reserved */ 528 u16 mmio_size; /* User MMIO size in KB */ 529 u8 rsvd2; /* Reserved */ 530 u8 sp_intr_num:4; /* Supported interrupts num */ 531 u32 rsvd3:28; /* Reserved */ 532 }; 533 }; 534 }; 535 536 struct feature_port_control { 537 union { 538 u64 csr; 539 struct { 540 u8 port_sftrst:1; /* Port Soft Reset */ 541 u8 rsvd1:1; /* Reserved */ 542 u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */ 543 u8 rsvd2:1; /* Reserved */ 544 u8 port_sftrst_ack:1; /* HW ACK for Soft Reset */ 545 u64 rsvd3:59; /* Reserved */ 546 }; 547 }; 548 }; 549 550 #define PORT_POWER_STATE_NORMAL 0 551 #define PORT_POWER_STATE_AP1 1 552 #define PORT_POWER_STATE_AP2 2 553 #define PORT_POWER_STATE_AP6 6 554 555 struct feature_port_status { 556 union { 557 u64 csr; 558 struct { 559 u8 port_freeze:1; /* '1' - freezed '0' - normal */ 560 u8 rsvd1:7; /* Reserved */ 561 u8 power_state:4; /* Power State */ 562 u8 ap1_event:1; /* AP1 event was detected */ 563 u8 ap2_event:1; /* AP2 event was detected */ 564 u64 rsvd2:50; /* Reserved */ 565 }; 566 }; 567 }; 568 569 /* Port Header Register Set */ 570 struct feature_port_header { 571 struct feature_header header; 572 struct feature_afu_header afu_header; 573 u64 port_mailbox; 574 u64 scratchpad; 575 struct feature_port_capability capability; 576 struct feature_port_control control; 577 struct feature_port_status status; 578 u64 rsvd2; 579 u64 user_clk_freq_cmd0; 580 u64 user_clk_freq_cmd1; 581 u64 user_clk_freq_sts0; 582 u64 user_clk_freq_sts1; 583 }; 584 585 struct feature_fme_tmp_threshold { 586 union { 587 u64 csr; 588 struct { 589 u8 tmp_thshold1:7; /* temperature Threshold 1 */ 590 /* temperature Threshold 1 enable/disable */ 591 u8 tmp_thshold1_enable:1; 592 u8 tmp_thshold2:7; /* temperature Threshold 2 */ 593 /* temperature Threshold 2 enable /disable */ 594 u8 tmp_thshold2_enable:1; 595 u8 pro_hot_setpoint:7; /* Proc Hot set point */ 596 u8 rsvd4:1; /* Reserved */ 597 u8 therm_trip_thshold:7; /* Thermeal Trip Threshold */ 598 u8 rsvd3:1; /* Reserved */ 599 u8 thshold1_status:1; /* Threshold 1 Status */ 600 u8 thshold2_status:1; /* Threshold 2 Status */ 601 u8 rsvd5:1; /* Reserved */ 602 /* Thermeal Trip Threshold status */ 603 u8 therm_trip_thshold_status:1; 604 u8 rsvd6:4; /* Reserved */ 605 /* Validation mode- Force Proc Hot */ 606 u8 valmodeforce:1; 607 /* Validation mode - Therm trip Hot */ 608 u8 valmodetherm:1; 609 u8 rsvd2:2; /* Reserved */ 610 u8 thshold_policy:1; /* threshold policy */ 611 u32 rsvd:19; /* Reserved */ 612 }; 613 }; 614 }; 615 616 /* Temperature Sensor Read values format 1 */ 617 struct feature_fme_temp_rdsensor_fmt1 { 618 union { 619 u64 csr; 620 struct { 621 /* Reads out FPGA temperature in celsius */ 622 u8 fpga_temp:7; 623 u8 rsvd0:1; /* Reserved */ 624 /* Temperature reading sequence number */ 625 u16 tmp_reading_seq_num; 626 /* Temperature reading is valid */ 627 u8 tmp_reading_valid:1; 628 u8 rsvd1:7; /* Reserved */ 629 u16 dbg_mode:10; /* Debug mode */ 630 u32 rsvd2:22; /* Reserved */ 631 }; 632 }; 633 }; 634 635 /* Temperature sensor read values format 2 */ 636 struct feature_fme_temp_rdsensor_fmt2 { 637 u64 rsvd; /* Reserved */ 638 }; 639 640 /* Temperature Threshold Capability Register */ 641 struct feature_fme_tmp_threshold_cap { 642 union { 643 u64 csr; 644 struct { 645 /* Temperature Threshold Unsupported */ 646 u8 tmp_thshold_disabled:1; 647 u64 rsvd:63; /* Reserved */ 648 }; 649 }; 650 }; 651 652 /* FME THERNAL FEATURE */ 653 struct feature_fme_thermal { 654 struct feature_header header; 655 struct feature_fme_tmp_threshold threshold; 656 struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1; 657 struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2; 658 struct feature_fme_tmp_threshold_cap threshold_cap; 659 }; 660 661 /* Power Status register */ 662 struct feature_fme_pm_status { 663 union { 664 u64 csr; 665 struct { 666 /* FPGA Power consumed, The format is to be defined */ 667 u32 pwr_consumed:18; 668 /* FPGA Latency Tolerance Reporting */ 669 u8 fpga_latency_report:1; 670 u64 rsvd:45; /* Reserved */ 671 }; 672 }; 673 }; 674 675 /* AP Thresholds */ 676 struct feature_fme_pm_ap_threshold { 677 union { 678 u64 csr; 679 struct { 680 /* 681 * Number of clocks (5ns period) for assertion 682 * of FME_data 683 */ 684 u8 threshold1:7; 685 u8 rsvd1:1; 686 u8 threshold2:7; 687 u8 rsvd2:1; 688 u8 threshold1_status:1; 689 u8 threshold2_status:1; 690 u64 rsvd3:46; /* Reserved */ 691 }; 692 }; 693 }; 694 695 /* Xeon Power Limit */ 696 struct feature_fme_pm_xeon_limit { 697 union { 698 u64 csr; 699 struct { 700 /* Power limit in Watts in 12.3 format */ 701 u16 pwr_limit:15; 702 /* Indicates that power limit has been written */ 703 u8 enable:1; 704 /* 0 - Turbe range, 1 - Entire range */ 705 u8 clamping:1; 706 /* Time constant in XXYYY format */ 707 u8 time:7; 708 u64 rsvd:40; /* Reserved */ 709 }; 710 }; 711 }; 712 713 /* FPGA Power Limit */ 714 struct feature_fme_pm_fpga_limit { 715 union { 716 u64 csr; 717 struct { 718 /* Power limit in Watts in 12.3 format */ 719 u16 pwr_limit:15; 720 /* Indicates that power limit has been written */ 721 u8 enable:1; 722 /* 0 - Turbe range, 1 - Entire range */ 723 u8 clamping:1; 724 /* Time constant in XXYYY format */ 725 u8 time:7; 726 u64 rsvd:40; /* Reserved */ 727 }; 728 }; 729 }; 730 731 /* FME POWER FEATURE */ 732 struct feature_fme_power { 733 struct feature_header header; 734 struct feature_fme_pm_status status; 735 struct feature_fme_pm_ap_threshold threshold; 736 struct feature_fme_pm_xeon_limit xeon_limit; 737 struct feature_fme_pm_fpga_limit fpga_limit; 738 }; 739 740 #define CACHE_CHANNEL_RD 0 741 #define CACHE_CHANNEL_WR 1 742 743 enum iperf_cache_events { 744 IPERF_CACHE_RD_HIT, 745 IPERF_CACHE_WR_HIT, 746 IPERF_CACHE_RD_MISS, 747 IPERF_CACHE_WR_MISS, 748 IPERF_CACHE_RSVD, /* reserved */ 749 IPERF_CACHE_HOLD_REQ, 750 IPERF_CACHE_DATA_WR_PORT_CONTEN, 751 IPERF_CACHE_TAG_WR_PORT_CONTEN, 752 IPERF_CACHE_TX_REQ_STALL, 753 IPERF_CACHE_RX_REQ_STALL, 754 IPERF_CACHE_EVICTIONS, 755 }; 756 757 /* FPMON Cache Control */ 758 struct feature_fme_ifpmon_ch_ctl { 759 union { 760 u64 csr; 761 struct { 762 u8 reset_counters:1; /* Reset Counters */ 763 u8 rsvd1:7; /* Reserved */ 764 u8 freeze:1; /* Freeze if set to 1 */ 765 u8 rsvd2:7; /* Reserved */ 766 u8 cache_event:4; /* Select the cache event */ 767 u8 cci_chsel:1; /* Select the channel */ 768 u64 rsvd3:43; /* Reserved */ 769 }; 770 }; 771 }; 772 773 /* FPMON Cache Counter */ 774 struct feature_fme_ifpmon_ch_ctr { 775 union { 776 u64 csr; 777 struct { 778 /* Cache Counter for even addresse */ 779 u64 cache_counter:48; 780 u16 rsvd:12; /* Reserved */ 781 /* Cache Event being reported */ 782 u8 event_code:4; 783 }; 784 }; 785 }; 786 787 enum iperf_fab_events { 788 IPERF_FAB_PCIE0_RD, 789 IPERF_FAB_PCIE0_WR, 790 IPERF_FAB_PCIE1_RD, 791 IPERF_FAB_PCIE1_WR, 792 IPERF_FAB_UPI_RD, 793 IPERF_FAB_UPI_WR, 794 IPERF_FAB_MMIO_RD, 795 IPERF_FAB_MMIO_WR, 796 }; 797 798 #define FAB_DISABLE_FILTER 0 799 #define FAB_ENABLE_FILTER 1 800 801 /* FPMON FAB Control */ 802 struct feature_fme_ifpmon_fab_ctl { 803 union { 804 u64 csr; 805 struct { 806 u8 reset_counters:1; /* Reset Counters */ 807 u8 rsvd:7; /* Reserved */ 808 u8 freeze:1; /* Set to 1 frozen counter */ 809 u8 rsvd1:7; /* Reserved */ 810 u8 fab_evtcode:4; /* Fabric Event Code */ 811 u8 port_id:2; /* Port ID */ 812 u8 rsvd2:1; /* Reserved */ 813 u8 port_filter:1; /* Port Filter */ 814 u64 rsvd3:40; /* Reserved */ 815 }; 816 }; 817 }; 818 819 /* FPMON Event Counter */ 820 struct feature_fme_ifpmon_fab_ctr { 821 union { 822 u64 csr; 823 struct { 824 u64 fab_cnt:60; /* Fabric event counter */ 825 /* Fabric event code being reported */ 826 u8 event_code:4; 827 }; 828 }; 829 }; 830 831 /* FPMON Clock Counter */ 832 struct feature_fme_ifpmon_clk_ctr { 833 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */ 834 }; 835 836 enum iperf_vtd_events { 837 IPERF_VTD_AFU_MEM_RD_TRANS, 838 IPERF_VTD_AFU_MEM_WR_TRANS, 839 IPERF_VTD_AFU_DEVTLB_RD_HIT, 840 IPERF_VTD_AFU_DEVTLB_WR_HIT, 841 IPERF_VTD_DEVTLB_4K_FILL, 842 IPERF_VTD_DEVTLB_2M_FILL, 843 IPERF_VTD_DEVTLB_1G_FILL, 844 }; 845 846 /* VT-d control register */ 847 struct feature_fme_ifpmon_vtd_ctl { 848 union { 849 u64 csr; 850 struct { 851 u8 reset_counters:1; /* Reset Counters */ 852 u8 rsvd:7; /* Reserved */ 853 u8 freeze:1; /* Set to 1 frozen counter */ 854 u8 rsvd1:7; /* Reserved */ 855 u8 vtd_evtcode:4; /* VTd and TLB event code */ 856 u64 rsvd2:44; /* Reserved */ 857 }; 858 }; 859 }; 860 861 /* VT-d event counter */ 862 struct feature_fme_ifpmon_vtd_ctr { 863 union { 864 u64 csr; 865 struct { 866 u64 vtd_counter:48; /* VTd event counter */ 867 u16 rsvd:12; /* Reserved */ 868 u8 event_code:4; /* VTd event code */ 869 }; 870 }; 871 }; 872 873 enum iperf_vtd_sip_events { 874 IPERF_VTD_SIP_IOTLB_4K_HIT, 875 IPERF_VTD_SIP_IOTLB_2M_HIT, 876 IPERF_VTD_SIP_IOTLB_1G_HIT, 877 IPERF_VTD_SIP_SLPWC_L3_HIT, 878 IPERF_VTD_SIP_SLPWC_L4_HIT, 879 IPERF_VTD_SIP_RCC_HIT, 880 IPERF_VTD_SIP_IOTLB_4K_MISS, 881 IPERF_VTD_SIP_IOTLB_2M_MISS, 882 IPERF_VTD_SIP_IOTLB_1G_MISS, 883 IPERF_VTD_SIP_SLPWC_L3_MISS, 884 IPERF_VTD_SIP_SLPWC_L4_MISS, 885 IPERF_VTD_SIP_RCC_MISS, 886 }; 887 888 /* VT-d SIP control register */ 889 struct feature_fme_ifpmon_vtd_sip_ctl { 890 union { 891 u64 csr; 892 struct { 893 u8 reset_counters:1; /* Reset Counters */ 894 u8 rsvd:7; /* Reserved */ 895 u8 freeze:1; /* Set to 1 frozen counter */ 896 u8 rsvd1:7; /* Reserved */ 897 u8 vtd_evtcode:4; /* VTd and TLB event code */ 898 u64 rsvd2:44; /* Reserved */ 899 }; 900 }; 901 }; 902 903 /* VT-d SIP event counter */ 904 struct feature_fme_ifpmon_vtd_sip_ctr { 905 union { 906 u64 csr; 907 struct { 908 u64 vtd_counter:48; /* VTd event counter */ 909 u16 rsvd:12; /* Reserved */ 910 u8 event_code:4; /* VTd event code */ 911 }; 912 }; 913 }; 914 915 /* FME IPERF FEATURE */ 916 struct feature_fme_iperf { 917 struct feature_header header; 918 struct feature_fme_ifpmon_ch_ctl ch_ctl; 919 struct feature_fme_ifpmon_ch_ctr ch_ctr0; 920 struct feature_fme_ifpmon_ch_ctr ch_ctr1; 921 struct feature_fme_ifpmon_fab_ctl fab_ctl; 922 struct feature_fme_ifpmon_fab_ctr fab_ctr; 923 struct feature_fme_ifpmon_clk_ctr clk; 924 struct feature_fme_ifpmon_vtd_ctl vtd_ctl; 925 struct feature_fme_ifpmon_vtd_ctr vtd_ctr; 926 struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl; 927 struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr; 928 }; 929 930 enum dperf_fab_events { 931 DPERF_FAB_PCIE0_RD, 932 DPERF_FAB_PCIE0_WR, 933 DPERF_FAB_MMIO_RD = 6, 934 DPERF_FAB_MMIO_WR, 935 }; 936 937 /* FPMON FAB Control */ 938 struct feature_fme_dfpmon_fab_ctl { 939 union { 940 u64 csr; 941 struct { 942 u8 reset_counters:1; /* Reset Counters */ 943 u8 rsvd:7; /* Reserved */ 944 u8 freeze:1; /* Set to 1 frozen counter */ 945 u8 rsvd1:7; /* Reserved */ 946 u8 fab_evtcode:4; /* Fabric Event Code */ 947 u8 port_id:2; /* Port ID */ 948 u8 rsvd2:1; /* Reserved */ 949 u8 port_filter:1; /* Port Filter */ 950 u64 rsvd3:40; /* Reserved */ 951 }; 952 }; 953 }; 954 955 /* FPMON Event Counter */ 956 struct feature_fme_dfpmon_fab_ctr { 957 union { 958 u64 csr; 959 struct { 960 u64 fab_cnt:60; /* Fabric event counter */ 961 /* Fabric event code being reported */ 962 u8 event_code:4; 963 }; 964 }; 965 }; 966 967 /* FPMON Clock Counter */ 968 struct feature_fme_dfpmon_clk_ctr { 969 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */ 970 }; 971 972 /* FME DPERF FEATURE */ 973 struct feature_fme_dperf { 974 struct feature_header header; 975 u64 rsvd[3]; 976 struct feature_fme_dfpmon_fab_ctl fab_ctl; 977 struct feature_fme_dfpmon_fab_ctr fab_ctr; 978 struct feature_fme_dfpmon_clk_ctr clk; 979 }; 980 981 struct feature_fme_error0 { 982 #define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */ 983 union { 984 u64 csr; 985 struct { 986 u8 fabric_err:1; /* Fabric error */ 987 u8 fabfifo_overflow:1; /* Fabric fifo overflow */ 988 u8 reserved2:3; 989 /* AFU PF/VF access mismatch detected */ 990 u8 afu_acc_mode_err:1; 991 u8 reserved6:1; 992 /* PCIE0 CDC Parity Error */ 993 u8 pcie0cdc_parity_err:5; 994 /* PCIE1 CDC Parity Error */ 995 u8 pcie1cdc_parity_err:5; 996 /* CVL CDC Parity Error */ 997 u8 cvlcdc_parity_err:3; 998 u8 fpgaseuerr:1; 999 u64 rsvd:43; /* Reserved */ 1000 }; 1001 }; 1002 }; 1003 1004 /* PCIe0 Error Status register */ 1005 struct feature_fme_pcie0_error { 1006 #define FME_PCIE0_ERROR_MASK 0xFFUL 1007 union { 1008 u64 csr; 1009 struct { 1010 u8 formattype_err:1; /* TLP format/type error */ 1011 u8 MWAddr_err:1; /* TLP MW address error */ 1012 u8 MWAddrLength_err:1; /* TLP MW length error */ 1013 u8 MRAddr_err:1; /* TLP MR address error */ 1014 u8 MRAddrLength_err:1; /* TLP MR length error */ 1015 u8 cpl_tag_err:1; /* TLP CPL tag error */ 1016 u8 cpl_status_err:1; /* TLP CPL status error */ 1017 u8 cpl_timeout_err:1; /* TLP CPL timeout */ 1018 u8 cci_parity_err:1; /* CCI bridge parity error */ 1019 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */ 1020 u64 rsvd:52; /* Reserved */ 1021 u8 vfnumb_err:1; /* Number of error VF */ 1022 u8 funct_type_err:1; /* Virtual (1) or Physical */ 1023 }; 1024 }; 1025 }; 1026 1027 /* PCIe1 Error Status register */ 1028 struct feature_fme_pcie1_error { 1029 #define FME_PCIE1_ERROR_MASK 0xFFUL 1030 union { 1031 u64 csr; 1032 struct { 1033 u8 formattype_err:1; /* TLP format/type error */ 1034 u8 MWAddr_err:1; /* TLP MW address error */ 1035 u8 MWAddrLength_err:1; /* TLP MW length error */ 1036 u8 MRAddr_err:1; /* TLP MR address error */ 1037 u8 MRAddrLength_err:1; /* TLP MR length error */ 1038 u8 cpl_tag_err:1; /* TLP CPL tag error */ 1039 u8 cpl_status_err:1; /* TLP CPL status error */ 1040 u8 cpl_timeout_err:1; /* TLP CPL timeout */ 1041 u8 cci_parity_err:1; /* CCI bridge parity error */ 1042 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */ 1043 u64 rsvd:54; /* Reserved */ 1044 }; 1045 }; 1046 }; 1047 1048 /* FME First Error register */ 1049 struct feature_fme_first_error { 1050 #define FME_FIRST_ERROR_MASK ((1ULL << 60) - 1) 1051 union { 1052 u64 csr; 1053 struct { 1054 /* 1055 * Indicates the Error Register that was 1056 * triggered first 1057 */ 1058 u64 err_reg_status:60; 1059 /* 1060 * Holds 60 LSBs from the Error register that was 1061 * triggered first 1062 */ 1063 u8 errReg_id:4; 1064 }; 1065 }; 1066 }; 1067 1068 /* FME Next Error register */ 1069 struct feature_fme_next_error { 1070 #define FME_NEXT_ERROR_MASK ((1ULL << 60) - 1) 1071 union { 1072 u64 csr; 1073 struct { 1074 /* 1075 * Indicates the Error Register that was 1076 * triggered second 1077 */ 1078 u64 err_reg_status:60; 1079 /* 1080 * Holds 60 LSBs from the Error register that was 1081 * triggered second 1082 */ 1083 u8 errReg_id:4; 1084 }; 1085 }; 1086 }; 1087 1088 /* RAS Non Fatal Error Status register */ 1089 struct feature_fme_ras_nonfaterror { 1090 union { 1091 u64 csr; 1092 struct { 1093 /* thremal threshold AP1 */ 1094 u8 temp_thresh_ap1:1; 1095 /* thremal threshold AP2 */ 1096 u8 temp_thresh_ap2:1; 1097 u8 pcie_error:1; /* pcie Error */ 1098 u8 portfatal_error:1; /* port fatal error */ 1099 u8 proc_hot:1; /* Indicates a ProcHot event */ 1100 /* Indicates an AFU PF/VF access mismatch */ 1101 u8 afu_acc_mode_err:1; 1102 /* Injected nonfata Error */ 1103 u8 injected_nonfata_err:1; 1104 u8 rsvd1:2; 1105 /* Temperature threshold triggered AP6*/ 1106 u8 temp_thresh_AP6:1; 1107 /* Power threshold triggered AP1 */ 1108 u8 power_thresh_AP1:1; 1109 /* Power threshold triggered AP2 */ 1110 u8 power_thresh_AP2:1; 1111 /* Indicates a MBP event */ 1112 u8 mbp_err:1; 1113 u64 rsvd2:51; /* Reserved */ 1114 }; 1115 }; 1116 }; 1117 1118 /* RAS Catastrophic Fatal Error Status register */ 1119 struct feature_fme_ras_catfaterror { 1120 union { 1121 u64 csr; 1122 struct { 1123 /* KTI Link layer error detected */ 1124 u8 ktilink_fatal_err:1; 1125 /* tag-n-cache error detected */ 1126 u8 tagcch_fatal_err:1; 1127 /* CCI error detected */ 1128 u8 cci_fatal_err:1; 1129 /* KTI Protocol error detected */ 1130 u8 ktiprpto_fatal_err:1; 1131 /* Fatal DRAM error detected */ 1132 u8 dram_fatal_err:1; 1133 /* IOMMU detected */ 1134 u8 iommu_fatal_err:1; 1135 /* Fabric Fatal Error */ 1136 u8 fabric_fatal_err:1; 1137 /* PCIe possion Error */ 1138 u8 pcie_poison_err:1; 1139 /* Injected fatal Error */ 1140 u8 inject_fata_err:1; 1141 /* Catastrophic CRC Error */ 1142 u8 crc_catast_err:1; 1143 /* Catastrophic Thermal Error */ 1144 u8 therm_catast_err:1; 1145 /* Injected Catastrophic Error */ 1146 u8 injected_catast_err:1; 1147 /* SEU error on BMC */ 1148 u8 bmc_seu_catast_err:1; 1149 u64 rsvd:51; 1150 }; 1151 }; 1152 }; 1153 1154 /* RAS Error injection register */ 1155 struct feature_fme_ras_error_inj { 1156 #define FME_RAS_ERROR_INJ_MASK 0x7UL 1157 union { 1158 u64 csr; 1159 struct { 1160 u8 catast_error:1; /* Catastrophic error flag */ 1161 u8 fatal_error:1; /* Fatal error flag */ 1162 u8 nonfatal_error:1; /* NonFatal error flag */ 1163 u64 rsvd:61; /* Reserved */ 1164 }; 1165 }; 1166 }; 1167 1168 /* FME error capabilities */ 1169 struct feature_fme_error_capability { 1170 union { 1171 u64 csr; 1172 struct { 1173 u8 support_intr:1; 1174 /* MSI-X vector table entry number */ 1175 u16 intr_vector_num:12; 1176 u64 rsvd:50; /* Reserved */ 1177 u64 seu_support:1; 1178 }; 1179 }; 1180 }; 1181 1182 /* FME ERR FEATURE */ 1183 struct feature_fme_err { 1184 struct feature_header header; 1185 struct feature_fme_error0 fme_err_mask; 1186 struct feature_fme_error0 fme_err; 1187 struct feature_fme_pcie0_error pcie0_err_mask; 1188 struct feature_fme_pcie0_error pcie0_err; 1189 struct feature_fme_pcie1_error pcie1_err_mask; 1190 struct feature_fme_pcie1_error pcie1_err; 1191 struct feature_fme_first_error fme_first_err; 1192 struct feature_fme_next_error fme_next_err; 1193 struct feature_fme_ras_nonfaterror ras_nonfat_mask; 1194 struct feature_fme_ras_nonfaterror ras_nonfaterr; 1195 struct feature_fme_ras_catfaterror ras_catfat_mask; 1196 struct feature_fme_ras_catfaterror ras_catfaterr; 1197 struct feature_fme_ras_error_inj ras_error_inj; 1198 struct feature_fme_error_capability fme_err_capability; 1199 u64 seu_emr_l; 1200 u64 seu_emr_h; 1201 }; 1202 1203 /* FME Partial Reconfiguration Control */ 1204 struct feature_fme_pr_ctl { 1205 union { 1206 u64 csr; 1207 struct { 1208 u8 pr_reset:1; /* Reset PR Engine */ 1209 u8 rsvd3:3; /* Reserved */ 1210 u8 pr_reset_ack:1; /* Reset PR Engine Ack */ 1211 u8 rsvd4:3; /* Reserved */ 1212 u8 pr_regionid:2; /* PR Region ID */ 1213 u8 rsvd1:2; /* Reserved */ 1214 u8 pr_start_req:1; /* PR Start Request */ 1215 u8 pr_push_complete:1; /* PR Data push complete */ 1216 u8 pr_kind:1; /* PR Data push complete */ 1217 u32 rsvd:17; /* Reserved */ 1218 u32 config_data; /* Config data TBD */ 1219 }; 1220 }; 1221 }; 1222 1223 /* FME Partial Reconfiguration Status */ 1224 struct feature_fme_pr_status { 1225 union { 1226 u64 csr; 1227 struct { 1228 u16 pr_credit:9; /* PR Credits */ 1229 u8 rsvd2:7; /* Reserved */ 1230 u8 pr_status:1; /* PR status */ 1231 u8 rsvd:3; /* Reserved */ 1232 /* Altra PR Controller Block status */ 1233 u8 pr_controller_status:3; 1234 u8 rsvd1:1; /* Reserved */ 1235 u8 pr_host_status:4; /* PR Host status */ 1236 u8 rsvd3:4; /* Reserved */ 1237 /* Security Block Status fields (TBD) */ 1238 u32 security_bstatus; 1239 }; 1240 }; 1241 }; 1242 1243 /* FME Partial Reconfiguration Data */ 1244 struct feature_fme_pr_data { 1245 union { 1246 u64 csr; /* PR data from the raw-binary file */ 1247 struct { 1248 /* PR data from the raw-binary file */ 1249 u32 pr_data_raw; 1250 u32 rsvd; 1251 }; 1252 }; 1253 }; 1254 1255 /* FME PR Public Key */ 1256 struct feature_fme_pr_key { 1257 u64 key; /* FME PR Public Hash */ 1258 }; 1259 1260 /* FME PR FEATURE */ 1261 struct feature_fme_pr { 1262 struct feature_header header; 1263 /*Partial Reconfiguration control */ 1264 struct feature_fme_pr_ctl ccip_fme_pr_control; 1265 1266 /* Partial Reconfiguration Status */ 1267 struct feature_fme_pr_status ccip_fme_pr_status; 1268 1269 /* Partial Reconfiguration data */ 1270 struct feature_fme_pr_data ccip_fme_pr_data; 1271 1272 /* Partial Reconfiguration data */ 1273 u64 ccip_fme_pr_err; 1274 1275 u64 rsvd1[3]; 1276 1277 /* Partial Reconfiguration data registers */ 1278 u64 fme_pr_data1; 1279 u64 fme_pr_data2; 1280 u64 fme_pr_data3; 1281 u64 fme_pr_data4; 1282 u64 fme_pr_data5; 1283 u64 fme_pr_data6; 1284 u64 fme_pr_data7; 1285 u64 fme_pr_data8; 1286 1287 u64 rsvd2[5]; 1288 1289 /* PR Interface ID */ 1290 u64 fme_pr_intfc_id_l; 1291 u64 fme_pr_intfc_id_h; 1292 1293 /* MSIX filed to be Added */ 1294 }; 1295 1296 /* FME HSSI Control */ 1297 struct feature_fme_hssi_eth_ctrl { 1298 union { 1299 u64 csr; 1300 struct { 1301 u32 data:32; /* HSSI data */ 1302 u16 address:16; /* HSSI address */ 1303 /* 1304 * HSSI comamnd 1305 * 0x0 - No request 1306 * 0x08 - SW register RD request 1307 * 0x10 - SW register WR request 1308 * 0x40 - Auxiliar bus RD request 1309 * 0x80 - Auxiliar bus WR request 1310 */ 1311 u16 cmd:16; 1312 }; 1313 }; 1314 }; 1315 1316 /* FME HSSI Status */ 1317 struct feature_fme_hssi_eth_stat { 1318 union { 1319 u64 csr; 1320 struct { 1321 u32 data:32; /* HSSI data */ 1322 u8 acknowledge:1; /* HSSI acknowledge */ 1323 u8 spare:1; /* HSSI spare */ 1324 u32 rsvd:30; /* Reserved */ 1325 }; 1326 }; 1327 }; 1328 1329 /* FME HSSI FEATURE */ 1330 struct feature_fme_hssi { 1331 struct feature_header header; 1332 struct feature_fme_hssi_eth_ctrl hssi_control; 1333 struct feature_fme_hssi_eth_stat hssi_status; 1334 }; 1335 1336 #define PORT_ERR_MASK 0xfff0703ff001f 1337 struct feature_port_err_key { 1338 union { 1339 u64 csr; 1340 struct { 1341 /* Tx Channel0: Overflow */ 1342 u8 tx_ch0_overflow:1; 1343 /* Tx Channel0: Invalid request encoding */ 1344 u8 tx_ch0_invaldreq :1; 1345 /* Tx Channel0: Request with cl_len=3 not supported */ 1346 u8 tx_ch0_cl_len3:1; 1347 /* Tx Channel0: Request with cl_len=2 not aligned 2CL */ 1348 u8 tx_ch0_cl_len2:1; 1349 /* Tx Channel0: Request with cl_len=4 not aligned 4CL */ 1350 u8 tx_ch0_cl_len4:1; 1351 1352 u16 rsvd1:4; /* Reserved */ 1353 1354 /* AFU MMIO RD received while PORT is in reset */ 1355 u8 mmio_rd_whilerst:1; 1356 /* AFU MMIO WR received while PORT is in reset */ 1357 u8 mmio_wr_whilerst:1; 1358 1359 u16 rsvd2:5; /* Reserved */ 1360 1361 /* Tx Channel1: Overflow */ 1362 u8 tx_ch1_overflow:1; 1363 /* Tx Channel1: Invalid request encoding */ 1364 u8 tx_ch1_invaldreq:1; 1365 /* Tx Channel1: Request with cl_len=3 not supported */ 1366 u8 tx_ch1_cl_len3:1; 1367 /* Tx Channel1: Request with cl_len=2 not aligned 2CL */ 1368 u8 tx_ch1_cl_len2:1; 1369 /* Tx Channel1: Request with cl_len=4 not aligned 4CL */ 1370 u8 tx_ch1_cl_len4:1; 1371 1372 /* Tx Channel1: Insufficient data payload */ 1373 u8 tx_ch1_insuff_data:1; 1374 /* Tx Channel1: Data payload overrun */ 1375 u8 tx_ch1_data_overrun:1; 1376 /* Tx Channel1 : Incorrect address */ 1377 u8 tx_ch1_incorr_addr:1; 1378 /* Tx Channel1 : NON-Zero SOP Detected */ 1379 u8 tx_ch1_nzsop:1; 1380 /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */ 1381 u8 tx_ch1_illegal_vcsel:1; 1382 1383 u8 rsvd3:6; /* Reserved */ 1384 1385 /* MMIO Read Timeout in AFU */ 1386 u8 mmioread_timeout:1; 1387 1388 /* Tx Channel2: FIFO Overflow */ 1389 u8 tx_ch2_fifo_overflow:1; 1390 1391 /* MMIO read is not matching pending request */ 1392 u8 unexp_mmio_resp:1; 1393 1394 u8 rsvd4:5; /* Reserved */ 1395 1396 /* Number of pending Requests: counter overflow */ 1397 u8 tx_req_counter_overflow:1; 1398 /* Req with Address violating SMM Range */ 1399 u8 llpr_smrr_err:1; 1400 /* Req with Address violating second SMM Range */ 1401 u8 llpr_smrr2_err:1; 1402 /* Req with Address violating ME Stolen message */ 1403 u8 llpr_mesg_err:1; 1404 /* Req with Address violating Generic Protected Range */ 1405 u8 genprot_range_err:1; 1406 /* Req with Address violating Legacy Range low */ 1407 u8 legrange_low_err:1; 1408 /* Req with Address violating Legacy Range High */ 1409 u8 legrange_high_err:1; 1410 /* Req with Address violating VGA memory range */ 1411 u8 vgmem_range_err:1; 1412 u8 page_fault_err:1; /* Page fault */ 1413 u8 pmr_err:1; /* PMR Error */ 1414 u8 ap6_event:1; /* AP6 event */ 1415 /* VF FLR detected on Port with PF access control */ 1416 u8 vfflr_access_err:1; 1417 u16 rsvd5:12; /* Reserved */ 1418 }; 1419 }; 1420 }; 1421 1422 /* Port first error register, not contain all error bits in error register. */ 1423 struct feature_port_first_err_key { 1424 union { 1425 u64 csr; 1426 struct { 1427 u8 tx_ch0_overflow:1; 1428 u8 tx_ch0_invaldreq :1; 1429 u8 tx_ch0_cl_len3:1; 1430 u8 tx_ch0_cl_len2:1; 1431 u8 tx_ch0_cl_len4:1; 1432 u8 rsvd1:4; /* Reserved */ 1433 u8 mmio_rd_whilerst:1; 1434 u8 mmio_wr_whilerst:1; 1435 u8 rsvd2:5; /* Reserved */ 1436 u8 tx_ch1_overflow:1; 1437 u8 tx_ch1_invaldreq:1; 1438 u8 tx_ch1_cl_len3:1; 1439 u8 tx_ch1_cl_len2:1; 1440 u8 tx_ch1_cl_len4:1; 1441 u8 tx_ch1_insuff_data:1; 1442 u8 tx_ch1_data_overrun:1; 1443 u8 tx_ch1_incorr_addr:1; 1444 u8 tx_ch1_nzsop:1; 1445 u8 tx_ch1_illegal_vcsel:1; 1446 u8 rsvd3:6; /* Reserved */ 1447 u8 mmioread_timeout:1; 1448 u8 tx_ch2_fifo_overflow:1; 1449 u8 rsvd4:6; /* Reserved */ 1450 u8 tx_req_counter_overflow:1; 1451 u32 rsvd5:23; /* Reserved */ 1452 }; 1453 }; 1454 }; 1455 1456 /* Port malformed Req0 */ 1457 struct feature_port_malformed_req0 { 1458 u64 header_lsb; 1459 }; 1460 1461 /* Port malformed Req1 */ 1462 struct feature_port_malformed_req1 { 1463 u64 header_msb; 1464 }; 1465 1466 /* Port debug register */ 1467 struct feature_port_debug { 1468 u64 port_debug; 1469 }; 1470 1471 /* Port error capabilities */ 1472 struct feature_port_err_capability { 1473 union { 1474 u64 csr; 1475 struct { 1476 u8 support_intr:1; 1477 /* MSI-X vector table entry number */ 1478 u16 intr_vector_num:12; 1479 u64 rsvd:51; /* Reserved */ 1480 }; 1481 }; 1482 }; 1483 1484 /* PORT FEATURE ERROR */ 1485 struct feature_port_error { 1486 struct feature_header header; 1487 struct feature_port_err_key error_mask; 1488 struct feature_port_err_key port_error; 1489 struct feature_port_first_err_key port_first_error; 1490 struct feature_port_malformed_req0 malreq0; 1491 struct feature_port_malformed_req1 malreq1; 1492 struct feature_port_debug port_debug; 1493 struct feature_port_err_capability error_capability; 1494 }; 1495 1496 /* Port UMSG Capability */ 1497 struct feature_port_umsg_cap { 1498 union { 1499 u64 csr; 1500 struct { 1501 /* Number of umsg allocated to this port */ 1502 u8 umsg_allocated; 1503 /* Enable / Disable UMsg engine for this port */ 1504 u8 umsg_enable:1; 1505 /* Usmg initialization status */ 1506 u8 umsg_init_complete:1; 1507 /* IOMMU can not translate the umsg base address */ 1508 u8 umsg_trans_error:1; 1509 u64 rsvd:53; /* Reserved */ 1510 }; 1511 }; 1512 }; 1513 1514 /* Port UMSG base address */ 1515 struct feature_port_umsg_baseaddr { 1516 union { 1517 u64 csr; 1518 struct { 1519 u64 base_addr:48; /* 48 bit physical address */ 1520 u16 rsvd; /* Reserved */ 1521 }; 1522 }; 1523 }; 1524 1525 struct feature_port_umsg_mode { 1526 union { 1527 u64 csr; 1528 struct { 1529 u32 umsg_hint_enable; /* UMSG hint enable/disable */ 1530 u32 rsvd; /* Reserved */ 1531 }; 1532 }; 1533 }; 1534 1535 /* PORT FEATURE UMSG */ 1536 struct feature_port_umsg { 1537 struct feature_header header; 1538 struct feature_port_umsg_cap capability; 1539 struct feature_port_umsg_baseaddr baseaddr; 1540 struct feature_port_umsg_mode mode; 1541 }; 1542 1543 #define UMSG_EN_POLL_INVL 10 /* us */ 1544 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */ 1545 1546 /* Port UINT Capability */ 1547 struct feature_port_uint_cap { 1548 union { 1549 u64 csr; 1550 struct { 1551 u16 intr_num:12; /* Supported interrupts num */ 1552 /* First MSI-X vector table entry number */ 1553 u16 first_vec_num:12; 1554 u64 rsvd:40; 1555 }; 1556 }; 1557 }; 1558 1559 /* PORT FEATURE UINT */ 1560 struct feature_port_uint { 1561 struct feature_header header; 1562 struct feature_port_uint_cap capability; 1563 }; 1564 1565 /* STP region supports mmap operation, so use page aligned size. */ 1566 #define PORT_FEATURE_STP_REGION_SIZE \ 1567 IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp)) 1568 1569 /* Port STP status register (for debug only)*/ 1570 struct feature_port_stp_status { 1571 union { 1572 u64 csr; 1573 struct { 1574 /* SLD Hub end-point read/write timeout */ 1575 u8 sld_ep_timeout:1; 1576 /* Remote STP in reset/disable */ 1577 u8 rstp_disabled:1; 1578 u8 unsupported_read:1; 1579 /* MMIO timeout detected and faked with a response */ 1580 u8 mmio_timeout:1; 1581 u8 txfifo_count:4; 1582 u8 rxfifo_count:4; 1583 u8 txfifo_overflow:1; 1584 u8 txfifo_underflow:1; 1585 u8 rxfifo_overflow:1; 1586 u8 rxfifo_underflow:1; 1587 /* Number of MMIO write requests */ 1588 u16 write_requests; 1589 /* Number of MMIO read requests */ 1590 u16 read_requests; 1591 /* Number of MMIO read responses */ 1592 u16 read_responses; 1593 }; 1594 }; 1595 }; 1596 1597 /* 1598 * PORT FEATURE STP 1599 * Most registers in STP region are not touched by driver, but mmapped to user 1600 * space. So they are not defined in below data structure, as its actual size 1601 * is 0x18c per spec. 1602 */ 1603 struct feature_port_stp { 1604 struct feature_header header; 1605 struct feature_port_stp_status stp_status; 1606 }; 1607 1608 /** 1609 * enum fpga_pr_states - fpga PR states 1610 * @FPGA_PR_STATE_UNKNOWN: can't determine state 1611 * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming 1612 * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 1613 * @FPGA_PR_STATE_WRITE: writing image to FPGA 1614 * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA 1615 * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps 1616 * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 1617 * @FPGA_PR_STATE_OPERATING: FPGA PR done 1618 */ 1619 enum fpga_pr_states { 1620 /* canot determine state states */ 1621 FPGA_PR_STATE_UNKNOWN, 1622 1623 /* write sequence: init, write, complete */ 1624 FPGA_PR_STATE_WRITE_INIT, 1625 FPGA_PR_STATE_WRITE_INIT_ERR, 1626 FPGA_PR_STATE_WRITE, 1627 FPGA_PR_STATE_WRITE_ERR, 1628 FPGA_PR_STATE_WRITE_COMPLETE, 1629 FPGA_PR_STATE_WRITE_COMPLETE_ERR, 1630 1631 /* FPGA PR done */ 1632 FPGA_PR_STATE_DONE, 1633 }; 1634 1635 /* 1636 * FPGA Manager flags 1637 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 1638 */ 1639 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 1640 1641 /** 1642 * struct fpga_pr_info - specific information to a FPGA PR 1643 * @flags: boolean flags as defined above 1644 * @pr_err: PR error code 1645 * @state: fpga manager state 1646 * @port_id: port id 1647 */ 1648 struct fpga_pr_info { 1649 u32 flags; 1650 u64 pr_err; 1651 enum fpga_pr_states state; 1652 int port_id; 1653 }; 1654 1655 #define DEFINE_FPGA_PR_ERR_MSG(_name_) \ 1656 static const char * const _name_[] = { \ 1657 "PR operation error detected", \ 1658 "PR CRC error detected", \ 1659 "PR incompatiable bitstream error detected", \ 1660 "PR IP protocol error detected", \ 1661 "PR FIFO overflow error detected", \ 1662 "PR timeout error detected", \ 1663 "PR secure load error detected", \ 1664 } 1665 1666 #define RST_POLL_INVL 10 /* us */ 1667 #define RST_POLL_TIMEOUT 1000 /* us */ 1668 1669 #define PR_WAIT_TIMEOUT 15000000 1670 1671 #define PR_HOST_STATUS_IDLE 0 1672 #define PR_MAX_ERR_NUM 7 1673 1674 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg); 1675 1676 /* 1677 * green bitstream header must be byte-packed to match the 1678 * real file format. 1679 */ 1680 struct bts_header { 1681 u64 guid_h; 1682 u64 guid_l; 1683 u32 metadata_len; 1684 }; 1685 1686 #define GBS_GUID_H 0x414750466e6f6558 1687 #define GBS_GUID_L 0x31303076534247b7 1688 #define is_valid_bts(bts_hdr) \ 1689 (((bts_hdr)->guid_h == GBS_GUID_H) && \ 1690 ((bts_hdr)->guid_l == GBS_GUID_L)) 1691 1692 #define check_support(n) (n == 1 ? "support" : "no") 1693 1694 enum board_interface { 1695 VC_8_10G = 0, 1696 VC_4_25G = 1, 1697 VC_2_1_25 = 2, 1698 VC_4_25G_2_25G = 3, 1699 VC_2_2_25G = 4, 1700 }; 1701 1702 enum fim_type { 1703 BASE_ADP = 0, 1704 BASE_FDK, 1705 BASE_X16_ADP, 1706 BASE_X16_FDK, 1707 FIMA_10G_ADP, 1708 FIMA_25G_ADP, 1709 FIMA_100G_ADP, 1710 FIMB_ADP, 1711 FIMC_ADP 1712 }; 1713 1714 enum hssi_id { 1715 NO_HSSI = 0, 1716 PCIE_RP, 1717 ETHER_NET 1718 }; 1719 1720 enum pac_major { 1721 VISTA_CREEK = 0, 1722 RUSH_CREEK = 1, 1723 DARBY_CREEK = 2, 1724 LIGHTNING_CREEK = 3, 1725 ARROW_CREEK = 5, 1726 }; 1727 1728 enum pac_minor { 1729 DCP_1_0 = 0, 1730 DCP_1_1 = 1, 1731 DCP_1_2 = 2, 1732 }; 1733 1734 struct opae_board_info { 1735 enum pac_major major; 1736 enum pac_minor minor; 1737 1738 u32 boot_page; 1739 u32 max10_version; 1740 u32 nios_fw_version; 1741 1742 union { 1743 struct { /* N3000 specific */ 1744 enum board_interface type; 1745 u8 fvl_bypass; 1746 u8 mac_lightweight; 1747 u8 disaggregate; 1748 u8 lightweight; 1749 u8 seu; 1750 u8 ptp; 1751 u32 nums_of_retimer; 1752 u32 ports_per_retimer; 1753 u32 nums_of_fvl; 1754 u32 ports_per_fvl; 1755 }; 1756 struct { 1757 enum fim_type n6000_fim_type; 1758 enum hssi_id n6000_hssi_id; 1759 }; 1760 }; 1761 }; 1762 1763 #pragma pack(pop) 1764 #endif /* _BASE_IFPGA_DEFINES_H_ */ 1765