1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #ifndef _THUNDERX_NICVF_HW_DEFS_H 6 #define _THUNDERX_NICVF_HW_DEFS_H 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include "nicvf_plat.h" 12 13 /* Virtual function register offsets */ 14 15 #define NIC_VF_CFG (0x000020) 16 #define NIC_VF_PF_MAILBOX_0_1 (0x000130) 17 #define NIC_VF_INT (0x000200) 18 #define NIC_VF_INT_W1S (0x000220) 19 #define NIC_VF_ENA_W1C (0x000240) 20 #define NIC_VF_ENA_W1S (0x000260) 21 22 #define NIC_VNIC_RSS_CFG (0x0020E0) 23 #define NIC_VNIC_RSS_KEY_0_4 (0x002200) 24 #define NIC_VNIC_TX_STAT_0_4 (0x004000) 25 #define NIC_VNIC_RX_STAT_0_13 (0x004100) 26 #define NIC_VNIC_RQ_GEN_CFG (0x010010) 27 28 #define NIC_QSET_CQ_0_7_CFG (0x010400) 29 #define NIC_QSET_CQ_0_7_CFG2 (0x010408) 30 #define NIC_QSET_CQ_0_7_THRESH (0x010410) 31 #define NIC_QSET_CQ_0_7_BASE (0x010420) 32 #define NIC_QSET_CQ_0_7_HEAD (0x010428) 33 #define NIC_QSET_CQ_0_7_TAIL (0x010430) 34 #define NIC_QSET_CQ_0_7_DOOR (0x010438) 35 #define NIC_QSET_CQ_0_7_STATUS (0x010440) 36 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448) 37 #define NIC_QSET_CQ_0_7_DEBUG (0x010450) 38 39 #define NIC_QSET_RQ_0_7_CFG (0x010600) 40 #define NIC_QSET_RQ_0_7_STATUS0 (0x010700) 41 #define NIC_QSET_RQ_0_7_STATUS1 (0x010708) 42 43 #define NIC_QSET_SQ_0_7_CFG (0x010800) 44 #define NIC_QSET_SQ_0_7_THRESH (0x010810) 45 #define NIC_QSET_SQ_0_7_BASE (0x010820) 46 #define NIC_QSET_SQ_0_7_HEAD (0x010828) 47 #define NIC_QSET_SQ_0_7_TAIL (0x010830) 48 #define NIC_QSET_SQ_0_7_DOOR (0x010838) 49 #define NIC_QSET_SQ_0_7_STATUS (0x010840) 50 #define NIC_QSET_SQ_0_7_DEBUG (0x010848) 51 #define NIC_QSET_SQ_0_7_STATUS0 (0x010900) 52 #define NIC_QSET_SQ_0_7_STATUS1 (0x010908) 53 54 #define NIC_QSET_RBDR_0_1_CFG (0x010C00) 55 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10) 56 #define NIC_QSET_RBDR_0_1_BASE (0x010C20) 57 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28) 58 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30) 59 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38) 60 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40) 61 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48) 62 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS (0x010C50) 63 64 /* vNIC HW Constants */ 65 66 #define NIC_Q_NUM_SHIFT 18 67 68 #define MAX_QUEUE_SET 128 69 #define MAX_RCV_QUEUES_PER_QS 8 70 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2 71 #define MAX_SND_QUEUES_PER_QS 8 72 #define MAX_CMP_QUEUES_PER_QS 8 73 74 #define NICVF_INTR_CQ_SHIFT 0 75 #define NICVF_INTR_SQ_SHIFT 8 76 #define NICVF_INTR_RBDR_SHIFT 16 77 #define NICVF_INTR_PKT_DROP_SHIFT 20 78 #define NICVF_INTR_TCP_TIMER_SHIFT 21 79 #define NICVF_INTR_MBOX_SHIFT 22 80 #define NICVF_INTR_QS_ERR_SHIFT 23 81 82 #define NICVF_QS_RQ_DIS_APAD_SHIFT 22 83 84 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 85 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 86 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 87 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT) 88 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT) 89 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT) 90 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT) 91 #define NICVF_INTR_ALL_MASK (0x7FFFFF) 92 93 #define NICVF_CQ_WR_FULL (1ULL << 26) 94 #define NICVF_CQ_WR_DISABLE (1ULL << 25) 95 #define NICVF_CQ_WR_FAULT (1ULL << 24) 96 #define NICVF_CQ_ERR_MASK (NICVF_CQ_WR_FULL |\ 97 NICVF_CQ_WR_DISABLE |\ 98 NICVF_CQ_WR_FAULT) 99 #define NICVF_CQ_CQE_COUNT_MASK (0xFFFF) 100 101 #define NICVF_SQ_ERR_STOPPED (1ULL << 21) 102 #define NICVF_SQ_ERR_SEND (1ULL << 20) 103 #define NICVF_SQ_ERR_DPE (1ULL << 19) 104 #define NICVF_SQ_ERR_MASK (NICVF_SQ_ERR_STOPPED |\ 105 NICVF_SQ_ERR_SEND |\ 106 NICVF_SQ_ERR_DPE) 107 #define NICVF_SQ_STATUS_STOPPED_BIT (21) 108 109 #define NICVF_RBDR_FIFO_STATE_SHIFT (62) 110 #define NICVF_RBDR_FIFO_STATE_MASK (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT) 111 #define NICVF_RBDR_COUNT_MASK (0x7FFFF) 112 113 /* Queue reset */ 114 #define NICVF_CQ_RESET (1ULL << 41) 115 #define NICVF_SQ_RESET (1ULL << 17) 116 #define NICVF_RBDR_RESET (1ULL << 43) 117 118 /* RSS constants */ 119 #define NIC_MAX_RSS_HASH_BITS (8) 120 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 121 #define RSS_HASH_KEY_SIZE (5) /* 320 bit key */ 122 #define RSS_HASH_KEY_BYTE_SIZE (40) /* 320 bit key */ 123 124 #define RSS_L2_EXTENDED_HASH_ENA (1 << 0) 125 #define RSS_IP_ENA (1 << 1) 126 #define RSS_TCP_ENA (1 << 2) 127 #define RSS_TCP_SYN_ENA (1 << 3) 128 #define RSS_UDP_ENA (1 << 4) 129 #define RSS_L4_EXTENDED_ENA (1 << 5) 130 #define RSS_L3_BI_DIRECTION_ENA (1 << 7) 131 #define RSS_L4_BI_DIRECTION_ENA (1 << 8) 132 #define RSS_TUN_VXLAN_ENA (1 << 9) 133 #define RSS_TUN_GENEVE_ENA (1 << 10) 134 #define RSS_TUN_NVGRE_ENA (1 << 11) 135 136 #define RBDR_QUEUE_SZ_8K (8 * 1024) 137 #define RBDR_QUEUE_SZ_16K (16 * 1024) 138 #define RBDR_QUEUE_SZ_32K (32 * 1024) 139 #define RBDR_QUEUE_SZ_64K (64 * 1024) 140 #define RBDR_QUEUE_SZ_128K (128 * 1024) 141 #define RBDR_QUEUE_SZ_256K (256 * 1024) 142 #define RBDR_QUEUE_SZ_512K (512 * 1024) 143 #define RBDR_QUEUE_SZ_MAX RBDR_QUEUE_SZ_512K 144 145 #define RBDR_SIZE_SHIFT (13) /* 8k */ 146 147 #define SND_QUEUE_SZ_1K (1 * 1024) 148 #define SND_QUEUE_SZ_2K (2 * 1024) 149 #define SND_QUEUE_SZ_4K (4 * 1024) 150 #define SND_QUEUE_SZ_8K (8 * 1024) 151 #define SND_QUEUE_SZ_16K (16 * 1024) 152 #define SND_QUEUE_SZ_32K (32 * 1024) 153 #define SND_QUEUE_SZ_64K (64 * 1024) 154 #define SND_QUEUE_SZ_MAX SND_QUEUE_SZ_64K 155 156 #define SND_QSIZE_SHIFT (10) /* 1k */ 157 158 #define CMP_QUEUE_SZ_1K (1 * 1024) 159 #define CMP_QUEUE_SZ_2K (2 * 1024) 160 #define CMP_QUEUE_SZ_4K (4 * 1024) 161 #define CMP_QUEUE_SZ_8K (8 * 1024) 162 #define CMP_QUEUE_SZ_16K (16 * 1024) 163 #define CMP_QUEUE_SZ_32K (32 * 1024) 164 #define CMP_QUEUE_SZ_64K (64 * 1024) 165 #define CMP_QUEUE_SZ_MAX CMP_QUEUE_SZ_64K 166 167 #define CMP_QSIZE_SHIFT (10) /* 1k */ 168 169 #define NICVF_QSIZE_MIN_VAL (0) 170 #define NICVF_QSIZE_MAX_VAL (6) 171 172 /* Min/Max packet size */ 173 #define NIC_HW_MIN_FRS (64) 174 /* ETH_HLEN+ETH_FCS_LEN+2*VLAN_HLEN */ 175 #define NIC_HW_L2_OVERHEAD (26) 176 #define NIC_HW_MAX_MTU (9190) 177 #define NIC_HW_MAX_FRS (NIC_HW_MAX_MTU + NIC_HW_L2_OVERHEAD) 178 #define NIC_HW_MAX_SEGS (12) 179 #define NIC_HW_L2_MAX_LEN (RTE_ETHER_MTU + NIC_HW_L2_OVERHEAD) 180 181 /* Descriptor alignments */ 182 #define NICVF_RBDR_BASE_ALIGN_BYTES (128) /* 7 bits */ 183 #define NICVF_CQ_BASE_ALIGN_BYTES (512) /* 9 bits */ 184 #define NICVF_SQ_BASE_ALIGN_BYTES (128) /* 7 bits */ 185 186 #define NICVF_CQE_RBPTR_WORD (6) 187 #define NICVF_CQE_RX2_RBPTR_WORD (7) 188 189 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s) 190 #define assert_primary(nic) assert((nic)->sqs_mode == 0) 191 192 typedef uint64_t nicvf_iova_addr_t; 193 194 /* vNIC HW Enumerations */ 195 196 enum nic_send_ld_type_e { 197 NIC_SEND_LD_TYPE_E_LDD, 198 NIC_SEND_LD_TYPE_E_LDT, 199 NIC_SEND_LD_TYPE_E_LDWB, 200 NIC_SEND_LD_TYPE_E_ENUM_LAST, 201 }; 202 203 enum ether_type_algorithm { 204 ETYPE_ALG_NONE, 205 ETYPE_ALG_SKIP, 206 ETYPE_ALG_ENDPARSE, 207 ETYPE_ALG_VLAN, 208 ETYPE_ALG_VLAN_STRIP, 209 }; 210 211 enum layer3_type { 212 L3TYPE_NONE, 213 L3TYPE_GRH, 214 L3TYPE_IPV4 = 0x4, 215 L3TYPE_IPV4_OPTIONS = 0x5, 216 L3TYPE_IPV6 = 0x6, 217 L3TYPE_IPV6_OPTIONS = 0x7, 218 L3TYPE_ET_STOP = 0xD, 219 L3TYPE_OTHER = 0xE, 220 }; 221 222 #define NICVF_L3TYPE_OPTIONS_MASK ((uint8_t)1) 223 #define NICVF_L3TYPE_IPVX_MASK ((uint8_t)0x06) 224 225 enum layer4_type { 226 L4TYPE_NONE, 227 L4TYPE_IPSEC_ESP, 228 L4TYPE_IPFRAG, 229 L4TYPE_IPCOMP, 230 L4TYPE_TCP, 231 L4TYPE_UDP, 232 L4TYPE_SCTP, 233 L4TYPE_GRE, 234 L4TYPE_ROCE_BTH, 235 L4TYPE_OTHER = 0xE, 236 }; 237 238 /* CPI and RSSI configuration */ 239 enum cpi_algorithm_type { 240 CPI_ALG_NONE, 241 CPI_ALG_VLAN, 242 CPI_ALG_VLAN16, 243 CPI_ALG_DIFF, 244 }; 245 246 enum rss_algorithm_type { 247 RSS_ALG_NONE, 248 RSS_ALG_PORT, 249 RSS_ALG_IP, 250 RSS_ALG_TCP_IP, 251 RSS_ALG_UDP_IP, 252 RSS_ALG_SCTP_IP, 253 RSS_ALG_GRE_IP, 254 RSS_ALG_ROCE, 255 }; 256 257 enum rss_hash_cfg { 258 RSS_HASH_L2ETC, 259 RSS_HASH_IP, 260 RSS_HASH_TCP, 261 RSS_HASH_TCP_SYN_DIS, 262 RSS_HASH_UDP, 263 RSS_HASH_L4ETC, 264 RSS_HASH_ROCE, 265 RSS_L3_BIDI, 266 RSS_L4_BIDI, 267 }; 268 269 /* Completion queue entry types */ 270 enum cqe_type { 271 CQE_TYPE_INVALID, 272 CQE_TYPE_RX = 0x2, 273 CQE_TYPE_RX_SPLIT = 0x3, 274 CQE_TYPE_RX_TCP = 0x4, 275 CQE_TYPE_SEND = 0x8, 276 CQE_TYPE_SEND_PTP = 0x9, 277 }; 278 279 enum cqe_rx_tcp_status { 280 CQE_RX_STATUS_VALID_TCP_CNXT, 281 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F, 282 }; 283 284 enum cqe_send_status { 285 CQE_SEND_STATUS_GOOD, 286 CQE_SEND_STATUS_DESC_FAULT = 0x01, 287 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11, 288 CQE_SEND_STATUS_SUBDESC_ERR = 0x12, 289 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80, 290 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81, 291 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82, 292 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83, 293 CQE_SEND_STATUS_LOCK_VIOL = 0x84, 294 CQE_SEND_STATUS_LOCK_UFLOW = 0x85, 295 CQE_SEND_STATUS_DATA_FAULT = 0x86, 296 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87, 297 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88, 298 CQE_SEND_STATUS_MEM_FAULT = 0x89, 299 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A, 300 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B, 301 }; 302 303 enum cqe_rx_tcp_end_reason { 304 CQE_RX_TCP_END_FIN_FLAG_DET, 305 CQE_RX_TCP_END_INVALID_FLAG, 306 CQE_RX_TCP_END_TIMEOUT, 307 CQE_RX_TCP_END_OUT_OF_SEQ, 308 CQE_RX_TCP_END_PKT_ERR, 309 CQE_RX_TCP_END_QS_DISABLED = 0x0F, 310 }; 311 312 /* Packet protocol level error enumeration */ 313 enum cqe_rx_err_level { 314 CQE_RX_ERRLVL_RE, 315 CQE_RX_ERRLVL_L2, 316 CQE_RX_ERRLVL_L3, 317 CQE_RX_ERRLVL_L4, 318 }; 319 320 /* Packet protocol level error type enumeration */ 321 enum cqe_rx_err_opcode { 322 CQE_RX_ERR_RE_NONE, 323 CQE_RX_ERR_RE_PARTIAL, 324 CQE_RX_ERR_RE_JABBER, 325 CQE_RX_ERR_RE_FCS = 0x7, 326 CQE_RX_ERR_RE_TERMINATE = 0x9, 327 CQE_RX_ERR_RE_RX_CTL = 0xb, 328 CQE_RX_ERR_PREL2_ERR = 0x1f, 329 CQE_RX_ERR_L2_FRAGMENT = 0x20, 330 CQE_RX_ERR_L2_OVERRUN = 0x21, 331 CQE_RX_ERR_L2_PFCS = 0x22, 332 CQE_RX_ERR_L2_PUNY = 0x23, 333 CQE_RX_ERR_L2_MAL = 0x24, 334 CQE_RX_ERR_L2_OVERSIZE = 0x25, 335 CQE_RX_ERR_L2_UNDERSIZE = 0x26, 336 CQE_RX_ERR_L2_LENMISM = 0x27, 337 CQE_RX_ERR_L2_PCLP = 0x28, 338 CQE_RX_ERR_IP_NOT = 0x41, 339 CQE_RX_ERR_IP_CHK = 0x42, 340 CQE_RX_ERR_IP_MAL = 0x43, 341 CQE_RX_ERR_IP_MALD = 0x44, 342 CQE_RX_ERR_IP_HOP = 0x45, 343 CQE_RX_ERR_L3_ICRC = 0x46, 344 CQE_RX_ERR_L3_PCLP = 0x47, 345 CQE_RX_ERR_L4_MAL = 0x61, 346 CQE_RX_ERR_L4_CHK = 0x62, 347 CQE_RX_ERR_UDP_LEN = 0x63, 348 CQE_RX_ERR_L4_PORT = 0x64, 349 CQE_RX_ERR_TCP_FLAG = 0x65, 350 CQE_RX_ERR_TCP_OFFSET = 0x66, 351 CQE_RX_ERR_L4_PCLP = 0x67, 352 CQE_RX_ERR_RBDR_TRUNC = 0x70, 353 }; 354 355 enum send_l4_csum_type { 356 SEND_L4_CSUM_DISABLE, 357 SEND_L4_CSUM_UDP, 358 SEND_L4_CSUM_TCP, 359 }; 360 361 enum send_crc_alg { 362 SEND_CRCALG_CRC32, 363 SEND_CRCALG_CRC32C, 364 SEND_CRCALG_ICRC, 365 }; 366 367 enum send_load_type { 368 SEND_LD_TYPE_LDD, 369 SEND_LD_TYPE_LDT, 370 SEND_LD_TYPE_LDWB, 371 }; 372 373 enum send_mem_alg_type { 374 SEND_MEMALG_SET, 375 SEND_MEMALG_ADD = 0x08, 376 SEND_MEMALG_SUB = 0x09, 377 SEND_MEMALG_ADDLEN = 0x0A, 378 SEND_MEMALG_SUBLEN = 0x0B, 379 }; 380 381 enum send_mem_dsz_type { 382 SEND_MEMDSZ_B64, 383 SEND_MEMDSZ_B32, 384 SEND_MEMDSZ_B8 = 0x03, 385 }; 386 387 enum sq_subdesc_type { 388 SQ_DESC_TYPE_INVALID, 389 SQ_DESC_TYPE_HEADER, 390 SQ_DESC_TYPE_CRC, 391 SQ_DESC_TYPE_IMMEDIATE, 392 SQ_DESC_TYPE_GATHER, 393 SQ_DESC_TYPE_MEMORY, 394 }; 395 396 enum l3_type_t { 397 L3_NONE, 398 L3_IPV4 = 0x04, 399 L3_IPV4_OPT = 0x05, 400 L3_IPV6 = 0x06, 401 L3_IPV6_OPT = 0x07, 402 L3_ET_STOP = 0x0D, 403 L3_OTHER = 0x0E 404 }; 405 406 enum l4_type_t { 407 L4_NONE, 408 L4_IPSEC_ESP = 0x01, 409 L4_IPFRAG = 0x02, 410 L4_IPCOMP = 0x03, 411 L4_TCP = 0x04, 412 L4_UDP_PASS1 = 0x05, 413 L4_GRE = 0x07, 414 L4_UDP_PASS2 = 0x08, 415 L4_UDP_GENEVE = 0x09, 416 L4_UDP_VXLAN = 0x0A, 417 L4_NVGRE = 0x0C, 418 L4_OTHER = 0x0E 419 }; 420 421 enum vlan_strip { 422 NO_STRIP, 423 STRIP_FIRST_VLAN, 424 STRIP_SECOND_VLAN, 425 STRIP_RESERV, 426 }; 427 428 enum rbdr_state { 429 RBDR_FIFO_STATE_INACTIVE, 430 RBDR_FIFO_STATE_ACTIVE, 431 RBDR_FIFO_STATE_RESET, 432 RBDR_FIFO_STATE_FAIL, 433 }; 434 435 enum rq_cache_allocation { 436 RQ_CACHE_ALLOC_OFF, 437 RQ_CACHE_ALLOC_ALL, 438 RQ_CACHE_ALLOC_FIRST, 439 RQ_CACHE_ALLOC_TWO, 440 }; 441 442 enum cq_rx_errlvl_e { 443 CQ_ERRLVL_MAC, 444 CQ_ERRLVL_L2, 445 CQ_ERRLVL_L3, 446 CQ_ERRLVL_L4, 447 }; 448 449 enum cq_rx_errop_e { 450 CQ_RX_ERROP_RE_NONE, 451 CQ_RX_ERROP_RE_PARTIAL = 0x1, 452 CQ_RX_ERROP_RE_JABBER = 0x2, 453 CQ_RX_ERROP_RE_FCS = 0x7, 454 CQ_RX_ERROP_RE_TERMINATE = 0x9, 455 CQ_RX_ERROP_RE_RX_CTL = 0xb, 456 CQ_RX_ERROP_PREL2_ERR = 0x1f, 457 CQ_RX_ERROP_L2_FRAGMENT = 0x20, 458 CQ_RX_ERROP_L2_OVERRUN = 0x21, 459 CQ_RX_ERROP_L2_PFCS = 0x22, 460 CQ_RX_ERROP_L2_PUNY = 0x23, 461 CQ_RX_ERROP_L2_MAL = 0x24, 462 CQ_RX_ERROP_L2_OVERSIZE = 0x25, 463 CQ_RX_ERROP_L2_UNDERSIZE = 0x26, 464 CQ_RX_ERROP_L2_LENMISM = 0x27, 465 CQ_RX_ERROP_L2_PCLP = 0x28, 466 CQ_RX_ERROP_IP_NOT = 0x41, 467 CQ_RX_ERROP_IP_CSUM_ERR = 0x42, 468 CQ_RX_ERROP_IP_MAL = 0x43, 469 CQ_RX_ERROP_IP_MALD = 0x44, 470 CQ_RX_ERROP_IP_HOP = 0x45, 471 CQ_RX_ERROP_L3_ICRC = 0x46, 472 CQ_RX_ERROP_L3_PCLP = 0x47, 473 CQ_RX_ERROP_L4_MAL = 0x61, 474 CQ_RX_ERROP_L4_CHK = 0x62, 475 CQ_RX_ERROP_UDP_LEN = 0x63, 476 CQ_RX_ERROP_L4_PORT = 0x64, 477 CQ_RX_ERROP_TCP_FLAG = 0x65, 478 CQ_RX_ERROP_TCP_OFFSET = 0x66, 479 CQ_RX_ERROP_L4_PCLP = 0x67, 480 CQ_RX_ERROP_RBDR_TRUNC = 0x70, 481 }; 482 483 enum cq_tx_errop_e { 484 CQ_TX_ERROP_GOOD, 485 CQ_TX_ERROP_DESC_FAULT = 0x10, 486 CQ_TX_ERROP_HDR_CONS_ERR = 0x11, 487 CQ_TX_ERROP_SUBDC_ERR = 0x12, 488 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80, 489 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81, 490 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82, 491 CQ_TX_ERROP_LOCK_VIOL = 0x83, 492 CQ_TX_ERROP_DATA_FAULT = 0x84, 493 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85, 494 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86, 495 CQ_TX_ERROP_MEM_FAULT = 0x87, 496 CQ_TX_ERROP_CK_OVERLAP = 0x88, 497 CQ_TX_ERROP_CK_OFLOW = 0x89, 498 CQ_TX_ERROP_ENUM_LAST = 0x8a, 499 }; 500 501 enum rq_sq_stats_reg_offset { 502 RQ_SQ_STATS_OCTS, 503 RQ_SQ_STATS_PKTS, 504 }; 505 506 enum nic_stat_vnic_rx_e { 507 RX_OCTS, 508 RX_UCAST, 509 RX_BCAST, 510 RX_MCAST, 511 RX_RED, 512 RX_RED_OCTS, 513 RX_ORUN, 514 RX_ORUN_OCTS, 515 RX_FCS, 516 RX_L2ERR, 517 RX_DRP_BCAST, 518 RX_DRP_MCAST, 519 RX_DRP_L3BCAST, 520 RX_DRP_L3MCAST, 521 }; 522 523 enum nic_stat_vnic_tx_e { 524 TX_OCTS, 525 TX_UCAST, 526 TX_BCAST, 527 TX_MCAST, 528 TX_DROP, 529 }; 530 531 /* vNIC HW Register structures */ 532 533 typedef union { 534 uint64_t u64; 535 struct { 536 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 537 uint64_t cqe_type:4; 538 uint64_t stdn_fault:1; 539 uint64_t rsvd0:1; 540 uint64_t rq_qs:7; 541 uint64_t rq_idx:3; 542 uint64_t rsvd1:12; 543 uint64_t rss_alg:4; 544 uint64_t rsvd2:4; 545 uint64_t rb_cnt:4; 546 uint64_t vlan_found:1; 547 uint64_t vlan_stripped:1; 548 uint64_t vlan2_found:1; 549 uint64_t vlan2_stripped:1; 550 uint64_t l4_type:4; 551 uint64_t l3_type:4; 552 uint64_t l2_present:1; 553 uint64_t err_level:3; 554 uint64_t err_opcode:8; 555 #else 556 uint64_t err_opcode:8; 557 uint64_t err_level:3; 558 uint64_t l2_present:1; 559 uint64_t l3_type:4; 560 uint64_t l4_type:4; 561 uint64_t vlan2_stripped:1; 562 uint64_t vlan2_found:1; 563 uint64_t vlan_stripped:1; 564 uint64_t vlan_found:1; 565 uint64_t rb_cnt:4; 566 uint64_t rsvd2:4; 567 uint64_t rss_alg:4; 568 uint64_t rsvd1:12; 569 uint64_t rq_idx:3; 570 uint64_t rq_qs:7; 571 uint64_t rsvd0:1; 572 uint64_t stdn_fault:1; 573 uint64_t cqe_type:4; 574 #endif 575 }; 576 } cqe_rx_word0_t; 577 578 typedef union { 579 uint64_t u64; 580 struct { 581 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 582 uint64_t pkt_len:16; 583 uint64_t l2_ptr:8; 584 uint64_t l3_ptr:8; 585 uint64_t l4_ptr:8; 586 uint64_t cq_pkt_len:8; 587 uint64_t align_pad:3; 588 uint64_t rsvd3:1; 589 uint64_t chan:12; 590 #else 591 uint64_t chan:12; 592 uint64_t rsvd3:1; 593 uint64_t align_pad:3; 594 uint64_t cq_pkt_len:8; 595 uint64_t l4_ptr:8; 596 uint64_t l3_ptr:8; 597 uint64_t l2_ptr:8; 598 uint64_t pkt_len:16; 599 #endif 600 }; 601 } cqe_rx_word1_t; 602 603 typedef union { 604 uint64_t u64; 605 struct { 606 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 607 uint64_t rss_tag:32; 608 uint64_t vlan_tci:16; 609 uint64_t vlan_ptr:8; 610 uint64_t vlan2_ptr:8; 611 #else 612 uint64_t vlan2_ptr:8; 613 uint64_t vlan_ptr:8; 614 uint64_t vlan_tci:16; 615 uint64_t rss_tag:32; 616 #endif 617 }; 618 } cqe_rx_word2_t; 619 620 typedef union { 621 uint64_t u64; 622 struct { 623 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 624 uint16_t rb3_sz; 625 uint16_t rb2_sz; 626 uint16_t rb1_sz; 627 uint16_t rb0_sz; 628 #else 629 uint16_t rb0_sz; 630 uint16_t rb1_sz; 631 uint16_t rb2_sz; 632 uint16_t rb3_sz; 633 #endif 634 }; 635 } cqe_rx_word3_t; 636 637 typedef union { 638 uint64_t u64; 639 struct { 640 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 641 uint16_t rb7_sz; 642 uint16_t rb6_sz; 643 uint16_t rb5_sz; 644 uint16_t rb4_sz; 645 #else 646 uint16_t rb4_sz; 647 uint16_t rb5_sz; 648 uint16_t rb6_sz; 649 uint16_t rb7_sz; 650 #endif 651 }; 652 } cqe_rx_word4_t; 653 654 typedef union { 655 uint64_t u64; 656 struct { 657 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 658 uint16_t rb11_sz; 659 uint16_t rb10_sz; 660 uint16_t rb9_sz; 661 uint16_t rb8_sz; 662 #else 663 uint16_t rb8_sz; 664 uint16_t rb9_sz; 665 uint16_t rb10_sz; 666 uint16_t rb11_sz; 667 #endif 668 }; 669 } cqe_rx_word5_t; 670 671 typedef union { 672 uint64_t u64; 673 struct { 674 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 675 uint64_t vlan_found:1; 676 uint64_t vlan_stripped:1; 677 uint64_t vlan2_found:1; 678 uint64_t vlan2_stripped:1; 679 uint64_t rsvd2:3; 680 uint64_t inner_l2:1; 681 uint64_t inner_l4type:4; 682 uint64_t inner_l3type:4; 683 uint64_t vlan_ptr:8; 684 uint64_t vlan2_ptr:8; 685 uint64_t rsvd1:8; 686 uint64_t rsvd0:8; 687 uint64_t inner_l3ptr:8; 688 uint64_t inner_l4ptr:8; 689 #else 690 uint64_t inner_l4ptr:8; 691 uint64_t inner_l3ptr:8; 692 uint64_t rsvd0:8; 693 uint64_t rsvd1:8; 694 uint64_t vlan2_ptr:8; 695 uint64_t vlan_ptr:8; 696 uint64_t inner_l3type:4; 697 uint64_t inner_l4type:4; 698 uint64_t inner_l2:1; 699 uint64_t rsvd2:3; 700 uint64_t vlan2_stripped:1; 701 uint64_t vlan2_found:1; 702 uint64_t vlan_stripped:1; 703 uint64_t vlan_found:1; 704 #endif 705 }; 706 } cqe_rx2_word6_t; 707 708 struct cqe_rx_t { 709 cqe_rx_word0_t word0; 710 cqe_rx_word1_t word1; 711 cqe_rx_word2_t word2; 712 cqe_rx_word3_t word3; 713 cqe_rx_word4_t word4; 714 cqe_rx_word5_t word5; 715 cqe_rx2_word6_t word6; /* if NIC_PF_RX_CFG[CQE_RX2_ENA] set */ 716 }; 717 718 struct cqe_rx_tcp_err_t { 719 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 720 uint64_t cqe_type:4; /* W0 */ 721 uint64_t rsvd0:60; 722 723 uint64_t rsvd1:4; /* W1 */ 724 uint64_t partial_first:1; 725 uint64_t rsvd2:27; 726 uint64_t rbdr_bytes:8; 727 uint64_t rsvd3:24; 728 #else 729 uint64_t rsvd0:60; 730 uint64_t cqe_type:4; 731 732 uint64_t rsvd3:24; 733 uint64_t rbdr_bytes:8; 734 uint64_t rsvd2:27; 735 uint64_t partial_first:1; 736 uint64_t rsvd1:4; 737 #endif 738 }; 739 740 struct cqe_rx_tcp_t { 741 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 742 uint64_t cqe_type:4; /* W0 */ 743 uint64_t rsvd0:52; 744 uint64_t cq_tcp_status:8; 745 746 uint64_t rsvd1:32; /* W1 */ 747 uint64_t tcp_cntx_bytes:8; 748 uint64_t rsvd2:8; 749 uint64_t tcp_err_bytes:16; 750 #else 751 uint64_t cq_tcp_status:8; 752 uint64_t rsvd0:52; 753 uint64_t cqe_type:4; /* W0 */ 754 755 uint64_t tcp_err_bytes:16; 756 uint64_t rsvd2:8; 757 uint64_t tcp_cntx_bytes:8; 758 uint64_t rsvd1:32; /* W1 */ 759 #endif 760 }; 761 762 struct cqe_send_t { 763 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 764 uint64_t cqe_type:4; /* W0 */ 765 uint64_t rsvd0:4; 766 uint64_t sqe_ptr:16; 767 uint64_t rsvd1:4; 768 uint64_t rsvd2:10; 769 uint64_t sq_qs:7; 770 uint64_t sq_idx:3; 771 uint64_t rsvd3:8; 772 uint64_t send_status:8; 773 774 uint64_t ptp_timestamp:64; /* W1 */ 775 #elif NICVF_BYTE_ORDER == NICVF_LITTLE_ENDIAN 776 uint64_t send_status:8; 777 uint64_t rsvd3:8; 778 uint64_t sq_idx:3; 779 uint64_t sq_qs:7; 780 uint64_t rsvd2:10; 781 uint64_t rsvd1:4; 782 uint64_t sqe_ptr:16; 783 uint64_t rsvd0:4; 784 uint64_t cqe_type:4; /* W0 */ 785 786 uint64_t ptp_timestamp:64; 787 #endif 788 }; 789 790 struct cq_entry_type_t { 791 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 792 uint64_t cqe_type:4; 793 uint64_t __pad:60; 794 #else 795 uint64_t __pad:60; 796 uint64_t cqe_type:4; 797 #endif 798 }; 799 800 union cq_entry_t { 801 uint64_t u[64]; 802 struct cq_entry_type_t type; 803 struct cqe_rx_t rx_hdr; 804 struct cqe_rx_tcp_t rx_tcp_hdr; 805 struct cqe_rx_tcp_err_t rx_tcp_err_hdr; 806 struct cqe_send_t cqe_send; 807 }; 808 809 NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512); 810 811 struct rbdr_entry_t { 812 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 813 union { 814 struct { 815 uint64_t rsvd0:15; 816 uint64_t buf_addr:42; 817 uint64_t cache_align:7; 818 }; 819 nicvf_iova_addr_t full_addr; 820 }; 821 #else 822 union { 823 struct { 824 uint64_t cache_align:7; 825 uint64_t buf_addr:42; 826 uint64_t rsvd0:15; 827 }; 828 nicvf_iova_addr_t full_addr; 829 }; 830 #endif 831 }; 832 833 NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t)); 834 835 /* TCP reassembly context */ 836 struct rbe_tcp_cnxt_t { 837 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 838 uint64_t tcp_pkt_cnt:12; 839 uint64_t rsvd1:4; 840 uint64_t align_hdr_bytes:4; 841 uint64_t align_ptr_bytes:4; 842 uint64_t ptr_bytes:16; 843 uint64_t rsvd2:24; 844 uint64_t cqe_type:4; 845 uint64_t rsvd0:54; 846 uint64_t tcp_end_reason:2; 847 uint64_t tcp_status:4; 848 #else 849 uint64_t tcp_status:4; 850 uint64_t tcp_end_reason:2; 851 uint64_t rsvd0:54; 852 uint64_t cqe_type:4; 853 uint64_t rsvd2:24; 854 uint64_t ptr_bytes:16; 855 uint64_t align_ptr_bytes:4; 856 uint64_t align_hdr_bytes:4; 857 uint64_t rsvd1:4; 858 uint64_t tcp_pkt_cnt:12; 859 #endif 860 }; 861 862 /* Always Big endian */ 863 struct rx_hdr_t { 864 uint64_t opaque:32; 865 uint64_t rss_flow:8; 866 uint64_t skip_length:6; 867 uint64_t disable_rss:1; 868 uint64_t disable_tcp_reassembly:1; 869 uint64_t nodrop:1; 870 uint64_t dest_alg:2; 871 uint64_t rsvd0:2; 872 uint64_t dest_rq:11; 873 }; 874 875 struct sq_crc_subdesc { 876 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 877 uint64_t rsvd1:32; 878 uint64_t crc_ival:32; 879 uint64_t subdesc_type:4; 880 uint64_t crc_alg:2; 881 uint64_t rsvd0:10; 882 uint64_t crc_insert_pos:16; 883 uint64_t hdr_start:16; 884 uint64_t crc_len:16; 885 #else 886 uint64_t crc_len:16; 887 uint64_t hdr_start:16; 888 uint64_t crc_insert_pos:16; 889 uint64_t rsvd0:10; 890 uint64_t crc_alg:2; 891 uint64_t subdesc_type:4; 892 uint64_t crc_ival:32; 893 uint64_t rsvd1:32; 894 #endif 895 }; 896 897 struct sq_gather_subdesc { 898 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 899 uint64_t subdesc_type:4; /* W0 */ 900 uint64_t ld_type:2; 901 uint64_t rsvd0:42; 902 uint64_t size:16; 903 904 uint64_t rsvd1:15; /* W1 */ 905 uint64_t addr:49; 906 #else 907 uint64_t size:16; 908 uint64_t rsvd0:42; 909 uint64_t ld_type:2; 910 uint64_t subdesc_type:4; /* W0 */ 911 912 uint64_t addr:49; 913 uint64_t rsvd1:15; /* W1 */ 914 #endif 915 }; 916 917 /* SQ immediate subdescriptor */ 918 struct sq_imm_subdesc { 919 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 920 uint64_t subdesc_type:4; /* W0 */ 921 uint64_t rsvd0:46; 922 uint64_t len:14; 923 924 uint64_t data:64; /* W1 */ 925 #else 926 uint64_t len:14; 927 uint64_t rsvd0:46; 928 uint64_t subdesc_type:4; /* W0 */ 929 930 uint64_t data:64; /* W1 */ 931 #endif 932 }; 933 934 struct sq_mem_subdesc { 935 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 936 uint64_t subdesc_type:4; /* W0 */ 937 uint64_t mem_alg:4; 938 uint64_t mem_dsz:2; 939 uint64_t wmem:1; 940 uint64_t rsvd0:21; 941 uint64_t offset:32; 942 943 uint64_t rsvd1:15; /* W1 */ 944 uint64_t addr:49; 945 #else 946 uint64_t offset:32; 947 uint64_t rsvd0:21; 948 uint64_t wmem:1; 949 uint64_t mem_dsz:2; 950 uint64_t mem_alg:4; 951 uint64_t subdesc_type:4; /* W0 */ 952 953 uint64_t addr:49; 954 uint64_t rsvd1:15; /* W1 */ 955 #endif 956 }; 957 958 struct sq_hdr_subdesc { 959 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 960 uint64_t subdesc_type:4; 961 uint64_t tso:1; 962 uint64_t post_cqe:1; /* Post CQE on no error also */ 963 uint64_t dont_send:1; 964 uint64_t tstmp:1; 965 uint64_t subdesc_cnt:8; 966 uint64_t csum_l4:2; 967 uint64_t csum_l3:1; 968 uint64_t csum_inner_l4:2; 969 uint64_t csum_inner_l3:1; 970 uint64_t rsvd0:2; 971 uint64_t l4_offset:8; 972 uint64_t l3_offset:8; 973 uint64_t rsvd1:4; 974 uint64_t tot_len:20; /* W0 */ 975 976 uint64_t rsvd2:24; 977 uint64_t inner_l4_offset:8; 978 uint64_t inner_l3_offset:8; 979 uint64_t tso_start:8; 980 uint64_t rsvd3:2; 981 uint64_t tso_max_paysize:14; /* W1 */ 982 #else 983 uint64_t tot_len:20; 984 uint64_t rsvd1:4; 985 uint64_t l3_offset:8; 986 uint64_t l4_offset:8; 987 uint64_t rsvd0:2; 988 uint64_t csum_inner_l3:1; 989 uint64_t csum_inner_l4:2; 990 uint64_t csum_l3:1; 991 uint64_t csum_l4:2; 992 uint64_t subdesc_cnt:8; 993 uint64_t tstmp:1; 994 uint64_t dont_send:1; 995 uint64_t post_cqe:1; /* Post CQE on no error also */ 996 uint64_t tso:1; 997 uint64_t subdesc_type:4; /* W0 */ 998 999 uint64_t tso_max_paysize:14; 1000 uint64_t rsvd3:2; 1001 uint64_t tso_start:8; 1002 uint64_t inner_l3_offset:8; 1003 uint64_t inner_l4_offset:8; 1004 uint64_t rsvd2:24; /* W1 */ 1005 #endif 1006 }; 1007 1008 /* Each sq entry is 128 bits wide */ 1009 union sq_entry_t { 1010 uint64_t buff[2]; 1011 struct sq_hdr_subdesc hdr; 1012 struct sq_imm_subdesc imm; 1013 struct sq_gather_subdesc gather; 1014 struct sq_crc_subdesc crc; 1015 struct sq_mem_subdesc mem; 1016 }; 1017 1018 NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16); 1019 1020 /* Queue config register formats */ 1021 struct rq_cfg { union { struct { 1022 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1023 uint64_t reserved_2_63:62; 1024 uint64_t ena:1; 1025 uint64_t reserved_0:1; 1026 #else 1027 uint64_t reserved_0:1; 1028 uint64_t ena:1; 1029 uint64_t reserved_2_63:62; 1030 #endif 1031 }; 1032 uint64_t value; 1033 }; }; 1034 1035 struct cq_cfg { union { struct { 1036 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1037 uint64_t reserved_43_63:21; 1038 uint64_t ena:1; 1039 uint64_t reset:1; 1040 uint64_t caching:1; 1041 uint64_t reserved_35_39:5; 1042 uint64_t qsize:3; 1043 uint64_t reserved_25_31:7; 1044 uint64_t avg_con:9; 1045 uint64_t reserved_0_15:16; 1046 #else 1047 uint64_t reserved_0_15:16; 1048 uint64_t avg_con:9; 1049 uint64_t reserved_25_31:7; 1050 uint64_t qsize:3; 1051 uint64_t reserved_35_39:5; 1052 uint64_t caching:1; 1053 uint64_t reset:1; 1054 uint64_t ena:1; 1055 uint64_t reserved_43_63:21; 1056 #endif 1057 }; 1058 uint64_t value; 1059 }; }; 1060 1061 struct sq_cfg { union { struct { 1062 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1063 uint64_t reserved_32_63:32; 1064 uint64_t cq_limit:8; 1065 uint64_t ena:1; 1066 uint64_t reserved_18_18:1; 1067 uint64_t reset:1; 1068 uint64_t ldwb:1; 1069 uint64_t reserved_11_15:5; 1070 uint64_t qsize:3; 1071 uint64_t reserved_3_7:5; 1072 uint64_t tstmp_bgx_intf:3; 1073 #else 1074 uint64_t tstmp_bgx_intf:3; 1075 uint64_t reserved_3_7:5; 1076 uint64_t qsize:3; 1077 uint64_t reserved_11_15:5; 1078 uint64_t ldwb:1; 1079 uint64_t reset:1; 1080 uint64_t reserved_18_18:1; 1081 uint64_t ena:1; 1082 uint64_t cq_limit:8; 1083 uint64_t reserved_32_63:32; 1084 #endif 1085 }; 1086 uint64_t value; 1087 }; }; 1088 1089 struct rbdr_cfg { union { struct { 1090 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1091 uint64_t reserved_45_63:19; 1092 uint64_t ena:1; 1093 uint64_t reset:1; 1094 uint64_t ldwb:1; 1095 uint64_t reserved_36_41:6; 1096 uint64_t qsize:4; 1097 uint64_t reserved_25_31:7; 1098 uint64_t avg_con:9; 1099 uint64_t reserved_12_15:4; 1100 uint64_t lines:12; 1101 #else 1102 uint64_t lines:12; 1103 uint64_t reserved_12_15:4; 1104 uint64_t avg_con:9; 1105 uint64_t reserved_25_31:7; 1106 uint64_t qsize:4; 1107 uint64_t reserved_36_41:6; 1108 uint64_t ldwb:1; 1109 uint64_t reset:1; 1110 uint64_t ena: 1; 1111 uint64_t reserved_45_63:19; 1112 #endif 1113 }; 1114 uint64_t value; 1115 }; }; 1116 1117 struct pf_qs_cfg { union { struct { 1118 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1119 uint64_t reserved_32_63:32; 1120 uint64_t ena:1; 1121 uint64_t reserved_27_30:4; 1122 uint64_t sq_ins_ena:1; 1123 uint64_t sq_ins_pos:6; 1124 uint64_t lock_ena:1; 1125 uint64_t lock_viol_cqe_ena:1; 1126 uint64_t send_tstmp_ena:1; 1127 uint64_t be:1; 1128 uint64_t reserved_7_15:9; 1129 uint64_t vnic:7; 1130 #else 1131 uint64_t vnic:7; 1132 uint64_t reserved_7_15:9; 1133 uint64_t be:1; 1134 uint64_t send_tstmp_ena:1; 1135 uint64_t lock_viol_cqe_ena:1; 1136 uint64_t lock_ena:1; 1137 uint64_t sq_ins_pos:6; 1138 uint64_t sq_ins_ena:1; 1139 uint64_t reserved_27_30:4; 1140 uint64_t ena:1; 1141 uint64_t reserved_32_63:32; 1142 #endif 1143 }; 1144 uint64_t value; 1145 }; }; 1146 1147 struct pf_rq_cfg { union { struct { 1148 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1149 uint64_t reserved1:1; 1150 uint64_t reserved0:34; 1151 uint64_t strip_pre_l2:1; 1152 uint64_t caching:2; 1153 uint64_t cq_qs:7; 1154 uint64_t cq_idx:3; 1155 uint64_t rbdr_cont_qs:7; 1156 uint64_t rbdr_cont_idx:1; 1157 uint64_t rbdr_strt_qs:7; 1158 uint64_t rbdr_strt_idx:1; 1159 #else 1160 uint64_t rbdr_strt_idx:1; 1161 uint64_t rbdr_strt_qs:7; 1162 uint64_t rbdr_cont_idx:1; 1163 uint64_t rbdr_cont_qs:7; 1164 uint64_t cq_idx:3; 1165 uint64_t cq_qs:7; 1166 uint64_t caching:2; 1167 uint64_t strip_pre_l2:1; 1168 uint64_t reserved0:34; 1169 uint64_t reserved1:1; 1170 #endif 1171 }; 1172 uint64_t value; 1173 }; }; 1174 1175 struct pf_rq_drop_cfg { union { struct { 1176 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN 1177 uint64_t rbdr_red:1; 1178 uint64_t cq_red:1; 1179 uint64_t reserved3:14; 1180 uint64_t rbdr_pass:8; 1181 uint64_t rbdr_drop:8; 1182 uint64_t reserved2:8; 1183 uint64_t cq_pass:8; 1184 uint64_t cq_drop:8; 1185 uint64_t reserved1:8; 1186 #else 1187 uint64_t reserved1:8; 1188 uint64_t cq_drop:8; 1189 uint64_t cq_pass:8; 1190 uint64_t reserved2:8; 1191 uint64_t rbdr_drop:8; 1192 uint64_t rbdr_pass:8; 1193 uint64_t reserved3:14; 1194 uint64_t cq_red:1; 1195 uint64_t rbdr_red:1; 1196 #endif 1197 }; 1198 uint64_t value; 1199 }; }; 1200 1201 #endif /* _THUNDERX_NICVF_HW_DEFS_H */ 1202