1 /* $NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 2010 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code was written by Alessandro Forin and Neil Pittman
8 * at Microsoft Research and contributed to The NetBSD Foundation
9 * by Microsoft Corporation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $");
35
36 #include <sys/param.h>
37 #include <sys/device.h>
38 #include <sys/proc.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <mips/psl.h>
43
44 #include <machine/locore.h>
45 #include <machine/autoconf.h>
46 #include <machine/sysconf.h>
47 #include <machine/intr.h>
48 #include <machine/emipsreg.h>
49
50 struct intrhand intrtab[MAX_DEV_NCOOKIES];
51
52 struct evcnt emips_clock_evcnt =
53 EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "clock", "intr");
54 struct evcnt emips_fpu_evcnt =
55 EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "fpu", "intr");
56 struct evcnt emips_memerr_evcnt =
57 EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "memerr", "intr");
58
59 static const char * const intrnames[MAX_DEV_NCOOKIES] = {
60 "int-0", "int-1", "int-2", "int-3", "int-4",
61 "int-5", "int-6", "int-7", "int-8", "int-9",
62 "int-10", "int-11", "int-12", "int-13", "int-14",
63 "int-15", "int-16", "int-17", "int-18", "int-19",
64 "int-20", "int-21`", "int-22", "int-23", "int-24",
65 "int-25", "int-26", "int-27", "int-28", "int-29",
66 "int-30", "int-31"
67 };
68
69 void
intr_init(void)70 intr_init(void)
71 {
72 int i;
73
74 for (i = 0; i < MAX_DEV_NCOOKIES; i++) {
75 evcnt_attach_dynamic(&intrtab[i].ih_count,
76 EVCNT_TYPE_INTR, NULL, "emips", intrnames[i]);
77 }
78
79 /* I am trying to make this standard so its here. Bah. */
80 struct tlbmask tlb;
81
82 /* This is ugly but efficient. Sigh. */
83 #define TheAic ((struct _Aic *)INTERRUPT_CONTROLLER_DEFAULT_ADDRESS)
84
85 tlb.tlb_hi = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS;
86 tlb.tlb_lo0 = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02;
87 tlb_write_entry(4, &tlb);
88
89 tlb.tlb_hi = TIMER_DEFAULT_ADDRESS;
90 tlb.tlb_lo0 = TIMER_DEFAULT_ADDRESS | 0xf02;
91 tlb_write_entry(5, &tlb);
92 }
93
94 /*
95 * emips uses one line for all I/O interrupts (0x8000).
96 */
97 void
cpu_intr(int ppl,vaddr_t pc,uint32_t status)98 cpu_intr(int ppl, vaddr_t pc, uint32_t status)
99 {
100 uint32_t ipending;
101 int ipl;
102
103 curcpu()->ci_data.cpu_nintr++;
104
105 #if 0
106 /*
107 * According to Giano simulator sources (Cpus/mips_cpu.cpp),
108 * interrupt register bits in CAUSE register are updated
109 * only when the exception is triggered. This means checking
110 * CAUSE register via splintr() in a while loop in this
111 * interrupt handler doesn't work as expected on Giano.
112 *
113 * I don't know whether the real FPGA eMIPS has the same
114 * design as the Giano simulator, but for now I'd like to
115 * choose 'call only one handler per each interrupt' strategy,
116 * as the original NetBSD/emips implementation.
117 */
118 while (ppl < (ipl = splintr(&ipending))) {
119 splx(ipl);
120 /* device interrupts */
121 if (ipending & MIPS_INT_MASK_5) {
122 (*platform.iointr)(status, pc, ipending);
123 }
124 (void)splhigh();
125 }
126 #else
127 ipl = splintr(&ipending);
128 __USE(ipl);
129 /* device interrupts */
130 if (ipending & MIPS_INT_MASK_5) {
131 (*platform.iointr)(status, pc, ipending);
132 }
133 #endif
134 }
135
136 /*
137 * Interrupt dispatcher for standard AIC-style interrupt controller
138 */
139 void
emips_aic_intr(uint32_t status,vaddr_t pc,uint32_t ipending)140 emips_aic_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
141 {
142 struct clockframe cf;
143
144 cf.pc = pc;
145 cf.sr = status;
146 cf.intr = (curcpu()->ci_idepth > 1);
147
148 ipending = TheAic->IrqStatus;
149
150 while (ipending) {
151 /* Take one (most likely, the only one) */
152 int index = ffs(ipending) - 1;
153 ipending &= ~(1 << index);
154
155 intrtab[index].ih_count.ev_count++;
156 (*intrtab[index].ih_func)(intrtab[index].ih_arg, &cf);
157 }
158 }
159
160
161 void
emips_intr_establish(device_t dev,void * cookie,int level,int (* handler)(void *,void *),void * arg)162 emips_intr_establish(device_t dev, void *cookie, int level,
163 int (*handler) (void *, void *), void *arg)
164 {
165 int index = (int) cookie;
166
167 /*
168 * First disable that interrupt source, in case it was enabled.
169 * This prevents us from getting very confused with ISRs and arguments.
170 */
171 TheAic->IrqEnableClear = 1 << index;
172
173 /* Second, the argument & isr. */
174 intrtab[index].ih_func = handler;
175 intrtab[index].ih_arg = arg;
176
177 /* Third, enable and done. */
178 TheAic->IrqEnable = 1 << index;
179 }
180