1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26 /*
27 * IntelVersion: 1.86 v3-1-10-1_2009-9-18_Release14-6
28 */
29 /*
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32 */
33
34 #include "e1000_api.h"
35
36 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
37 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
38 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
39 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
40 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
41 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
42 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
44 u32 offset, u16 *data);
45 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
46 u32 offset, u16 data);
47 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
48 u16 words, u16 *data);
49 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
50 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
51 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
52 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
53 u16 *duplex);
54 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
57 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
58 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
59 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
60 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
61 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
63 u16 *data);
64 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
65 u16 data);
66 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
67 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
68 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
69 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
70 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
71
72 /*
73 * A table for the GG82563 cable length where the range is defined with a
74 * lower bound at "index" and the upper bound at "index + 5".
75 */
76 static const u16 e1000_gg82563_cable_length_table[] =
77 {0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF};
78
79 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
80 (sizeof (e1000_gg82563_cable_length_table) / \
81 sizeof (e1000_gg82563_cable_length_table[0]))
82
83 /*
84 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
85 * @hw: pointer to the HW structure
86 */
87 static s32
e1000_init_phy_params_80003es2lan(struct e1000_hw * hw)88 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
89 {
90 struct e1000_phy_info *phy = &hw->phy;
91 s32 ret_val = E1000_SUCCESS;
92
93 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
94
95 if (hw->phy.media_type != e1000_media_type_copper) {
96 phy->type = e1000_phy_none;
97 goto out;
98 } else {
99 phy->ops.power_up = e1000_power_up_phy_copper;
100 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
101 }
102
103 phy->addr = 1;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106 phy->type = e1000_phy_gg82563;
107
108 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
109 phy->ops.check_polarity = e1000_check_polarity_m88;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.commit = e1000_phy_sw_reset_generic;
112 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
113 phy->ops.get_info = e1000_get_phy_info_m88;
114 phy->ops.release = e1000_release_phy_80003es2lan;
115 phy->ops.reset = e1000_phy_hw_reset_generic;
116 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
117
118 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
119 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
120 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
121 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
122
123 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
124
125 /* This can only be done after all function pointers are setup. */
126 ret_val = e1000_get_phy_id(hw);
127
128 /* Verify phy id */
129 if (phy->id != GG82563_E_PHY_ID) {
130 ret_val = -E1000_ERR_PHY;
131 goto out;
132 }
133
134 out:
135 return (ret_val);
136 }
137
138 /*
139 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
140 * @hw: pointer to the HW structure
141 */
142 static s32
e1000_init_nvm_params_80003es2lan(struct e1000_hw * hw)143 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
144 {
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
147 u16 size;
148
149 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
150
151 nvm->opcode_bits = 8;
152 nvm->delay_usec = 1;
153 switch (nvm->override) {
154 case e1000_nvm_override_spi_large:
155 nvm->page_size = 32;
156 nvm->address_bits = 16;
157 break;
158 case e1000_nvm_override_spi_small:
159 nvm->page_size = 8;
160 nvm->address_bits = 8;
161 break;
162 default:
163 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
164 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
165 break;
166 }
167
168 nvm->type = e1000_nvm_eeprom_spi;
169
170 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
171 E1000_EECD_SIZE_EX_SHIFT);
172
173 /*
174 * Added to a constant, "size" becomes the left-shift value
175 * for setting word_size.
176 */
177 size += NVM_WORD_SIZE_BASE_SHIFT;
178
179 /* EEPROM access above 16k is unsupported */
180 if (size > 14)
181 size = 14;
182 nvm->word_size = 1 << size;
183
184 /* Function Pointers */
185 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
186 nvm->ops.read = e1000_read_nvm_eerd;
187 nvm->ops.release = e1000_release_nvm_80003es2lan;
188 nvm->ops.update = e1000_update_nvm_checksum_generic;
189 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
190 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
191 nvm->ops.write = e1000_write_nvm_80003es2lan;
192
193 return (E1000_SUCCESS);
194 }
195
196 /*
197 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
198 * @hw: pointer to the HW structure
199 */
200 static s32
e1000_init_mac_params_80003es2lan(struct e1000_hw * hw)201 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
202 {
203 struct e1000_mac_info *mac = &hw->mac;
204 s32 ret_val = E1000_SUCCESS;
205
206 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
207
208 /* Set media type */
209 switch (hw->device_id) {
210 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
211 hw->phy.media_type = e1000_media_type_internal_serdes;
212 break;
213 default:
214 hw->phy.media_type = e1000_media_type_copper;
215 break;
216 }
217
218 /* Set mta register count */
219 mac->mta_reg_count = 128;
220 /* Set rar entry count */
221 mac->rar_entry_count = E1000_RAR_ENTRIES;
222 /* Set if part includes ASF firmware */
223 mac->asf_firmware_present = true;
224 /* Set if manageability features are enabled. */
225 mac->arc_subsystem_valid =
226 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
227 ? true : false;
228
229 /* Function pointers */
230
231 /* bus type/speed/width */
232 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
233 /* reset */
234 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
235 /* hw initialization */
236 mac->ops.init_hw = e1000_init_hw_80003es2lan;
237 /* link setup */
238 mac->ops.setup_link = e1000_setup_link_generic;
239 /* physical interface link setup */
240 mac->ops.setup_physical_interface =
241 (hw->phy.media_type == e1000_media_type_copper)
242 ? e1000_setup_copper_link_80003es2lan
243 : e1000_setup_fiber_serdes_link_generic;
244 /* check for link */
245 switch (hw->phy.media_type) {
246 case e1000_media_type_copper:
247 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
248 break;
249 case e1000_media_type_fiber:
250 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
251 break;
252 case e1000_media_type_internal_serdes:
253 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
254 break;
255 default:
256 ret_val = -E1000_ERR_CONFIG;
257 goto out;
258 }
259 /* check management mode */
260 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
261 /* multicast address update */
262 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
263 /* writing VFTA */
264 mac->ops.write_vfta = e1000_write_vfta_generic;
265 /* clearing VFTA */
266 mac->ops.clear_vfta = e1000_clear_vfta_generic;
267 /* setting MTA */
268 mac->ops.mta_set = e1000_mta_set_generic;
269 /* read mac address */
270 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
271 /* ID LED init */
272 mac->ops.id_led_init = e1000_id_led_init_generic;
273 /* blink LED */
274 mac->ops.blink_led = e1000_blink_led_generic;
275 /* setup LED */
276 mac->ops.setup_led = e1000_setup_led_generic;
277 /* cleanup LED */
278 mac->ops.cleanup_led = e1000_cleanup_led_generic;
279 /* turn on/off LED */
280 mac->ops.led_on = e1000_led_on_generic;
281 mac->ops.led_off = e1000_led_off_generic;
282 /* clear hardware counters */
283 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
284 /* link info */
285 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
286
287 /* set lan id for port to determine which phy lock to use */
288 hw->mac.ops.set_lan_id(hw);
289 out:
290 return (ret_val);
291 }
292
293 /*
294 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
295 * @hw: pointer to the HW structure
296 *
297 * Called to initialize all function pointers and parameters.
298 */
299 void
e1000_init_function_pointers_80003es2lan(struct e1000_hw * hw)300 e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
301 {
302 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
303
304 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
305 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
306 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
307 }
308
309 /*
310 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
311 * @hw: pointer to the HW structure
312 *
313 * A wrapper to acquire access rights to the correct PHY.
314 */
315 static s32
e1000_acquire_phy_80003es2lan(struct e1000_hw * hw)316 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
317 {
318 u16 mask;
319
320 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
321
322 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
323
324 return (e1000_acquire_swfw_sync_80003es2lan(hw, mask));
325 }
326
327 /*
328 * e1000_release_phy_80003es2lan - Release rights to access PHY
329 * @hw: pointer to the HW structure
330 *
331 * A wrapper to release access rights to the correct PHY.
332 */
333 static void
e1000_release_phy_80003es2lan(struct e1000_hw * hw)334 e1000_release_phy_80003es2lan(struct e1000_hw *hw)
335 {
336 u16 mask;
337
338 DEBUGFUNC("e1000_release_phy_80003es2lan");
339
340 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
341 e1000_release_swfw_sync_80003es2lan(hw, mask);
342 }
343
344 /*
345 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
346 * @hw: pointer to the HW structure
347 *
348 * Acquire the semaphore to access the Kumeran interface.
349 *
350 */
351 static s32
e1000_acquire_mac_csr_80003es2lan(struct e1000_hw * hw)352 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
353 {
354 u16 mask;
355
356 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
357
358 mask = E1000_SWFW_CSR_SM;
359
360 return (e1000_acquire_swfw_sync_80003es2lan(hw, mask));
361 }
362
363 /*
364 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
365 * @hw: pointer to the HW structure
366 *
367 * Release the semaphore used to access the Kumeran interface
368 */
369 static void
e1000_release_mac_csr_80003es2lan(struct e1000_hw * hw)370 e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
371 {
372 u16 mask;
373
374 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
375
376 mask = E1000_SWFW_CSR_SM;
377
378 e1000_release_swfw_sync_80003es2lan(hw, mask);
379 }
380
381 /*
382 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
383 * @hw: pointer to the HW structure
384 *
385 * Acquire the semaphore to access the EEPROM.
386 */
387 static s32
e1000_acquire_nvm_80003es2lan(struct e1000_hw * hw)388 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
389 {
390 s32 ret_val;
391
392 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
393
394 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
395 if (ret_val)
396 goto out;
397
398 ret_val = e1000_acquire_nvm_generic(hw);
399
400 if (ret_val)
401 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
402
403 out:
404 return (ret_val);
405 }
406
407 /*
408 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
409 * @hw: pointer to the HW structure
410 *
411 * Release the semaphore used to access the EEPROM.
412 */
413 static void
e1000_release_nvm_80003es2lan(struct e1000_hw * hw)414 e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
415 {
416 DEBUGFUNC("e1000_release_nvm_80003es2lan");
417
418 e1000_release_nvm_generic(hw);
419 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
420 }
421
422 /*
423 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
424 * @hw: pointer to the HW structure
425 * @mask: specifies which semaphore to acquire
426 *
427 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
428 * will also specify which port we're acquiring the lock for.
429 */
430 static s32
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)431 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
432 {
433 u32 swfw_sync;
434 u32 swmask = mask;
435 u32 fwmask = mask << 16;
436 s32 ret_val = E1000_SUCCESS;
437 s32 i = 0, timeout = 50;
438
439 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
440
441 while (i < timeout) {
442 if (e1000_get_hw_semaphore_generic(hw)) {
443 ret_val = -E1000_ERR_SWFW_SYNC;
444 goto out;
445 }
446
447 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
448 if (!(swfw_sync & (fwmask | swmask)))
449 break;
450
451 /*
452 * Firmware currently using resource (fwmask)
453 * or other software thread using resource (swmask)
454 */
455 e1000_put_hw_semaphore_generic(hw);
456 msec_delay_irq(5);
457 i++;
458 }
459
460 if (i == timeout) {
461 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
462 ret_val = -E1000_ERR_SWFW_SYNC;
463 goto out;
464 }
465
466 swfw_sync |= swmask;
467 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
468
469 e1000_put_hw_semaphore_generic(hw);
470
471 out:
472 return (ret_val);
473 }
474
475 /*
476 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
477 * @hw: pointer to the HW structure
478 * @mask: specifies which semaphore to acquire
479 *
480 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
481 * will also specify which port we're releasing the lock for.
482 */
483 static void
e1000_release_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)484 e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
485 {
486 u32 swfw_sync;
487
488 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
489
490 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) {
491 /* Empty */
492 }
493
494 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
495 swfw_sync &= ~mask;
496 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
497
498 e1000_put_hw_semaphore_generic(hw);
499 }
500
501 /*
502 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
503 * @hw: pointer to the HW structure
504 * @offset: offset of the register to read
505 * @data: pointer to the data returned from the operation
506 *
507 * Read the GG82563 PHY register.
508 */
509 static s32
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)510 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
511 u32 offset, u16 *data)
512 {
513 s32 ret_val;
514 u32 page_select;
515 u16 temp;
516
517 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
518
519 ret_val = e1000_acquire_phy_80003es2lan(hw);
520 if (ret_val)
521 goto out;
522
523 /* Select Configuration Page */
524 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
525 page_select = GG82563_PHY_PAGE_SELECT;
526 } else {
527 /*
528 * Use Alternative Page Select register to access
529 * registers 30 and 31
530 */
531 page_select = GG82563_PHY_PAGE_SELECT_ALT;
532 }
533
534 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
535 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
536 if (ret_val) {
537 e1000_release_phy_80003es2lan(hw);
538 goto out;
539 }
540
541 if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
542 /*
543 * The "ready" bit in the MDIC register may be incorrectly set
544 * before the device has completed the "Page Select" MDI
545 * transaction. So we wait 200us after each MDI command...
546 */
547 usec_delay(200);
548
549 /* ...and verify the command was successful. */
550 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
551
552 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
553 ret_val = -E1000_ERR_PHY;
554 e1000_release_phy_80003es2lan(hw);
555 goto out;
556 }
557
558 usec_delay(200);
559
560 ret_val = e1000_read_phy_reg_mdic(hw,
561 MAX_PHY_REG_ADDRESS & offset,
562 data);
563
564 usec_delay(200);
565 } else
566 ret_val = e1000_read_phy_reg_mdic(hw,
567 MAX_PHY_REG_ADDRESS & offset,
568 data);
569
570 e1000_release_phy_80003es2lan(hw);
571
572 out:
573 return (ret_val);
574 }
575
576 /*
577 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
578 * @hw: pointer to the HW structure
579 * @offset: offset of the register to read
580 * @data: value to write to the register
581 *
582 * Write to the GG82563 PHY register.
583 */
584 static s32
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)585 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
586 u32 offset, u16 data)
587 {
588 s32 ret_val;
589 u32 page_select;
590 u16 temp;
591
592 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
593
594 ret_val = e1000_acquire_phy_80003es2lan(hw);
595 if (ret_val)
596 goto out;
597
598 /* Select Configuration Page */
599 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
600 page_select = GG82563_PHY_PAGE_SELECT;
601 } else {
602 /*
603 * Use Alternative Page Select register to access
604 * registers 30 and 31
605 */
606 page_select = GG82563_PHY_PAGE_SELECT_ALT;
607 }
608
609 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
610 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
611 if (ret_val) {
612 e1000_release_phy_80003es2lan(hw);
613 goto out;
614 }
615
616 if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
617 /*
618 * The "ready" bit in the MDIC register may be incorrectly set
619 * before the device has completed the "Page Select" MDI
620 * transaction. So we wait 200us after each MDI command...
621 */
622 usec_delay(200);
623
624 /* ...and verify the command was successful. */
625 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
626
627 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
628 ret_val = -E1000_ERR_PHY;
629 e1000_release_phy_80003es2lan(hw);
630 goto out;
631 }
632
633 usec_delay(200);
634
635 ret_val = e1000_write_phy_reg_mdic(hw,
636 MAX_PHY_REG_ADDRESS & offset,
637 data);
638
639 usec_delay(200);
640 } else
641 ret_val = e1000_write_phy_reg_mdic(hw,
642 MAX_PHY_REG_ADDRESS & offset,
643 data);
644
645 e1000_release_phy_80003es2lan(hw);
646
647 out:
648 return (ret_val);
649 }
650
651 /*
652 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
653 * @hw: pointer to the HW structure
654 * @offset: offset of the register to read
655 * @words: number of words to write
656 * @data: buffer of data to write to the NVM
657 *
658 * Write "words" of data to the ESB2 NVM.
659 */
660 static s32
e1000_write_nvm_80003es2lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)661 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
662 u16 words, u16 *data)
663 {
664 DEBUGFUNC("e1000_write_nvm_80003es2lan");
665
666 return (e1000_write_nvm_spi(hw, offset, words, data));
667 }
668
669 /*
670 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
671 * @hw: pointer to the HW structure
672 *
673 * Wait a specific amount of time for manageability processes to complete.
674 * This is a function pointer entry point called by the phy module.
675 */
676 static s32
e1000_get_cfg_done_80003es2lan(struct e1000_hw * hw)677 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
678 {
679 s32 timeout = PHY_CFG_TIMEOUT;
680 s32 ret_val = E1000_SUCCESS;
681 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
682
683 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
684
685 if (hw->bus.func == 1)
686 mask = E1000_NVM_CFG_DONE_PORT_1;
687
688 while (timeout) {
689 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
690 break;
691 msec_delay(1);
692 timeout--;
693 }
694 if (!timeout) {
695 DEBUGOUT("MNG configuration cycle has not completed.\n");
696 ret_val = -E1000_ERR_RESET;
697 goto out;
698 }
699
700 out:
701 return (ret_val);
702 }
703
704 /*
705 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
706 * @hw: pointer to the HW structure
707 *
708 * Force the speed and duplex settings onto the PHY. This is a
709 * function pointer entry point called by the phy module.
710 */
711 static s32
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw * hw)712 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
713 {
714 s32 ret_val = E1000_SUCCESS;
715 u16 phy_data;
716 bool link;
717
718 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
719
720 if (!(hw->phy.ops.read_reg))
721 goto out;
722
723 /*
724 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
725 * forced whenever speed and duplex are forced.
726 */
727 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
728 if (ret_val)
729 goto out;
730
731 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
732 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
733 if (ret_val)
734 goto out;
735
736 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
737
738 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
739 if (ret_val)
740 goto out;
741
742 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
743
744 /* Reset the phy to commit changes. */
745 phy_data |= MII_CR_RESET;
746
747 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
748 if (ret_val)
749 goto out;
750
751 usec_delay(1);
752
753 if (hw->phy.autoneg_wait_to_complete) {
754 DEBUGOUT("Waiting for forced speed/duplex link "
755 "on GG82563 phy.\n");
756
757 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
758 100000, &link);
759 if (ret_val)
760 goto out;
761
762 if (!link) {
763 /*
764 * We didn't get link.
765 * Reset the DSP and cross our fingers.
766 */
767 ret_val = e1000_phy_reset_dsp_generic(hw);
768 if (ret_val)
769 goto out;
770 }
771
772 /* Try once more */
773 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
774 100000, &link);
775 if (ret_val)
776 goto out;
777 }
778
779 ret_val =
780 hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
781 if (ret_val)
782 goto out;
783
784 /*
785 * Resetting the phy means we need to verify the TX_CLK corresponds
786 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
787 */
788 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
789 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
790 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
791 else
792 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
793
794 /*
795 * In addition, we must re-enable CRS on Tx for both half and full
796 * duplex.
797 */
798 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
799 ret_val =
800 hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
801
802 out:
803 return (ret_val);
804 }
805
806 /*
807 * e1000_get_cable_length_80003es2lan - Set approximate cable length
808 * @hw: pointer to the HW structure
809 *
810 * Find the approximate cable length as measured by the GG82563 PHY.
811 * This is a function pointer entry point called by the phy module.
812 */
813 static s32
e1000_get_cable_length_80003es2lan(struct e1000_hw * hw)814 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
815 {
816 struct e1000_phy_info *phy = &hw->phy;
817 s32 ret_val = E1000_SUCCESS;
818 u16 phy_data, index;
819
820 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
821
822 if (!(hw->phy.ops.read_reg))
823 goto out;
824
825 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
826 if (ret_val)
827 goto out;
828
829 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
830
831 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
832 ret_val = E1000_ERR_PHY;
833 goto out;
834 }
835
836 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
837 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
838
839 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
840
841 out:
842 return (ret_val);
843 }
844
845 /*
846 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
847 * @hw: pointer to the HW structure
848 * @speed: pointer to speed buffer
849 * @duplex: pointer to duplex buffer
850 *
851 * Retrieve the current speed and duplex configuration.
852 */
853 static s32
e1000_get_link_up_info_80003es2lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)854 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
855 {
856 s32 ret_val;
857
858 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
859
860 if (hw->phy.media_type == e1000_media_type_copper) {
861 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
862 speed,
863 duplex);
864 hw->phy.ops.cfg_on_link_up(hw);
865 } else {
866 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
867 speed,
868 duplex);
869 }
870
871 return (ret_val);
872 }
873
874 /*
875 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
876 * @hw: pointer to the HW structure
877 *
878 * Perform a global reset to the ESB2 controller.
879 */
880 static s32
e1000_reset_hw_80003es2lan(struct e1000_hw * hw)881 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
882 {
883 u32 ctrl;
884 s32 ret_val;
885
886 DEBUGFUNC("e1000_reset_hw_80003es2lan");
887
888 /*
889 * Prevent the PCI-E bus from sticking if there is no TLP connection
890 * on the last TLP read/write transaction when MAC is reset.
891 */
892 ret_val = e1000_disable_pcie_master_generic(hw);
893 if (ret_val) {
894 /* EMPTY */
895 DEBUGOUT("PCI-E Master disable polling has failed.\n");
896 }
897
898 DEBUGOUT("Masking off all interrupts\n");
899 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
900
901 E1000_WRITE_REG(hw, E1000_RCTL, 0);
902 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
903 E1000_WRITE_FLUSH(hw);
904
905 msec_delay(10);
906
907 ctrl = E1000_READ_REG(hw, E1000_CTRL);
908
909 ret_val = e1000_acquire_phy_80003es2lan(hw);
910 DEBUGOUT("Issuing a global reset to MAC\n");
911 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
912 e1000_release_phy_80003es2lan(hw);
913
914 ret_val = e1000_get_auto_rd_done_generic(hw);
915 if (ret_val)
916 /* We don't want to continue accessing MAC registers. */
917 goto out;
918
919 /* Clear any pending interrupt events. */
920 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
921 (void) E1000_READ_REG(hw, E1000_ICR);
922
923 ret_val = e1000_check_alt_mac_addr_generic(hw);
924
925 out:
926 return (ret_val);
927 }
928
929 /*
930 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
931 * @hw: pointer to the HW structure
932 *
933 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
934 */
935 static s32
e1000_init_hw_80003es2lan(struct e1000_hw * hw)936 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
937 {
938 struct e1000_mac_info *mac = &hw->mac;
939 u32 reg_data;
940 s32 ret_val;
941 u16 i;
942
943 DEBUGFUNC("e1000_init_hw_80003es2lan");
944
945 e1000_initialize_hw_bits_80003es2lan(hw);
946
947 /* Initialize identification LED */
948 ret_val = mac->ops.id_led_init(hw);
949 if (ret_val) {
950 /* EMPTY */
951 DEBUGOUT("Error initializing identification LED\n");
952 /* This is not fatal and we should not stop init due to this */
953 }
954
955 /* Disabling VLAN filtering */
956 DEBUGOUT("Initializing the IEEE VLAN\n");
957 mac->ops.clear_vfta(hw);
958
959 /* Setup the receive address. */
960 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
961
962 /* Zero out the Multicast HASH table */
963 DEBUGOUT("Zeroing the MTA\n");
964 for (i = 0; i < mac->mta_reg_count; i++)
965 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
966
967 /* Setup link and flow control */
968 ret_val = mac->ops.setup_link(hw);
969
970 /* Set the transmit descriptor write-back policy */
971 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
972 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
973 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
974 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
975
976 /* ...for both queues. */
977 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
978 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
979 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
980 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
981
982 /* Enable retransmit on late collisions */
983 reg_data = E1000_READ_REG(hw, E1000_TCTL);
984 reg_data |= E1000_TCTL_RTLC;
985 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
986
987 /* Configure Gigabit Carry Extend Padding */
988 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
989 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
990 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
991 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
992
993 /* Configure Transmit Inter-Packet Gap */
994 reg_data = E1000_READ_REG(hw, E1000_TIPG);
995 reg_data &= ~E1000_TIPG_IPGT_MASK;
996 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
997 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
998
999 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
1000 reg_data &= ~0x00100000;
1001 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
1002
1003 /* default to true to enable the MDIC W/A */
1004 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
1005
1006 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1007 E1000_KMRNCTRLSTA_OFFSET >>
1008 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
1009 &i);
1010 if (!ret_val) {
1011 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
1012 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
1013 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
1014 }
1015
1016 /*
1017 * Clear all of the statistics registers (clear on read). It is
1018 * important that we do this after we have tried to establish link
1019 * because the symbol error count will increment wildly if there
1020 * is no link.
1021 */
1022 e1000_clear_hw_cntrs_80003es2lan(hw);
1023
1024 return (ret_val);
1025 }
1026
1027 /*
1028 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
1029 * @hw: pointer to the HW structure
1030 *
1031 * Initializes required hardware-dependent bits needed for normal operation.
1032 */
1033 static void
e1000_initialize_hw_bits_80003es2lan(struct e1000_hw * hw)1034 e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1035 {
1036 u32 reg;
1037
1038 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
1039
1040 /* Transmit Descriptor Control 0 */
1041 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1042 reg |= (1 << 22);
1043 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1044
1045 /* Transmit Descriptor Control 1 */
1046 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1047 reg |= (1 << 22);
1048 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1049
1050 /* Transmit Arbitration Control 0 */
1051 reg = E1000_READ_REG(hw, E1000_TARC(0));
1052 reg &= ~(0xF << 27); /* 30:27 */
1053 if (hw->phy.media_type != e1000_media_type_copper)
1054 reg &= ~(1 << 20);
1055 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1056
1057 /* Transmit Arbitration Control 1 */
1058 reg = E1000_READ_REG(hw, E1000_TARC(1));
1059 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1060 reg &= ~(1 << 28);
1061 else
1062 reg |= (1 << 28);
1063 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1064 }
1065
1066 /*
1067 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1068 * @hw: pointer to the HW structure
1069 *
1070 * Setup some GG82563 PHY registers for obtaining link
1071 */
1072 static s32
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw * hw)1073 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1074 {
1075 struct e1000_phy_info *phy = &hw->phy;
1076 s32 ret_val;
1077 u32 ctrl_ext;
1078 u16 data;
1079
1080 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1081
1082 if (!phy->reset_disable) {
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1084 &data);
1085 if (ret_val)
1086 goto out;
1087
1088 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1089 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1090 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1091
1092 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1093 data);
1094 if (ret_val)
1095 goto out;
1096
1097 /*
1098 * Options:
1099 * MDI/MDI-X = 0 (default)
1100 * 0 - Auto for all speeds
1101 * 1 - MDI mode
1102 * 2 - MDI-X mode
1103 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1104 */
1105 ret_val =
1106 hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1107 if (ret_val)
1108 goto out;
1109
1110 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1111
1112 switch (phy->mdix) {
1113 case 1:
1114 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1115 break;
1116 case 2:
1117 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1118 break;
1119 case 0:
1120 default:
1121 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1122 break;
1123 }
1124
1125 /*
1126 * Options:
1127 * disable_polarity_correction = 0 (default)
1128 * Automatic Correction for Reversed Cable Polarity
1129 * 0 - Disabled
1130 * 1 - Enabled
1131 */
1132 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1133 if (phy->disable_polarity_correction)
1134 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1135
1136 ret_val =
1137 hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1138 if (ret_val)
1139 goto out;
1140
1141 /* SW Reset the PHY so all changes take effect */
1142 ret_val = hw->phy.ops.commit(hw);
1143 if (ret_val) {
1144 DEBUGOUT("Error Resetting the PHY\n");
1145 goto out;
1146 }
1147
1148 }
1149
1150 /* Bypass Rx and Tx FIFO's */
1151 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1152 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1153 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1154 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1155 if (ret_val)
1156 goto out;
1157
1158 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1159 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1160 &data);
1161 if (ret_val)
1162 goto out;
1163
1164 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1165 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1166 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1167 data);
1168 if (ret_val)
1169 goto out;
1170
1171 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1172 if (ret_val)
1173 goto out;
1174
1175 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1176 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1177 if (ret_val)
1178 goto out;
1179
1180 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1181 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1182 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1183
1184 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1185 if (ret_val)
1186 goto out;
1187
1188 /*
1189 * Do not init these registers when the HW is in IAMT mode, since the
1190 * firmware will have already initialized them. We only initialize
1191 * them if the HW is not in IAMT mode.
1192 */
1193 if (!(hw->mac.ops.check_mng_mode(hw))) {
1194 /* Enable Electrical Idle on the PHY */
1195 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1196 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1197 data);
1198 if (ret_val)
1199 goto out;
1200 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1201 &data);
1202
1203 if (ret_val)
1204 goto out;
1205
1206 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1207 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1208 data);
1209
1210 if (ret_val)
1211 goto out;
1212 }
1213
1214 /*
1215 * Workaround: Disable padding in Kumeran interface in the MAC
1216 * and in the PHY to avoid CRC errors.
1217 */
1218 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1219 if (ret_val)
1220 goto out;
1221
1222 data |= GG82563_ICR_DIS_PADDING;
1223 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1224 if (ret_val)
1225 goto out;
1226
1227 out:
1228 return (ret_val);
1229 }
1230
1231 /*
1232 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1233 * @hw: pointer to the HW structure
1234 *
1235 * Essentially a wrapper for setting up all things "copper" related.
1236 * This is a function pointer entry point called by the mac module.
1237 */
1238 static s32
e1000_setup_copper_link_80003es2lan(struct e1000_hw * hw)1239 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1240 {
1241 u32 ctrl;
1242 s32 ret_val;
1243 u16 reg_data;
1244
1245 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1246
1247 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1248 ctrl |= E1000_CTRL_SLU;
1249 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1250 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1251
1252 /*
1253 * Set the mac to wait the maximum time between each
1254 * iteration and increase the max iterations when
1255 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1256 */
1257 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1258 0xFFFF);
1259 if (ret_val)
1260 goto out;
1261 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1262 ®_data);
1263 if (ret_val)
1264 goto out;
1265 reg_data |= 0x3F;
1266 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1267 reg_data);
1268 if (ret_val)
1269 goto out;
1270 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1271 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1272 ®_data);
1273 if (ret_val)
1274 goto out;
1275 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1276 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1277 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1278 reg_data);
1279 if (ret_val)
1280 goto out;
1281
1282 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1283 if (ret_val)
1284 goto out;
1285
1286 ret_val = e1000_setup_copper_link_generic(hw);
1287
1288 out:
1289 return (ret_val);
1290 }
1291
1292 /*
1293 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1294 * @hw: pointer to the HW structure
1295 * @duplex: current duplex setting
1296 *
1297 * Configure the KMRN interface by applying last minute quirks for
1298 * 10/100 operation.
1299 */
1300 static s32
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw * hw)1301 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1302 {
1303 s32 ret_val = E1000_SUCCESS;
1304 u16 speed;
1305 u16 duplex;
1306
1307 DEBUGFUNC("e1000_configure_on_link_up");
1308
1309 if (hw->phy.media_type == e1000_media_type_copper) {
1310
1311 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1312 &speed,
1313 &duplex);
1314 if (ret_val)
1315 goto out;
1316
1317 if (speed == SPEED_1000)
1318 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1319 else
1320 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1321 }
1322
1323 out:
1324 return (ret_val);
1325 }
1326
1327 /*
1328 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1329 * @hw: pointer to the HW structure
1330 * @duplex: current duplex setting
1331 *
1332 * Configure the KMRN interface by applying last minute quirks for
1333 * 10/100 operation.
1334 */
1335 static s32
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw * hw,u16 duplex)1336 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1337 {
1338 s32 ret_val = E1000_SUCCESS;
1339 u32 tipg;
1340 u32 i = 0;
1341 u16 reg_data, reg_data2;
1342
1343 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1344
1345 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1346 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1347 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1348 reg_data);
1349 if (ret_val)
1350 goto out;
1351
1352 /* Configure Transmit Inter-Packet Gap */
1353 tipg = E1000_READ_REG(hw, E1000_TIPG);
1354 tipg &= ~E1000_TIPG_IPGT_MASK;
1355 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1356 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1357
1358
1359 do {
1360 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1361 ®_data);
1362 if (ret_val)
1363 goto out;
1364
1365 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1366 ®_data2);
1367 if (ret_val)
1368 goto out;
1369 i++;
1370 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1371
1372 if (duplex == HALF_DUPLEX)
1373 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1374 else
1375 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1376
1377 ret_val =
1378 hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1379
1380 out:
1381 return (ret_val);
1382 }
1383
1384 /*
1385 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1386 * @hw: pointer to the HW structure
1387 *
1388 * Configure the KMRN interface by applying last minute quirks for
1389 * gigabit operation.
1390 */
1391 static s32
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw * hw)1392 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1393 {
1394 s32 ret_val = E1000_SUCCESS;
1395 u16 reg_data, reg_data2;
1396 u32 tipg;
1397 u32 i = 0;
1398
1399 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1400
1401 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1402 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1403 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1404 reg_data);
1405 if (ret_val)
1406 goto out;
1407
1408 /* Configure Transmit Inter-Packet Gap */
1409 tipg = E1000_READ_REG(hw, E1000_TIPG);
1410 tipg &= ~E1000_TIPG_IPGT_MASK;
1411 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1412 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1413
1414
1415 do {
1416 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1417 ®_data);
1418 if (ret_val)
1419 goto out;
1420
1421 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1422 ®_data2);
1423 if (ret_val)
1424 goto out;
1425 i++;
1426 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1427
1428 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1429 ret_val =
1430 hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1431
1432 out:
1433 return (ret_val);
1434 }
1435
1436 /*
1437 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1438 * @hw: pointer to the HW structure
1439 * @offset: register offset to be read
1440 * @data: pointer to the read data
1441 *
1442 * Acquire semaphore, then read the PHY register at offset
1443 * using the kumeran interface. The information retrieved is stored in data.
1444 * Release the semaphore before exiting.
1445 */
1446 static s32
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)1447 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data)
1448 {
1449 u32 kmrnctrlsta;
1450 s32 ret_val = E1000_SUCCESS;
1451
1452 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1453
1454 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1455 if (ret_val)
1456 goto out;
1457
1458 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1459 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1460 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1461
1462 usec_delay(2);
1463
1464 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1465 *data = (u16)kmrnctrlsta;
1466
1467 e1000_release_mac_csr_80003es2lan(hw);
1468
1469 out:
1470 return (ret_val);
1471 }
1472
1473 /*
1474 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1475 * @hw: pointer to the HW structure
1476 * @offset: register offset to write to
1477 * @data: data to write at register offset
1478 *
1479 * Acquire semaphore, then write the data to PHY register
1480 * at the offset using the kumeran interface. Release semaphore
1481 * before exiting.
1482 */
1483 static s32
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)1484 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data)
1485 {
1486 u32 kmrnctrlsta;
1487 s32 ret_val = E1000_SUCCESS;
1488
1489 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1490
1491 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1492 if (ret_val)
1493 goto out;
1494
1495 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1496 E1000_KMRNCTRLSTA_OFFSET) | data;
1497 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1498
1499 usec_delay(2);
1500
1501 e1000_release_mac_csr_80003es2lan(hw);
1502
1503 out:
1504 return (ret_val);
1505 }
1506
1507 /*
1508 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1509 * @hw: pointer to the HW structure
1510 */
1511 static s32
e1000_read_mac_addr_80003es2lan(struct e1000_hw * hw)1512 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1513 {
1514 s32 ret_val = E1000_SUCCESS;
1515
1516 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1517 /*
1518 * If there's an alternate MAC address place it in RAR0
1519 * so that it will override the Si installed default perm
1520 * address.
1521 */
1522 ret_val = e1000_check_alt_mac_addr_generic(hw);
1523 if (ret_val)
1524 goto out;
1525
1526 ret_val = e1000_read_mac_addr_generic(hw);
1527
1528 out:
1529 return (ret_val);
1530 }
1531
1532 /*
1533 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1534 * @hw: pointer to the HW structure
1535 *
1536 * In the case of a PHY power down to save power, or to turn off link during a
1537 * driver unload, or wake on lan is not enabled, remove the link.
1538 */
1539 static void
e1000_power_down_phy_copper_80003es2lan(struct e1000_hw * hw)1540 e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1541 {
1542 /* If the management interface is not enabled, then power down */
1543 if (!(hw->mac.ops.check_mng_mode(hw) ||
1544 hw->phy.ops.check_reset_block(hw)))
1545 e1000_power_down_phy_copper(hw);
1546 }
1547
1548 /*
1549 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1550 * @hw: pointer to the HW structure
1551 *
1552 * Clears the hardware counters by reading the counter registers.
1553 */
1554 static void
e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw * hw)1555 e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1556 {
1557 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1558
1559 e1000_clear_hw_cntrs_base_generic(hw);
1560
1561 (void) E1000_READ_REG(hw, E1000_PRC64);
1562 (void) E1000_READ_REG(hw, E1000_PRC127);
1563 (void) E1000_READ_REG(hw, E1000_PRC255);
1564 (void) E1000_READ_REG(hw, E1000_PRC511);
1565 (void) E1000_READ_REG(hw, E1000_PRC1023);
1566 (void) E1000_READ_REG(hw, E1000_PRC1522);
1567 (void) E1000_READ_REG(hw, E1000_PTC64);
1568 (void) E1000_READ_REG(hw, E1000_PTC127);
1569 (void) E1000_READ_REG(hw, E1000_PTC255);
1570 (void) E1000_READ_REG(hw, E1000_PTC511);
1571 (void) E1000_READ_REG(hw, E1000_PTC1023);
1572 (void) E1000_READ_REG(hw, E1000_PTC1522);
1573
1574 (void) E1000_READ_REG(hw, E1000_ALGNERRC);
1575 (void) E1000_READ_REG(hw, E1000_RXERRC);
1576 (void) E1000_READ_REG(hw, E1000_TNCRS);
1577 (void) E1000_READ_REG(hw, E1000_CEXTERR);
1578 (void) E1000_READ_REG(hw, E1000_TSCTC);
1579 (void) E1000_READ_REG(hw, E1000_TSCTFC);
1580
1581 (void) E1000_READ_REG(hw, E1000_MGTPRC);
1582 (void) E1000_READ_REG(hw, E1000_MGTPDC);
1583 (void) E1000_READ_REG(hw, E1000_MGTPTC);
1584
1585 (void) E1000_READ_REG(hw, E1000_IAC);
1586 (void) E1000_READ_REG(hw, E1000_ICRXOC);
1587
1588 (void) E1000_READ_REG(hw, E1000_ICRXPTC);
1589 (void) E1000_READ_REG(hw, E1000_ICRXATC);
1590 (void) E1000_READ_REG(hw, E1000_ICTXPTC);
1591 (void) E1000_READ_REG(hw, E1000_ICTXATC);
1592 (void) E1000_READ_REG(hw, E1000_ICTXQEC);
1593 (void) E1000_READ_REG(hw, E1000_ICTXQMTC);
1594 (void) E1000_READ_REG(hw, E1000_ICRXDMTC);
1595 }
1596