1 /* $NetBSD: amdgpu_dcn10_dpp_dscl.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn10_dpp_dscl.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31 #include "dm_services.h"
32
33 #include "core_types.h"
34
35 #include "reg_helper.h"
36 #include "dcn10_dpp.h"
37 #include "basics/conversion.h"
38
39
40 #define NUM_PHASES 64
41 #define HORZ_MAX_TAPS 8
42 #define VERT_MAX_TAPS 8
43
44 #define BLACK_OFFSET_RGB_Y 0x0
45 #define BLACK_OFFSET_CBCR 0x8000
46
47 #define REG(reg)\
48 dpp->tf_regs->reg
49
50 #define CTX \
51 dpp->base.ctx
52
53 #undef FN
54 #define FN(reg_name, field_name) \
55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56
57 enum dcn10_coef_filter_type_sel {
58 SCL_COEF_LUMA_VERT_FILTER = 0,
59 SCL_COEF_LUMA_HORZ_FILTER = 1,
60 SCL_COEF_CHROMA_VERT_FILTER = 2,
61 SCL_COEF_CHROMA_HORZ_FILTER = 3,
62 SCL_COEF_ALPHA_VERT_FILTER = 4,
63 SCL_COEF_ALPHA_HORZ_FILTER = 5
64 };
65
66 enum dscl_autocal_mode {
67 AUTOCAL_MODE_OFF = 0,
68
69 /* Autocal calculate the scaling ratio and initial phase and the
70 * DSCL_MODE_SEL must be set to 1
71 */
72 AUTOCAL_MODE_AUTOSCALE = 1,
73 /* Autocal perform auto centering without replication and the
74 * DSCL_MODE_SEL must be set to 0
75 */
76 AUTOCAL_MODE_AUTOCENTER = 2,
77 /* Autocal perform auto centering and auto replication and the
78 * DSCL_MODE_SEL must be set to 0
79 */
80 AUTOCAL_MODE_AUTOREPLICATE = 3
81 };
82
83 enum dscl_mode_sel {
84 DSCL_MODE_SCALING_444_BYPASS = 0,
85 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
86 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
87 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
88 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
89 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
90 DSCL_MODE_DSCL_BYPASS = 6
91 };
92
dpp1_dscl_set_overscan(struct dcn10_dpp * dpp,const struct scaler_data * data)93 static void dpp1_dscl_set_overscan(
94 struct dcn10_dpp *dpp,
95 const struct scaler_data *data)
96 {
97 uint32_t left = data->recout.x;
98 uint32_t top = data->recout.y;
99
100 int right = data->h_active - data->recout.x - data->recout.width;
101 int bottom = data->v_active - data->recout.y - data->recout.height;
102
103 if (right < 0) {
104 BREAK_TO_DEBUGGER();
105 right = 0;
106 }
107 if (bottom < 0) {
108 BREAK_TO_DEBUGGER();
109 bottom = 0;
110 }
111
112 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
113 EXT_OVERSCAN_LEFT, left,
114 EXT_OVERSCAN_RIGHT, right);
115
116 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
117 EXT_OVERSCAN_BOTTOM, bottom,
118 EXT_OVERSCAN_TOP, top);
119 }
120
dpp1_dscl_set_otg_blank(struct dcn10_dpp * dpp,const struct scaler_data * data)121 static void dpp1_dscl_set_otg_blank(
122 struct dcn10_dpp *dpp, const struct scaler_data *data)
123 {
124 uint32_t h_blank_start = data->h_active;
125 uint32_t h_blank_end = 0;
126 uint32_t v_blank_start = data->v_active;
127 uint32_t v_blank_end = 0;
128
129 REG_SET_2(OTG_H_BLANK, 0,
130 OTG_H_BLANK_START, h_blank_start,
131 OTG_H_BLANK_END, h_blank_end);
132
133 REG_SET_2(OTG_V_BLANK, 0,
134 OTG_V_BLANK_START, v_blank_start,
135 OTG_V_BLANK_END, v_blank_end);
136 }
137
dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)138 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
139 {
140 if (depth == LB_PIXEL_DEPTH_30BPP)
141 return 0; /* 10 bpc */
142 else if (depth == LB_PIXEL_DEPTH_24BPP)
143 return 1; /* 8 bpc */
144 else if (depth == LB_PIXEL_DEPTH_18BPP)
145 return 2; /* 6 bpc */
146 else if (depth == LB_PIXEL_DEPTH_36BPP)
147 return 3; /* 12 bpc */
148 else {
149 ASSERT(0);
150 return -1; /* Unsupported */
151 }
152 }
153
dpp1_dscl_is_video_format(enum pixel_format format)154 static bool dpp1_dscl_is_video_format(enum pixel_format format)
155 {
156 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
157 && format <= PIXEL_FORMAT_VIDEO_END)
158 return true;
159 else
160 return false;
161 }
162
dpp1_dscl_is_420_format(enum pixel_format format)163 static bool dpp1_dscl_is_420_format(enum pixel_format format)
164 {
165 if (format == PIXEL_FORMAT_420BPP8 ||
166 format == PIXEL_FORMAT_420BPP10)
167 return true;
168 else
169 return false;
170 }
171
dpp1_dscl_get_dscl_mode(struct dpp * dpp_base,const struct scaler_data * data,bool dbg_always_scale)172 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
173 struct dpp *dpp_base,
174 const struct scaler_data *data,
175 bool dbg_always_scale)
176 {
177 const long long one = dc_fixpt_one.value;
178
179 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
180 /* DSCL is processing data in fixed format */
181 if (data->format == PIXEL_FORMAT_FP16)
182 return DSCL_MODE_DSCL_BYPASS;
183 }
184
185 if (data->ratios.horz.value == one
186 && data->ratios.vert.value == one
187 && data->ratios.horz_c.value == one
188 && data->ratios.vert_c.value == one
189 && !dbg_always_scale)
190 return DSCL_MODE_SCALING_444_BYPASS;
191
192 if (!dpp1_dscl_is_420_format(data->format)) {
193 if (dpp1_dscl_is_video_format(data->format))
194 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
195 else
196 return DSCL_MODE_SCALING_444_RGB_ENABLE;
197 }
198 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
199 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
200 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
201 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
202
203 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
204 }
205
dpp1_dscl_set_lb(struct dcn10_dpp * dpp,const struct line_buffer_params * lb_params,enum lb_memory_config mem_size_config)206 static void dpp1_dscl_set_lb(
207 struct dcn10_dpp *dpp,
208 const struct line_buffer_params *lb_params,
209 enum lb_memory_config mem_size_config)
210 {
211 /* LB */
212 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
213 /* DSCL caps: pixel data processed in fixed format */
214 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
215 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
216
217 REG_SET_7(LB_DATA_FORMAT, 0,
218 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
219 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
220 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
221 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
222 DITHER_EN, 0, /* Dithering enable: Disabled */
223 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
224 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
225 }
226 else {
227 /* DSCL caps: pixel data processed in float format */
228 REG_SET_2(LB_DATA_FORMAT, 0,
229 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
230 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
231 }
232
233 REG_SET_2(LB_MEMORY_CTRL, 0,
234 MEMORY_CONFIG, mem_size_config,
235 LB_MAX_PARTITIONS, 63);
236 }
237
dpp1_dscl_get_filter_coeffs_64p(int taps,struct fixed31_32 ratio)238 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
239 {
240 if (taps == 8)
241 return get_filter_8tap_64p(ratio);
242 else if (taps == 7)
243 return get_filter_7tap_64p(ratio);
244 else if (taps == 6)
245 return get_filter_6tap_64p(ratio);
246 else if (taps == 5)
247 return get_filter_5tap_64p(ratio);
248 else if (taps == 4)
249 return get_filter_4tap_64p(ratio);
250 else if (taps == 3)
251 return get_filter_3tap_64p(ratio);
252 else if (taps == 2)
253 return get_filter_2tap_64p();
254 else if (taps == 1)
255 return NULL;
256 else {
257 /* should never happen, bug */
258 BREAK_TO_DEBUGGER();
259 return NULL;
260 }
261 }
262
dpp1_dscl_set_scaler_filter(struct dcn10_dpp * dpp,uint32_t taps,enum dcn10_coef_filter_type_sel filter_type,const uint16_t * filter)263 static void dpp1_dscl_set_scaler_filter(
264 struct dcn10_dpp *dpp,
265 uint32_t taps,
266 enum dcn10_coef_filter_type_sel filter_type,
267 const uint16_t *filter)
268 {
269 const int tap_pairs = (taps + 1) / 2;
270 int phase;
271 int pair;
272 uint16_t odd_coef, even_coef;
273
274 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
275 SCL_COEF_RAM_TAP_PAIR_IDX, 0,
276 SCL_COEF_RAM_PHASE, 0,
277 SCL_COEF_RAM_FILTER_TYPE, filter_type);
278
279 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
280 for (pair = 0; pair < tap_pairs; pair++) {
281 even_coef = filter[phase * taps + 2 * pair];
282 if ((pair * 2 + 1) < taps)
283 odd_coef = filter[phase * taps + 2 * pair + 1];
284 else
285 odd_coef = 0;
286
287 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
288 /* Even tap coefficient (bits 1:0 fixed to 0) */
289 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
290 /* Write/read control for even coefficient */
291 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
292 /* Odd tap coefficient (bits 1:0 fixed to 0) */
293 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
294 /* Write/read control for odd coefficient */
295 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
296 }
297 }
298
299 }
300
dpp1_dscl_set_scl_filter(struct dcn10_dpp * dpp,const struct scaler_data * scl_data,bool chroma_coef_mode)301 static void dpp1_dscl_set_scl_filter(
302 struct dcn10_dpp *dpp,
303 const struct scaler_data *scl_data,
304 bool chroma_coef_mode)
305 {
306 bool h_2tap_hardcode_coef_en = false;
307 bool v_2tap_hardcode_coef_en = false;
308 bool h_2tap_sharp_en = false;
309 bool v_2tap_sharp_en = false;
310 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
311 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
312 bool coef_ram_current;
313 const uint16_t *filter_h = NULL;
314 const uint16_t *filter_v = NULL;
315 const uint16_t *filter_h_c = NULL;
316 const uint16_t *filter_v_c = NULL;
317
318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
319 && scl_data->taps.h_taps_c < 3
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
321 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
322 && scl_data->taps.v_taps_c < 3
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
324
325 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
326 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
327
328 REG_UPDATE_6(DSCL_2TAP_CONTROL,
329 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
330 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
331 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
332 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
333 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
334 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
335
336 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
337 bool filter_updated = false;
338
339 filter_h = dpp1_dscl_get_filter_coeffs_64p(
340 scl_data->taps.h_taps, scl_data->ratios.horz);
341 filter_v = dpp1_dscl_get_filter_coeffs_64p(
342 scl_data->taps.v_taps, scl_data->ratios.vert);
343
344 filter_updated = (filter_h && (filter_h != dpp->filter_h))
345 || (filter_v && (filter_v != dpp->filter_v));
346
347 if (chroma_coef_mode) {
348 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
349 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
350 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
351 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
352 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
353 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
354 }
355
356 if (filter_updated) {
357 uint32_t scl_mode = REG_READ(SCL_MODE);
358
359 if (!h_2tap_hardcode_coef_en && filter_h) {
360 dpp1_dscl_set_scaler_filter(
361 dpp, scl_data->taps.h_taps,
362 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
363 }
364 dpp->filter_h = filter_h;
365 if (!v_2tap_hardcode_coef_en && filter_v) {
366 dpp1_dscl_set_scaler_filter(
367 dpp, scl_data->taps.v_taps,
368 SCL_COEF_LUMA_VERT_FILTER, filter_v);
369 }
370 dpp->filter_v = filter_v;
371 if (chroma_coef_mode) {
372 if (!h_2tap_hardcode_coef_en && filter_h_c) {
373 dpp1_dscl_set_scaler_filter(
374 dpp, scl_data->taps.h_taps_c,
375 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
376 }
377 if (!v_2tap_hardcode_coef_en && filter_v_c) {
378 dpp1_dscl_set_scaler_filter(
379 dpp, scl_data->taps.v_taps_c,
380 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
381 }
382 }
383 dpp->filter_h_c = filter_h_c;
384 dpp->filter_v_c = filter_v_c;
385
386 coef_ram_current = get_reg_field_value_ex(
387 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
388 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
389
390 /* Swap coefficient RAM and set chroma coefficient mode */
391 REG_SET_2(SCL_MODE, scl_mode,
392 SCL_COEF_RAM_SELECT, !coef_ram_current,
393 SCL_CHROMA_COEF_MODE, chroma_coef_mode);
394 }
395 }
396 }
397
dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)398 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
399 {
400 if (depth == LB_PIXEL_DEPTH_30BPP)
401 return 10;
402 else if (depth == LB_PIXEL_DEPTH_24BPP)
403 return 8;
404 else if (depth == LB_PIXEL_DEPTH_18BPP)
405 return 6;
406 else if (depth == LB_PIXEL_DEPTH_36BPP)
407 return 12;
408 else {
409 BREAK_TO_DEBUGGER();
410 return -1; /* Unsupported */
411 }
412 }
413
dpp1_dscl_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)414 void dpp1_dscl_calc_lb_num_partitions(
415 const struct scaler_data *scl_data,
416 enum lb_memory_config lb_config,
417 int *num_part_y,
418 int *num_part_c)
419 {
420 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
421 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
422
423 int line_size = scl_data->viewport.width < scl_data->recout.width ?
424 scl_data->viewport.width : scl_data->recout.width;
425 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
426 scl_data->viewport_c.width : scl_data->recout.width;
427
428 if (line_size == 0)
429 line_size = 1;
430
431 if (line_size_c == 0)
432 line_size_c = 1;
433
434
435 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
436 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
437 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
438 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
439
440 if (lb_config == LB_MEMORY_CONFIG_1) {
441 lb_memory_size = 816;
442 lb_memory_size_c = 816;
443 lb_memory_size_a = 984;
444 } else if (lb_config == LB_MEMORY_CONFIG_2) {
445 lb_memory_size = 1088;
446 lb_memory_size_c = 1088;
447 lb_memory_size_a = 1312;
448 } else if (lb_config == LB_MEMORY_CONFIG_3) {
449 /* 420 mode: using 3rd mem from Y, Cr and Cb */
450 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
451 lb_memory_size_c = 816 + 1088;
452 lb_memory_size_a = 984 + 1312 + 456;
453 } else {
454 lb_memory_size = 816 + 1088 + 848;
455 lb_memory_size_c = 816 + 1088 + 848;
456 lb_memory_size_a = 984 + 1312 + 456;
457 }
458 *num_part_y = lb_memory_size / memory_line_size_y;
459 *num_part_c = lb_memory_size_c / memory_line_size_c;
460 num_partitions_a = lb_memory_size_a / memory_line_size_a;
461
462 if (scl_data->lb_params.alpha_en
463 && (num_partitions_a < *num_part_y))
464 *num_part_y = num_partitions_a;
465
466 if (*num_part_y > 64)
467 *num_part_y = 64;
468 if (*num_part_c > 64)
469 *num_part_c = 64;
470
471 }
472
dpp1_dscl_is_lb_conf_valid(int ceil_vratio,int num_partitions,int vtaps)473 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
474 {
475 if (ceil_vratio > 2)
476 return vtaps <= (num_partitions - ceil_vratio + 2);
477 else
478 return vtaps <= num_partitions;
479 }
480
481 /*find first match configuration which meets the min required lb size*/
dpp1_dscl_find_lb_memory_config(struct dcn10_dpp * dpp,const struct scaler_data * scl_data)482 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
483 const struct scaler_data *scl_data)
484 {
485 int num_part_y, num_part_c;
486 int vtaps = scl_data->taps.v_taps;
487 int vtaps_c = scl_data->taps.v_taps_c;
488 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
489 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
490 enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
491
492 if (dpp->base.ctx->dc->debug.use_max_lb)
493 return mem_cfg;
494
495 dpp->base.caps->dscl_calc_lb_num_partitions(
496 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
497
498 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
499 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
500 return LB_MEMORY_CONFIG_1;
501
502 dpp->base.caps->dscl_calc_lb_num_partitions(
503 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
504
505 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
506 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
507 return LB_MEMORY_CONFIG_2;
508
509 if (scl_data->format == PIXEL_FORMAT_420BPP8
510 || scl_data->format == PIXEL_FORMAT_420BPP10) {
511 dpp->base.caps->dscl_calc_lb_num_partitions(
512 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
513
514 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
515 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
516 return LB_MEMORY_CONFIG_3;
517 }
518
519 dpp->base.caps->dscl_calc_lb_num_partitions(
520 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
521
522 /*Ensure we can support the requested number of vtaps*/
523 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
524 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
525
526 return LB_MEMORY_CONFIG_0;
527 }
528
dpp1_dscl_set_scaler_auto_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)529 void dpp1_dscl_set_scaler_auto_scale(
530 struct dpp *dpp_base,
531 const struct scaler_data *scl_data)
532 {
533 enum lb_memory_config lb_config;
534 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
535 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
536 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
537 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
538 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
539
540 dpp1_dscl_set_overscan(dpp, scl_data);
541
542 dpp1_dscl_set_otg_blank(dpp, scl_data);
543
544 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
545
546 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
547 return;
548
549 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
550 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
551
552 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
553 return;
554
555 /* TODO: v_min */
556 REG_SET_3(DSCL_AUTOCAL, 0,
557 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
558 AUTOCAL_NUM_PIPE, 0,
559 AUTOCAL_PIPE_ID, 0);
560
561 /* Black offsets */
562 if (ycbcr)
563 REG_SET_2(SCL_BLACK_OFFSET, 0,
564 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
565 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
566 else
567
568 REG_SET_2(SCL_BLACK_OFFSET, 0,
569 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
570 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
571
572 REG_SET_4(SCL_TAP_CONTROL, 0,
573 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
574 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
575 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
576 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
577
578 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
579 }
580
581
dpp1_dscl_set_manual_ratio_init(struct dcn10_dpp * dpp,const struct scaler_data * data)582 static void dpp1_dscl_set_manual_ratio_init(
583 struct dcn10_dpp *dpp, const struct scaler_data *data)
584 {
585 uint32_t init_frac = 0;
586 uint32_t init_int = 0;
587
588 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
589 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
590
591 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
592 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
593
594 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
595 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
596
597 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
598 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
599
600 /*
601 * 0.24 format for fraction, first five bits zeroed
602 */
603 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
604 init_int = dc_fixpt_floor(data->inits.h);
605 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
606 SCL_H_INIT_FRAC, init_frac,
607 SCL_H_INIT_INT, init_int);
608
609 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
610 init_int = dc_fixpt_floor(data->inits.h_c);
611 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
612 SCL_H_INIT_FRAC_C, init_frac,
613 SCL_H_INIT_INT_C, init_int);
614
615 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
616 init_int = dc_fixpt_floor(data->inits.v);
617 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
618 SCL_V_INIT_FRAC, init_frac,
619 SCL_V_INIT_INT, init_int);
620
621 if (REG(SCL_VERT_FILTER_INIT_BOT)) {
622 init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
623 init_int = dc_fixpt_floor(data->inits.v_bot);
624 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
625 SCL_V_INIT_FRAC_BOT, init_frac,
626 SCL_V_INIT_INT_BOT, init_int);
627 }
628
629 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
630 init_int = dc_fixpt_floor(data->inits.v_c);
631 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
632 SCL_V_INIT_FRAC_C, init_frac,
633 SCL_V_INIT_INT_C, init_int);
634
635 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
636 init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
637 init_int = dc_fixpt_floor(data->inits.v_c_bot);
638 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
639 SCL_V_INIT_FRAC_BOT_C, init_frac,
640 SCL_V_INIT_INT_BOT_C, init_int);
641 }
642 }
643
644
645
dpp1_dscl_set_recout(struct dcn10_dpp * dpp,const struct rect * recout)646 static void dpp1_dscl_set_recout(
647 struct dcn10_dpp *dpp, const struct rect *recout)
648 {
649 int visual_confirm_on = 0;
650 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
651 visual_confirm_on = 1;
652
653 REG_SET_2(RECOUT_START, 0,
654 /* First pixel of RECOUT */
655 RECOUT_START_X, recout->x,
656 /* First line of RECOUT */
657 RECOUT_START_Y, recout->y);
658
659 REG_SET_2(RECOUT_SIZE, 0,
660 /* Number of RECOUT horizontal pixels */
661 RECOUT_WIDTH, recout->width,
662 /* Number of RECOUT vertical lines */
663 RECOUT_HEIGHT, recout->height
664 - visual_confirm_on * 4 * (dpp->base.inst + 1));
665 }
666
667 /* Main function to program scaler and line buffer in manual scaling mode */
dpp1_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)668 void dpp1_dscl_set_scaler_manual_scale(
669 struct dpp *dpp_base,
670 const struct scaler_data *scl_data)
671 {
672 enum lb_memory_config lb_config;
673 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
674 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
675 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
676 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
677 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
678
679 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
680 return;
681
682 PERF_TRACE();
683
684 dpp->scl_data = *scl_data;
685
686 /* Autocal off */
687 REG_SET_3(DSCL_AUTOCAL, 0,
688 AUTOCAL_MODE, AUTOCAL_MODE_OFF,
689 AUTOCAL_NUM_PIPE, 0,
690 AUTOCAL_PIPE_ID, 0);
691
692 /* Recout */
693 dpp1_dscl_set_recout(dpp, &scl_data->recout);
694
695 /* MPC Size */
696 REG_SET_2(MPC_SIZE, 0,
697 /* Number of horizontal pixels of MPC */
698 MPC_WIDTH, scl_data->h_active,
699 /* Number of vertical lines of MPC */
700 MPC_HEIGHT, scl_data->v_active);
701
702 /* SCL mode */
703 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
704
705 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
706 return;
707
708 /* LB */
709 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
710 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
711
712 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
713 return;
714
715 /* Black offsets */
716 if (REG(SCL_BLACK_OFFSET)) {
717 if (ycbcr)
718 REG_SET_2(SCL_BLACK_OFFSET, 0,
719 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
720 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
721 else
722
723 REG_SET_2(SCL_BLACK_OFFSET, 0,
724 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
725 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
726 }
727
728 /* Manually calculate scale ratio and init values */
729 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
730
731 /* HTaps/VTaps */
732 REG_SET_4(SCL_TAP_CONTROL, 0,
733 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
734 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
735 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
736 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
737
738 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
739 PERF_TRACE();
740 }
741