1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 #include "amdgpu_dm_hdcp.h" 35 36 #include "dc.h" 37 #include "dm_helpers.h" 38 39 #include "ddc_service_types.h" 40 #include "dpcd_defs.h" 41 42 #include "dmub_cmd.h" 43 #if defined(CONFIG_DEBUG_FS) 44 #include "amdgpu_dm_debugfs.h" 45 #endif 46 47 #include "dc/dcn20/dcn20_resource.h" 48 49 #define PEAK_FACTOR_X1000 1006 50 51 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 52 struct drm_dp_aux_msg *msg) 53 { 54 ssize_t result = 0; 55 struct aux_payload payload; 56 enum aux_return_code_type operation_result; 57 struct amdgpu_device *adev; 58 struct ddc_service *ddc; 59 60 if (WARN_ON(msg->size > 16)) 61 return -E2BIG; 62 63 payload.address = msg->address; 64 payload.data = msg->buffer; 65 payload.length = msg->size; 66 payload.reply = &msg->reply; 67 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 68 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 69 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 70 payload.write_status_update = 71 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 72 payload.defer_delay = 0; 73 74 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 75 &operation_result); 76 77 /* 78 * w/a on certain intel platform where hpd is unexpected to pull low during 79 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 80 * aux transaction is succuess in such case, therefore bypass the error 81 */ 82 ddc = TO_DM_AUX(aux)->ddc_service; 83 adev = ddc->ctx->driver_context; 84 if (adev->dm.aux_hpd_discon_quirk) { 85 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 86 operation_result == AUX_RET_ERROR_HPD_DISCON) { 87 result = 0; 88 operation_result = AUX_RET_SUCCESS; 89 } 90 } 91 92 if (payload.write && result >= 0) 93 result = msg->size; 94 95 if (result < 0) 96 switch (operation_result) { 97 case AUX_RET_SUCCESS: 98 break; 99 case AUX_RET_ERROR_HPD_DISCON: 100 case AUX_RET_ERROR_UNKNOWN: 101 case AUX_RET_ERROR_INVALID_OPERATION: 102 case AUX_RET_ERROR_PROTOCOL_ERROR: 103 result = -EIO; 104 break; 105 case AUX_RET_ERROR_INVALID_REPLY: 106 case AUX_RET_ERROR_ENGINE_ACQUIRE: 107 result = -EBUSY; 108 break; 109 case AUX_RET_ERROR_TIMEOUT: 110 result = -ETIMEDOUT; 111 break; 112 } 113 114 return result; 115 } 116 117 static void 118 dm_dp_mst_connector_destroy(struct drm_connector *connector) 119 { 120 struct amdgpu_dm_connector *aconnector = 121 to_amdgpu_dm_connector(connector); 122 123 if (aconnector->dc_sink) { 124 dc_link_remove_remote_sink(aconnector->dc_link, 125 aconnector->dc_sink); 126 dc_sink_release(aconnector->dc_sink); 127 } 128 129 kfree(aconnector->edid); 130 131 drm_connector_cleanup(connector); 132 drm_dp_mst_put_port_malloc(aconnector->mst_output_port); 133 kfree(aconnector); 134 } 135 136 static int 137 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 138 { 139 struct amdgpu_dm_connector *amdgpu_dm_connector = 140 to_amdgpu_dm_connector(connector); 141 int r; 142 143 r = drm_dp_mst_connector_late_register(connector, 144 amdgpu_dm_connector->mst_output_port); 145 if (r < 0) 146 return r; 147 148 #if defined(CONFIG_DEBUG_FS) 149 connector_debugfs_init(amdgpu_dm_connector); 150 #endif 151 152 return 0; 153 } 154 155 static void 156 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 157 { 158 struct amdgpu_dm_connector *aconnector = 159 to_amdgpu_dm_connector(connector); 160 struct drm_dp_mst_port *port = aconnector->mst_output_port; 161 struct amdgpu_dm_connector *root = aconnector->mst_root; 162 struct dc_link *dc_link = aconnector->dc_link; 163 struct dc_sink *dc_sink = aconnector->dc_sink; 164 165 drm_dp_mst_connector_early_unregister(connector, port); 166 167 /* 168 * Release dc_sink for connector which its attached port is 169 * no longer in the mst topology 170 */ 171 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 172 if (dc_sink) { 173 if (dc_link->sink_count) 174 dc_link_remove_remote_sink(dc_link, dc_sink); 175 176 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 177 dc_sink, dc_link->sink_count); 178 179 dc_sink_release(dc_sink); 180 aconnector->dc_sink = NULL; 181 aconnector->edid = NULL; 182 aconnector->dsc_aux = NULL; 183 port->passthrough_aux = NULL; 184 } 185 186 aconnector->mst_status = MST_STATUS_DEFAULT; 187 drm_modeset_unlock(&root->mst_mgr.base.lock); 188 } 189 190 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 191 .fill_modes = drm_helper_probe_single_connector_modes, 192 .destroy = dm_dp_mst_connector_destroy, 193 .reset = amdgpu_dm_connector_funcs_reset, 194 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 195 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 196 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 197 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 198 .late_register = amdgpu_dm_mst_connector_late_register, 199 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 200 }; 201 202 bool needs_dsc_aux_workaround(struct dc_link *link) 203 { 204 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 205 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 206 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 207 return true; 208 209 return false; 210 } 211 212 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port) 213 { 214 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F 215 216 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) { 217 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 218 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) { 219 DRM_INFO("Synaptics Cascaded MST hub\n"); 220 return true; 221 } 222 } 223 224 return false; 225 } 226 227 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 228 { 229 struct dc_sink *dc_sink = aconnector->dc_sink; 230 struct drm_dp_mst_port *port = aconnector->mst_output_port; 231 u8 dsc_caps[16] = { 0 }; 232 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 233 u8 *dsc_branch_dec_caps = NULL; 234 235 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 236 237 /* 238 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 239 * because it only check the dsc/fec caps of the "port variable" and not the dock 240 * 241 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 242 * 243 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 244 * 245 */ 246 if (!aconnector->dsc_aux && !port->parent->port_parent && 247 needs_dsc_aux_workaround(aconnector->dc_link)) 248 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; 249 250 /* synaptics cascaded MST hub case */ 251 if (is_synaptics_cascaded_panamera(aconnector->dc_link, port)) 252 aconnector->dsc_aux = port->mgr->aux; 253 254 if (!aconnector->dsc_aux) 255 return false; 256 257 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 258 return false; 259 260 if (drm_dp_dpcd_read(aconnector->dsc_aux, 261 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 262 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 263 264 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 265 dsc_caps, dsc_branch_dec_caps, 266 &dc_sink->dsc_caps.dsc_dec_caps)) 267 return false; 268 269 return true; 270 } 271 272 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 273 { 274 union dp_downstream_port_present ds_port_present; 275 276 if (!aconnector->dsc_aux) 277 return false; 278 279 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 280 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 281 return false; 282 } 283 284 aconnector->mst_downstream_port_present = ds_port_present; 285 DRM_INFO("Downstream port present %d, type %d\n", 286 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 287 288 return true; 289 } 290 291 static int dm_dp_mst_get_modes(struct drm_connector *connector) 292 { 293 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 294 int ret = 0; 295 296 if (!aconnector) 297 return drm_add_edid_modes(connector, NULL); 298 299 if (!aconnector->edid) { 300 struct edid *edid; 301 302 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); 303 304 if (!edid) { 305 amdgpu_dm_set_mst_status(&aconnector->mst_status, 306 MST_REMOTE_EDID, false); 307 308 drm_connector_update_edid_property( 309 &aconnector->base, 310 NULL); 311 312 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 313 if (!aconnector->dc_sink) { 314 struct dc_sink *dc_sink; 315 struct dc_sink_init_data init_params = { 316 .link = aconnector->dc_link, 317 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 318 319 dc_sink = dc_link_add_remote_sink( 320 aconnector->dc_link, 321 NULL, 322 0, 323 &init_params); 324 325 if (!dc_sink) { 326 DRM_ERROR("Unable to add a remote sink\n"); 327 return 0; 328 } 329 330 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 331 dc_sink, aconnector->dc_link->sink_count); 332 333 dc_sink->priv = aconnector; 334 aconnector->dc_sink = dc_sink; 335 } 336 337 return ret; 338 } 339 340 aconnector->edid = edid; 341 amdgpu_dm_set_mst_status(&aconnector->mst_status, 342 MST_REMOTE_EDID, true); 343 } 344 345 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 346 dc_sink_release(aconnector->dc_sink); 347 aconnector->dc_sink = NULL; 348 } 349 350 if (!aconnector->dc_sink) { 351 struct dc_sink *dc_sink; 352 struct dc_sink_init_data init_params = { 353 .link = aconnector->dc_link, 354 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 355 dc_sink = dc_link_add_remote_sink( 356 aconnector->dc_link, 357 (uint8_t *)aconnector->edid, 358 (aconnector->edid->extensions + 1) * EDID_LENGTH, 359 &init_params); 360 361 if (!dc_sink) { 362 DRM_ERROR("Unable to add a remote sink\n"); 363 return 0; 364 } 365 366 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 367 dc_sink, aconnector->dc_link->sink_count); 368 369 dc_sink->priv = aconnector; 370 /* dc_link_add_remote_sink returns a new reference */ 371 aconnector->dc_sink = dc_sink; 372 373 /* when display is unplugged from mst hub, connctor will be 374 * destroyed within dm_dp_mst_connector_destroy. connector 375 * hdcp perperties, like type, undesired, desired, enabled, 376 * will be lost. So, save hdcp properties into hdcp_work within 377 * amdgpu_dm_atomic_commit_tail. if the same display is 378 * plugged back with same display index, its hdcp properties 379 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 380 */ 381 if (aconnector->dc_sink && connector->state) { 382 struct drm_device *dev = connector->dev; 383 struct amdgpu_device *adev = drm_to_adev(dev); 384 385 if (adev->dm.hdcp_workqueue) { 386 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 387 struct hdcp_workqueue *hdcp_w = 388 &hdcp_work[aconnector->dc_link->link_index]; 389 390 connector->state->hdcp_content_type = 391 hdcp_w->hdcp_content_type[connector->index]; 392 connector->state->content_protection = 393 hdcp_w->content_protection[connector->index]; 394 } 395 } 396 397 if (aconnector->dc_sink) { 398 amdgpu_dm_update_freesync_caps( 399 connector, aconnector->edid); 400 401 if (!validate_dsc_caps_on_connector(aconnector)) 402 memset(&aconnector->dc_sink->dsc_caps, 403 0, sizeof(aconnector->dc_sink->dsc_caps)); 404 405 if (!retrieve_downstream_port_device(aconnector)) 406 memset(&aconnector->mst_downstream_port_present, 407 0, sizeof(aconnector->mst_downstream_port_present)); 408 } 409 } 410 411 drm_connector_update_edid_property( 412 &aconnector->base, aconnector->edid); 413 414 ret = drm_add_edid_modes(connector, aconnector->edid); 415 416 return ret; 417 } 418 419 static struct drm_encoder * 420 dm_mst_atomic_best_encoder(struct drm_connector *connector, 421 struct drm_atomic_state *state) 422 { 423 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 424 connector); 425 struct drm_device *dev = connector->dev; 426 struct amdgpu_device *adev = drm_to_adev(dev); 427 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 428 429 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 430 } 431 432 static int 433 dm_dp_mst_detect(struct drm_connector *connector, 434 struct drm_modeset_acquire_ctx *ctx, bool force) 435 { 436 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 437 struct amdgpu_dm_connector *master = aconnector->mst_root; 438 struct drm_dp_mst_port *port = aconnector->mst_output_port; 439 int connection_status; 440 441 if (drm_connector_is_unregistered(connector)) 442 return connector_status_disconnected; 443 444 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 445 aconnector->mst_output_port); 446 447 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 448 uint8_t dpcd_rev; 449 int ret; 450 451 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 452 453 if (ret == 1) { 454 port->dpcd_rev = dpcd_rev; 455 456 /* Could be DP1.2 DP Rx case*/ 457 if (!dpcd_rev) { 458 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 459 460 if (ret == 1) 461 port->dpcd_rev = dpcd_rev; 462 } 463 464 if (!dpcd_rev) 465 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 466 } 467 468 /* 469 * Could be legacy sink, logical port etc on DP1.2. 470 * Will get Nack under these cases when issue remote 471 * DPCD read. 472 */ 473 if (ret != 1) 474 DRM_DEBUG_KMS("Can't access DPCD"); 475 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 476 port->dpcd_rev = 0; 477 } 478 479 /* 480 * Release dc_sink for connector which unplug event is notified by CSN msg 481 */ 482 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 483 if (aconnector->dc_link->sink_count) 484 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 485 486 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 487 aconnector->dc_link, aconnector->dc_link->sink_count); 488 489 dc_sink_release(aconnector->dc_sink); 490 aconnector->dc_sink = NULL; 491 aconnector->edid = NULL; 492 aconnector->dsc_aux = NULL; 493 port->passthrough_aux = NULL; 494 495 amdgpu_dm_set_mst_status(&aconnector->mst_status, 496 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 497 false); 498 } 499 500 return connection_status; 501 } 502 503 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 504 struct drm_atomic_state *state) 505 { 506 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 507 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; 508 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; 509 510 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 511 } 512 513 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 514 .get_modes = dm_dp_mst_get_modes, 515 .mode_valid = amdgpu_dm_connector_mode_valid, 516 .atomic_best_encoder = dm_mst_atomic_best_encoder, 517 .detect_ctx = dm_dp_mst_detect, 518 .atomic_check = dm_dp_mst_atomic_check, 519 }; 520 521 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 522 { 523 drm_encoder_cleanup(encoder); 524 } 525 526 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 527 .destroy = amdgpu_dm_encoder_destroy, 528 }; 529 530 void 531 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 532 { 533 struct drm_device *dev = adev_to_drm(adev); 534 int i; 535 536 for (i = 0; i < adev->dm.display_indexes_num; i++) { 537 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 538 struct drm_encoder *encoder = &amdgpu_encoder->base; 539 540 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 541 542 drm_encoder_init( 543 dev, 544 &amdgpu_encoder->base, 545 &amdgpu_dm_encoder_funcs, 546 DRM_MODE_ENCODER_DPMST, 547 NULL); 548 549 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 550 } 551 } 552 553 static struct drm_connector * 554 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 555 struct drm_dp_mst_port *port, 556 const char *pathprop) 557 { 558 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 559 struct drm_device *dev = master->base.dev; 560 struct amdgpu_device *adev = drm_to_adev(dev); 561 struct amdgpu_dm_connector *aconnector; 562 struct drm_connector *connector; 563 int i; 564 565 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 566 if (!aconnector) 567 return NULL; 568 569 connector = &aconnector->base; 570 aconnector->mst_output_port = port; 571 aconnector->mst_root = master; 572 amdgpu_dm_set_mst_status(&aconnector->mst_status, 573 MST_PROBE, true); 574 575 if (drm_connector_init( 576 dev, 577 connector, 578 &dm_dp_mst_connector_funcs, 579 DRM_MODE_CONNECTOR_DisplayPort)) { 580 kfree(aconnector); 581 return NULL; 582 } 583 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 584 585 amdgpu_dm_connector_init_helper( 586 &adev->dm, 587 aconnector, 588 DRM_MODE_CONNECTOR_DisplayPort, 589 master->dc_link, 590 master->connector_id); 591 592 for (i = 0; i < adev->dm.display_indexes_num; i++) { 593 drm_connector_attach_encoder(&aconnector->base, 594 &adev->dm.mst_encoders[i].base); 595 } 596 597 connector->max_bpc_property = master->base.max_bpc_property; 598 if (connector->max_bpc_property) 599 drm_connector_attach_max_bpc_property(connector, 8, 16); 600 601 connector->vrr_capable_property = master->base.vrr_capable_property; 602 if (connector->vrr_capable_property) 603 drm_connector_attach_vrr_capable_property(connector); 604 605 drm_object_attach_property( 606 &connector->base, 607 dev->mode_config.path_property, 608 0); 609 drm_object_attach_property( 610 &connector->base, 611 dev->mode_config.tile_property, 612 0); 613 connector->colorspace_property = master->base.colorspace_property; 614 if (connector->colorspace_property) 615 drm_connector_attach_colorspace_property(connector); 616 617 drm_connector_set_path_property(connector, pathprop); 618 619 /* 620 * Initialize connector state before adding the connectror to drm and 621 * framebuffer lists 622 */ 623 amdgpu_dm_connector_funcs_reset(connector); 624 625 drm_dp_mst_get_port_malloc(port); 626 627 return connector; 628 } 629 630 void dm_handle_mst_sideband_msg_ready_event( 631 struct drm_dp_mst_topology_mgr *mgr, 632 enum mst_msg_ready_type msg_rdy_type) 633 { 634 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 635 uint8_t dret; 636 bool new_irq_handled = false; 637 int dpcd_addr; 638 uint8_t dpcd_bytes_to_read; 639 const uint8_t max_process_count = 30; 640 uint8_t process_count = 0; 641 u8 retry; 642 struct amdgpu_dm_connector *aconnector = 643 container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 644 645 646 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 647 648 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 649 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 650 /* DPCD 0x200 - 0x201 for downstream IRQ */ 651 dpcd_addr = DP_SINK_COUNT; 652 } else { 653 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 654 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 655 dpcd_addr = DP_SINK_COUNT_ESI; 656 } 657 658 mutex_lock(&aconnector->handle_mst_msg_ready); 659 660 while (process_count < max_process_count) { 661 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 662 663 process_count++; 664 665 dret = drm_dp_dpcd_read( 666 &aconnector->dm_dp_aux.aux, 667 dpcd_addr, 668 esi, 669 dpcd_bytes_to_read); 670 671 if (dret != dpcd_bytes_to_read) { 672 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!"); 673 break; 674 } 675 676 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 677 678 switch (msg_rdy_type) { 679 case DOWN_REP_MSG_RDY_EVENT: 680 /* Only handle DOWN_REP_MSG_RDY case*/ 681 esi[1] &= DP_DOWN_REP_MSG_RDY; 682 break; 683 case UP_REQ_MSG_RDY_EVENT: 684 /* Only handle UP_REQ_MSG_RDY case*/ 685 esi[1] &= DP_UP_REQ_MSG_RDY; 686 break; 687 default: 688 /* Handle both cases*/ 689 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY); 690 break; 691 } 692 693 if (!esi[1]) 694 break; 695 696 /* handle MST irq */ 697 if (aconnector->mst_mgr.mst_state) 698 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 699 esi, 700 ack, 701 &new_irq_handled); 702 703 if (new_irq_handled) { 704 /* ACK at DPCD to notify down stream */ 705 for (retry = 0; retry < 3; retry++) { 706 ssize_t wret; 707 708 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 709 dpcd_addr + 1, 710 ack[1]); 711 if (wret == 1) 712 break; 713 } 714 715 if (retry == 3) { 716 DRM_ERROR("Failed to ack MST event.\n"); 717 break; 718 } 719 720 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 721 722 new_irq_handled = false; 723 } else { 724 break; 725 } 726 } 727 728 mutex_unlock(&aconnector->handle_mst_msg_ready); 729 730 if (process_count == max_process_count) 731 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 732 } 733 734 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) 735 { 736 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); 737 } 738 739 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 740 .add_connector = dm_dp_add_mst_connector, 741 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, 742 }; 743 744 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 745 struct amdgpu_dm_connector *aconnector, 746 int link_index) 747 { 748 struct dc_link_settings max_link_enc_cap = {0}; 749 750 aconnector->dm_dp_aux.aux.name = 751 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 752 link_index); 753 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 754 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 755 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 756 757 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 758 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 759 &aconnector->base); 760 761 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 762 return; 763 764 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 765 aconnector->mst_mgr.cbs = &dm_mst_cbs; 766 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 767 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 768 769 drm_connector_attach_dp_subconnector_property(&aconnector->base); 770 } 771 772 int dm_mst_get_pbn_divider(struct dc_link *link) 773 { 774 if (!link) 775 return 0; 776 777 return dc_link_bandwidth_kbps(link, 778 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 779 } 780 781 struct dsc_mst_fairness_params { 782 struct dc_crtc_timing *timing; 783 struct dc_sink *sink; 784 struct dc_dsc_bw_range bw_range; 785 bool compression_possible; 786 struct drm_dp_mst_port *port; 787 enum dsc_clock_force_state clock_force_enable; 788 uint32_t num_slices_h; 789 uint32_t num_slices_v; 790 uint32_t bpp_overwrite; 791 struct amdgpu_dm_connector *aconnector; 792 }; 793 794 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) 795 { 796 u8 link_coding_cap; 797 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B; 798 799 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link); 800 if (link_coding_cap == DP_128b_132b_ENCODING) 801 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B; 802 803 return fec_overhead_multiplier_x1000; 804 } 805 806 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) 807 { 808 u64 peak_kbps = kbps; 809 810 peak_kbps *= 1006; 811 peak_kbps *= fec_overhead_multiplier_x1000; 812 peak_kbps = div_u64(peak_kbps, 1000 * 1000); 813 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 814 } 815 816 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 817 struct dsc_mst_fairness_vars *vars, 818 int count, 819 int k) 820 { 821 struct drm_connector *drm_connector; 822 int i; 823 struct dc_dsc_config_options dsc_options = {0}; 824 825 for (i = 0; i < count; i++) { 826 drm_connector = ¶ms[i].aconnector->base; 827 828 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); 829 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 830 831 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 832 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 833 params[i].sink->ctx->dc->res_pool->dscs[0], 834 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 835 &dsc_options, 836 0, 837 params[i].timing, 838 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link), 839 ¶ms[i].timing->dsc_cfg)) { 840 params[i].timing->flags.DSC = 1; 841 842 if (params[i].bpp_overwrite) 843 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 844 else 845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 846 847 if (params[i].num_slices_h) 848 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 849 850 if (params[i].num_slices_v) 851 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 852 } else { 853 params[i].timing->flags.DSC = 0; 854 } 855 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 856 } 857 858 for (i = 0; i < count; i++) { 859 if (params[i].sink) { 860 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 861 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 862 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 863 params[i].sink->edid_caps.display_name); 864 } 865 866 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 867 params[i].timing->flags.DSC, 868 params[i].timing->dsc_cfg.bits_per_pixel, 869 vars[i + k].pbn); 870 } 871 } 872 873 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 874 { 875 struct dc_dsc_config dsc_config; 876 u64 kbps; 877 878 struct drm_connector *drm_connector = ¶m.aconnector->base; 879 struct dc_dsc_config_options dsc_options = {0}; 880 881 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); 882 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 883 884 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 885 dc_dsc_compute_config( 886 param.sink->ctx->dc->res_pool->dscs[0], 887 ¶m.sink->dsc_caps.dsc_dec_caps, 888 &dsc_options, 889 (int) kbps, param.timing, 890 dc_link_get_highest_encoding_format(param.aconnector->dc_link), 891 &dsc_config); 892 893 return dsc_config.bits_per_pixel; 894 } 895 896 static int increase_dsc_bpp(struct drm_atomic_state *state, 897 struct drm_dp_mst_topology_state *mst_state, 898 struct dc_link *dc_link, 899 struct dsc_mst_fairness_params *params, 900 struct dsc_mst_fairness_vars *vars, 901 int count, 902 int k) 903 { 904 int i; 905 bool bpp_increased[MAX_PIPES]; 906 int initial_slack[MAX_PIPES]; 907 int min_initial_slack; 908 int next_index; 909 int remaining_to_increase = 0; 910 int link_timeslots_used; 911 int fair_pbn_alloc; 912 int ret = 0; 913 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 914 915 for (i = 0; i < count; i++) { 916 if (vars[i + k].dsc_enabled) { 917 initial_slack[i] = 918 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn; 919 bpp_increased[i] = false; 920 remaining_to_increase += 1; 921 } else { 922 initial_slack[i] = 0; 923 bpp_increased[i] = true; 924 } 925 } 926 927 while (remaining_to_increase) { 928 next_index = -1; 929 min_initial_slack = -1; 930 for (i = 0; i < count; i++) { 931 if (!bpp_increased[i]) { 932 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 933 min_initial_slack = initial_slack[i]; 934 next_index = i; 935 } 936 } 937 } 938 939 if (next_index == -1) 940 break; 941 942 link_timeslots_used = 0; 943 944 for (i = 0; i < count; i++) 945 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); 946 947 fair_pbn_alloc = 948 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; 949 950 if (initial_slack[next_index] > fair_pbn_alloc) { 951 vars[next_index].pbn += fair_pbn_alloc; 952 ret = drm_dp_atomic_find_time_slots(state, 953 params[next_index].port->mgr, 954 params[next_index].port, 955 vars[next_index].pbn); 956 if (ret < 0) 957 return ret; 958 959 ret = drm_dp_mst_atomic_check(state); 960 if (ret == 0) { 961 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 962 } else { 963 vars[next_index].pbn -= fair_pbn_alloc; 964 ret = drm_dp_atomic_find_time_slots(state, 965 params[next_index].port->mgr, 966 params[next_index].port, 967 vars[next_index].pbn); 968 if (ret < 0) 969 return ret; 970 } 971 } else { 972 vars[next_index].pbn += initial_slack[next_index]; 973 ret = drm_dp_atomic_find_time_slots(state, 974 params[next_index].port->mgr, 975 params[next_index].port, 976 vars[next_index].pbn); 977 if (ret < 0) 978 return ret; 979 980 ret = drm_dp_mst_atomic_check(state); 981 if (ret == 0) { 982 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 983 } else { 984 vars[next_index].pbn -= initial_slack[next_index]; 985 ret = drm_dp_atomic_find_time_slots(state, 986 params[next_index].port->mgr, 987 params[next_index].port, 988 vars[next_index].pbn); 989 if (ret < 0) 990 return ret; 991 } 992 } 993 994 bpp_increased[next_index] = true; 995 remaining_to_increase--; 996 } 997 return 0; 998 } 999 1000 static int try_disable_dsc(struct drm_atomic_state *state, 1001 struct dc_link *dc_link, 1002 struct dsc_mst_fairness_params *params, 1003 struct dsc_mst_fairness_vars *vars, 1004 int count, 1005 int k) 1006 { 1007 int i; 1008 bool tried[MAX_PIPES]; 1009 int kbps_increase[MAX_PIPES]; 1010 int max_kbps_increase; 1011 int next_index; 1012 int remaining_to_try = 0; 1013 int ret; 1014 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1015 1016 for (i = 0; i < count; i++) { 1017 if (vars[i + k].dsc_enabled 1018 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 1019 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 1020 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 1021 tried[i] = false; 1022 remaining_to_try += 1; 1023 } else { 1024 kbps_increase[i] = 0; 1025 tried[i] = true; 1026 } 1027 } 1028 1029 while (remaining_to_try) { 1030 next_index = -1; 1031 max_kbps_increase = -1; 1032 for (i = 0; i < count; i++) { 1033 if (!tried[i]) { 1034 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 1035 max_kbps_increase = kbps_increase[i]; 1036 next_index = i; 1037 } 1038 } 1039 } 1040 1041 if (next_index == -1) 1042 break; 1043 1044 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1045 ret = drm_dp_atomic_find_time_slots(state, 1046 params[next_index].port->mgr, 1047 params[next_index].port, 1048 vars[next_index].pbn); 1049 if (ret < 0) 1050 return ret; 1051 1052 ret = drm_dp_mst_atomic_check(state); 1053 if (ret == 0) { 1054 vars[next_index].dsc_enabled = false; 1055 vars[next_index].bpp_x16 = 0; 1056 } else { 1057 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); 1058 ret = drm_dp_atomic_find_time_slots(state, 1059 params[next_index].port->mgr, 1060 params[next_index].port, 1061 vars[next_index].pbn); 1062 if (ret < 0) 1063 return ret; 1064 } 1065 1066 tried[next_index] = true; 1067 remaining_to_try--; 1068 } 1069 return 0; 1070 } 1071 1072 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 1073 struct dc_state *dc_state, 1074 struct dc_link *dc_link, 1075 struct dsc_mst_fairness_vars *vars, 1076 struct drm_dp_mst_topology_mgr *mgr, 1077 int *link_vars_start_index) 1078 { 1079 struct dc_stream_state *stream; 1080 struct dsc_mst_fairness_params params[MAX_PIPES]; 1081 struct amdgpu_dm_connector *aconnector; 1082 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 1083 int count = 0; 1084 int i, k, ret; 1085 bool debugfs_overwrite = false; 1086 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1087 1088 memset(params, 0, sizeof(params)); 1089 1090 if (IS_ERR(mst_state)) 1091 return PTR_ERR(mst_state); 1092 1093 /* Set up params */ 1094 for (i = 0; i < dc_state->stream_count; i++) { 1095 struct dc_dsc_policy dsc_policy = {0}; 1096 1097 stream = dc_state->streams[i]; 1098 1099 if (stream->link != dc_link) 1100 continue; 1101 1102 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1103 if (!aconnector) 1104 continue; 1105 1106 if (!aconnector->mst_output_port) 1107 continue; 1108 1109 stream->timing.flags.DSC = 0; 1110 1111 params[count].timing = &stream->timing; 1112 params[count].sink = stream->sink; 1113 params[count].aconnector = aconnector; 1114 params[count].port = aconnector->mst_output_port; 1115 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 1116 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 1117 debugfs_overwrite = true; 1118 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 1119 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1120 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 1121 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 1122 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); 1123 if (!dc_dsc_compute_bandwidth_range( 1124 stream->sink->ctx->dc->res_pool->dscs[0], 1125 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1126 dsc_policy.min_target_bpp * 16, 1127 dsc_policy.max_target_bpp * 16, 1128 &stream->sink->dsc_caps.dsc_dec_caps, 1129 &stream->timing, 1130 dc_link_get_highest_encoding_format(dc_link), 1131 ¶ms[count].bw_range)) 1132 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 1133 dc_link_get_highest_encoding_format(dc_link)); 1134 1135 count++; 1136 } 1137 1138 if (count == 0) { 1139 ASSERT(0); 1140 return 0; 1141 } 1142 1143 /* k is start index of vars for current phy link used by mst hub */ 1144 k = *link_vars_start_index; 1145 /* set vars start index for next mst hub phy link */ 1146 *link_vars_start_index += count; 1147 1148 /* Try no compression */ 1149 for (i = 0; i < count; i++) { 1150 vars[i + k].aconnector = params[i].aconnector; 1151 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1152 vars[i + k].dsc_enabled = false; 1153 vars[i + k].bpp_x16 = 0; 1154 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 1155 vars[i + k].pbn); 1156 if (ret < 0) 1157 return ret; 1158 } 1159 ret = drm_dp_mst_atomic_check(state); 1160 if (ret == 0 && !debugfs_overwrite) { 1161 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1162 return 0; 1163 } else if (ret != -ENOSPC) { 1164 return ret; 1165 } 1166 1167 /* Try max compression */ 1168 for (i = 0; i < count; i++) { 1169 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1170 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); 1171 vars[i + k].dsc_enabled = true; 1172 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1173 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1174 params[i].port, vars[i + k].pbn); 1175 if (ret < 0) 1176 return ret; 1177 } else { 1178 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1179 vars[i + k].dsc_enabled = false; 1180 vars[i + k].bpp_x16 = 0; 1181 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1182 params[i].port, vars[i + k].pbn); 1183 if (ret < 0) 1184 return ret; 1185 } 1186 } 1187 ret = drm_dp_mst_atomic_check(state); 1188 if (ret != 0) 1189 return ret; 1190 1191 /* Optimize degree of compression */ 1192 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1193 if (ret < 0) 1194 return ret; 1195 1196 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1197 if (ret < 0) 1198 return ret; 1199 1200 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1201 1202 return 0; 1203 } 1204 1205 static bool is_dsc_need_re_compute( 1206 struct drm_atomic_state *state, 1207 struct dc_state *dc_state, 1208 struct dc_link *dc_link) 1209 { 1210 int i, j; 1211 bool is_dsc_need_re_compute = false; 1212 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1213 int new_stream_on_link_num = 0; 1214 struct amdgpu_dm_connector *aconnector; 1215 struct dc_stream_state *stream; 1216 const struct dc *dc = dc_link->dc; 1217 1218 /* only check phy used by dsc mst branch */ 1219 if (dc_link->type != dc_connection_mst_branch) 1220 return false; 1221 1222 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1223 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1224 return false; 1225 1226 for (i = 0; i < MAX_PIPES; i++) 1227 stream_on_link[i] = NULL; 1228 1229 /* check if there is mode change in new request */ 1230 for (i = 0; i < dc_state->stream_count; i++) { 1231 struct drm_crtc_state *new_crtc_state; 1232 struct drm_connector_state *new_conn_state; 1233 1234 stream = dc_state->streams[i]; 1235 if (!stream) 1236 continue; 1237 1238 /* check if stream using the same link for mst */ 1239 if (stream->link != dc_link) 1240 continue; 1241 1242 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1243 if (!aconnector) 1244 continue; 1245 1246 stream_on_link[new_stream_on_link_num] = aconnector; 1247 new_stream_on_link_num++; 1248 1249 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1250 if (!new_conn_state) 1251 continue; 1252 1253 if (IS_ERR(new_conn_state)) 1254 continue; 1255 1256 if (!new_conn_state->crtc) 1257 continue; 1258 1259 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1260 if (!new_crtc_state) 1261 continue; 1262 1263 if (IS_ERR(new_crtc_state)) 1264 continue; 1265 1266 if (new_crtc_state->enable && new_crtc_state->active) { 1267 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1268 new_crtc_state->connectors_changed) 1269 return true; 1270 } 1271 } 1272 1273 if (new_stream_on_link_num == 0) 1274 return false; 1275 1276 /* check current_state if there stream on link but it is not in 1277 * new request state 1278 */ 1279 for (i = 0; i < dc->current_state->stream_count; i++) { 1280 stream = dc->current_state->streams[i]; 1281 /* only check stream on the mst hub */ 1282 if (stream->link != dc_link) 1283 continue; 1284 1285 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1286 if (!aconnector) 1287 continue; 1288 1289 for (j = 0; j < new_stream_on_link_num; j++) { 1290 if (stream_on_link[j]) { 1291 if (aconnector == stream_on_link[j]) 1292 break; 1293 } 1294 } 1295 1296 if (j == new_stream_on_link_num) { 1297 /* not in new state */ 1298 is_dsc_need_re_compute = true; 1299 break; 1300 } 1301 } 1302 1303 return is_dsc_need_re_compute; 1304 } 1305 1306 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1307 struct dc_state *dc_state, 1308 struct dsc_mst_fairness_vars *vars) 1309 { 1310 int i, j; 1311 struct dc_stream_state *stream; 1312 bool computed_streams[MAX_PIPES]; 1313 struct amdgpu_dm_connector *aconnector; 1314 struct drm_dp_mst_topology_mgr *mst_mgr; 1315 struct resource_pool *res_pool; 1316 int link_vars_start_index = 0; 1317 int ret = 0; 1318 1319 for (i = 0; i < dc_state->stream_count; i++) 1320 computed_streams[i] = false; 1321 1322 for (i = 0; i < dc_state->stream_count; i++) { 1323 stream = dc_state->streams[i]; 1324 res_pool = stream->ctx->dc->res_pool; 1325 1326 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1327 continue; 1328 1329 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1330 1331 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1332 continue; 1333 1334 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1335 continue; 1336 1337 if (computed_streams[i]) 1338 continue; 1339 1340 if (res_pool->funcs->remove_stream_from_ctx && 1341 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1342 return -EINVAL; 1343 1344 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1345 continue; 1346 1347 mst_mgr = aconnector->mst_output_port->mgr; 1348 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1349 &link_vars_start_index); 1350 if (ret != 0) 1351 return ret; 1352 1353 for (j = 0; j < dc_state->stream_count; j++) { 1354 if (dc_state->streams[j]->link == stream->link) 1355 computed_streams[j] = true; 1356 } 1357 } 1358 1359 for (i = 0; i < dc_state->stream_count; i++) { 1360 stream = dc_state->streams[i]; 1361 1362 if (stream->timing.flags.DSC == 1) 1363 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1364 return -EINVAL; 1365 } 1366 1367 return ret; 1368 } 1369 1370 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1371 struct dc_state *dc_state, 1372 struct dsc_mst_fairness_vars *vars) 1373 { 1374 int i, j; 1375 struct dc_stream_state *stream; 1376 bool computed_streams[MAX_PIPES]; 1377 struct amdgpu_dm_connector *aconnector; 1378 struct drm_dp_mst_topology_mgr *mst_mgr; 1379 int link_vars_start_index = 0; 1380 int ret = 0; 1381 1382 for (i = 0; i < dc_state->stream_count; i++) 1383 computed_streams[i] = false; 1384 1385 for (i = 0; i < dc_state->stream_count; i++) { 1386 stream = dc_state->streams[i]; 1387 1388 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1389 continue; 1390 1391 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1392 1393 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1394 continue; 1395 1396 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1397 continue; 1398 1399 if (computed_streams[i]) 1400 continue; 1401 1402 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1403 continue; 1404 1405 mst_mgr = aconnector->mst_output_port->mgr; 1406 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1407 &link_vars_start_index); 1408 if (ret != 0) 1409 return ret; 1410 1411 for (j = 0; j < dc_state->stream_count; j++) { 1412 if (dc_state->streams[j]->link == stream->link) 1413 computed_streams[j] = true; 1414 } 1415 } 1416 1417 return ret; 1418 } 1419 1420 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1421 struct dc_stream_state *stream) 1422 { 1423 int i; 1424 struct drm_crtc *crtc; 1425 struct drm_crtc_state *new_state, *old_state; 1426 1427 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1428 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1429 1430 if (dm_state->stream == stream) 1431 return i; 1432 } 1433 return -1; 1434 } 1435 1436 static bool is_link_to_dschub(struct dc_link *dc_link) 1437 { 1438 union dpcd_dsc_basic_capabilities *dsc_caps = 1439 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1440 1441 /* only check phy used by dsc mst branch */ 1442 if (dc_link->type != dc_connection_mst_branch) 1443 return false; 1444 1445 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1446 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1447 return false; 1448 return true; 1449 } 1450 1451 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1452 { 1453 int i; 1454 struct drm_crtc *crtc; 1455 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1456 bool ret = false; 1457 1458 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1459 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1460 1461 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1462 ret = false; 1463 break; 1464 } 1465 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1466 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1467 ret = true; 1468 } 1469 return ret; 1470 } 1471 1472 int pre_validate_dsc(struct drm_atomic_state *state, 1473 struct dm_atomic_state **dm_state_ptr, 1474 struct dsc_mst_fairness_vars *vars) 1475 { 1476 int i; 1477 struct dm_atomic_state *dm_state; 1478 struct dc_state *local_dc_state = NULL; 1479 int ret = 0; 1480 1481 if (!is_dsc_precompute_needed(state)) { 1482 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1483 return 0; 1484 } 1485 ret = dm_atomic_get_state(state, dm_state_ptr); 1486 if (ret != 0) { 1487 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1488 return ret; 1489 } 1490 dm_state = *dm_state_ptr; 1491 1492 /* 1493 * create local vailable for dc_state. copy content of streams of dm_state->context 1494 * to local variable. make sure stream pointer of local variable not the same as stream 1495 * from dm_state->context. 1496 */ 1497 1498 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1499 if (!local_dc_state) 1500 return -ENOMEM; 1501 1502 for (i = 0; i < local_dc_state->stream_count; i++) { 1503 struct dc_stream_state *stream = dm_state->context->streams[i]; 1504 int ind = find_crtc_index_in_state_by_stream(state, stream); 1505 1506 if (ind >= 0) { 1507 struct amdgpu_dm_connector *aconnector; 1508 struct drm_connector_state *drm_new_conn_state; 1509 struct dm_connector_state *dm_new_conn_state; 1510 struct dm_crtc_state *dm_old_crtc_state; 1511 1512 aconnector = 1513 amdgpu_dm_find_first_crtc_matching_connector(state, 1514 state->crtcs[ind].ptr); 1515 drm_new_conn_state = 1516 drm_atomic_get_new_connector_state(state, 1517 &aconnector->base); 1518 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1519 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1520 1521 local_dc_state->streams[i] = 1522 create_validate_stream_for_sink(aconnector, 1523 &state->crtcs[ind].new_state->mode, 1524 dm_new_conn_state, 1525 dm_old_crtc_state->stream); 1526 if (local_dc_state->streams[i] == NULL) { 1527 ret = -EINVAL; 1528 break; 1529 } 1530 } 1531 } 1532 1533 if (ret != 0) 1534 goto clean_exit; 1535 1536 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1537 if (ret != 0) { 1538 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1539 ret = -EINVAL; 1540 goto clean_exit; 1541 } 1542 1543 /* 1544 * compare local_streams -> timing with dm_state->context, 1545 * if the same set crtc_state->mode-change = 0; 1546 */ 1547 for (i = 0; i < local_dc_state->stream_count; i++) { 1548 struct dc_stream_state *stream = dm_state->context->streams[i]; 1549 1550 if (local_dc_state->streams[i] && 1551 dc_is_timing_changed(stream, local_dc_state->streams[i])) { 1552 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1553 } else { 1554 int ind = find_crtc_index_in_state_by_stream(state, stream); 1555 1556 if (ind >= 0) 1557 state->crtcs[ind].new_state->mode_changed = 0; 1558 } 1559 } 1560 clean_exit: 1561 for (i = 0; i < local_dc_state->stream_count; i++) { 1562 struct dc_stream_state *stream = dm_state->context->streams[i]; 1563 1564 if (local_dc_state->streams[i] != stream) 1565 dc_stream_release(local_dc_state->streams[i]); 1566 } 1567 1568 kfree(local_dc_state); 1569 1570 return ret; 1571 } 1572 1573 static unsigned int kbps_from_pbn(unsigned int pbn) 1574 { 1575 unsigned int kbps = pbn; 1576 1577 kbps *= (1000000 / PEAK_FACTOR_X1000); 1578 kbps *= 8; 1579 kbps *= 54; 1580 kbps /= 64; 1581 1582 return kbps; 1583 } 1584 1585 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1586 struct dc_dsc_bw_range *bw_range) 1587 { 1588 struct dc_dsc_policy dsc_policy = {0}; 1589 1590 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); 1591 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1592 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1593 dsc_policy.min_target_bpp * 16, 1594 dsc_policy.max_target_bpp * 16, 1595 &stream->sink->dsc_caps.dsc_dec_caps, 1596 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range); 1597 1598 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1599 } 1600 1601 enum dc_status dm_dp_mst_is_port_support_mode( 1602 struct amdgpu_dm_connector *aconnector, 1603 struct dc_stream_state *stream) 1604 { 1605 int bpp, pbn, branch_max_throughput_mps = 0; 1606 struct dc_link_settings cur_link_settings; 1607 unsigned int end_to_end_bw_in_kbps = 0; 1608 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1609 unsigned int max_compressed_bw_in_kbps = 0; 1610 struct dc_dsc_bw_range bw_range = {0}; 1611 uint16_t full_pbn = aconnector->mst_output_port->full_pbn; 1612 1613 /* 1614 * Consider the case with the depth of the mst topology tree is equal or less than 2 1615 * A. When dsc bitstream can be transmitted along the entire path 1616 * 1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND 1617 * 2. dsc passthrough supported at MST branch, or 1618 * 3. dsc decoding supported at leaf MST device 1619 * Use maximum dsc compression as bw constraint 1620 * B. When dsc bitstream cannot be transmitted along the entire path 1621 * Use native bw as bw constraint 1622 */ 1623 if (is_dsc_common_config_possible(stream, &bw_range) && 1624 (aconnector->mst_output_port->passthrough_aux || 1625 aconnector->dsc_aux == &aconnector->mst_output_port->aux)) { 1626 cur_link_settings = stream->link->verified_link_cap; 1627 1628 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1629 &cur_link_settings); 1630 down_link_bw_in_kbps = kbps_from_pbn(full_pbn); 1631 1632 /* pick the bottleneck */ 1633 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, 1634 down_link_bw_in_kbps); 1635 1636 /* 1637 * use the maximum dsc compression bandwidth as the required 1638 * bandwidth for the mode 1639 */ 1640 max_compressed_bw_in_kbps = bw_range.min_kbps; 1641 1642 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) { 1643 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n"); 1644 return DC_FAIL_BANDWIDTH_VALIDATE; 1645 } 1646 } else { 1647 /* check if mode could be supported within full_pbn */ 1648 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1649 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4); 1650 if (pbn > full_pbn) 1651 return DC_FAIL_BANDWIDTH_VALIDATE; 1652 } 1653 1654 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1655 switch (stream->timing.pixel_encoding) { 1656 case PIXEL_ENCODING_RGB: 1657 case PIXEL_ENCODING_YCBCR444: 1658 branch_max_throughput_mps = 1659 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1660 break; 1661 case PIXEL_ENCODING_YCBCR422: 1662 case PIXEL_ENCODING_YCBCR420: 1663 branch_max_throughput_mps = 1664 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1665 break; 1666 default: 1667 break; 1668 } 1669 1670 if (branch_max_throughput_mps != 0 && 1671 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1672 return DC_FAIL_BANDWIDTH_VALIDATE; 1673 1674 return DC_OK; 1675 } 1676