1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Cavium, Inc 3 */ 4 5 #ifndef _CPT_HW_TYPES_H_ 6 #define _CPT_HW_TYPES_H_ 7 8 #include <rte_byteorder.h> 9 10 /* 11 * This file defines HRM specific structs. 12 * 13 */ 14 15 #define CPT_VF_INTR_MBOX_MASK (1<<0) 16 #define CPT_VF_INTR_DOVF_MASK (1<<1) 17 #define CPT_VF_INTR_IRDE_MASK (1<<2) 18 #define CPT_VF_INTR_NWRP_MASK (1<<3) 19 #define CPT_VF_INTR_SWERR_MASK (1<<4) 20 #define CPT_VF_INTR_HWERR_MASK (1<<5) 21 #define CPT_VF_INTR_FAULT_MASK (1<<6) 22 23 #define CPT_INST_SIZE (64) 24 #define CPT_NEXT_CHUNK_PTR_SIZE (8) 25 26 /* 27 * CPT_INST_S software command definitions 28 * Words EI (0-3) 29 */ 30 typedef union { 31 uint64_t u64; 32 struct { 33 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 34 struct { 35 uint8_t minor; 36 uint8_t major; 37 } opcode; 38 uint16_t param1; 39 uint16_t param2; 40 uint16_t dlen; 41 #else 42 uint16_t dlen; 43 uint16_t param2; 44 uint16_t param1; 45 struct { 46 uint8_t major; 47 uint8_t minor; 48 } opcode; 49 #endif 50 } s; 51 } vq_cmd_word0_t; 52 53 typedef union { 54 uint64_t u64; 55 struct { 56 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 57 uint64_t grp : 3; 58 uint64_t cptr : 61; 59 #else 60 uint64_t cptr : 61; 61 uint64_t grp : 3; 62 #endif 63 } s; 64 } vq_cmd_word3_t; 65 66 typedef struct cpt_vq_command { 67 vq_cmd_word0_t cmd; 68 uint64_t dptr; 69 uint64_t rptr; 70 vq_cmd_word3_t cptr; 71 } cpt_vq_cmd_t; 72 73 /** 74 * Structure cpt_inst_s 75 * 76 * CPT Instruction Structure 77 * This structure specifies the instruction layout. 78 * Instructions are stored in memory as little-endian unless 79 * CPT()_PF_Q()_CTL[INST_BE] is set. 80 */ 81 typedef union cpt_inst_s { 82 uint64_t u[8]; 83 struct cpt_inst_s_8s { 84 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 85 uint64_t reserved_17_63 : 47; 86 /* [ 16: 16] Done interrupt. 87 * 0 = No interrupts related to this instruction. 88 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE] 89 * will be incremented, and based on the rules described 90 * there an interrupt may occur. 91 */ 92 uint64_t doneint : 1; 93 uint64_t reserved_0_15 : 16; 94 #else /* Word 0 - Little Endian */ 95 uint64_t reserved_0_15 : 16; 96 uint64_t doneint : 1; 97 uint64_t reserved_17_63 : 47; 98 #endif /* Word 0 - End */ 99 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */ 100 /* [127: 64] Result IOVA. 101 * If nonzero, specifies where to write CPT_RES_S. 102 * If zero, no result structure will be written. 103 * Address must be 16-byte aligned. 104 * 105 * Bits <63:49> are ignored by hardware; software should 106 * use a sign-extended bit <48> for forward compatibility. 107 */ 108 uint64_t res_addr : 64; 109 #else /* Word 1 - Little Endian */ 110 uint64_t res_addr : 64; 111 #endif /* Word 1 - End */ 112 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */ 113 uint64_t reserved_172_191 : 20; 114 /* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to 115 * use when CPT submits work to SSO. 116 * For the SSO to not discard the add-work request, FPA_PF_MAP() 117 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. 118 */ 119 uint64_t grp : 10; 120 /* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use 121 * when CPT submits work to SSO. 122 */ 123 uint64_t tt : 2; 124 /* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when 125 * CPT submits work to SSO. 126 */ 127 uint64_t tag : 32; 128 #else /* Word 2 - Little Endian */ 129 uint64_t tag : 32; 130 uint64_t tt : 2; 131 uint64_t grp : 10; 132 uint64_t reserved_172_191 : 20; 133 #endif /* Word 2 - End */ 134 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */ 135 /** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a 136 * work-queue entry that CPT submits work to SSO after all 137 * context, output data, and result write operations are 138 * visible to other CNXXXX units and the cores. 139 * Bits <2:0> must be zero. 140 * Bits <63:49> are ignored by hardware; software should use a 141 * sign-extended bit <48> for forward compatibility. 142 * Internal:Bits <63:49>, <2:0> are ignored by hardware, 143 * treated as always 0x0. 144 **/ 145 uint64_t wq_ptr : 64; 146 #else /* Word 3 - Little Endian */ 147 uint64_t wq_ptr : 64; 148 #endif /* Word 3 - End */ 149 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */ 150 union { 151 /** [319:256] Engine instruction word 0. Passed to the 152 * AE/SE. 153 **/ 154 uint64_t ei0 : 64; 155 vq_cmd_word0_t vq_cmd_w0; 156 }; 157 #else /* Word 4 - Little Endian */ 158 union { 159 uint64_t ei0 : 64; 160 vq_cmd_word0_t vq_cmd_w0; 161 }; 162 #endif /* Word 4 - End */ 163 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */ 164 union { 165 /** [383:320] Engine instruction word 1. Passed to the 166 * AE/SE. 167 **/ 168 uint64_t ei1 : 64; 169 uint64_t dptr; 170 }; 171 #else /* Word 5 - Little Endian */ 172 union { 173 uint64_t ei1 : 64; 174 uint64_t dptr; 175 }; 176 #endif /* Word 5 - End */ 177 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */ 178 union { 179 /** [447:384] Engine instruction word 2. Passed to the 180 * AE/SE. 181 **/ 182 uint64_t ei2 : 64; 183 uint64_t rptr; 184 }; 185 #else /* Word 6 - Little Endian */ 186 union { 187 uint64_t ei2 : 64; 188 uint64_t rptr; 189 }; 190 #endif /* Word 6 - End */ 191 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */ 192 union { 193 /** [511:448] Engine instruction word 3. Passed to the 194 * AE/SE. 195 **/ 196 uint64_t ei3 : 64; 197 vq_cmd_word3_t vq_cmd_w3; 198 }; 199 #else /* Word 7 - Little Endian */ 200 union { 201 uint64_t ei3 : 64; 202 vq_cmd_word3_t vq_cmd_w3; 203 }; 204 #endif /* Word 7 - End */ 205 } s8x; 206 struct cpt_inst_s_9s { 207 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 208 uint64_t nixtx_addr : 60; 209 uint64_t doneint : 1; 210 uint64_t nixtxl : 3; 211 #else /* Word 0 - Little Endian */ 212 uint64_t nixtxl : 3; 213 uint64_t doneint : 1; 214 uint64_t nixtx_addr : 60; 215 #endif /* Word 0 - End */ 216 uint64_t res_addr; 217 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */ 218 uint64_t rvu_pf_func : 16; 219 uint64_t reserved_172_175 : 4; 220 uint64_t grp : 10; 221 uint64_t tt : 2; 222 uint64_t tag : 32; 223 #else /* Word 2 - Little Endian */ 224 uint64_t tag : 32; 225 uint64_t tt : 2; 226 uint64_t grp : 10; 227 uint64_t reserved_172_175 : 4; 228 uint64_t rvu_pf_func : 16; 229 #endif /* Word 2 - End */ 230 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */ 231 uint64_t wq_ptr : 61; 232 uint64_t reserved_194_193 : 2; 233 uint64_t qord : 1; 234 #else /* Word 3 - Little Endian */ 235 uint64_t qord : 1; 236 uint64_t reserved_194_193 : 2; 237 uint64_t wq_ptr : 61; 238 #endif /* Word 3 - End */ 239 uint64_t ei0; 240 uint64_t ei1; 241 uint64_t ei2; 242 uint64_t ei3; 243 } s9x; 244 } cpt_inst_s_t; 245 246 /** 247 * Structure cpt_res_s 248 * 249 * CPT Result Structure 250 * The CPT coprocessor writes the result structure after it completes a 251 * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each 252 * instruction completion produces exactly one result structure. 253 * 254 * This structure is stored in memory as little-endian unless 255 * CPT()_PF_Q()_CTL[INST_BE] is set. 256 */ 257 typedef union cpt_res_s { 258 uint64_t u[2]; 259 struct cpt_res_s_8s { 260 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 261 uint64_t reserved_17_63 : 47; 262 /** [ 16: 16] Done interrupt. This bit is copied from the 263 * corresponding instruction's CPT_INST_S[DONEINT]. 264 **/ 265 uint64_t doneint : 1; 266 uint64_t reserved_8_15 : 8; 267 /** [ 7: 0] Indicates completion/error status of the CPT 268 * coprocessor for the associated instruction, as enumerated by 269 * CPT_COMP_E. Core software may write the memory location 270 * containing [COMPCODE] to 0x0 before ringing the doorbell, and 271 * then poll for completion by checking for a nonzero value. 272 * 273 * Once the core observes a nonzero [COMPCODE] value in this 274 * case, the CPT coprocessor will have also completed L2/DRAM 275 * write operations. 276 **/ 277 uint64_t compcode : 8; 278 #else /* Word 0 - Little Endian */ 279 uint64_t compcode : 8; 280 uint64_t reserved_8_15 : 8; 281 uint64_t doneint : 1; 282 uint64_t reserved_17_63 : 47; 283 #endif /* Word 0 - End */ 284 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */ 285 uint64_t reserved_64_127 : 64; 286 #else /* Word 1 - Little Endian */ 287 uint64_t reserved_64_127 : 64; 288 #endif /* Word 1 - End */ 289 } s8x; 290 struct cpt_res_s_9s { 291 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 292 uint64_t reserved_17_63:47; 293 uint64_t doneint:1; 294 uint64_t uc_compcode:8; 295 uint64_t compcode:8; 296 #else /* Word 0 - Little Endian */ 297 uint64_t compcode:8; 298 uint64_t uc_compcode:8; 299 uint64_t doneint:1; 300 uint64_t reserved_17_63:47; 301 #endif /* Word 0 - End */ 302 uint64_t reserved_64_127; 303 } s9x; 304 } cpt_res_s_t; 305 306 /** 307 * Register (NCB) cpt#_vq#_ctl 308 * 309 * CPT VF Queue Control Registers 310 * This register configures queues. This register should be changed (other than 311 * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]). 312 */ 313 typedef union { 314 uint64_t u; 315 struct cptx_vqx_ctl_s { 316 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 317 uint64_t reserved_1_63 : 63; 318 /** [ 0: 0](R/W/H) Enables the logical instruction queue. 319 * See also CPT()_PF_Q()_CTL[CONT_ERR] and 320 * CPT()_VQ()_INPROG[INFLIGHT]. 321 * 1 = Queue is enabled. 322 * 0 = Queue is disabled. 323 **/ 324 uint64_t ena : 1; 325 #else /* Word 0 - Little Endian */ 326 uint64_t ena : 1; 327 uint64_t reserved_1_63 : 63; 328 #endif /* Word 0 - End */ 329 } s; 330 } cptx_vqx_ctl_t; 331 332 /** 333 * Register (NCB) cpt#_vq#_done 334 * 335 * CPT Queue Done Count Registers 336 * These registers contain the per-queue instruction done count. 337 */ 338 typedef union { 339 uint64_t u; 340 struct cptx_vqx_done_s { 341 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 342 uint64_t reserved_20_63 : 44; 343 /** [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set 344 * and that instruction completes,CPT()_VQ()_DONE[DONE] is 345 * incremented when the instruction finishes. Write to this 346 * field are for diagnostic use only; instead software writes 347 * CPT()_VQ()_DONE_ACK with the number of decrements for this 348 * field. 349 * 350 * Interrupts are sent as follows: 351 * 352 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, 353 * the interrupt coalescing timer is held to zero, and an 354 * interrupt is not sent. 355 * 356 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt 357 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE 358 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ() 359 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough 360 * results have arrived, then the interrupt is sent. Otherwise, 361 * it is not sent due to coalescing. 362 * 363 * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is 364 * written but this is not typical), the interrupt coalescing 365 * timer restarts. Note after decrementing this interrupt 366 * equation is recomputed, for example if CPT()_VQ()_DONE[DONE] 367 * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is 368 * zero, the interrupt will be resent immediately. (This covers 369 * the race case between software acknowledging an interrupt and 370 * a result returning.) 371 * 372 * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not 373 * sent, but the counting described above still occurs. 374 * 375 * Since CPT instructions complete out-of-order, if software is 376 * using completion interrupts the suggested scheme is to 377 * request a DONEINT on each request, and when an interrupt 378 * arrives perform a "greedy" scan for completions; even if a 379 * later command is acknowledged first this will not result in 380 * missing a completion. 381 * 382 * Software is responsible for making sure [DONE] does not 383 * overflow; for example by insuring there are not more than 384 * 2^20-1 instructions in flight that may request interrupts. 385 **/ 386 uint64_t done : 20; 387 #else /* Word 0 - Little Endian */ 388 uint64_t done : 20; 389 uint64_t reserved_20_63 : 44; 390 #endif /* Word 0 - End */ 391 } s; 392 } cptx_vqx_done_t; 393 394 /** 395 * Register (NCB) cpt#_vq#_done_ack 396 * 397 * CPT Queue Done Count Ack Registers 398 * This register is written by software to acknowledge interrupts. 399 */ 400 typedef union { 401 uint64_t u; 402 struct cptx_vqx_done_ack_s { 403 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 404 uint64_t reserved_20_63 : 44; 405 /** [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE 406 * [DONE]. Reads CPT()_VQ()_DONE[DONE]. 407 * 408 * Written by software to acknowledge interrupts. If CPT()_VQ()_ 409 * DONE[DONE] is still nonzero the interrupt will be re-sent if 410 * the conditions described in CPT()_VQ()_DONE[DONE] are 411 * satisfied. 412 **/ 413 uint64_t done_ack : 20; 414 #else /* Word 0 - Little Endian */ 415 uint64_t done_ack : 20; 416 uint64_t reserved_20_63 : 44; 417 #endif /* Word 0 - End */ 418 } s; 419 } cptx_vqx_done_ack_t; 420 421 /** 422 * Register (NCB) cpt#_vq#_done_wait 423 * 424 * CPT Queue Done Interrupt Coalescing Wait Registers 425 * Specifies the per queue interrupt coalescing settings. 426 */ 427 typedef union { 428 uint64_t u; 429 struct cptx_vqx_done_wait_s { 430 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 431 uint64_t reserved_48_63 : 16; 432 /** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = 433 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When 434 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing 435 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is 436 * disabled. 437 **/ 438 uint64_t time_wait : 16; 439 uint64_t reserved_20_31 : 12; 440 /** [ 19: 0](R/W) Number of messages hold-off. When 441 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing 442 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as 443 * 0x1. 444 **/ 445 uint64_t num_wait : 20; 446 #else /* Word 0 - Little Endian */ 447 uint64_t num_wait : 20; 448 uint64_t reserved_20_31 : 12; 449 uint64_t time_wait : 16; 450 uint64_t reserved_48_63 : 16; 451 #endif /* Word 0 - End */ 452 } s; 453 } cptx_vqx_done_wait_t; 454 455 /** 456 * Register (NCB) cpt#_vq#_doorbell 457 * 458 * CPT Queue Doorbell Registers 459 * Doorbells for the CPT instruction queues. 460 */ 461 typedef union { 462 uint64_t u; 463 struct cptx_vqx_doorbell_s { 464 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 465 uint64_t reserved_20_63 : 44; 466 uint64_t dbell_cnt : 20; 467 /** [ 19: 0](R/W/H) Number of instruction queue 64-bit words 468 * to add to the CPT instruction doorbell count. Readback value 469 * is the current number of pending doorbell requests. 470 * 471 * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. 472 * 473 * To reset the count back to zero, write one to clear 474 * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value 475 * of 2^20 minus the read [DBELL_CNT], then write one to 476 * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and 477 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. 478 * 479 * Must be a multiple of 8. All CPT instructions are 8 words 480 * and require a doorbell count of multiple of 8. 481 **/ 482 #else /* Word 0 - Little Endian */ 483 uint64_t dbell_cnt : 20; 484 uint64_t reserved_20_63 : 44; 485 #endif /* Word 0 - End */ 486 } s; 487 } cptx_vqx_doorbell_t; 488 489 /** 490 * Register (NCB) cpt#_vq#_inprog 491 * 492 * CPT Queue In Progress Count Registers 493 * These registers contain the per-queue instruction in flight registers. 494 */ 495 typedef union { 496 uint64_t u; 497 struct cptx_vqx_inprog_s { 498 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 499 uint64_t reserved_8_63 : 56; 500 /** [ 7: 0](RO/H) Inflight count. Counts the number of 501 * instructions for the VF for which CPT is fetching, executing 502 * or responding to instructions. However this does not include 503 * any interrupts that are awaiting software handling 504 * (CPT()_VQ()_DONE[DONE] != 0x0). 505 * 506 * A queue may not be reconfigured until: 507 * 1. CPT()_VQ()_CTL[ENA] is cleared by software. 508 * 2. [INFLIGHT] is polled until equals to zero. 509 **/ 510 uint64_t inflight : 8; 511 #else /* Word 0 - Little Endian */ 512 uint64_t inflight : 8; 513 uint64_t reserved_8_63 : 56; 514 #endif /* Word 0 - End */ 515 } s; 516 } cptx_vqx_inprog_t; 517 518 /** 519 * Register (NCB) cpt#_vq#_misc_int 520 * 521 * CPT Queue Misc Interrupt Register 522 * These registers contain the per-queue miscellaneous interrupts. 523 */ 524 typedef union { 525 uint64_t u; 526 struct cptx_vqx_misc_int_s { 527 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 528 uint64_t reserved_7_63 : 57; 529 /** [ 6: 6](R/W1C/H) Translation fault detected. */ 530 uint64_t fault : 1; 531 /** [ 5: 5](R/W1C/H) Hardware error from engines. */ 532 uint64_t hwerr : 1; 533 /** [ 4: 4](R/W1C/H) Software error from engines. */ 534 uint64_t swerr : 1; 535 /** [ 3: 3](R/W1C/H) NCB result write response error. */ 536 uint64_t nwrp : 1; 537 /** [ 2: 2](R/W1C/H) Instruction NCB read response error. */ 538 uint64_t irde : 1; 539 /** [ 1: 1](R/W1C/H) Doorbell overflow. */ 540 uint64_t dovf : 1; 541 /** [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when 542 * CPT()_VF()_PF_MBOX(0) is written. 543 **/ 544 uint64_t mbox : 1; 545 #else /* Word 0 - Little Endian */ 546 uint64_t mbox : 1; 547 uint64_t dovf : 1; 548 uint64_t irde : 1; 549 uint64_t nwrp : 1; 550 uint64_t swerr : 1; 551 uint64_t hwerr : 1; 552 uint64_t fault : 1; 553 uint64_t reserved_5_63 : 59; 554 #endif /* Word 0 - End */ 555 } s; 556 } cptx_vqx_misc_int_t; 557 558 /** 559 * Register (NCB) cpt#_vq#_saddr 560 * 561 * CPT Queue Starting Buffer Address Registers 562 * These registers set the instruction buffer starting address. 563 */ 564 typedef union { 565 uint64_t u; 566 struct cptx_vqx_saddr_s { 567 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ 568 uint64_t reserved_49_63 : 15; 569 /** [ 48: 6](R/W/H) Instruction buffer IOVA <48:6> 570 * (64-byte aligned). When written, it is the initial buffer 571 * starting address; when read, it is the next read pointer to 572 * be requested from L2C. The PTR field is overwritten with the 573 * next pointer each time that the command buffer segment is 574 * exhausted. New commands will then be read from the newly 575 * specified command buffer pointer. 576 **/ 577 uint64_t ptr : 43; 578 uint64_t reserved_0_5 : 6; 579 #else /* Word 0 - Little Endian */ 580 uint64_t reserved_0_5 : 6; 581 uint64_t ptr : 43; 582 uint64_t reserved_49_63 : 15; 583 #endif /* Word 0 - End */ 584 } s; 585 } cptx_vqx_saddr_t; 586 587 #endif /*_CPT_HW_TYPES_H_ */ 588