1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2007 VMware, Inc. All rights reserved. 3 */ 4 5 /* 6 * vmxnet3_defs.h -- 7 * 8 * Definitions shared by device emulation and guest drivers for 9 * VMXNET3 NIC 10 */ 11 12 #ifndef _VMXNET3_DEFS_H_ 13 #define _VMXNET3_DEFS_H_ 14 15 #include "vmxnet3_osdep.h" 16 #include "upt1_defs.h" 17 18 /* all registers are 32 bit wide */ 19 /* BAR 1 */ 20 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */ 21 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */ 22 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */ 23 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */ 24 #define VMXNET3_REG_CMD 0x20 /* Command */ 25 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */ 26 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ 27 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ 28 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ 29 #define VMXNET3_REG_DCR 0x48 /* Device capability register, 30 * from 0x48 to 0x80 31 */ 32 #define VMXNET3_REG_PTCR 0x88 /* Passthru capbility register 33 * from 0x88 to 0xb0 34 */ 35 36 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ 37 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ 38 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */ 39 40 /* BAR 0 */ 41 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */ 42 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */ 43 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ 44 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ 45 46 /* For Large PT BAR, the following offset to DB register */ 47 #define VMXNET3_REG_LB_TXPROD 0x1000 /* Tx Producer Index */ 48 #define VMXNET3_REG_LB_RXPROD 0x1400 /* Rx Producer Index for ring 1 */ 49 #define VMXNET3_REG_LB_RXPROD2 0x1800 /* Rx Producer Index for ring 2 */ 50 51 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 52 #define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */ 53 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 54 #define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */ 55 #define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */ 56 57 /* 58 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at 59 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region: 60 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE--> 61 * ------------------------------------------------------------------------- 62 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table | 63 * ------------------------------------------------------------------------- 64 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" 65 */ 66 #define VMXNET3_PHYSMEM_PAGES 4 67 #define VMXNET3_PHYSMEM_LB_PAGES 4099 /* 4096 + 1 + 2 */ 68 69 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 70 #define VMXNET3_REG_ALIGN_MASK 0x7 71 72 /* I/O Mapped access to registers */ 73 #define VMXNET3_IO_TYPE_PT 0 74 #define VMXNET3_IO_TYPE_VD 1 75 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 76 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 77 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 78 79 #ifndef __le16 80 #define __le16 uint16 81 #endif 82 #ifndef __le32 83 #define __le32 uint32 84 #endif 85 #ifndef __le64 86 #define __le64 uint64 87 #endif 88 89 typedef enum { 90 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 91 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 92 VMXNET3_CMD_QUIESCE_DEV, 93 VMXNET3_CMD_RESET_DEV, 94 VMXNET3_CMD_UPDATE_RX_MODE, 95 VMXNET3_CMD_UPDATE_MAC_FILTERS, 96 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 97 VMXNET3_CMD_UPDATE_RSSIDT, 98 VMXNET3_CMD_UPDATE_IML, 99 VMXNET3_CMD_UPDATE_PMCFG, 100 VMXNET3_CMD_UPDATE_FEATURE, 101 VMXNET3_CMD_STOP_EMULATION, 102 VMXNET3_CMD_LOAD_PLUGIN, 103 VMXNET3_CMD_ACTIVATE_VF, 104 VMXNET3_CMD_RESERVED3, 105 VMXNET3_CMD_RESERVED4, 106 VMXNET3_CMD_REGISTER_MEMREGS, 107 VMXNET3_CMD_SET_RSS_FIELDS, 108 VMXNET3_CMD_RESERVED9, 109 VMXNET3_CMD_RESERVED10, 110 VMXNET3_CMD_SET_RING_BUFFER_SIZE, 111 112 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 113 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 114 VMXNET3_CMD_GET_STATS, 115 VMXNET3_CMD_GET_LINK, 116 VMXNET3_CMD_GET_PERM_MAC_LO, 117 VMXNET3_CMD_GET_PERM_MAC_HI, 118 VMXNET3_CMD_GET_DID_LO, 119 VMXNET3_CMD_GET_DID_HI, 120 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 121 VMXNET3_CMD_GET_CONF_INTR, 122 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO, 123 VMXNET3_CMD_GET_TXDATA_DESC_SIZE, 124 VMXNET3_CMD_RESERVED5, 125 VMXNET3_CMD_RESERVED6, 126 VMXNET3_CMD_RESERVED7, 127 VMXNET3_CMD_RESERVED8, 128 VMXNET3_CMD_GET_MAX_QUEUES_CONF, 129 VMXNET3_CMD_RESERVED11, 130 VMXNET3_CMD_GET_MAX_CAPABILITIES, 131 VMXNET3_CMD_GET_DCR0_REG, 132 } Vmxnet3_Cmd; 133 134 /* Adaptive Ring Info Flags */ 135 #define VMXNET3_DISABLE_ADAPTIVE_RING 1 136 137 /* 138 * Little Endian layout of bitfields - 139 * Byte 0 : 7.....len.....0 140 * Byte 1 : rsvd gen 13.len.8 141 * Byte 2 : 5.msscof.0 ext1 dtype 142 * Byte 3 : 13...msscof...6 143 * 144 * Big Endian layout of bitfields - 145 * Byte 0: 13...msscof...6 146 * Byte 1 : 5.msscof.0 ext1 dtype 147 * Byte 2 : rsvd gen 13.len.8 148 * Byte 3 : 7.....len.....0 149 * 150 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 151 * the bit fields correctly. And cpu_to_le32 will convert bitfields 152 * bit fields written by big endian driver to format required by device. 153 */ 154 155 typedef 156 #include "vmware_pack_begin.h" 157 struct Vmxnet3_TxDesc { 158 __le64 addr; 159 160 #ifdef __BIG_ENDIAN_BITFIELD 161 uint32 msscof:14; /* MSS, checksum offset, flags */ 162 uint32 ext1:1; 163 uint32 dtype:1; /* descriptor type */ 164 uint32 rsvd:1; 165 uint32 gen:1; /* generation bit */ 166 uint32 len:14; 167 #else 168 uint32 len:14; 169 uint32 gen:1; /* generation bit */ 170 uint32 rsvd:1; 171 uint32 dtype:1; /* descriptor type */ 172 uint32 ext1:1; 173 uint32 msscof:14; /* MSS, checksum offset, flags */ 174 #endif /* __BIG_ENDIAN_BITFIELD */ 175 176 #ifdef __BIG_ENDIAN_BITFIELD 177 uint32 tci:16; /* Tag to Insert */ 178 uint32 ti:1; /* VLAN Tag Insertion */ 179 uint32 ext2:1; 180 uint32 cq:1; /* completion request */ 181 uint32 eop:1; /* End Of Packet */ 182 uint32 om:2; /* offload mode */ 183 uint32 hlen:10; /* header len */ 184 #else 185 uint32 hlen:10; /* header len */ 186 uint32 om:2; /* offload mode */ 187 uint32 eop:1; /* End Of Packet */ 188 uint32 cq:1; /* completion request */ 189 uint32 ext2:1; 190 uint32 ti:1; /* VLAN Tag Insertion */ 191 uint32 tci:16; /* Tag to Insert */ 192 #endif /* __BIG_ENDIAN_BITFIELD */ 193 } 194 #include "vmware_pack_end.h" 195 Vmxnet3_TxDesc; 196 197 /* TxDesc.OM values */ 198 #define VMXNET3_OM_NONE 0 199 #define VMXNET3_OM_CSUM 2 200 #define VMXNET3_OM_TSO 3 201 202 /* fields in TxDesc we access w/o using bit fields */ 203 #define VMXNET3_TXD_EOP_SHIFT 12 204 #define VMXNET3_TXD_CQ_SHIFT 13 205 #define VMXNET3_TXD_GEN_SHIFT 14 206 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 207 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 208 209 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 210 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 211 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 212 213 #define VMXNET3_TXD_GEN_SIZE 1 214 #define VMXNET3_TXD_EOP_SIZE 1 215 216 #define VMXNET3_HDR_COPY_SIZE 128 217 218 typedef 219 #include "vmware_pack_begin.h" 220 struct Vmxnet3_TxDataDesc { 221 uint8 data[VMXNET3_HDR_COPY_SIZE]; 222 } 223 #include "vmware_pack_end.h" 224 Vmxnet3_TxDataDesc; 225 226 #define VMXNET3_TCD_GEN_SHIFT 31 227 #define VMXNET3_TCD_GEN_SIZE 1 228 #define VMXNET3_TCD_TXIDX_SHIFT 0 229 #define VMXNET3_TCD_TXIDX_SIZE 12 230 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 231 232 typedef 233 #include "vmware_pack_begin.h" 234 struct Vmxnet3_TxCompDesc { 235 uint32 txdIdx:12; /* Index of the EOP TxDesc */ 236 uint32 ext1:20; 237 238 __le32 ext2; 239 __le32 ext3; 240 241 uint32 rsvd:24; 242 uint32 type:7; /* completion type */ 243 uint32 gen:1; /* generation bit */ 244 } 245 #include "vmware_pack_end.h" 246 Vmxnet3_TxCompDesc; 247 248 typedef 249 #include "vmware_pack_begin.h" 250 struct Vmxnet3_RxDesc { 251 __le64 addr; 252 253 #ifdef __BIG_ENDIAN_BITFIELD 254 uint32 gen:1; /* Generation bit */ 255 uint32 rsvd:15; 256 uint32 dtype:1; /* Descriptor type */ 257 uint32 btype:1; /* Buffer Type */ 258 uint32 len:14; 259 #else 260 uint32 len:14; 261 uint32 btype:1; /* Buffer Type */ 262 uint32 dtype:1; /* Descriptor type */ 263 uint32 rsvd:15; 264 uint32 gen:1; /* Generation bit */ 265 #endif 266 __le32 ext1; 267 } 268 #include "vmware_pack_end.h" 269 Vmxnet3_RxDesc; 270 271 /* values of RXD.BTYPE */ 272 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 273 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 274 275 /* fields in RxDesc we access w/o using bit fields */ 276 #define VMXNET3_RXD_BTYPE_SHIFT 14 277 #define VMXNET3_RXD_GEN_SHIFT 31 278 279 typedef 280 #include "vmware_pack_begin.h" 281 struct Vmxnet3_RxCompDesc { 282 #ifdef __BIG_ENDIAN_BITFIELD 283 uint32 ext2:1; 284 uint32 cnc:1; /* Checksum Not Calculated */ 285 uint32 rssType:4; /* RSS hash type used */ 286 uint32 rqID:10; /* rx queue/ring ID */ 287 uint32 sop:1; /* Start of Packet */ 288 uint32 eop:1; /* End of Packet */ 289 uint32 ext1:2; 290 uint32 rxdIdx:12; /* Index of the RxDesc */ 291 #else 292 uint32 rxdIdx:12; /* Index of the RxDesc */ 293 uint32 ext1:2; 294 uint32 eop:1; /* End of Packet */ 295 uint32 sop:1; /* Start of Packet */ 296 uint32 rqID:10; /* rx queue/ring ID */ 297 uint32 rssType:4; /* RSS hash type used */ 298 uint32 cnc:1; /* Checksum Not Calculated */ 299 uint32 ext2:1; 300 #endif /* __BIG_ENDIAN_BITFIELD */ 301 302 __le32 rssHash; /* RSS hash value */ 303 304 #ifdef __BIG_ENDIAN_BITFIELD 305 uint32 tci:16; /* Tag stripped */ 306 uint32 ts:1; /* Tag is stripped */ 307 uint32 err:1; /* Error */ 308 uint32 len:14; /* data length */ 309 #else 310 uint32 len:14; /* data length */ 311 uint32 err:1; /* Error */ 312 uint32 ts:1; /* Tag is stripped */ 313 uint32 tci:16; /* Tag stripped */ 314 #endif /* __BIG_ENDIAN_BITFIELD */ 315 316 317 #ifdef __BIG_ENDIAN_BITFIELD 318 uint32 gen:1; /* generation bit */ 319 uint32 type:7; /* completion type */ 320 uint32 fcs:1; /* Frame CRC correct */ 321 uint32 frg:1; /* IP Fragment */ 322 uint32 v4:1; /* IPv4 */ 323 uint32 v6:1; /* IPv6 */ 324 uint32 ipc:1; /* IP Checksum Correct */ 325 uint32 tcp:1; /* TCP packet */ 326 uint32 udp:1; /* UDP packet */ 327 uint32 tuc:1; /* TCP/UDP Checksum Correct */ 328 uint32 csum:16; 329 #else 330 uint32 csum:16; 331 uint32 tuc:1; /* TCP/UDP Checksum Correct */ 332 uint32 udp:1; /* UDP packet */ 333 uint32 tcp:1; /* TCP packet */ 334 uint32 ipc:1; /* IP Checksum Correct */ 335 uint32 v6:1; /* IPv6 */ 336 uint32 v4:1; /* IPv4 */ 337 uint32 frg:1; /* IP Fragment */ 338 uint32 fcs:1; /* Frame CRC correct */ 339 uint32 type:7; /* completion type */ 340 uint32 gen:1; /* generation bit */ 341 #endif /* __BIG_ENDIAN_BITFIELD */ 342 } 343 #include "vmware_pack_end.h" 344 Vmxnet3_RxCompDesc; 345 346 typedef 347 #include "vmware_pack_begin.h" 348 struct Vmxnet3_RxCompDescExt { 349 __le32 dword1; 350 uint8 segCnt; /* Number of aggregated packets */ 351 uint8 dupAckCnt; /* Number of duplicate Acks */ 352 __le16 tsDelta; /* TCP timestamp difference */ 353 __le32 dword2; 354 #ifdef __BIG_ENDIAN_BITFIELD 355 uint32 gen : 1; /* generation bit */ 356 uint32 type : 7; /* completion type */ 357 uint32 fcs : 1; /* Frame CRC correct */ 358 uint32 frg : 1; /* IP Fragment */ 359 uint32 v4 : 1; /* IPv4 */ 360 uint32 v6 : 1; /* IPv6 */ 361 uint32 ipc : 1; /* IP Checksum Correct */ 362 uint32 tcp : 1; /* TCP packet */ 363 uint32 udp : 1; /* UDP packet */ 364 uint32 tuc : 1; /* TCP/UDP Checksum Correct */ 365 uint32 mss : 16; 366 #else 367 uint32 mss : 16; 368 uint32 tuc : 1; /* TCP/UDP Checksum Correct */ 369 uint32 udp : 1; /* UDP packet */ 370 uint32 tcp : 1; /* TCP packet */ 371 uint32 ipc : 1; /* IP Checksum Correct */ 372 uint32 v6 : 1; /* IPv6 */ 373 uint32 v4 : 1; /* IPv4 */ 374 uint32 frg : 1; /* IP Fragment */ 375 uint32 fcs : 1; /* Frame CRC correct */ 376 uint32 type : 7; /* completion type */ 377 uint32 gen : 1; /* generation bit */ 378 #endif /* __BIG_ENDIAN_BITFIELD */ 379 } 380 #include "vmware_pack_end.h" 381 Vmxnet3_RxCompDescExt; 382 383 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 384 #define VMXNET3_RCD_TUC_SHIFT 16 385 #define VMXNET3_RCD_IPC_SHIFT 19 386 387 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 388 #define VMXNET3_RCD_TYPE_SHIFT 56 389 #define VMXNET3_RCD_GEN_SHIFT 63 390 391 /* csum OK for TCP/UDP pkts over IP */ 392 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT) 393 394 /* value of RxCompDesc.rssType */ 395 #define VMXNET3_RCD_RSS_TYPE_NONE 0 396 #define VMXNET3_RCD_RSS_TYPE_IPV4 1 397 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 398 #define VMXNET3_RCD_RSS_TYPE_IPV6 3 399 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 400 401 /* a union for accessing all cmd/completion descriptors */ 402 typedef union Vmxnet3_GenericDesc { 403 __le64 qword[2]; 404 __le32 dword[4]; 405 __le16 word[8]; 406 Vmxnet3_TxDesc txd; 407 Vmxnet3_RxDesc rxd; 408 Vmxnet3_TxCompDesc tcd; 409 Vmxnet3_RxCompDesc rcd; 410 Vmxnet3_RxCompDescExt rcdExt; 411 } Vmxnet3_GenericDesc; 412 413 #define VMXNET3_INIT_GEN 1 414 415 /* Max size of a single tx buffer */ 416 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 417 418 /* # of tx desc needed for a tx buffer size */ 419 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE) 420 421 /* max # of tx descs for a non-tso pkt */ 422 #define VMXNET3_MAX_TXD_PER_PKT 16 423 /* max # of tx descs for a tso pkt */ 424 #define VMXNET3_MAX_TSO_TXD_PER_PKT 24 425 426 /* Max size of a single rx buffer */ 427 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 428 /* Minimum size of a type 0 buffer */ 429 #define VMXNET3_MIN_T0_BUF_SIZE 128 430 #define VMXNET3_MAX_CSUM_OFFSET 1024 431 432 /* Ring base address alignment */ 433 #define VMXNET3_RING_BA_ALIGN 512 434 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 435 436 /* Ring size must be a multiple of 32 */ 437 #define VMXNET3_RING_SIZE_ALIGN 32 438 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 439 440 /* Tx Data Ring buffer size must be a multiple of 64 */ 441 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 442 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) 443 444 /* Rx Data Ring buffer size must be a multiple of 64 */ 445 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64 446 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1) 447 448 /* Max ring size */ 449 #define VMXNET3_TX_RING_MAX_SIZE 4096 450 #define VMXNET3_TC_RING_MAX_SIZE 4096 451 #define VMXNET3_RX_RING_MAX_SIZE 4096 452 #define VMXNET3_RC_RING_MAX_SIZE 8192 453 454 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128 455 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 456 457 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 458 459 /* a list of reasons for queue stop */ 460 461 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */ 462 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */ 463 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */ 464 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */ 465 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */ 466 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */ 467 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */ 468 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */ 469 470 /* completion descriptor types */ 471 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 472 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 473 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */ 474 475 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */ 476 #define VMXNET3_GOS_BITS_32 1 477 #define VMXNET3_GOS_BITS_64 2 478 479 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 480 #define VMXNET3_GOS_TYPE_LINUX 1 481 #define VMXNET3_GOS_TYPE_WIN 2 482 #define VMXNET3_GOS_TYPE_SOLARIS 3 483 #define VMXNET3_GOS_TYPE_FREEBSD 4 484 #define VMXNET3_GOS_TYPE_PXE 5 485 486 /* All structures in DriverShared are padded to multiples of 8 bytes */ 487 488 typedef 489 #include "vmware_pack_begin.h" 490 struct Vmxnet3_GOSInfo { 491 #ifdef __BIG_ENDIAN_BITFIELD 492 uint32 gosMisc: 10; /* other info about gos */ 493 uint32 gosVer: 16; /* gos version */ 494 uint32 gosType: 4; /* which guest */ 495 uint32 gosBits: 2; /* 32-bit or 64-bit? */ 496 #else 497 uint32 gosBits: 2; /* 32-bit or 64-bit? */ 498 uint32 gosType: 4; /* which guest */ 499 uint32 gosVer: 16; /* gos version */ 500 uint32 gosMisc: 10; /* other info about gos */ 501 #endif /* __BIG_ENDIAN_BITFIELD */ 502 } 503 #include "vmware_pack_end.h" 504 Vmxnet3_GOSInfo; 505 506 typedef 507 #include "vmware_pack_begin.h" 508 struct Vmxnet3_DriverInfo { 509 __le32 version; /* driver version */ 510 Vmxnet3_GOSInfo gos; 511 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */ 512 __le32 uptVerSpt; /* upt version supported */ 513 } 514 #include "vmware_pack_end.h" 515 Vmxnet3_DriverInfo; 516 517 #define VMXNET3_REV1_MAGIC 0xbabefee1 518 519 /* 520 * QueueDescPA must be 128 bytes aligned. It points to an array of 521 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 522 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 523 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 524 */ 525 #define VMXNET3_QUEUE_DESC_ALIGN 128 526 527 typedef 528 #include "vmware_pack_begin.h" 529 struct Vmxnet3_MiscConf { 530 Vmxnet3_DriverInfo driverInfo; 531 __le64 uptFeatures; 532 __le64 ddPA; /* driver data PA */ 533 __le64 queueDescPA; /* queue descriptor table PA */ 534 __le32 ddLen; /* driver data len */ 535 __le32 queueDescLen; /* queue descriptor table len, in bytes */ 536 __le32 mtu; 537 __le16 maxNumRxSG; 538 uint8 numTxQueues; 539 uint8 numRxQueues; 540 __le32 reserved[4]; 541 } 542 #include "vmware_pack_end.h" 543 Vmxnet3_MiscConf; 544 545 typedef 546 #include "vmware_pack_begin.h" 547 struct Vmxnet3_TxQueueConf { 548 __le64 txRingBasePA; 549 __le64 dataRingBasePA; 550 __le64 compRingBasePA; 551 __le64 ddPA; /* driver data */ 552 __le64 reserved; 553 __le32 txRingSize; /* # of tx desc */ 554 __le32 dataRingSize; /* # of data desc */ 555 __le32 compRingSize; /* # of comp desc */ 556 __le32 ddLen; /* size of driver data */ 557 uint8 intrIdx; 558 uint8 _pad[1]; 559 __le16 txDataRingDescSize; 560 uint8 _pad2[4]; 561 } 562 #include "vmware_pack_end.h" 563 Vmxnet3_TxQueueConf; 564 565 typedef 566 #include "vmware_pack_begin.h" 567 struct Vmxnet3_RxQueueConf { 568 __le64 rxRingBasePA[2]; 569 __le64 compRingBasePA; 570 __le64 ddPA; /* driver data */ 571 __le64 rxDataRingBasePA; 572 __le32 rxRingSize[2]; /* # of rx desc */ 573 __le32 compRingSize; /* # of rx comp desc */ 574 __le32 ddLen; /* size of driver data */ 575 uint8 intrIdx; 576 uint8 _pad1[1]; 577 __le16 rxDataRingDescSize; /* size of rx data ring buffer */ 578 uint8 _pad2[4]; 579 } 580 #include "vmware_pack_end.h" 581 Vmxnet3_RxQueueConf; 582 583 enum vmxnet3_intr_mask_mode { 584 VMXNET3_IMM_AUTO = 0, 585 VMXNET3_IMM_ACTIVE = 1, 586 VMXNET3_IMM_LAZY = 2 587 }; 588 589 enum vmxnet3_intr_type { 590 VMXNET3_IT_AUTO = 0, 591 VMXNET3_IT_INTX = 1, 592 VMXNET3_IT_MSI = 2, 593 VMXNET3_IT_MSIX = 3 594 }; 595 596 #define VMXNET3_MAX_TX_QUEUES 8 597 #define VMXNET3_MAX_RX_QUEUES 16 598 /* addition 1 for events */ 599 #define VMXNET3_MAX_INTRS 25 600 601 /* Version 6 and later will use below macros */ 602 #define VMXNET3_EXT_MAX_TX_QUEUES 32 603 #define VMXNET3_EXT_MAX_RX_QUEUES 32 604 605 /* Version-dependent MAX RX/TX queues macro */ 606 #define MAX_RX_QUEUES(hw) \ 607 (VMXNET3_VERSION_GE_6((hw)) ? \ 608 VMXNET3_EXT_MAX_RX_QUEUES : \ 609 VMXNET3_MAX_RX_QUEUES) 610 #define MAX_TX_QUEUES(hw) \ 611 (VMXNET3_VERSION_GE_6((hw)) ? \ 612 VMXNET3_EXT_MAX_TX_QUEUES : \ 613 VMXNET3_MAX_TX_QUEUES) 614 615 /* addition 1 for events */ 616 #define VMXNET3_EXT_MAX_INTRS 65 617 #define VMXNET3_FIRST_SET_INTRS 64 618 619 /* value of intrCtrl */ 620 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 621 622 typedef 623 #include "vmware_pack_begin.h" 624 struct Vmxnet3_IntrConf { 625 bool autoMask; 626 uint8 numIntrs; /* # of interrupts */ 627 uint8 eventIntrIdx; 628 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */ 629 __le32 intrCtrl; 630 __le32 reserved[2]; 631 } 632 #include "vmware_pack_end.h" 633 Vmxnet3_IntrConf; 634 635 typedef 636 #include "vmware_pack_begin.h" 637 struct Vmxnet3_IntrConfExt { 638 uint8 autoMask; 639 uint8 numIntrs; /* # of interrupts */ 640 uint8 eventIntrIdx; 641 uint8 reserved; 642 __le32 intrCtrl; 643 __le32 reserved1; 644 uint8 modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for each intr */ 645 uint8 reserved2[3]; 646 } 647 #include "vmware_pack_end.h" 648 Vmxnet3_IntrConfExt; 649 650 /* one bit per VLAN ID, the size is in the units of uint32 */ 651 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8)) 652 653 typedef 654 #include "vmware_pack_begin.h" 655 struct Vmxnet3_QueueStatus { 656 bool stopped; 657 uint8 _pad[3]; 658 __le32 error; 659 } 660 #include "vmware_pack_end.h" 661 Vmxnet3_QueueStatus; 662 663 typedef 664 #include "vmware_pack_begin.h" 665 struct Vmxnet3_TxQueueCtrl { 666 __le32 txNumDeferred; 667 __le32 txThreshold; 668 __le64 reserved; 669 } 670 #include "vmware_pack_end.h" 671 Vmxnet3_TxQueueCtrl; 672 673 typedef 674 #include "vmware_pack_begin.h" 675 struct Vmxnet3_RxQueueCtrl { 676 bool updateRxProd; 677 uint8 _pad[7]; 678 __le64 reserved; 679 } 680 #include "vmware_pack_end.h" 681 Vmxnet3_RxQueueCtrl; 682 683 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */ 684 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */ 685 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */ 686 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */ 687 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */ 688 689 typedef 690 #include "vmware_pack_begin.h" 691 struct Vmxnet3_RxFilterConf { 692 __le32 rxMode; /* VMXNET3_RXM_xxx */ 693 __le16 mfTableLen; /* size of the multicast filter table */ 694 __le16 _pad1; 695 __le64 mfTablePA; /* PA of the multicast filters table */ 696 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 697 } 698 #include "vmware_pack_end.h" 699 Vmxnet3_RxFilterConf; 700 701 #define VMXNET3_PM_MAX_FILTERS 6 702 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 703 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 704 705 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */ 706 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */ 707 708 typedef 709 #include "vmware_pack_begin.h" 710 struct Vmxnet3_PM_PktFilter { 711 uint8 maskSize; 712 uint8 patternSize; 713 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 714 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 715 uint8 pad[6]; 716 } 717 #include "vmware_pack_end.h" 718 Vmxnet3_PM_PktFilter; 719 720 typedef 721 #include "vmware_pack_begin.h" 722 struct Vmxnet3_PMConf { 723 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 724 uint8 numFilters; 725 uint8 pad[5]; 726 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 727 } 728 #include "vmware_pack_end.h" 729 Vmxnet3_PMConf; 730 731 typedef 732 #include "vmware_pack_begin.h" 733 struct Vmxnet3_VariableLenConfDesc { 734 __le32 confVer; 735 __le32 confLen; 736 __le64 confPA; 737 } 738 #include "vmware_pack_end.h" 739 Vmxnet3_VariableLenConfDesc; 740 741 typedef 742 #include "vmware_pack_begin.h" 743 struct Vmxnet3_DSDevRead { 744 /* read-only region for device, read by dev in response to a SET cmd */ 745 Vmxnet3_MiscConf misc; 746 Vmxnet3_IntrConf intrConf; 747 Vmxnet3_RxFilterConf rxFilterConf; 748 Vmxnet3_VariableLenConfDesc rssConfDesc; 749 Vmxnet3_VariableLenConfDesc pmConfDesc; 750 Vmxnet3_VariableLenConfDesc pluginConfDesc; 751 } 752 #include "vmware_pack_end.h" 753 Vmxnet3_DSDevRead; 754 755 typedef 756 #include "vmware_pack_begin.h" 757 struct Vmxnet3_DSDevReadExt { 758 /* read-only region for device, read by dev in response to a SET cmd */ 759 struct Vmxnet3_IntrConfExt intrConfExt; 760 } 761 #include "vmware_pack_end.h" 762 Vmxnet3_DSDevReadExt; 763 764 typedef 765 #include "vmware_pack_begin.h" 766 struct Vmxnet3_TxQueueDesc { 767 Vmxnet3_TxQueueCtrl ctrl; 768 Vmxnet3_TxQueueConf conf; 769 /* Driver read after a GET command */ 770 Vmxnet3_QueueStatus status; 771 UPT1_TxStats stats; 772 uint8 _pad[88]; /* 128 aligned */ 773 } 774 #include "vmware_pack_end.h" 775 Vmxnet3_TxQueueDesc; 776 777 typedef 778 #include "vmware_pack_begin.h" 779 struct Vmxnet3_RxQueueDesc { 780 Vmxnet3_RxQueueCtrl ctrl; 781 Vmxnet3_RxQueueConf conf; 782 /* Driver read after a GET command */ 783 Vmxnet3_QueueStatus status; 784 UPT1_RxStats stats; 785 uint8 _pad[88]; /* 128 aligned */ 786 } 787 #include "vmware_pack_end.h" 788 Vmxnet3_RxQueueDesc; 789 790 typedef 791 #include "vmware_pack_begin.h" 792 struct Vmxnet3_SetPolling { 793 uint8 enablePolling; 794 } 795 #include "vmware_pack_end.h" 796 Vmxnet3_SetPolling; 797 798 typedef 799 #include "vmware_pack_begin.h" 800 struct Vmxnet3_MemoryRegion { 801 __le64 startPA; 802 __le32 length; 803 __le16 txQueueBits; /* bit n corresponding to tx queue n */ 804 __le16 rxQueueBits; /* bit n corresponding to rx queue n */ 805 } 806 #include "vmware_pack_end.h" 807 Vmxnet3_MemoryRegion; 808 809 #define MAX_MEMORY_REGION_PER_QUEUE 16 810 #define MAX_MEMORY_REGION_PER_DEVICE 256 811 812 typedef 813 #include "vmware_pack_begin.h" 814 struct Vmxnet3_MemRegs { 815 __le16 numRegs; 816 __le16 pad[3]; 817 Vmxnet3_MemoryRegion memRegs[1]; 818 } 819 #include "vmware_pack_end.h" 820 Vmxnet3_MemRegs; 821 822 typedef enum Vmxnet3_RSSField { 823 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001, 824 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002, 825 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004, 826 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008, 827 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010, 828 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020, 829 } Vmxnet3_RSSField; 830 831 typedef 832 #include "vmware_pack_begin.h" 833 struct Vmxnet3_RingBufferSize { 834 __le16 ring1BufSizeType0; 835 __le16 ring1BufSizeType1; 836 __le16 ring2BufSizeType1; 837 __le16 pad; 838 } 839 #include "vmware_pack_end.h" 840 Vmxnet3_RingBufferSize; 841 842 /* 843 * If the command data <= 16 bytes, use the shared memory direcly. 844 * Otherwise, use the variable length configuration descriptor. 845 */ 846 typedef 847 #include "vmware_pack_begin.h" 848 union Vmxnet3_CmdInfo { 849 Vmxnet3_VariableLenConfDesc varConf; 850 Vmxnet3_SetPolling setPolling; 851 Vmxnet3_RSSField setRSSFields; 852 Vmxnet3_RingBufferSize ringBufSize; 853 __le16 reserved[2]; 854 __le64 data[2]; 855 } 856 #include "vmware_pack_end.h" 857 Vmxnet3_CmdInfo; 858 859 typedef 860 #include "vmware_pack_begin.h" 861 struct Vmxnet3_DriverShared { 862 __le32 magic; 863 __le32 size; /* size of DriverShared */ 864 Vmxnet3_DSDevRead devRead; 865 __le32 ecr; 866 __le32 reserved; 867 868 union { 869 __le32 reserved1[4]; 870 /* only valid in the context of executing the relevant command */ 871 Vmxnet3_CmdInfo cmdInfo; 872 } cu; 873 struct Vmxnet3_DSDevReadExt devReadExt; 874 } 875 #include "vmware_pack_end.h" 876 Vmxnet3_DriverShared; 877 878 #define VMXNET3_ECR_RQERR (1 << 0) 879 #define VMXNET3_ECR_TQERR (1 << 1) 880 #define VMXNET3_ECR_LINK (1 << 2) 881 #define VMXNET3_ECR_DIC (1 << 3) 882 #define VMXNET3_ECR_DEBUG (1 << 4) 883 884 /* flip the gen bit of a ring */ 885 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 886 887 /* only use this if moving the idx won't affect the gen bit */ 888 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 889 do {\ 890 (idx)++;\ 891 if (UNLIKELY((idx) == (ring_size))) {\ 892 (idx) = 0;\ 893 }\ 894 } while (0) 895 896 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 897 vfTable[vid >> 5] |= (1 << (vid & 31)) 898 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 899 vfTable[vid >> 5] &= ~(1 << (vid & 31)) 900 901 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 902 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 903 904 #define VMXNET3_MAX_MTU 9000 905 #define VMXNET3_V6_MAX_MTU 9190 906 #define VMXNET3_MIN_MTU 60 907 908 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up 909 #define VMXNET3_LINK_DOWN 0 910 911 #define VMXWIFI_DRIVER_SHARED_LEN 8192 912 913 #define VMXNET3_DID_PASSTHRU 0xFFFF 914 915 #define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */ 916 #define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */ 917 #define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */ 918 #define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */ 919 #define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */ 920 #define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */ 921 #define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */ 922 #define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */ 923 #define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */ 924 #define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */ 925 #define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4 926 #define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */ 927 #define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6 928 #define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */ 929 #define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */ 930 #define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */ 931 #define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */ 932 #define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC 933 #define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */ 934 #define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */ 935 #define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */ 936 #define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */ 937 #define VMXNET3_CAP_VERSION_7_MAX 18 938 /* when new capability is introduced, update VMXNET3_CAP_MAX */ 939 #define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX 940 941 #endif /* _VMXNET3_DEFS_H_ */ 942