1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include "dcn32_fpu.h" 27 #include "dcn32/dcn32_resource.h" 28 #include "dcn20/dcn20_resource.h" 29 #include "display_mode_vba_util_32.h" 30 #include "dml/dcn32/display_mode_vba_32.h" 31 // We need this includes for WATERMARKS_* defines 32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" 33 #include "dcn30/dcn30_resource.h" 34 #include "link.h" 35 36 #define DC_LOGGER_INIT(logger) 37 38 static const struct subvp_high_refresh_list subvp_high_refresh_list = { 39 .min_refresh = 120, 40 .max_refresh = 175, 41 .res = { 42 {.width = 3840, .height = 2160, }, 43 {.width = 3440, .height = 1440, }, 44 {.width = 2560, .height = 1440, }}, 45 }; 46 47 struct _vcs_dpi_ip_params_st dcn3_2_ip = { 48 .gpuvm_enable = 0, 49 .gpuvm_max_page_table_levels = 4, 50 .hostvm_enable = 0, 51 .rob_buffer_size_kbytes = 128, 52 .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE, 53 .config_return_buffer_size_in_kbytes = 1280, 54 .compressed_buffer_segment_size_in_kbytes = 64, 55 .meta_fifo_size_in_kentries = 22, 56 .zero_size_buffer_entries = 512, 57 .compbuf_reserved_space_64b = 256, 58 .compbuf_reserved_space_zs = 64, 59 .dpp_output_buffer_pixels = 2560, 60 .opp_output_buffer_lines = 1, 61 .pixel_chunk_size_kbytes = 8, 62 .alpha_pixel_chunk_size_kbytes = 4, 63 .min_pixel_chunk_size_bytes = 1024, 64 .dcc_meta_buffer_size_bytes = 6272, 65 .meta_chunk_size_kbytes = 2, 66 .min_meta_chunk_size_bytes = 256, 67 .writeback_chunk_size_kbytes = 8, 68 .ptoi_supported = false, 69 .num_dsc = 4, 70 .maximum_dsc_bits_per_component = 12, 71 .maximum_pixels_per_line_per_dsc_unit = 6016, 72 .dsc422_native_support = true, 73 .is_line_buffer_bpp_fixed = true, 74 .line_buffer_fixed_bpp = 57, 75 .line_buffer_size_bits = 1171920, 76 .max_line_buffer_lines = 32, 77 .writeback_interface_buffer_size_kbytes = 90, 78 .max_num_dpp = 4, 79 .max_num_otg = 4, 80 .max_num_hdmi_frl_outputs = 1, 81 .max_num_wb = 1, 82 .max_dchub_pscl_bw_pix_per_clk = 4, 83 .max_pscl_lb_bw_pix_per_clk = 2, 84 .max_lb_vscl_bw_pix_per_clk = 4, 85 .max_vscl_hscl_bw_pix_per_clk = 4, 86 .max_hscl_ratio = 6, 87 .max_vscl_ratio = 6, 88 .max_hscl_taps = 8, 89 .max_vscl_taps = 8, 90 .dpte_buffer_size_in_pte_reqs_luma = 64, 91 .dpte_buffer_size_in_pte_reqs_chroma = 34, 92 .dispclk_ramp_margin_percent = 1, 93 .max_inter_dcn_tile_repeaters = 8, 94 .cursor_buffer_size = 16, 95 .cursor_chunk_size = 2, 96 .writeback_line_buffer_buffer_size = 0, 97 .writeback_min_hscl_ratio = 1, 98 .writeback_min_vscl_ratio = 1, 99 .writeback_max_hscl_ratio = 1, 100 .writeback_max_vscl_ratio = 1, 101 .writeback_max_hscl_taps = 1, 102 .writeback_max_vscl_taps = 1, 103 .dppclk_delay_subtotal = 47, 104 .dppclk_delay_scl = 50, 105 .dppclk_delay_scl_lb_only = 16, 106 .dppclk_delay_cnvc_formatter = 28, 107 .dppclk_delay_cnvc_cursor = 6, 108 .dispclk_delay_subtotal = 125, 109 .dynamic_metadata_vm_enabled = false, 110 .odm_combine_4to1_supported = false, 111 .dcc_supported = true, 112 .max_num_dp2p0_outputs = 2, 113 .max_num_dp2p0_streams = 4, 114 }; 115 116 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { 117 .clock_limits = { 118 { 119 .state = 0, 120 .dcfclk_mhz = 1564.0, 121 .fabricclk_mhz = 2500.0, 122 .dispclk_mhz = 2150.0, 123 .dppclk_mhz = 2150.0, 124 .phyclk_mhz = 810.0, 125 .phyclk_d18_mhz = 667.0, 126 .phyclk_d32_mhz = 625.0, 127 .socclk_mhz = 1200.0, 128 .dscclk_mhz = 716.667, 129 .dram_speed_mts = 18000.0, 130 .dtbclk_mhz = 1564.0, 131 }, 132 }, 133 .num_states = 1, 134 .sr_exit_time_us = 42.97, 135 .sr_enter_plus_exit_time_us = 49.94, 136 .sr_exit_z8_time_us = 285.0, 137 .sr_enter_plus_exit_z8_time_us = 320, 138 .writeback_latency_us = 12.0, 139 .round_trip_ping_latency_dcfclk_cycles = 263, 140 .urgent_latency_pixel_data_only_us = 4.0, 141 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 142 .urgent_latency_vm_data_only_us = 4.0, 143 .fclk_change_latency_us = 25, 144 .usr_retraining_latency_us = 2, 145 .smn_latency_us = 2, 146 .mall_allocated_for_dcn_mbytes = 64, 147 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 148 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 149 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 150 .pct_ideal_sdp_bw_after_urgent = 90.0, 151 .pct_ideal_fabric_bw_after_urgent = 67.0, 152 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, 153 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented 154 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented 155 .pct_ideal_dram_bw_after_urgent_strobe = 67.0, 156 .max_avg_sdp_bw_use_normal_percent = 80.0, 157 .max_avg_fabric_bw_use_normal_percent = 60.0, 158 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 159 .max_avg_dram_bw_use_normal_percent = 15.0, 160 .num_chans = 24, 161 .dram_channel_width_bytes = 2, 162 .fabric_datapath_to_dcn_data_return_bytes = 64, 163 .return_bus_width_bytes = 64, 164 .downspread_percent = 0.38, 165 .dcn_downspread_percent = 0.5, 166 .dram_clock_change_latency_us = 400, 167 .dispclk_dppclk_vco_speed_mhz = 4300.0, 168 .do_urgent_latency_adjustment = true, 169 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 170 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, 171 }; 172 173 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 174 { 175 /* defaults */ 176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; 178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 180 /* For min clocks use as reported by PM FW and report those as min */ 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 183 uint16_t setb_min_uclk_mhz = min_uclk_mhz; 184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; 185 186 dc_assert_fp_enabled(); 187 188 /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ 189 if (dcfclk_mhz_for_the_second_state) 190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; 191 else 192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; 193 194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) 195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; 196 197 /* Set A - Normal - default values */ 198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us; 201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 205 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 206 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 207 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 208 209 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ 210 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us; 213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; 218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 219 220 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 221 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ 222 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { 223 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 224 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; 225 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us; 226 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 227 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 228 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 229 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 230 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 231 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 232 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 233 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; 234 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; 235 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; 236 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; 237 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; 238 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; 239 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; 240 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; 241 } 242 /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ 243 /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ 244 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; 245 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; 246 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us; 247 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD 248 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD 249 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 250 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; 251 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 252 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 253 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 254 } 255 256 /* 257 * Finds dummy_latency_index when MCLK switching using firmware based 258 * vblank stretch is enabled. This function will iterate through the 259 * table of dummy pstate latencies until the lowest value that allows 260 * dm_allow_self_refresh_and_mclk_switch to happen is found 261 */ 262 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 263 struct dc_state *context, 264 display_e2e_pipe_params_st *pipes, 265 int pipe_cnt, 266 int vlevel) 267 { 268 const int max_latency_table_entries = 4; 269 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 270 int dummy_latency_index = 0; 271 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 272 273 dc_assert_fp_enabled(); 274 275 while (dummy_latency_index < max_latency_table_entries) { 276 if (temp_clock_change_support != dm_dram_clock_change_unsupported) 277 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 278 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 279 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 281 282 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ 283 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && 284 dcn32_subvp_in_use(dc, context)) 285 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; 286 287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && 288 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) 289 break; 290 291 dummy_latency_index++; 292 } 293 294 if (dummy_latency_index == max_latency_table_entries) { 295 ASSERT(dummy_latency_index != max_latency_table_entries); 296 /* If the execution gets here, it means dummy p_states are 297 * not possible. This should never happen and would mean 298 * something is severely wrong. 299 * Here we reset dummy_latency_index to 3, because it is 300 * better to have underflows than system crashes. 301 */ 302 dummy_latency_index = max_latency_table_entries - 1; 303 } 304 305 return dummy_latency_index; 306 } 307 308 /** 309 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 310 * and populate pipe_ctx with those params. 311 * @dc: [in] current dc state 312 * @context: [in] new dc state 313 * @pipes: [in] DML pipe params array 314 * @pipe_cnt: [in] DML pipe count 315 * 316 * This function must be called AFTER the phantom pipes are added to context 317 * and run through DML (so that the DLG params for the phantom pipes can be 318 * populated), and BEFORE we program the timing for the phantom pipes. 319 */ 320 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 321 struct dc_state *context, 322 display_e2e_pipe_params_st *pipes, 323 int pipe_cnt) 324 { 325 uint32_t i, pipe_idx; 326 327 dc_assert_fp_enabled(); 328 329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 330 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 331 332 if (!pipe->stream) 333 continue; 334 335 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 336 pipes[pipe_idx].pipe.dest.vstartup_start = 337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 338 pipes[pipe_idx].pipe.dest.vupdate_offset = 339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 340 pipes[pipe_idx].pipe.dest.vupdate_width = 341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 342 pipes[pipe_idx].pipe.dest.vready_offset = 343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 344 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 345 } 346 pipe_idx++; 347 } 348 } 349 350 /** 351 * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe 352 * @context: [in] New DC state to be programmed 353 * @pipe_e2e: [in] DML pipe end to end context 354 * 355 * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both 356 * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is 357 * determined by DPPClk requirements 358 * 359 * This function follows the same policy as DML: 360 * - Check for ODM combine requirements / policy first 361 * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and 362 * MPC is required 363 * 364 * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits). 365 */ 366 uint8_t dcn32_predict_pipe_split(struct dc_state *context, 367 display_e2e_pipe_params_st *pipe_e2e) 368 { 369 double pscl_throughput; 370 double pscl_throughput_chroma; 371 double dpp_clk_single_dpp, clock; 372 double clk_frequency = 0.0; 373 double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; 374 bool total_available_pipes_support = false; 375 uint32_t number_of_dpp = 0; 376 enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled; 377 double req_dispclk_per_surface = 0; 378 uint8_t num_splits = 0; 379 380 dc_assert_fp_enabled(); 381 382 dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, 383 pipe_e2e->pipe.dest.hactive, 384 pipe_e2e->dout.output_format, 385 pipe_e2e->dout.output_type, 386 pipe_e2e->pipe.dest.odm_combine_policy, 387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, 389 pipe_e2e->dout.dsc_enable != 0, 390 0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */ 391 context->bw_ctx.dml.ip.max_num_dpp, 392 pipe_e2e->pipe.dest.pixel_rate_mhz, 393 context->bw_ctx.dml.soc.dcn_downspread_percent, 394 context->bw_ctx.dml.ip.dispclk_ramp_margin_percent, 395 context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz, 396 pipe_e2e->dout.dsc_slices, 397 /* Output */ 398 &total_available_pipes_support, 399 &number_of_dpp, 400 &odm_mode, 401 &req_dispclk_per_surface); 402 403 dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio, 404 pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c, 405 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio, 406 pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c, 407 context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk, 408 context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk, 409 pipe_e2e->pipe.dest.pixel_rate_mhz, 410 pipe_e2e->pipe.src.source_format, 411 pipe_e2e->pipe.scale_taps.htaps, 412 pipe_e2e->pipe.scale_taps.htaps_c, 413 pipe_e2e->pipe.scale_taps.vtaps, 414 pipe_e2e->pipe.scale_taps.vtaps_c, 415 /* Output */ 416 &pscl_throughput, &pscl_throughput_chroma, 417 &dpp_clk_single_dpp); 418 419 clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100); 420 421 if (clock > 0) 422 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock); 423 424 if (odm_mode == dm_odm_combine_mode_2to1) 425 num_splits = 1; 426 else if (odm_mode == dm_odm_combine_mode_4to1) 427 num_splits = 3; 428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) 429 num_splits = 1; 430 431 return num_splits; 432 } 433 434 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) 435 { 436 float memory_bw_kbytes_sec; 437 float fabric_bw_kbytes_sec; 438 float sdp_bw_kbytes_sec; 439 float limiting_bw_kbytes_sec; 440 441 memory_bw_kbytes_sec = entry->dram_speed_mts * 442 dcn3_2_soc.num_chans * 443 dcn3_2_soc.dram_channel_width_bytes * 444 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 445 446 fabric_bw_kbytes_sec = entry->fabricclk_mhz * 447 dcn3_2_soc.return_bus_width_bytes * 448 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 449 450 sdp_bw_kbytes_sec = entry->dcfclk_mhz * 451 dcn3_2_soc.return_bus_width_bytes * 452 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 453 454 limiting_bw_kbytes_sec = memory_bw_kbytes_sec; 455 456 if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) 457 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; 458 459 if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) 460 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; 461 462 return limiting_bw_kbytes_sec; 463 } 464 465 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) 466 { 467 if (entry->dcfclk_mhz > 0) { 468 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); 469 470 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 471 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * 472 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 473 } else if (entry->fabricclk_mhz > 0) { 474 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); 475 476 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 477 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * 478 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); 479 } else if (entry->dram_speed_mts > 0) { 480 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * 481 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); 482 483 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); 484 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); 485 } 486 } 487 488 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, 489 unsigned int *num_entries, 490 struct _vcs_dpi_voltage_scaling_st *entry) 491 { 492 int i = 0; 493 int index = 0; 494 495 dc_assert_fp_enabled(); 496 497 if (*num_entries == 0) { 498 table[0] = *entry; 499 (*num_entries)++; 500 } else { 501 while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) { 502 index++; 503 if (index >= *num_entries) 504 break; 505 } 506 507 for (i = *num_entries; i > index; i--) 508 table[i] = table[i - 1]; 509 510 table[index] = *entry; 511 (*num_entries)++; 512 } 513 } 514 515 /** 516 * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream 517 * @dc: current dc state 518 * @context: new dc state 519 * @ref_pipe: Main pipe for the phantom stream 520 * @phantom_stream: target phantom stream state 521 * @pipes: DML pipe params 522 * @pipe_cnt: number of DML pipes 523 * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) 524 * 525 * Set timing params of the phantom stream based on calculated output from DML. 526 * This function first gets the DML pipe index using the DC pipe index, then 527 * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of 528 * lines required for SubVP MCLK switching and assigns to the phantom stream 529 * accordingly. 530 * 531 * - The number of SubVP lines calculated in DML does not take into account 532 * FW processing delays and required pstate allow width, so we must include 533 * that separately. 534 * 535 * - Set phantom backporch = vstartup of main pipe 536 */ 537 void dcn32_set_phantom_stream_timing(struct dc *dc, 538 struct dc_state *context, 539 struct pipe_ctx *ref_pipe, 540 struct dc_stream_state *phantom_stream, 541 display_e2e_pipe_params_st *pipes, 542 unsigned int pipe_cnt, 543 unsigned int dc_pipe_idx) 544 { 545 unsigned int i, pipe_idx; 546 struct pipe_ctx *pipe; 547 uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; 548 unsigned int num_dpp; 549 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; 550 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 551 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; 552 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 553 struct dc_stream_state *main_stream = ref_pipe->stream; 554 555 dc_assert_fp_enabled(); 556 557 // Find DML pipe index (pipe_idx) using dc_pipe_idx 558 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 559 pipe = &context->res_ctx.pipe_ctx[i]; 560 561 if (!pipe->stream) 562 continue; 563 564 if (i == dc_pipe_idx) 565 break; 566 567 pipe_idx++; 568 } 569 570 // Calculate lines required for pstate allow width and FW processing delays 571 pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + 572 dc->caps.subvp_pstate_allow_width_us) / 1000000) * 573 (ref_pipe->stream->timing.pix_clk_100hz * 100) / 574 (double)ref_pipe->stream->timing.h_total; 575 576 // Update clks_cfg for calling into recalculate 577 pipes[0].clks_cfg.voltage = vlevel; 578 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 579 pipes[0].clks_cfg.socclk_mhz = socclk; 580 581 // DML calculation for MALL region doesn't take into account FW delay 582 // and required pstate allow width for multi-display cases 583 /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned 584 * to 2 swaths (i.e. 16 lines) 585 */ 586 phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + 587 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; 588 589 // W/A for DCC corruption with certain high resolution timings. 590 // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. 591 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; 592 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; 593 594 /* dc->debug.subvp_extra_lines 0 by default*/ 595 phantom_vactive += dc->debug.subvp_extra_lines; 596 597 // For backporch of phantom pipe, use vstartup of the main pipe 598 phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 599 600 phantom_stream->dst.y = 0; 601 phantom_stream->dst.height = phantom_vactive; 602 /* When scaling, DML provides the end to end required number of lines for MALL. 603 * dst.height is always correct for this case, but src.height is not which causes a 604 * delta between main and phantom pipe scaling outputs. Need to adjust src.height on 605 * phantom for this case. 606 */ 607 phantom_stream->src.y = 0; 608 phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height; 609 610 phantom_stream->timing.v_addressable = phantom_vactive; 611 phantom_stream->timing.v_front_porch = 1; 612 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + 613 phantom_stream->timing.v_front_porch + 614 phantom_stream->timing.v_sync_width + 615 phantom_bp; 616 phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing 617 } 618 619 /** 620 * dcn32_get_num_free_pipes - Calculate number of free pipes 621 * @dc: current dc state 622 * @context: new dc state 623 * 624 * This function assumes that a "used" pipe is a pipe that has 625 * both a stream and a plane assigned to it. 626 * 627 * Return: Number of free pipes available in the context 628 */ 629 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) 630 { 631 unsigned int i; 632 unsigned int free_pipes = 0; 633 unsigned int num_pipes = 0; 634 635 for (i = 0; i < dc->res_pool->pipe_count; i++) { 636 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 637 638 if (pipe->stream && !pipe->top_pipe) { 639 while (pipe) { 640 num_pipes++; 641 pipe = pipe->bottom_pipe; 642 } 643 } 644 } 645 646 free_pipes = dc->res_pool->pipe_count - num_pipes; 647 return free_pipes; 648 } 649 650 /** 651 * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP. 652 * @dc: current dc state 653 * @context: new dc state 654 * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned 655 * 656 * We enter this function if we are Sub-VP capable (i.e. enough pipes available) 657 * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if 658 * we are forcing SubVP P-State switching on the current config. 659 * 660 * The number of pipes used for the chosen surface must be less than or equal to the 661 * number of free pipes available. 662 * 663 * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK). 664 * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own 665 * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't 666 * support MCLK switching naturally [i.e. ACTIVE or VBLANK]). 667 * 668 * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. 669 */ 670 static bool dcn32_assign_subvp_pipe(struct dc *dc, 671 struct dc_state *context, 672 unsigned int *index) 673 { 674 unsigned int i, pipe_idx; 675 unsigned int max_frame_time = 0; 676 bool valid_assignment_found = false; 677 unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); 678 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 679 680 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 681 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 682 unsigned int num_pipes = 0; 683 unsigned int refresh_rate = 0; 684 685 if (!pipe->stream) 686 continue; 687 688 // Round up 689 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 690 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 691 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 692 /* SubVP pipe candidate requirements: 693 * - Refresh rate < 120hz 694 * - Not able to switch in vactive naturally (switching in active means the 695 * DET provides enough buffer to hide the P-State switch latency -- trying 696 * to combine this with SubVP can cause issues with the scheduling). 697 * - Not TMZ surface 698 */ 699 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && 700 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && 701 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && 702 pipe->stream->mall_stream_config.type == SUBVP_NONE && 703 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) && 704 !pipe->plane_state->address.tmz_surface && 705 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 || 706 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && 707 dcn32_allow_subvp_with_active_margin(pipe)))) { 708 while (pipe) { 709 num_pipes++; 710 pipe = pipe->bottom_pipe; 711 } 712 713 pipe = &context->res_ctx.pipe_ctx[i]; 714 if (num_pipes <= free_pipes) { 715 struct dc_stream_state *stream = pipe->stream; 716 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / 717 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; 718 if (frame_us > max_frame_time) { 719 *index = i; 720 max_frame_time = frame_us; 721 valid_assignment_found = true; 722 } 723 } 724 } 725 pipe_idx++; 726 } 727 return valid_assignment_found; 728 } 729 730 /** 731 * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP. 732 * @dc: current dc state 733 * @context: new dc state 734 * 735 * This function returns true if there are enough free pipes 736 * to create the required phantom pipes for any given stream 737 * (that does not already have phantom pipe assigned). 738 * 739 * e.g. For a 2 stream config where the first stream uses one 740 * pipe and the second stream uses 2 pipes (i.e. pipe split), 741 * this function will return true because there is 1 remaining 742 * pipe which can be used as the phantom pipe for the non pipe 743 * split pipe. 744 * 745 * Return: 746 * True if there are enough free pipes to assign phantom pipes to at least one 747 * stream that does not already have phantom pipes assigned. Otherwise false. 748 */ 749 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) 750 { 751 unsigned int i, split_cnt, free_pipes; 752 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 753 bool subvp_possible = false; 754 755 for (i = 0; i < dc->res_pool->pipe_count; i++) { 756 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 757 758 // Find the minimum pipe split count for non SubVP pipes 759 if (resource_is_pipe_type(pipe, OPP_HEAD) && 760 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 761 split_cnt = 0; 762 while (pipe) { 763 split_cnt++; 764 pipe = pipe->bottom_pipe; 765 } 766 767 if (split_cnt < min_pipe_split) 768 min_pipe_split = split_cnt; 769 } 770 } 771 772 free_pipes = dcn32_get_num_free_pipes(dc, context); 773 774 // SubVP only possible if at least one pipe is being used (i.e. free_pipes 775 // should not equal to the pipe_count) 776 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) 777 subvp_possible = true; 778 779 return subvp_possible; 780 } 781 782 /** 783 * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable 784 * @dc: current dc state 785 * @context: new dc state 786 * 787 * High level algorithm: 788 * 1. Find longest microschedule length (in us) between the two SubVP pipes 789 * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both 790 * pipes still allows for the maximum microschedule to fit in the active 791 * region for both pipes. 792 * 793 * Return: True if the SubVP + SubVP config is schedulable, false otherwise 794 */ 795 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) 796 { 797 struct pipe_ctx *subvp_pipes[2]; 798 struct dc_stream_state *phantom = NULL; 799 uint32_t microschedule_lines = 0; 800 uint32_t index = 0; 801 uint32_t i; 802 uint32_t max_microschedule_us = 0; 803 int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; 804 805 for (i = 0; i < dc->res_pool->pipe_count; i++) { 806 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 807 uint32_t time_us = 0; 808 809 /* Loop to calculate the maximum microschedule time between the two SubVP pipes, 810 * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. 811 */ 812 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 813 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 814 phantom = pipe->stream->mall_stream_config.paired_stream; 815 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + 816 phantom->timing.v_addressable; 817 818 // Round up when calculating microschedule time (+ 1 at the end) 819 time_us = (microschedule_lines * phantom->timing.h_total) / 820 (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + 821 dc->caps.subvp_prefetch_end_to_mall_start_us + 822 dc->caps.subvp_fw_processing_delay_us + 1; 823 if (time_us > max_microschedule_us) 824 max_microschedule_us = time_us; 825 826 subvp_pipes[index] = pipe; 827 index++; 828 829 // Maximum 2 SubVP pipes 830 if (index == 2) 831 break; 832 } 833 } 834 vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / 835 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 836 vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / 837 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 838 vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * 839 subvp_pipes[0]->stream->timing.h_total) / 840 (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; 841 vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * 842 subvp_pipes[1]->stream->timing.h_total) / 843 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; 844 845 if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && 846 (vactive2_us - vblank1_us) / 2 > max_microschedule_us) 847 return true; 848 849 return false; 850 } 851 852 /** 853 * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable 854 * @dc: current dc state 855 * @context: new dc state 856 * 857 * High level algorithm: 858 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 859 * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching 860 * (the margin is equal to the MALL region + DRR margin (500us)) 861 * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) 862 * then report the configuration as supported 863 * 864 * Return: True if the SubVP + DRR config is schedulable, false otherwise 865 */ 866 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) 867 { 868 bool schedulable = false; 869 uint32_t i; 870 struct pipe_ctx *pipe = NULL; 871 struct pipe_ctx *drr_pipe = NULL; 872 struct dc_crtc_timing *main_timing = NULL; 873 struct dc_crtc_timing *phantom_timing = NULL; 874 struct dc_crtc_timing *drr_timing = NULL; 875 int16_t prefetch_us = 0; 876 int16_t mall_region_us = 0; 877 int16_t drr_frame_us = 0; // nominal frame time 878 int16_t subvp_active_us = 0; 879 int16_t stretched_drr_us = 0; 880 int16_t drr_stretched_vblank_us = 0; 881 int16_t max_vblank_mallregion = 0; 882 883 // Find SubVP pipe 884 for (i = 0; i < dc->res_pool->pipe_count; i++) { 885 pipe = &context->res_ctx.pipe_ctx[i]; 886 887 // We check for master pipe, but it shouldn't matter since we only need 888 // the pipe for timing info (stream should be same for any pipe splits) 889 if (!resource_is_pipe_type(pipe, OTG_MASTER) || 890 !resource_is_pipe_type(pipe, DPP_PIPE)) 891 continue; 892 893 // Find the SubVP pipe 894 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 895 break; 896 } 897 898 // Find the DRR pipe 899 for (i = 0; i < dc->res_pool->pipe_count; i++) { 900 drr_pipe = &context->res_ctx.pipe_ctx[i]; 901 902 // We check for master pipe only 903 if (!resource_is_pipe_type(pipe, OTG_MASTER) || 904 !resource_is_pipe_type(pipe, DPP_PIPE)) 905 continue; 906 907 if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param && 908 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable)) 909 break; 910 } 911 912 main_timing = &pipe->stream->timing; 913 phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; 914 drr_timing = &drr_pipe->stream->timing; 915 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 916 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 917 dc->caps.subvp_prefetch_end_to_mall_start_us; 918 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 919 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 920 drr_frame_us = drr_timing->v_total * drr_timing->h_total / 921 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 922 // P-State allow width and FW delays already included phantom_timing->v_addressable 923 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 924 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 925 stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 926 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / 927 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); 928 max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; 929 930 /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the 931 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis 932 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 933 * and the max of (VBLANK blanking time, MALL region)). 934 */ 935 if (drr_timing && 936 stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && 937 subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) 938 schedulable = true; 939 940 return schedulable; 941 } 942 943 944 /** 945 * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable 946 * @dc: current dc state 947 * @context: new dc state 948 * 949 * High level algorithm: 950 * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe 951 * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) 952 * then report the configuration as supported 953 * 3. If the VBLANK display is DRR, then take the DRR static schedulability path 954 * 955 * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise 956 */ 957 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) 958 { 959 struct pipe_ctx *pipe = NULL; 960 struct pipe_ctx *subvp_pipe = NULL; 961 bool found = false; 962 bool schedulable = false; 963 uint32_t i = 0; 964 uint8_t vblank_index = 0; 965 uint16_t prefetch_us = 0; 966 uint16_t mall_region_us = 0; 967 uint16_t vblank_frame_us = 0; 968 uint16_t subvp_active_us = 0; 969 uint16_t vblank_blank_us = 0; 970 uint16_t max_vblank_mallregion = 0; 971 struct dc_crtc_timing *main_timing = NULL; 972 struct dc_crtc_timing *phantom_timing = NULL; 973 struct dc_crtc_timing *vblank_timing = NULL; 974 975 /* For SubVP + VBLANK/DRR cases, we assume there can only be 976 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK 977 * is supported, it is either a single VBLANK case or two VBLANK 978 * displays which are synchronized (in which case they have identical 979 * timings). 980 */ 981 for (i = 0; i < dc->res_pool->pipe_count; i++) { 982 pipe = &context->res_ctx.pipe_ctx[i]; 983 984 // We check for master pipe, but it shouldn't matter since we only need 985 // the pipe for timing info (stream should be same for any pipe splits) 986 if (!resource_is_pipe_type(pipe, OTG_MASTER) || 987 !resource_is_pipe_type(pipe, DPP_PIPE)) 988 continue; 989 990 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 991 // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). 992 vblank_index = i; 993 found = true; 994 } 995 996 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) 997 subvp_pipe = pipe; 998 } 999 if (found && subvp_pipe) { 1000 main_timing = &subvp_pipe->stream->timing; 1001 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 1002 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; 1003 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe 1004 // Also include the prefetch end to mallstart delay time 1005 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 1006 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 1007 dc->caps.subvp_prefetch_end_to_mall_start_us; 1008 // P-State allow width and FW delays already included phantom_timing->v_addressable 1009 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 1010 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 1011 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / 1012 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1013 vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / 1014 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; 1015 subvp_active_us = main_timing->v_addressable * main_timing->h_total / 1016 (double)(main_timing->pix_clk_100hz * 100) * 1000000; 1017 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; 1018 1019 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, 1020 // and the max of (VBLANK blanking time, MALL region) 1021 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) 1022 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) 1023 schedulable = true; 1024 } 1025 return schedulable; 1026 } 1027 1028 /** 1029 * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible 1030 * 1031 * @dc: Current DC state 1032 * @context: New DC state to be programmed 1033 * 1034 * SubVP + SubVP is admissible under the following conditions: 1035 * - All SubVP pipes are < 120Hz OR 1036 * - All SubVP pipes are >= 120hz 1037 * 1038 * Return: True if admissible, false otherwise 1039 */ 1040 static bool subvp_subvp_admissable(struct dc *dc, 1041 struct dc_state *context) 1042 { 1043 bool result = false; 1044 uint32_t i; 1045 uint8_t subvp_count = 0; 1046 uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0; 1047 uint64_t refresh_rate = 0; 1048 1049 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1050 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1051 1052 if (!pipe->stream) 1053 continue; 1054 1055 if (pipe->plane_state && !pipe->top_pipe && 1056 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 1057 refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + 1058 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); 1059 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); 1060 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); 1061 1062 if ((uint32_t)refresh_rate < min_refresh) 1063 min_refresh = (uint32_t)refresh_rate; 1064 if ((uint32_t)refresh_rate > max_refresh) 1065 max_refresh = (uint32_t)refresh_rate; 1066 subvp_count++; 1067 } 1068 } 1069 1070 if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) || 1071 (min_refresh >= subvp_high_refresh_list.min_refresh && 1072 max_refresh <= subvp_high_refresh_list.max_refresh))) 1073 result = true; 1074 1075 return result; 1076 } 1077 1078 /** 1079 * subvp_validate_static_schedulability - Check which SubVP case is calculated 1080 * and handle static analysis based on the case. 1081 * @dc: current dc state 1082 * @context: new dc state 1083 * @vlevel: Voltage level calculated by DML 1084 * 1085 * Three cases: 1086 * 1. SubVP + SubVP 1087 * 2. SubVP + VBLANK (DRR checked internally) 1088 * 3. SubVP + VACTIVE (currently unsupported) 1089 * 1090 * Return: True if statically schedulable, false otherwise 1091 */ 1092 static bool subvp_validate_static_schedulability(struct dc *dc, 1093 struct dc_state *context, 1094 int vlevel) 1095 { 1096 bool schedulable = false; 1097 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1098 uint32_t i, pipe_idx; 1099 uint8_t subvp_count = 0; 1100 uint8_t vactive_count = 0; 1101 uint8_t non_subvp_pipes = 0; 1102 1103 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1104 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1105 1106 if (!pipe->stream) 1107 continue; 1108 1109 if (pipe->plane_state && !pipe->top_pipe) { 1110 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 1111 subvp_count++; 1112 if (pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1113 non_subvp_pipes++; 1114 } 1115 } 1116 1117 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE 1118 // switching (SubVP + VACTIVE unsupported). In situations where we force 1119 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count. 1120 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && 1121 pipe->stream->mall_stream_config.type == SUBVP_NONE) { 1122 vactive_count++; 1123 } 1124 pipe_idx++; 1125 } 1126 1127 if (subvp_count == 2) { 1128 // Static schedulability check for SubVP + SubVP case 1129 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context); 1130 } else if (subvp_count == 1 && non_subvp_pipes == 0) { 1131 // Single SubVP configs will be supported by default as long as it's suppported by DML 1132 schedulable = true; 1133 } else if (subvp_count == 1 && non_subvp_pipes == 1) { 1134 if (dcn32_subvp_drr_admissable(dc, context)) 1135 schedulable = subvp_drr_schedulable(dc, context); 1136 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel)) 1137 schedulable = subvp_vblank_schedulable(dc, context); 1138 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp && 1139 vactive_count > 0) { 1140 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default. 1141 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count. 1142 // SubVP + VACTIVE currently unsupported 1143 schedulable = false; 1144 } 1145 return schedulable; 1146 } 1147 1148 static void dcn32_full_validate_bw_helper(struct dc *dc, 1149 struct dc_state *context, 1150 display_e2e_pipe_params_st *pipes, 1151 int *vlevel, 1152 int *split, 1153 bool *merge, 1154 int *pipe_cnt) 1155 { 1156 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1157 unsigned int dc_pipe_idx = 0; 1158 int i = 0; 1159 bool found_supported_config = false; 1160 1161 dc_assert_fp_enabled(); 1162 1163 /* 1164 * DML favors voltage over p-state, but we're more interested in 1165 * supporting p-state over voltage. We can't support p-state in 1166 * prefetch mode > 0 so try capping the prefetch mode to start. 1167 * Override present for testing. 1168 */ 1169 if (dc->debug.dml_disallow_alternate_prefetch_modes) 1170 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1171 dm_prefetch_support_uclk_fclk_and_stutter; 1172 else 1173 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1174 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1175 1176 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1177 /* This may adjust vlevel and maxMpcComb */ 1178 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1179 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1180 vba->VoltageLevel = *vlevel; 1181 } 1182 1183 /* Conditions for setting up phantom pipes for SubVP: 1184 * 1. Not force disable SubVP 1185 * 2. Full update (i.e. !fast_validate) 1186 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) 1187 * 4. Display configuration passes validation 1188 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) 1189 */ 1190 if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) && 1191 !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && 1192 (*vlevel == context->bw_ctx.dml.soc.num_states || 1193 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || 1194 dc->debug.force_subvp_mclk_switch)) { 1195 1196 dcn32_merge_pipes_for_subvp(dc, context); 1197 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1198 1199 /* to re-initialize viewport after the pipe merge */ 1200 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1201 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1202 1203 if (!pipe_ctx->plane_state || !pipe_ctx->stream) 1204 continue; 1205 1206 resource_build_scaling_params(pipe_ctx); 1207 } 1208 1209 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && 1210 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { 1211 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. 1212 * Adding phantom pipes won't change the validation result, so change the DML input param 1213 * for P-State support before adding phantom pipes and recalculating the DML result. 1214 * However, this case is only applicable for SubVP + DRR cases because the prefetch mode 1215 * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched 1216 * enough to support MCLK switching. 1217 */ 1218 if (*vlevel == context->bw_ctx.dml.soc.num_states && 1219 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final == 1220 dm_prefetch_support_uclk_fclk_and_stutter) { 1221 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1222 dm_prefetch_support_fclk_and_stutter; 1223 /* There are params (such as FabricClock) that need to be recalculated 1224 * after validation fails (otherwise it will be 0). Calculation for 1225 * phantom vactive requires call into DML, so we must ensure all the 1226 * vba params are valid otherwise we'll get incorrect phantom vactive. 1227 */ 1228 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1229 } 1230 1231 dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); 1232 1233 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1234 // Populate dppclk to trigger a recalculate in dml_get_voltage_level 1235 // so the phantom pipe DLG params can be assigned correctly. 1236 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); 1237 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1238 1239 /* Check that vlevel requested supports pstate or not 1240 * if not, select the lowest vlevel that supports it 1241 */ 1242 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1243 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { 1244 *vlevel = i; 1245 break; 1246 } 1247 } 1248 1249 if (*vlevel < context->bw_ctx.dml.soc.num_states 1250 && subvp_validate_static_schedulability(dc, context, *vlevel)) 1251 found_supported_config = true; 1252 if (found_supported_config) { 1253 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode 1254 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) { 1255 /* find lowest vlevel that supports the config */ 1256 for (i = *vlevel; i >= 0; i--) { 1257 if (vba->ModeSupport[i][vba->maxMpcComb]) { 1258 *vlevel = i; 1259 } else { 1260 break; 1261 } 1262 } 1263 } 1264 } 1265 } 1266 1267 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) 1268 // remove phantom pipes and repopulate dml pipes 1269 if (!found_supported_config) { 1270 dc->res_pool->funcs->remove_phantom_pipes(dc, context, false); 1271 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; 1272 *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false); 1273 1274 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); 1275 /* This may adjust vlevel and maxMpcComb */ 1276 if (*vlevel < context->bw_ctx.dml.soc.num_states) { 1277 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1278 vba->VoltageLevel = *vlevel; 1279 } 1280 } else { 1281 // Most populate phantom DLG params before programming hardware / timing for phantom pipe 1282 dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); 1283 1284 /* Call validate_apply_pipe_split flags after calling DML getters for 1285 * phantom dlg params, or some of the VBA params indicating pipe split 1286 * can be overwritten by the getters. 1287 * 1288 * When setting up SubVP config, all pipes are merged before attempting to 1289 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main 1290 * and phantom pipes will be split in the regular pipe splitting sequence. 1291 */ 1292 memset(split, 0, MAX_PIPES * sizeof(int)); 1293 memset(merge, 0, MAX_PIPES * sizeof(bool)); 1294 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 1295 vba->VoltageLevel = *vlevel; 1296 // Note: We can't apply the phantom pipes to hardware at this time. We have to wait 1297 // until driver has acquired the DMCUB lock to do it safely. 1298 } 1299 } 1300 } 1301 1302 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 1303 { 1304 int i; 1305 1306 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1307 if (!context->res_ctx.pipe_ctx[i].stream) 1308 continue; 1309 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) 1310 return true; 1311 } 1312 return false; 1313 } 1314 1315 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start) 1316 { 1317 struct dc_crtc_timing patched_crtc_timing; 1318 uint32_t asic_blank_end = 0; 1319 uint32_t asic_blank_start = 0; 1320 uint32_t newVstartup = 0; 1321 1322 patched_crtc_timing = *dc_crtc_timing; 1323 1324 if (patched_crtc_timing.flags.INTERLACE == 1) { 1325 if (patched_crtc_timing.v_front_porch < 2) 1326 patched_crtc_timing.v_front_porch = 2; 1327 } else { 1328 if (patched_crtc_timing.v_front_porch < 1) 1329 patched_crtc_timing.v_front_porch = 1; 1330 } 1331 1332 /* blank_start = frame end - front porch */ 1333 asic_blank_start = patched_crtc_timing.v_total - 1334 patched_crtc_timing.v_front_porch; 1335 1336 /* blank_end = blank_start - active */ 1337 asic_blank_end = asic_blank_start - 1338 patched_crtc_timing.v_border_bottom - 1339 patched_crtc_timing.v_addressable - 1340 patched_crtc_timing.v_border_top; 1341 1342 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); 1343 1344 *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); 1345 } 1346 1347 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 1348 display_e2e_pipe_params_st *pipes, 1349 int pipe_cnt, int vlevel) 1350 { 1351 int i, pipe_idx, active_hubp_count = 0; 1352 bool usr_retraining_support = false; 1353 bool unbounded_req_enabled = false; 1354 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1355 1356 dc_assert_fp_enabled(); 1357 1358 /* Writeback MCIF_WB arbitration parameters */ 1359 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1360 1361 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; 1362 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; 1363 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; 1364 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 1365 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; 1366 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; 1367 context->bw_ctx.bw.dcn.clk.p_state_change_support = 1368 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 1369 != dm_dram_clock_change_unsupported; 1370 1371 /* Pstate change might not be supported by hardware, but it might be 1372 * possible with firmware driven vertical blank stretching. 1373 */ 1374 context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; 1375 1376 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1377 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 1378 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; 1379 if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) 1380 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; 1381 else 1382 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1383 1384 usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1385 ASSERT(usr_retraining_support); 1386 1387 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 1388 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; 1389 1390 unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); 1391 1392 if (unbounded_req_enabled && pipe_cnt > 1) { 1393 // Unbounded requesting should not ever be used when more than 1 pipe is enabled. 1394 ASSERT(false); 1395 unbounded_req_enabled = false; 1396 } 1397 1398 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 1399 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 1400 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 1401 1402 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1403 if (!context->res_ctx.pipe_ctx[i].stream) 1404 continue; 1405 if (context->res_ctx.pipe_ctx[i].plane_state) 1406 active_hubp_count++; 1407 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, 1408 pipe_idx); 1409 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1410 pipe_idx); 1411 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, 1412 pipe_idx); 1413 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 1414 pipe_idx); 1415 1416 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1417 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests 1418 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; 1419 context->res_ctx.pipe_ctx[i].unbounded_req = false; 1420 } else { 1421 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, 1422 pipe_idx); 1423 context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; 1424 } 1425 1426 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1427 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1428 if (context->res_ctx.pipe_ctx[i].plane_state) 1429 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1430 else 1431 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; 1432 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; 1433 1434 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1435 1436 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) 1437 context->res_ctx.pipe_ctx[i].has_vactive_margin = true; 1438 else 1439 context->res_ctx.pipe_ctx[i].has_vactive_margin = false; 1440 1441 /* MALL Allocation Sizes */ 1442 /* count from active, top pipes per plane only */ 1443 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state && 1444 (context->res_ctx.pipe_ctx[i].top_pipe == NULL || 1445 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) && 1446 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1447 /* SS: all active surfaces stored in MALL */ 1448 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { 1449 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1450 1451 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) { 1452 /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */ 1453 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1454 } 1455 } else { 1456 /* SUBVP: phantom surfaces only stored in MALL */ 1457 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes; 1458 } 1459 } 1460 1461 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) 1462 dcn20_adjust_freesync_v_startup( 1463 &context->res_ctx.pipe_ctx[i].stream->timing, 1464 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); 1465 1466 pipe_idx++; 1467 } 1468 /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ 1469 if (!active_hubp_count) { 1470 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; 1471 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1472 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; 1473 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; 1474 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; 1475 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; 1476 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 1477 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; 1478 } 1479 /*save a original dppclock copy*/ 1480 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 1481 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 1482 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz 1483 * 1000; 1484 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz 1485 * 1000; 1486 1487 context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); 1488 1489 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes; 1490 1491 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1492 if (context->res_ctx.pipe_ctx[i].stream) 1493 context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb; 1494 } 1495 1496 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1497 1498 if (!context->res_ctx.pipe_ctx[i].stream) 1499 continue; 1500 1501 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, 1502 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, 1503 pipe_cnt, pipe_idx); 1504 1505 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, 1506 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1507 pipe_idx++; 1508 } 1509 } 1510 1511 static struct pipe_ctx *dcn32_find_split_pipe( 1512 struct dc *dc, 1513 struct dc_state *context, 1514 int old_index) 1515 { 1516 struct pipe_ctx *pipe = NULL; 1517 int i; 1518 1519 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { 1520 pipe = &context->res_ctx.pipe_ctx[old_index]; 1521 pipe->pipe_idx = old_index; 1522 } 1523 1524 if (!pipe) 1525 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1526 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL 1527 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1528 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1529 pipe = &context->res_ctx.pipe_ctx[i]; 1530 pipe->pipe_idx = i; 1531 break; 1532 } 1533 } 1534 } 1535 1536 /* 1537 * May need to fix pipes getting tossed from 1 opp to another on flip 1538 * Add for debugging transient underflow during topology updates: 1539 * ASSERT(pipe); 1540 */ 1541 if (!pipe) 1542 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1543 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1544 pipe = &context->res_ctx.pipe_ctx[i]; 1545 pipe->pipe_idx = i; 1546 break; 1547 } 1548 } 1549 1550 return pipe; 1551 } 1552 1553 static bool dcn32_split_stream_for_mpc_or_odm( 1554 const struct dc *dc, 1555 struct resource_context *res_ctx, 1556 struct pipe_ctx *pri_pipe, 1557 struct pipe_ctx *sec_pipe, 1558 bool odm) 1559 { 1560 int pipe_idx = sec_pipe->pipe_idx; 1561 const struct resource_pool *pool = dc->res_pool; 1562 1563 DC_LOGGER_INIT(dc->ctx->logger); 1564 1565 if (odm && pri_pipe->plane_state) { 1566 /* ODM + window MPO, where MPO window is on left half only */ 1567 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= 1568 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1569 1570 DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n", 1571 __func__, 1572 pri_pipe->pipe_idx); 1573 return true; 1574 } 1575 1576 /* ODM + window MPO, where MPO window is on right half only */ 1577 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { 1578 1579 DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n", 1580 __func__, 1581 pri_pipe->pipe_idx); 1582 return true; 1583 } 1584 } 1585 1586 *sec_pipe = *pri_pipe; 1587 1588 sec_pipe->pipe_idx = pipe_idx; 1589 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1590 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1591 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1592 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1593 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1594 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1595 sec_pipe->stream_res.dsc = NULL; 1596 if (odm) { 1597 if (pri_pipe->next_odm_pipe) { 1598 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1599 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1600 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1601 } 1602 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { 1603 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; 1604 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; 1605 } 1606 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { 1607 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; 1608 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; 1609 } 1610 pri_pipe->next_odm_pipe = sec_pipe; 1611 sec_pipe->prev_odm_pipe = pri_pipe; 1612 ASSERT(sec_pipe->top_pipe == NULL); 1613 1614 if (!sec_pipe->top_pipe) 1615 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1616 else 1617 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 1618 if (sec_pipe->stream->timing.flags.DSC == 1) { 1619 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1620 ASSERT(sec_pipe->stream_res.dsc); 1621 if (sec_pipe->stream_res.dsc == NULL) 1622 return false; 1623 } 1624 } else { 1625 if (pri_pipe->bottom_pipe) { 1626 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1627 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1628 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1629 } 1630 pri_pipe->bottom_pipe = sec_pipe; 1631 sec_pipe->top_pipe = pri_pipe; 1632 1633 ASSERT(pri_pipe->plane_state); 1634 } 1635 1636 return true; 1637 } 1638 1639 bool dcn32_internal_validate_bw(struct dc *dc, 1640 struct dc_state *context, 1641 display_e2e_pipe_params_st *pipes, 1642 int *pipe_cnt_out, 1643 int *vlevel_out, 1644 bool fast_validate) 1645 { 1646 bool out = false; 1647 bool repopulate_pipes = false; 1648 int split[MAX_PIPES] = { 0 }; 1649 bool merge[MAX_PIPES] = { false }; 1650 bool newly_split[MAX_PIPES] = { false }; 1651 int pipe_cnt, i, pipe_idx; 1652 int vlevel = context->bw_ctx.dml.soc.num_states; 1653 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1654 1655 dc_assert_fp_enabled(); 1656 1657 ASSERT(pipes); 1658 if (!pipes) 1659 return false; 1660 1661 // For each full update, remove all existing phantom pipes first 1662 dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate); 1663 1664 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1665 1666 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1667 1668 if (!pipe_cnt) { 1669 out = true; 1670 goto validate_out; 1671 } 1672 1673 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1674 context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context); 1675 1676 if (!fast_validate) 1677 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); 1678 1679 if (fast_validate || 1680 (dc->debug.dml_disallow_alternate_prefetch_modes && 1681 (vlevel == context->bw_ctx.dml.soc.num_states || 1682 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { 1683 /* 1684 * If dml_disallow_alternate_prefetch_modes is false, then we have already 1685 * tried alternate prefetch modes during full validation. 1686 * 1687 * If mode is unsupported or there is no p-state support, then 1688 * fall back to favouring voltage. 1689 * 1690 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try 1691 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2) 1692 */ 1693 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1694 dm_prefetch_support_none; 1695 1696 context->bw_ctx.dml.validate_max_state = fast_validate; 1697 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1698 1699 context->bw_ctx.dml.validate_max_state = false; 1700 1701 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1702 memset(split, 0, sizeof(split)); 1703 memset(merge, 0, sizeof(merge)); 1704 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1705 // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML 1706 vba->VoltageLevel = vlevel; 1707 } 1708 } 1709 1710 dml_log_mode_support_params(&context->bw_ctx.dml); 1711 1712 if (vlevel == context->bw_ctx.dml.soc.num_states) 1713 goto validate_fail; 1714 1715 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1716 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1717 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1718 1719 if (!pipe->stream) 1720 continue; 1721 1722 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1723 && !dc->config.enable_windowed_mpo_odm 1724 && pipe->plane_state && mpo_pipe 1725 && memcmp(&mpo_pipe->plane_state->clip_rect, 1726 &pipe->stream->src, 1727 sizeof(struct rect)) != 0) { 1728 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1729 goto validate_fail; 1730 } 1731 pipe_idx++; 1732 } 1733 1734 /* merge pipes if necessary */ 1735 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1736 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1737 1738 /*skip pipes that don't need merging*/ 1739 if (!merge[i]) 1740 continue; 1741 1742 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 1743 if (pipe->prev_odm_pipe) { 1744 /*split off odm pipe*/ 1745 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 1746 if (pipe->next_odm_pipe) 1747 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 1748 1749 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/ 1750 if (pipe->bottom_pipe) { 1751 if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) { 1752 /*MPC split rules will handle this case*/ 1753 pipe->bottom_pipe->top_pipe = NULL; 1754 } else { 1755 /* when merging an ODM pipes, the bottom MPC pipe must now point to 1756 * the previous ODM pipe and its associated stream assets 1757 */ 1758 if (pipe->prev_odm_pipe->bottom_pipe) { 1759 /* 3 plane MPO*/ 1760 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe; 1761 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; 1762 } else { 1763 /* 2 plane MPO*/ 1764 pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe; 1765 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; 1766 } 1767 1768 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource)); 1769 } 1770 } 1771 1772 if (pipe->top_pipe) { 1773 pipe->top_pipe->bottom_pipe = NULL; 1774 } 1775 1776 pipe->bottom_pipe = NULL; 1777 pipe->next_odm_pipe = NULL; 1778 pipe->plane_state = NULL; 1779 pipe->stream = NULL; 1780 pipe->top_pipe = NULL; 1781 pipe->prev_odm_pipe = NULL; 1782 if (pipe->stream_res.dsc) 1783 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 1784 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1785 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1786 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1787 repopulate_pipes = true; 1788 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 1789 struct pipe_ctx *top_pipe = pipe->top_pipe; 1790 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 1791 1792 top_pipe->bottom_pipe = bottom_pipe; 1793 if (bottom_pipe) 1794 bottom_pipe->top_pipe = top_pipe; 1795 1796 pipe->top_pipe = NULL; 1797 pipe->bottom_pipe = NULL; 1798 pipe->plane_state = NULL; 1799 pipe->stream = NULL; 1800 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1801 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1802 memset(&pipe->link_res, 0, sizeof(pipe->link_res)); 1803 repopulate_pipes = true; 1804 } else 1805 ASSERT(0); /* Should never try to merge master pipe */ 1806 1807 } 1808 1809 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1810 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1811 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1812 struct pipe_ctx *hsplit_pipe = NULL; 1813 bool odm; 1814 int old_index = -1; 1815 1816 if (!pipe->stream || newly_split[i]) 1817 continue; 1818 1819 pipe_idx++; 1820 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 1821 1822 if (!pipe->plane_state && !odm) 1823 continue; 1824 1825 if (split[i]) { 1826 if (odm) { 1827 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) 1828 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1829 else if (old_pipe->next_odm_pipe) 1830 old_index = old_pipe->next_odm_pipe->pipe_idx; 1831 } else { 1832 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1833 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1834 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1835 else if (old_pipe->bottom_pipe && 1836 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1837 old_index = old_pipe->bottom_pipe->pipe_idx; 1838 } 1839 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); 1840 ASSERT(hsplit_pipe); 1841 if (!hsplit_pipe) 1842 goto validate_fail; 1843 1844 if (!dcn32_split_stream_for_mpc_or_odm( 1845 dc, &context->res_ctx, 1846 pipe, hsplit_pipe, odm)) 1847 goto validate_fail; 1848 1849 newly_split[hsplit_pipe->pipe_idx] = true; 1850 repopulate_pipes = true; 1851 } 1852 if (split[i] == 4) { 1853 struct pipe_ctx *pipe_4to1; 1854 1855 if (odm && old_pipe->next_odm_pipe) 1856 old_index = old_pipe->next_odm_pipe->pipe_idx; 1857 else if (!odm && old_pipe->bottom_pipe && 1858 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1859 old_index = old_pipe->bottom_pipe->pipe_idx; 1860 else 1861 old_index = -1; 1862 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1863 ASSERT(pipe_4to1); 1864 if (!pipe_4to1) 1865 goto validate_fail; 1866 if (!dcn32_split_stream_for_mpc_or_odm( 1867 dc, &context->res_ctx, 1868 pipe, pipe_4to1, odm)) 1869 goto validate_fail; 1870 newly_split[pipe_4to1->pipe_idx] = true; 1871 1872 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe 1873 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) 1874 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1875 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1876 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && 1877 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1878 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1879 else 1880 old_index = -1; 1881 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); 1882 ASSERT(pipe_4to1); 1883 if (!pipe_4to1) 1884 goto validate_fail; 1885 if (!dcn32_split_stream_for_mpc_or_odm( 1886 dc, &context->res_ctx, 1887 hsplit_pipe, pipe_4to1, odm)) 1888 goto validate_fail; 1889 newly_split[pipe_4to1->pipe_idx] = true; 1890 } 1891 if (odm) 1892 dcn20_build_mapped_resource(dc, context, pipe->stream); 1893 } 1894 1895 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1896 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1897 1898 if (pipe->plane_state) { 1899 if (!resource_build_scaling_params(pipe)) 1900 goto validate_fail; 1901 } 1902 } 1903 1904 /* Actual dsc count per stream dsc validation*/ 1905 if (!dcn20_validate_dsc(dc, context)) { 1906 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 1907 goto validate_fail; 1908 } 1909 1910 if (repopulate_pipes) { 1911 int flag_max_mpc_comb = vba->maxMpcComb; 1912 int flag_vlevel = vlevel; 1913 int i; 1914 1915 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1916 1917 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case 1918 * we have to re-calculate the DET allocation and run through DML once more to 1919 * ensure all the params are calculated correctly. We do not need to run the 1920 * pipe split check again after this call (pipes are already split / merged). 1921 * */ 1922 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = 1923 dm_prefetch_support_uclk_fclk_and_stutter_if_possible; 1924 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1925 if (vlevel == context->bw_ctx.dml.soc.num_states) { 1926 /* failed after DET size changes */ 1927 goto validate_fail; 1928 } else if (flag_max_mpc_comb == 0 && 1929 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { 1930 /* check the context constructed with pipe split flags is still valid*/ 1931 bool flags_valid = false; 1932 for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { 1933 if (vba->ModeSupport[i][flag_max_mpc_comb]) { 1934 vba->maxMpcComb = flag_max_mpc_comb; 1935 vba->VoltageLevel = i; 1936 vlevel = i; 1937 flags_valid = true; 1938 } 1939 } 1940 1941 /* this should never happen */ 1942 if (!flags_valid) 1943 goto validate_fail; 1944 } 1945 } 1946 *vlevel_out = vlevel; 1947 *pipe_cnt_out = pipe_cnt; 1948 1949 out = true; 1950 goto validate_out; 1951 1952 validate_fail: 1953 out = false; 1954 1955 validate_out: 1956 return out; 1957 } 1958 1959 1960 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 1961 display_e2e_pipe_params_st *pipes, 1962 int pipe_cnt, 1963 int vlevel) 1964 { 1965 int i, pipe_idx, vlevel_temp = 0; 1966 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 1967 double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 1968 double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; 1969 double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; 1970 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 1971 dm_dram_clock_change_unsupported; 1972 unsigned int dummy_latency_index = 0; 1973 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1974 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1975 bool subvp_in_use = dcn32_subvp_in_use(dc, context); 1976 unsigned int min_dram_speed_mts_margin; 1977 bool need_fclk_lat_as_dummy = false; 1978 bool is_subvp_p_drr = false; 1979 struct dc_stream_state *fpo_candidate_stream = NULL; 1980 1981 dc_assert_fp_enabled(); 1982 1983 /* need to find dummy latency index for subvp */ 1984 if (subvp_in_use) { 1985 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */ 1986 if (!pstate_en) { 1987 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 1988 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter; 1989 pstate_en = true; 1990 is_subvp_p_drr = true; 1991 } 1992 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 1993 context, pipes, pipe_cnt, vlevel); 1994 1995 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is 1996 * scheduled correctly to account for dummy pstate. 1997 */ 1998 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 1999 need_fclk_lat_as_dummy = true; 2000 context->bw_ctx.dml.soc.fclk_change_latency_us = 2001 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2002 } 2003 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2004 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2005 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2006 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 2007 if (is_subvp_p_drr) { 2008 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; 2009 } 2010 } 2011 2012 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 2013 for (i = 0; i < context->stream_count; i++) { 2014 if (context->streams[i]) 2015 context->streams[i]->fpo_in_use = false; 2016 } 2017 2018 if (!pstate_en || (!dc->debug.disable_fpo_optimizations && 2019 pstate_en && vlevel != 0)) { 2020 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ 2021 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); 2022 if (fpo_candidate_stream) { 2023 fpo_candidate_stream->fpo_in_use = true; 2024 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; 2025 } 2026 2027 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2028 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, 2029 context, pipes, pipe_cnt, vlevel); 2030 2031 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch 2032 * we reinstate the original dram_clock_change_latency_us on the context 2033 * and all variables that may have changed up to this point, except the 2034 * newly found dummy_latency_index 2035 */ 2036 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2037 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2038 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so 2039 * prefetch is scheduled correctly to account for dummy pstate. 2040 */ 2041 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) { 2042 need_fclk_lat_as_dummy = true; 2043 context->bw_ctx.dml.soc.fclk_change_latency_us = 2044 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2045 } 2046 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false); 2047 if (vlevel_temp < vlevel) { 2048 vlevel = vlevel_temp; 2049 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 2050 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2051 pstate_en = true; 2052 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank; 2053 } else { 2054 /* Restore FCLK latency and re-run validation to go back to original validation 2055 * output if we find that enabling FPO does not give us any benefit (i.e. lower 2056 * voltage level) 2057 */ 2058 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 2059 for (i = 0; i < context->stream_count; i++) { 2060 if (context->streams[i]) 2061 context->streams[i]->fpo_in_use = false; 2062 } 2063 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2064 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2065 } 2066 } 2067 } 2068 2069 /* Set B: 2070 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, 2071 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark 2072 * calculations to cover bootup clocks. 2073 * DCFCLK: soc.clock_limits[2] when available 2074 * UCLK: soc.clock_limits[2] when available 2075 */ 2076 if (dcn3_2_soc.num_states > 2) { 2077 vlevel_temp = 2; 2078 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; 2079 } else 2080 dcfclk = 615; //DCFCLK Vmin_lv 2081 2082 pipes[0].clks_cfg.voltage = vlevel_temp; 2083 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2084 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2085 2086 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 2087 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 2088 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us; 2089 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 2090 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 2091 } 2092 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2093 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2094 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2095 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2096 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2097 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2098 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2099 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2100 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2101 context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2102 2103 /* Set D: 2104 * All clocks min. 2105 * DCFCLK: Min, as reported by PM FW when available 2106 * UCLK : Min, as reported by PM FW when available 2107 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) 2108 */ 2109 2110 /* 2111 if (dcn3_2_soc.num_states > 2) { 2112 vlevel_temp = 0; 2113 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; 2114 } else 2115 dcfclk = 615; //DCFCLK Vmin_lv 2116 2117 pipes[0].clks_cfg.voltage = vlevel_temp; 2118 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2119 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; 2120 2121 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 2122 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 2123 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us; 2124 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 2125 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 2126 } 2127 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2128 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2129 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2130 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2131 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2132 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2133 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2134 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2135 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2136 context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2137 */ 2138 2139 /* Set C, for Dummy P-State: 2140 * All clocks min. 2141 * DCFCLK: Min, as reported by PM FW, when available 2142 * UCLK : Min, as reported by PM FW, when available 2143 * pstate latency as per UCLK state dummy pstate latency 2144 */ 2145 2146 // For Set A and Set C use values from validation 2147 pipes[0].clks_cfg.voltage = vlevel; 2148 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; 2149 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2150 2151 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2152 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching; 2153 } 2154 2155 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 2156 min_dram_speed_mts = dram_speed_from_validation; 2157 min_dram_speed_mts_margin = 160; 2158 2159 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2160 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; 2161 2162 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == 2163 dm_dram_clock_change_unsupported) { 2164 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; 2165 2166 min_dram_speed_mts = 2167 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; 2168 } 2169 2170 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) { 2171 /* find largest table entry that is lower than dram speed, 2172 * but lower than DPM0 still uses DPM0 2173 */ 2174 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) 2175 if (min_dram_speed_mts + min_dram_speed_mts_margin > 2176 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) 2177 break; 2178 } 2179 2180 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2181 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2182 2183 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us; 2184 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 2185 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 2186 } 2187 2188 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2189 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2190 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2191 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2192 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2193 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2194 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2195 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2196 /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. 2197 * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM 2198 * value. 2199 */ 2200 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2201 context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2202 2203 if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { 2204 /* The only difference between A and C is p-state latency, if p-state is not supported 2205 * with full p-state latency we want to calculate DLG based on dummy p-state latency, 2206 * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30. 2207 */ 2208 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 2209 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 2210 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case 2211 * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported 2212 */ 2213 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2214 } else { 2215 /* Set A: 2216 * All clocks min. 2217 * DCFCLK: Min, as reported by PM FW, when available 2218 * UCLK: Min, as reported by PM FW, when available 2219 */ 2220 2221 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally 2222 */ 2223 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2224 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 2225 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 2226 2227 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2228 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2229 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2230 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2231 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2232 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2233 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2234 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2235 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2236 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2237 } 2238 2239 /* Make set D = set A since we do not optimized watermarks for MALL */ 2240 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 2241 2242 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2243 if (!context->res_ctx.pipe_ctx[i].stream) 2244 continue; 2245 2246 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 2247 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 2248 2249 if (dc->config.forced_clocks) { 2250 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2251 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2252 } 2253 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 2254 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2255 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2256 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2257 2258 pipe_idx++; 2259 } 2260 2261 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 2262 2263 /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */ 2264 if (need_fclk_lat_as_dummy) 2265 context->bw_ctx.dml.soc.fclk_change_latency_us = 2266 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2267 2268 dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2269 2270 if (!pstate_en) 2271 /* Restore full p-state latency */ 2272 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2273 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2274 2275 /* revert fclk lat changes if required */ 2276 if (need_fclk_lat_as_dummy) 2277 context->bw_ctx.dml.soc.fclk_change_latency_us = 2278 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; 2279 } 2280 2281 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 2282 unsigned int *optimal_dcfclk, 2283 unsigned int *optimal_fclk) 2284 { 2285 double bw_from_dram, bw_from_dram1, bw_from_dram2; 2286 2287 bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * 2288 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); 2289 bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * 2290 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); 2291 2292 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 2293 2294 if (optimal_fclk) 2295 *optimal_fclk = bw_from_dram / 2296 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2297 2298 if (optimal_dcfclk) 2299 *optimal_dcfclk = bw_from_dram / 2300 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2301 } 2302 2303 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, 2304 unsigned int index) 2305 { 2306 int i; 2307 2308 if (*num_entries == 0) 2309 return; 2310 2311 for (i = index; i < *num_entries - 1; i++) { 2312 table[i] = table[i + 1]; 2313 } 2314 memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st)); 2315 } 2316 2317 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) 2318 { 2319 int i; 2320 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, 2321 max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; 2322 2323 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2324 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2325 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2326 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) 2327 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2328 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) 2329 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2330 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2331 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2332 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2333 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2334 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2335 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2336 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) 2337 max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2338 } 2339 2340 /* Scan through clock values we currently have and if they are 0, 2341 * then populate it with dcn3_2_soc.clock_limits[] value. 2342 * 2343 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being 2344 * 0, will cause it to skip building the clock table. 2345 */ 2346 if (max_dcfclk_mhz == 0) 2347 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2348 if (max_dispclk_mhz == 0) 2349 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2350 if (max_dtbclk_mhz == 0) 2351 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; 2352 if (max_uclk_mhz == 0) 2353 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; 2354 } 2355 2356 static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry, 2357 struct _vcs_dpi_voltage_scaling_st *second_entry) 2358 { 2359 struct _vcs_dpi_voltage_scaling_st temp_entry = *first_entry; 2360 *first_entry = *second_entry; 2361 *second_entry = temp_entry; 2362 } 2363 2364 /* 2365 * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK 2366 */ 2367 static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2368 { 2369 unsigned int start_index = 0; 2370 unsigned int end_index = 0; 2371 unsigned int current_bw = 0; 2372 2373 for (int i = 0; i < (*num_entries - 1); i++) { 2374 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { 2375 current_bw = table[i].net_bw_in_kbytes_sec; 2376 start_index = i; 2377 end_index = ++i; 2378 2379 while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) 2380 end_index = ++i; 2381 } 2382 2383 if (start_index != end_index) { 2384 for (int j = start_index; j < end_index; j++) { 2385 for (int k = start_index; k < end_index; k++) { 2386 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) 2387 swap_table_entries(&table[k], &table[k+1]); 2388 } 2389 } 2390 } 2391 2392 start_index = 0; 2393 end_index = 0; 2394 2395 } 2396 } 2397 2398 /* 2399 * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing 2400 * and remove entries that do not 2401 */ 2402 static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2403 { 2404 for (int i = 0; i < (*num_entries - 1); i++) { 2405 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { 2406 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || 2407 (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) 2408 remove_entry_from_table_at_index(table, num_entries, i); 2409 } 2410 } 2411 } 2412 2413 /* 2414 * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings 2415 * Input: 2416 * max_clk_limit - struct containing the desired clock timings 2417 * Output: 2418 * curr_clk_limit - struct containing the timings that need to be overwritten 2419 * Return: 0 upon success, non-zero for failure 2420 */ 2421 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, 2422 struct clk_limit_table_entry *curr_clk_limit) 2423 { 2424 if (NULL == max_clk_limit || NULL == curr_clk_limit) 2425 return -1; //invalid parameters 2426 2427 //only overwrite if desired max clock frequency is initialized 2428 if (max_clk_limit->dcfclk_mhz != 0) 2429 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; 2430 2431 if (max_clk_limit->fclk_mhz != 0) 2432 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz; 2433 2434 if (max_clk_limit->memclk_mhz != 0) 2435 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz; 2436 2437 if (max_clk_limit->socclk_mhz != 0) 2438 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz; 2439 2440 if (max_clk_limit->dtbclk_mhz != 0) 2441 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz; 2442 2443 if (max_clk_limit->dispclk_mhz != 0) 2444 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz; 2445 2446 return 0; 2447 } 2448 2449 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, 2450 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) 2451 { 2452 int i, j; 2453 struct _vcs_dpi_voltage_scaling_st entry = {0}; 2454 struct clk_limit_table_entry max_clk_data = {0}; 2455 2456 unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 2457 2458 static const unsigned int num_dcfclk_stas = 5; 2459 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2460 2461 unsigned int num_uclk_dpms = 0; 2462 unsigned int num_fclk_dpms = 0; 2463 unsigned int num_dcfclk_dpms = 0; 2464 2465 unsigned int num_dc_uclk_dpms = 0; 2466 unsigned int num_dc_fclk_dpms = 0; 2467 unsigned int num_dc_dcfclk_dpms = 0; 2468 2469 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2470 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) 2471 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2472 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) 2473 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2474 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) 2475 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; 2476 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) 2477 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2478 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) 2479 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2480 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz) 2481 max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2482 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz) 2483 max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2484 2485 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { 2486 num_uclk_dpms++; 2487 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) 2488 num_dc_uclk_dpms++; 2489 } 2490 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { 2491 num_fclk_dpms++; 2492 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) 2493 num_dc_fclk_dpms++; 2494 } 2495 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) { 2496 num_dcfclk_dpms++; 2497 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) 2498 num_dc_dcfclk_dpms++; 2499 } 2500 } 2501 2502 if (!disable_dc_mode_overwrite) { 2503 //Overwrite max frequencies with max DC mode frequencies for DC mode systems 2504 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); 2505 num_uclk_dpms = num_dc_uclk_dpms; 2506 num_fclk_dpms = num_dc_fclk_dpms; 2507 num_dcfclk_dpms = num_dc_dcfclk_dpms; 2508 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; 2509 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; 2510 } 2511 2512 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) 2513 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; 2514 2515 if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz) 2516 return -1; 2517 2518 if (max_clk_data.dppclk_mhz == 0) 2519 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; 2520 2521 if (max_clk_data.fclk_mhz == 0) 2522 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * 2523 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 2524 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; 2525 2526 if (max_clk_data.phyclk_mhz == 0) 2527 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2528 2529 *num_entries = 0; 2530 entry.dispclk_mhz = max_clk_data.dispclk_mhz; 2531 entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3; 2532 entry.dppclk_mhz = max_clk_data.dppclk_mhz; 2533 entry.dtbclk_mhz = max_clk_data.dtbclk_mhz; 2534 entry.phyclk_mhz = max_clk_data.phyclk_mhz; 2535 entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2536 entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2537 2538 // Insert all the DCFCLK STAs 2539 for (i = 0; i < num_dcfclk_stas; i++) { 2540 entry.dcfclk_mhz = dcfclk_sta_targets[i]; 2541 entry.fabricclk_mhz = 0; 2542 entry.dram_speed_mts = 0; 2543 2544 get_optimal_ntuple(&entry); 2545 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2546 insert_entry_into_table_sorted(table, num_entries, &entry); 2547 } 2548 2549 // Insert the max DCFCLK 2550 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; 2551 entry.fabricclk_mhz = 0; 2552 entry.dram_speed_mts = 0; 2553 2554 get_optimal_ntuple(&entry); 2555 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2556 insert_entry_into_table_sorted(table, num_entries, &entry); 2557 2558 // Insert the UCLK DPMS 2559 for (i = 0; i < num_uclk_dpms; i++) { 2560 entry.dcfclk_mhz = 0; 2561 entry.fabricclk_mhz = 0; 2562 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; 2563 2564 get_optimal_ntuple(&entry); 2565 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2566 insert_entry_into_table_sorted(table, num_entries, &entry); 2567 } 2568 2569 // If FCLK is coarse grained, insert individual DPMs. 2570 if (num_fclk_dpms > 2) { 2571 for (i = 0; i < num_fclk_dpms; i++) { 2572 entry.dcfclk_mhz = 0; 2573 entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 2574 entry.dram_speed_mts = 0; 2575 2576 get_optimal_ntuple(&entry); 2577 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2578 insert_entry_into_table_sorted(table, num_entries, &entry); 2579 } 2580 } 2581 // If FCLK fine grained, only insert max 2582 else { 2583 entry.dcfclk_mhz = 0; 2584 entry.fabricclk_mhz = max_clk_data.fclk_mhz; 2585 entry.dram_speed_mts = 0; 2586 2587 get_optimal_ntuple(&entry); 2588 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); 2589 insert_entry_into_table_sorted(table, num_entries, &entry); 2590 } 2591 2592 // At this point, the table contains all "points of interest" based on 2593 // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock 2594 // ratios (by derate, are exact). 2595 2596 // Remove states that require higher clocks than are supported 2597 for (i = *num_entries - 1; i >= 0 ; i--) { 2598 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || 2599 table[i].fabricclk_mhz > max_clk_data.fclk_mhz || 2600 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16) 2601 remove_entry_from_table_at_index(table, num_entries, i); 2602 } 2603 2604 // Insert entry with all max dc limits without bandwidth matching 2605 if (!disable_dc_mode_overwrite) { 2606 struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry; 2607 2608 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; 2609 max_dc_limits_entry.fabricclk_mhz = max_clk_data.fclk_mhz; 2610 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16; 2611 2612 max_dc_limits_entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&max_dc_limits_entry); 2613 insert_entry_into_table_sorted(table, num_entries, &max_dc_limits_entry); 2614 2615 sort_entries_with_same_bw(table, num_entries); 2616 remove_inconsistent_entries(table, num_entries); 2617 } 2618 2619 // At this point, the table only contains supported points of interest 2620 // it could be used as is, but some states may be redundant due to 2621 // coarse grained nature of some clocks, so we want to round up to 2622 // coarse grained DPMs and remove duplicates. 2623 2624 // Round up UCLKs 2625 for (i = *num_entries - 1; i >= 0 ; i--) { 2626 for (j = 0; j < num_uclk_dpms; j++) { 2627 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { 2628 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; 2629 break; 2630 } 2631 } 2632 } 2633 2634 // If FCLK is coarse grained, round up to next DPMs 2635 if (num_fclk_dpms > 2) { 2636 for (i = *num_entries - 1; i >= 0 ; i--) { 2637 for (j = 0; j < num_fclk_dpms; j++) { 2638 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { 2639 table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; 2640 break; 2641 } 2642 } 2643 } 2644 } 2645 // Otherwise, round up to minimum. 2646 else { 2647 for (i = *num_entries - 1; i >= 0 ; i--) { 2648 if (table[i].fabricclk_mhz < min_fclk_mhz) { 2649 table[i].fabricclk_mhz = min_fclk_mhz; 2650 } 2651 } 2652 } 2653 2654 // Round DCFCLKs up to minimum 2655 for (i = *num_entries - 1; i >= 0 ; i--) { 2656 if (table[i].dcfclk_mhz < min_dcfclk_mhz) { 2657 table[i].dcfclk_mhz = min_dcfclk_mhz; 2658 } 2659 } 2660 2661 // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. 2662 i = 0; 2663 while (i < *num_entries - 1) { 2664 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && 2665 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && 2666 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) 2667 remove_entry_from_table_at_index(table, num_entries, i + 1); 2668 else 2669 i++; 2670 } 2671 2672 // Fix up the state indicies 2673 for (i = *num_entries - 1; i >= 0 ; i--) { 2674 table[i].state = i; 2675 } 2676 2677 return 0; 2678 } 2679 2680 /* 2681 * dcn32_update_bw_bounding_box 2682 * 2683 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from 2684 * spreadsheet with actual values as per dGPU SKU: 2685 * - with passed few options from dc->config 2686 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might 2687 * need to get it from PM FW) 2688 * - with passed latency values (passed in ns units) in dc-> bb override for 2689 * debugging purposes 2690 * - with passed latencies from VBIOS (in 100_ns units) if available for 2691 * certain dGPU SKU 2692 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU 2693 * of the same ASIC) 2694 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM 2695 * FW for different clocks (which might differ for certain dGPU SKU of the 2696 * same ASIC) 2697 */ 2698 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 2699 { 2700 dc_assert_fp_enabled(); 2701 2702 /* Overrides from dc->config options */ 2703 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 2704 2705 /* Override from passed dc->bb_overrides if available*/ 2706 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns 2707 && dc->bb_overrides.sr_exit_time_ns) { 2708 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; 2709 } 2710 2711 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) 2712 != dc->bb_overrides.sr_enter_plus_exit_time_ns 2713 && dc->bb_overrides.sr_enter_plus_exit_time_ns) { 2714 dcn3_2_soc.sr_enter_plus_exit_time_us = 2715 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; 2716 } 2717 2718 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns 2719 && dc->bb_overrides.urgent_latency_ns) { 2720 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2721 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; 2722 } 2723 2724 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) 2725 != dc->bb_overrides.dram_clock_change_latency_ns 2726 && dc->bb_overrides.dram_clock_change_latency_ns) { 2727 dcn3_2_soc.dram_clock_change_latency_us = 2728 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; 2729 } 2730 2731 if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000) 2732 != dc->bb_overrides.fclk_clock_change_latency_ns 2733 && dc->bb_overrides.fclk_clock_change_latency_ns) { 2734 dcn3_2_soc.fclk_change_latency_us = 2735 dc->bb_overrides.fclk_clock_change_latency_ns / 1000; 2736 } 2737 2738 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) 2739 != dc->bb_overrides.dummy_clock_change_latency_ns 2740 && dc->bb_overrides.dummy_clock_change_latency_ns) { 2741 dcn3_2_soc.dummy_pstate_latency_us = 2742 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; 2743 } 2744 2745 /* Override from VBIOS if VBIOS bb_info available */ 2746 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 2747 struct bp_soc_bb_info bb_info = {0}; 2748 2749 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 2750 if (bb_info.dram_clock_change_latency_100ns > 0) 2751 dcn3_2_soc.dram_clock_change_latency_us = 2752 bb_info.dram_clock_change_latency_100ns * 10; 2753 2754 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 2755 dcn3_2_soc.sr_enter_plus_exit_time_us = 2756 bb_info.dram_sr_enter_exit_latency_100ns * 10; 2757 2758 if (bb_info.dram_sr_exit_latency_100ns > 0) 2759 dcn3_2_soc.sr_exit_time_us = 2760 bb_info.dram_sr_exit_latency_100ns * 10; 2761 } 2762 } 2763 2764 /* Override from VBIOS for num_chan */ 2765 if (dc->ctx->dc_bios->vram_info.num_chans) { 2766 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2767 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc, 2768 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); 2769 } 2770 2771 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2772 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2773 2774 /* DML DSC delay factor workaround */ 2775 dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; 2776 2777 dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; 2778 2779 /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ 2780 dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2781 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2782 2783 /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ 2784 if (bw_params->clk_table.entries[0].memclk_mhz) { 2785 if (dc->debug.use_legacy_soc_bb_mechanism) { 2786 unsigned int i = 0, j = 0, num_states = 0; 2787 2788 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2789 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2790 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2791 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2792 unsigned int min_dcfclk = UINT_MAX; 2793 /* Set 199 as first value in STA target array to have a minimum DCFCLK value. 2794 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */ 2795 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; 2796 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; 2797 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 2798 2799 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2800 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2801 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2802 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && 2803 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk) 2804 min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz; 2805 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2806 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2807 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2808 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2809 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2810 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2811 } 2812 if (min_dcfclk > dcfclk_sta_targets[0]) 2813 dcfclk_sta_targets[0] = min_dcfclk; 2814 if (!max_dcfclk_mhz) 2815 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; 2816 if (!max_dispclk_mhz) 2817 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; 2818 if (!max_dppclk_mhz) 2819 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; 2820 if (!max_phyclk_mhz) 2821 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; 2822 2823 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2824 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2825 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2826 num_dcfclk_sta_targets++; 2827 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2828 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2829 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2830 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2831 dcfclk_sta_targets[i] = max_dcfclk_mhz; 2832 break; 2833 } 2834 } 2835 // Update size of array since we "removed" duplicates 2836 num_dcfclk_sta_targets = i + 1; 2837 } 2838 2839 num_uclk_states = bw_params->clk_table.num_entries; 2840 2841 // Calculate optimal dcfclk for each uclk 2842 for (i = 0; i < num_uclk_states; i++) { 2843 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2844 &optimal_dcfclk_for_uclk[i], NULL); 2845 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2846 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2847 } 2848 } 2849 2850 // Calculate optimal uclk for each dcfclk sta target 2851 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2852 for (j = 0; j < num_uclk_states; j++) { 2853 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2854 optimal_uclk_for_dcfclk_sta_targets[i] = 2855 bw_params->clk_table.entries[j].memclk_mhz * 16; 2856 break; 2857 } 2858 } 2859 } 2860 2861 i = 0; 2862 j = 0; 2863 // create the final dcfclk and uclk table 2864 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2865 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2866 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2867 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2868 } else { 2869 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2870 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2871 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2872 } else { 2873 j = num_uclk_states; 2874 } 2875 } 2876 } 2877 2878 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2879 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2880 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2881 } 2882 2883 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2884 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2885 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2886 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2887 } 2888 2889 /* bw_params->clk_table.entries[MAX_NUM_DPM_LVL]. 2890 * MAX_NUM_DPM_LVL is 8. 2891 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES]. 2892 * DC__VOLTAGE_STATES is 40. 2893 */ 2894 if (num_states > MAX_NUM_DPM_LVL) { 2895 ASSERT(0); 2896 return; 2897 } 2898 2899 dcn3_2_soc.num_states = num_states; 2900 for (i = 0; i < dcn3_2_soc.num_states; i++) { 2901 dcn3_2_soc.clock_limits[i].state = i; 2902 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2903 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2904 2905 /* Fill all states with max values of all these clocks */ 2906 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2907 dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2908 dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2909 dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; 2910 2911 /* Populate from bw_params for DTBCLK, SOCCLK */ 2912 if (i > 0) { 2913 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { 2914 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; 2915 } else { 2916 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2917 } 2918 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { 2919 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 2920 } 2921 2922 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 2923 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; 2924 else 2925 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 2926 2927 if (!dram_speed_mts[i] && i > 0) 2928 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; 2929 else 2930 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2931 2932 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ 2933 /* PHYCLK_D18, PHYCLK_D32 */ 2934 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; 2935 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; 2936 } 2937 } else { 2938 build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params, 2939 dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); 2940 } 2941 2942 /* Re-init DML with updated bb */ 2943 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2944 if (dc->current_state) 2945 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2946 } 2947 } 2948 2949 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 2950 int pipe_cnt) 2951 { 2952 dc_assert_fp_enabled(); 2953 2954 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 2955 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 2956 } 2957 2958 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) 2959 { 2960 bool allow = false; 2961 uint32_t refresh_rate = 0; 2962 2963 /* Allow subvp on displays that have active margin for 2560x1440@60hz displays 2964 * only for now. There must be no scaling as well. 2965 * 2966 * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs 2967 * for p-state switching. 2968 */ 2969 if (pipe->stream && pipe->plane_state) { 2970 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 2971 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 2972 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 2973 if (pipe->stream->timing.v_addressable == 1440 && 2974 pipe->stream->timing.h_addressable == 2560 && 2975 refresh_rate >= 55 && refresh_rate <= 65 && 2976 pipe->plane_state->src_rect.height == 1440 && 2977 pipe->plane_state->src_rect.width == 2560 && 2978 pipe->plane_state->dst_rect.height == 1440 && 2979 pipe->plane_state->dst_rect.width == 2560) 2980 allow = true; 2981 } 2982 return allow; 2983 } 2984 2985 /** 2986 * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp 2987 * 2988 * @dc: Current DC state 2989 * @context: New DC state to be programmed 2990 * @pipe: Pipe to be considered for use in subvp 2991 * 2992 * On high refresh rate display configs, we will allow subvp under the following conditions: 2993 * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440 2994 * 2. Refresh rate is between 120hz - 165hz 2995 * 3. No scaling 2996 * 4. Freesync is inactive 2997 * 5. For single display cases, freesync must be disabled 2998 * 2999 * Return: True if pipe can be used for subvp, false otherwise 3000 */ 3001 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe) 3002 { 3003 bool allow = false; 3004 uint32_t refresh_rate = 0; 3005 uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh; 3006 uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh; 3007 uint32_t min_refresh = subvp_max_refresh; 3008 uint32_t i; 3009 3010 /* Only allow SubVP on high refresh displays if all connected displays 3011 * are considered "high refresh" (i.e. >= 120hz). We do not want to 3012 * allow combinations such as 120hz (SubVP) + 60hz (SubVP). 3013 */ 3014 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3015 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3016 3017 if (!pipe_ctx->stream) 3018 continue; 3019 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 + 3020 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1) 3021 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total); 3022 3023 if (refresh_rate < min_refresh) 3024 min_refresh = refresh_rate; 3025 } 3026 3027 if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream && 3028 pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) { 3029 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 3030 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 3031 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 3032 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) { 3033 for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) { 3034 uint32_t width = subvp_high_refresh_list.res[i].width; 3035 uint32_t height = subvp_high_refresh_list.res[i].height; 3036 3037 if (dcn32_check_native_scaling_for_res(pipe, width, height)) { 3038 if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) { 3039 allow = true; 3040 break; 3041 } 3042 } 3043 } 3044 } 3045 } 3046 return allow; 3047 } 3048 3049 /** 3050 * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy 3051 * 3052 * @dc: Current DC state 3053 * @context: New DC state to be programmed 3054 * 3055 * Return: Max vratio for prefetch 3056 */ 3057 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context) 3058 { 3059 double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4 3060 int i; 3061 3062 /* For single display MPO configs, allow the max vratio to be 8 3063 * if any plane is YUV420 format 3064 */ 3065 if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) { 3066 for (i = 0; i < context->stream_status[0].plane_count; i++) { 3067 if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr || 3068 context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) { 3069 max_vratio_pre = __DML_MAX_VRATIO_PRE__; 3070 } 3071 } 3072 } 3073 return max_vratio_pre; 3074 } 3075 3076 /** 3077 * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case 3078 * 3079 * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config). 3080 * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the 3081 * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has 3082 * ActiveMargin <= 0 to be the FPO stream candidate if found. 3083 * 3084 * 3085 * @dc: current dc state 3086 * @context: new dc state 3087 * @fpo_candidate_stream: pointer to FPO stream candidate if one is found 3088 * 3089 * Return: void 3090 */ 3091 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream) 3092 { 3093 unsigned int i, pipe_idx; 3094 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 3095 3096 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3097 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3098 3099 if (!pipe->stream) 3100 continue; 3101 3102 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { 3103 *fpo_candidate_stream = pipe->stream; 3104 break; 3105 } 3106 pipe_idx++; 3107 } 3108 } 3109 3110 /** 3111 * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE 3112 * 3113 * @dc: current dc state 3114 * @context: new dc state 3115 * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found" 3116 * 3117 * Return: True if VACTIVE display is found, false otherwise 3118 */ 3119 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us) 3120 { 3121 unsigned int i, pipe_idx; 3122 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 3123 bool vactive_found = false; 3124 unsigned int blank_us = 0; 3125 3126 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3127 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3128 3129 if (!pipe->stream) 3130 continue; 3131 3132 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / 3133 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000; 3134 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us && 3135 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) { 3136 vactive_found = true; 3137 break; 3138 } 3139 pipe_idx++; 3140 } 3141 return vactive_found; 3142 } 3143 3144 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 3145 { 3146 dc_assert_fp_enabled(); 3147 dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0; 3148 } 3149 3150 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) 3151 { 3152 // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue) 3153 if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) && 3154 dc->dml.soc.num_chans <= 8) { 3155 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; 3156 3157 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 && 3158 num_mclk_levels > 1) { 3159 context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16; 3160 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; 3161 } 3162 } 3163 } 3164