1 /* $NetBSD: amdgpu_dcn10_resource.c,v 1.4 2021/12/19 11:59:31 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn10_resource.c,v 1.4 2021/12/19 11:59:31 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34 #include "dc.h"
35
36 #include "dcn10_init.h"
37
38 #include "resource.h"
39 #include "include/irq_service_interface.h"
40 #include "dcn10_resource.h"
41 #include "dcn10_ipp.h"
42 #include "dcn10_mpc.h"
43 #include "irq/dcn10/irq_service_dcn10.h"
44 #include "dcn10_dpp.h"
45 #include "dcn10_optc.h"
46 #include "dcn10_hw_sequencer.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn10_opp.h"
49 #include "dcn10_link_encoder.h"
50 #include "dcn10_stream_encoder.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_hwseq.h"
54 #include "virtual/virtual_stream_encoder.h"
55 #include "dce110/dce110_resource.h"
56 #include "dce112/dce112_resource.h"
57 #include "dcn10_hubp.h"
58 #include "dcn10_hubbub.h"
59
60 #include "soc15_hw_ip.h"
61 #include "vega10_ip_offset.h"
62
63 #include "dcn/dcn_1_0_offset.h"
64 #include "dcn/dcn_1_0_sh_mask.h"
65
66 #include "nbio/nbio_7_0_offset.h"
67
68 #include "mmhub/mmhub_9_1_offset.h"
69 #include "mmhub/mmhub_9_1_sh_mask.h"
70
71 #include "reg_helper.h"
72 #include "dce/dce_abm.h"
73 #include "dce/dce_dmcu.h"
74 #include "dce/dce_aux.h"
75 #include "dce/dce_i2c.h"
76
77 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
78 .rob_buffer_size_kbytes = 64,
79 .det_buffer_size_kbytes = 164,
80 .dpte_buffer_size_in_pte_reqs_luma = 42,
81 .dpp_output_buffer_pixels = 2560,
82 .opp_output_buffer_lines = 1,
83 .pixel_chunk_size_kbytes = 8,
84 .pte_enable = 1,
85 .pte_chunk_size_kbytes = 2,
86 .meta_chunk_size_kbytes = 2,
87 .writeback_chunk_size_kbytes = 2,
88 .line_buffer_size_bits = 589824,
89 .max_line_buffer_lines = 12,
90 .IsLineBufferBppFixed = 0,
91 .LineBufferFixedBpp = -1,
92 .writeback_luma_buffer_size_kbytes = 12,
93 .writeback_chroma_buffer_size_kbytes = 8,
94 .max_num_dpp = 4,
95 .max_num_wb = 2,
96 .max_dchub_pscl_bw_pix_per_clk = 4,
97 .max_pscl_lb_bw_pix_per_clk = 2,
98 .max_lb_vscl_bw_pix_per_clk = 4,
99 .max_vscl_hscl_bw_pix_per_clk = 4,
100 .max_hscl_ratio = 4,
101 .max_vscl_ratio = 4,
102 .hscl_mults = 4,
103 .vscl_mults = 4,
104 .max_hscl_taps = 8,
105 .max_vscl_taps = 8,
106 .dispclk_ramp_margin_percent = 1,
107 .underscan_factor = 1.10,
108 .min_vblank_lines = 14,
109 .dppclk_delay_subtotal = 90,
110 .dispclk_delay_subtotal = 42,
111 .dcfclk_cstate_latency = 10,
112 .max_inter_dcn_tile_repeaters = 8,
113 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
114 .bug_forcing_LC_req_same_size_fixed = 0,
115 };
116
117 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
118 .sr_exit_time_us = 9.0,
119 .sr_enter_plus_exit_time_us = 11.0,
120 .urgent_latency_us = 4.0,
121 .writeback_latency_us = 12.0,
122 .ideal_dram_bw_after_urgent_percent = 80.0,
123 .max_request_size_bytes = 256,
124 .downspread_percent = 0.5,
125 .dram_page_open_time_ns = 50.0,
126 .dram_rw_turnaround_time_ns = 17.5,
127 .dram_return_buffer_per_channel_bytes = 8192,
128 .round_trip_ping_latency_dcfclk_cycles = 128,
129 .urgent_out_of_order_return_per_channel_bytes = 256,
130 .channel_interleave_bytes = 256,
131 .num_banks = 8,
132 .num_chans = 2,
133 .vmm_page_size_bytes = 4096,
134 .dram_clock_change_latency_us = 17.0,
135 .writeback_dram_clock_change_latency_us = 23.0,
136 .return_bus_width_bytes = 64,
137 };
138
139 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
140 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
141 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
142 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
143 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
144 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
145 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
146 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
147 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
148 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
149 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
150 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
151 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
152 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
153 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
154 #endif
155
156
157 enum dcn10_clk_src_array_id {
158 DCN10_CLK_SRC_PLL0,
159 DCN10_CLK_SRC_PLL1,
160 DCN10_CLK_SRC_PLL2,
161 DCN10_CLK_SRC_PLL3,
162 DCN10_CLK_SRC_TOTAL,
163 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
164 };
165
166 /* begin *********************
167 * macros to expend register list macro defined in HW object header file */
168
169 /* DCN */
170 #define BASE_INNER(seg) \
171 DCE_BASE__INST0_SEG ## seg
172
173 #define BASE(seg) \
174 BASE_INNER(seg)
175
176 #define SR(reg_name)\
177 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
178 mm ## reg_name
179
180 #define SRI(reg_name, block, id)\
181 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 mm ## block ## id ## _ ## reg_name
183
184
185 #define SRII(reg_name, block, id)\
186 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
187 mm ## block ## id ## _ ## reg_name
188
189 /* NBIO */
190 #define NBIO_BASE_INNER(seg) \
191 NBIF_BASE__INST0_SEG ## seg
192
193 #define NBIO_BASE(seg) \
194 NBIO_BASE_INNER(seg)
195
196 #define NBIO_SR(reg_name)\
197 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
198 mm ## reg_name
199
200 /* MMHUB */
201 #define MMHUB_BASE_INNER(seg) \
202 MMHUB_BASE__INST0_SEG ## seg
203
204 #define MMHUB_BASE(seg) \
205 MMHUB_BASE_INNER(seg)
206
207 #define MMHUB_SR(reg_name)\
208 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
209 mm ## reg_name
210
211 /* macros to expend register list macro defined in HW object header file
212 * end *********************/
213
214
215 static const struct dce_dmcu_registers dmcu_regs = {
216 DMCU_DCN10_REG_LIST()
217 };
218
219 static const struct dce_dmcu_shift dmcu_shift = {
220 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
221 };
222
223 static const struct dce_dmcu_mask dmcu_mask = {
224 DMCU_MASK_SH_LIST_DCN10(_MASK)
225 };
226
227 static const struct dce_abm_registers abm_regs = {
228 ABM_DCN10_REG_LIST(0)
229 };
230
231 static const struct dce_abm_shift abm_shift = {
232 ABM_MASK_SH_LIST_DCN10(__SHIFT)
233 };
234
235 static const struct dce_abm_mask abm_mask = {
236 ABM_MASK_SH_LIST_DCN10(_MASK)
237 };
238
239 #define stream_enc_regs(id)\
240 [id] = {\
241 SE_DCN_REG_LIST(id)\
242 }
243
244 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
245 stream_enc_regs(0),
246 stream_enc_regs(1),
247 stream_enc_regs(2),
248 stream_enc_regs(3),
249 };
250
251 static const struct dcn10_stream_encoder_shift se_shift = {
252 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
253 };
254
255 static const struct dcn10_stream_encoder_mask se_mask = {
256 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
257 };
258
259 #define audio_regs(id)\
260 [id] = {\
261 AUD_COMMON_REG_LIST(id)\
262 }
263
264 static const struct dce_audio_registers audio_regs[] = {
265 audio_regs(0),
266 audio_regs(1),
267 audio_regs(2),
268 audio_regs(3),
269 };
270
271 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
274 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
275
276 static const struct dce_audio_shift audio_shift = {
277 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_audio_mask audio_mask = {
281 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
282 };
283
284 #define aux_regs(id)\
285 [id] = {\
286 AUX_REG_LIST(id)\
287 }
288
289 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
290 aux_regs(0),
291 aux_regs(1),
292 aux_regs(2),
293 aux_regs(3)
294 };
295
296 #define hpd_regs(id)\
297 [id] = {\
298 HPD_REG_LIST(id)\
299 }
300
301 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
302 hpd_regs(0),
303 hpd_regs(1),
304 hpd_regs(2),
305 hpd_regs(3)
306 };
307
308 #define link_regs(id)\
309 [id] = {\
310 LE_DCN10_REG_LIST(id), \
311 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
312 }
313
314 static const struct dcn10_link_enc_registers link_enc_regs[] = {
315 link_regs(0),
316 link_regs(1),
317 link_regs(2),
318 link_regs(3)
319 };
320
321 static const struct dcn10_link_enc_shift le_shift = {
322 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
323 };
324
325 static const struct dcn10_link_enc_mask le_mask = {
326 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
327 };
328
329 static const struct dce110_aux_registers_shift aux_shift = {
330 DCN10_AUX_MASK_SH_LIST(__SHIFT)
331 };
332
333 static const struct dce110_aux_registers_mask aux_mask = {
334 DCN10_AUX_MASK_SH_LIST(_MASK)
335 };
336
337 #define ipp_regs(id)\
338 [id] = {\
339 IPP_REG_LIST_DCN10(id),\
340 }
341
342 static const struct dcn10_ipp_registers ipp_regs[] = {
343 ipp_regs(0),
344 ipp_regs(1),
345 ipp_regs(2),
346 ipp_regs(3),
347 };
348
349 static const struct dcn10_ipp_shift ipp_shift = {
350 IPP_MASK_SH_LIST_DCN10(__SHIFT)
351 };
352
353 static const struct dcn10_ipp_mask ipp_mask = {
354 IPP_MASK_SH_LIST_DCN10(_MASK),
355 };
356
357 #define opp_regs(id)\
358 [id] = {\
359 OPP_REG_LIST_DCN10(id),\
360 }
361
362 static const struct dcn10_opp_registers opp_regs[] = {
363 opp_regs(0),
364 opp_regs(1),
365 opp_regs(2),
366 opp_regs(3),
367 };
368
369 static const struct dcn10_opp_shift opp_shift = {
370 OPP_MASK_SH_LIST_DCN10(__SHIFT)
371 };
372
373 static const struct dcn10_opp_mask opp_mask = {
374 OPP_MASK_SH_LIST_DCN10(_MASK),
375 };
376
377 #define aux_engine_regs(id)\
378 [id] = {\
379 AUX_COMMON_REG_LIST(id), \
380 .AUX_RESET_MASK = 0 \
381 }
382
383 static const struct dce110_aux_registers aux_engine_regs[] = {
384 aux_engine_regs(0),
385 aux_engine_regs(1),
386 aux_engine_regs(2),
387 aux_engine_regs(3),
388 aux_engine_regs(4),
389 aux_engine_regs(5)
390 };
391
392 #define tf_regs(id)\
393 [id] = {\
394 TF_REG_LIST_DCN10(id),\
395 }
396
397 static const struct dcn_dpp_registers tf_regs[] = {
398 tf_regs(0),
399 tf_regs(1),
400 tf_regs(2),
401 tf_regs(3),
402 };
403
404 static const struct dcn_dpp_shift tf_shift = {
405 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
406 TF_DEBUG_REG_LIST_SH_DCN10
407
408 };
409
410 static const struct dcn_dpp_mask tf_mask = {
411 TF_REG_LIST_SH_MASK_DCN10(_MASK),
412 TF_DEBUG_REG_LIST_MASK_DCN10
413 };
414
415 static const struct dcn_mpc_registers mpc_regs = {
416 MPC_COMMON_REG_LIST_DCN1_0(0),
417 MPC_COMMON_REG_LIST_DCN1_0(1),
418 MPC_COMMON_REG_LIST_DCN1_0(2),
419 MPC_COMMON_REG_LIST_DCN1_0(3),
420 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
421 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
422 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
423 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
424 };
425
426 static const struct dcn_mpc_shift mpc_shift = {
427 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
428 };
429
430 static const struct dcn_mpc_mask mpc_mask = {
431 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
432 };
433
434 #define tg_regs(id)\
435 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
436
437 static const struct dcn_optc_registers tg_regs[] = {
438 tg_regs(0),
439 tg_regs(1),
440 tg_regs(2),
441 tg_regs(3),
442 };
443
444 static const struct dcn_optc_shift tg_shift = {
445 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
446 };
447
448 static const struct dcn_optc_mask tg_mask = {
449 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
450 };
451
452 static const struct bios_registers bios_regs = {
453 NBIO_SR(BIOS_SCRATCH_3),
454 NBIO_SR(BIOS_SCRATCH_6)
455 };
456
457 #define hubp_regs(id)\
458 [id] = {\
459 HUBP_REG_LIST_DCN10(id)\
460 }
461
462 static const struct dcn_mi_registers hubp_regs[] = {
463 hubp_regs(0),
464 hubp_regs(1),
465 hubp_regs(2),
466 hubp_regs(3),
467 };
468
469 static const struct dcn_mi_shift hubp_shift = {
470 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
471 };
472
473 static const struct dcn_mi_mask hubp_mask = {
474 HUBP_MASK_SH_LIST_DCN10(_MASK)
475 };
476
477 static const struct dcn_hubbub_registers hubbub_reg = {
478 HUBBUB_REG_LIST_DCN10(0)
479 };
480
481 static const struct dcn_hubbub_shift hubbub_shift = {
482 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
483 };
484
485 static const struct dcn_hubbub_mask hubbub_mask = {
486 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
487 };
488
map_transmitter_id_to_phy_instance(enum transmitter transmitter)489 static int map_transmitter_id_to_phy_instance(
490 enum transmitter transmitter)
491 {
492 switch (transmitter) {
493 case TRANSMITTER_UNIPHY_A:
494 return 0;
495 break;
496 case TRANSMITTER_UNIPHY_B:
497 return 1;
498 break;
499 case TRANSMITTER_UNIPHY_C:
500 return 2;
501 break;
502 case TRANSMITTER_UNIPHY_D:
503 return 3;
504 break;
505 default:
506 ASSERT(0);
507 return 0;
508 }
509 }
510
511 #define clk_src_regs(index, pllid)\
512 [index] = {\
513 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
514 }
515
516 static const struct dce110_clk_src_regs clk_src_regs[] = {
517 clk_src_regs(0, A),
518 clk_src_regs(1, B),
519 clk_src_regs(2, C),
520 clk_src_regs(3, D)
521 };
522
523 static const struct dce110_clk_src_shift cs_shift = {
524 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
525 };
526
527 static const struct dce110_clk_src_mask cs_mask = {
528 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
529 };
530
531 static const struct resource_caps res_cap = {
532 .num_timing_generator = 4,
533 .num_opp = 4,
534 .num_video_plane = 4,
535 .num_audio = 4,
536 .num_stream_encoder = 4,
537 .num_pll = 4,
538 .num_ddc = 4,
539 };
540
541 static const struct resource_caps rv2_res_cap = {
542 .num_timing_generator = 3,
543 .num_opp = 3,
544 .num_video_plane = 3,
545 .num_audio = 3,
546 .num_stream_encoder = 3,
547 .num_pll = 3,
548 .num_ddc = 4,
549 };
550
551 static const struct dc_plane_cap plane_cap = {
552 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
553 .blends_with_above = true,
554 .blends_with_below = true,
555 .per_pixel_alpha = true,
556
557 .pixel_format_support = {
558 .argb8888 = true,
559 .nv12 = true,
560 .fp16 = true
561 },
562
563 .max_upscale_factor = {
564 .argb8888 = 16000,
565 .nv12 = 16000,
566 .fp16 = 1
567 },
568
569 .max_downscale_factor = {
570 .argb8888 = 250,
571 .nv12 = 250,
572 .fp16 = 1
573 }
574 };
575
576 static const struct dc_debug_options debug_defaults_drv = {
577 .sanity_checks = true,
578 .disable_dmcu = true,
579 .force_abm_enable = false,
580 .timing_trace = false,
581 .clock_trace = true,
582
583 /* raven smu dones't allow 0 disp clk,
584 * smu min disp clk limit is 50Mhz
585 * keep min disp clk 100Mhz avoid smu hang
586 */
587 .min_disp_clk_khz = 100000,
588
589 .disable_pplib_clock_request = false,
590 .disable_pplib_wm_range = false,
591 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
592 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
593 .force_single_disp_pipe_split = true,
594 .disable_dcc = DCC_ENABLE,
595 .voltage_align_fclk = true,
596 .disable_stereo_support = true,
597 .vsr_support = true,
598 .performance_trace = false,
599 .az_endpoint_mute_only = true,
600 .recovery_enabled = false, /*enable this by default after testing.*/
601 .max_downscale_src_width = 3840,
602 .underflow_assert_delay_us = 0xFFFFFFFF,
603 };
604
605 static const struct dc_debug_options debug_defaults_diags = {
606 .disable_dmcu = true,
607 .force_abm_enable = false,
608 .timing_trace = true,
609 .clock_trace = true,
610 .disable_stutter = true,
611 .disable_pplib_clock_request = true,
612 .disable_pplib_wm_range = true,
613 .underflow_assert_delay_us = 0xFFFFFFFF,
614 };
615
dcn10_dpp_destroy(struct dpp ** dpp)616 static void dcn10_dpp_destroy(struct dpp **dpp)
617 {
618 kfree(TO_DCN10_DPP(*dpp));
619 *dpp = NULL;
620 }
621
dcn10_dpp_create(struct dc_context * ctx,uint32_t inst)622 static struct dpp *dcn10_dpp_create(
623 struct dc_context *ctx,
624 uint32_t inst)
625 {
626 struct dcn10_dpp *dpp =
627 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
628
629 if (!dpp)
630 return NULL;
631
632 dpp1_construct(dpp, ctx, inst,
633 &tf_regs[inst], &tf_shift, &tf_mask);
634 return &dpp->base;
635 }
636
dcn10_ipp_create(struct dc_context * ctx,uint32_t inst)637 static struct input_pixel_processor *dcn10_ipp_create(
638 struct dc_context *ctx, uint32_t inst)
639 {
640 struct dcn10_ipp *ipp =
641 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
642
643 if (!ipp) {
644 BREAK_TO_DEBUGGER();
645 return NULL;
646 }
647
648 dcn10_ipp_construct(ipp, ctx, inst,
649 &ipp_regs[inst], &ipp_shift, &ipp_mask);
650 return &ipp->base;
651 }
652
653
dcn10_opp_create(struct dc_context * ctx,uint32_t inst)654 static struct output_pixel_processor *dcn10_opp_create(
655 struct dc_context *ctx, uint32_t inst)
656 {
657 struct dcn10_opp *opp =
658 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
659
660 if (!opp) {
661 BREAK_TO_DEBUGGER();
662 return NULL;
663 }
664
665 dcn10_opp_construct(opp, ctx, inst,
666 &opp_regs[inst], &opp_shift, &opp_mask);
667 return &opp->base;
668 }
669
dcn10_aux_engine_create(struct dc_context * ctx,uint32_t inst)670 struct dce_aux *dcn10_aux_engine_create(
671 struct dc_context *ctx,
672 uint32_t inst)
673 {
674 struct aux_engine_dce110 *aux_engine =
675 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
676
677 if (!aux_engine)
678 return NULL;
679
680 dce110_aux_engine_construct(aux_engine, ctx, inst,
681 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
682 &aux_engine_regs[inst],
683 &aux_mask,
684 &aux_shift,
685 ctx->dc->caps.extended_aux_timeout_support);
686
687 return &aux_engine->base;
688 }
689 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
690
691 static const struct dce_i2c_registers i2c_hw_regs[] = {
692 i2c_inst_regs(1),
693 i2c_inst_regs(2),
694 i2c_inst_regs(3),
695 i2c_inst_regs(4),
696 i2c_inst_regs(5),
697 i2c_inst_regs(6),
698 };
699
700 static const struct dce_i2c_shift i2c_shifts = {
701 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
702 };
703
704 static const struct dce_i2c_mask i2c_masks = {
705 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
706 };
707
dcn10_i2c_hw_create(struct dc_context * ctx,uint32_t inst)708 struct dce_i2c_hw *dcn10_i2c_hw_create(
709 struct dc_context *ctx,
710 uint32_t inst)
711 {
712 struct dce_i2c_hw *dce_i2c_hw =
713 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
714
715 if (!dce_i2c_hw)
716 return NULL;
717
718 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
719 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
720
721 return dce_i2c_hw;
722 }
dcn10_mpc_create(struct dc_context * ctx)723 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
724 {
725 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
726 GFP_KERNEL);
727
728 if (!mpc10)
729 return NULL;
730
731 dcn10_mpc_construct(mpc10, ctx,
732 &mpc_regs,
733 &mpc_shift,
734 &mpc_mask,
735 4);
736
737 return &mpc10->base;
738 }
739
dcn10_hubbub_create(struct dc_context * ctx)740 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
741 {
742 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
743 GFP_KERNEL);
744
745 if (!dcn10_hubbub)
746 return NULL;
747
748 hubbub1_construct(&dcn10_hubbub->base, ctx,
749 &hubbub_reg,
750 &hubbub_shift,
751 &hubbub_mask);
752
753 return &dcn10_hubbub->base;
754 }
755
dcn10_timing_generator_create(struct dc_context * ctx,uint32_t instance)756 static struct timing_generator *dcn10_timing_generator_create(
757 struct dc_context *ctx,
758 uint32_t instance)
759 {
760 struct optc *tgn10 =
761 kzalloc(sizeof(struct optc), GFP_KERNEL);
762
763 if (!tgn10)
764 return NULL;
765
766 tgn10->base.inst = instance;
767 tgn10->base.ctx = ctx;
768
769 tgn10->tg_regs = &tg_regs[instance];
770 tgn10->tg_shift = &tg_shift;
771 tgn10->tg_mask = &tg_mask;
772
773 dcn10_timing_generator_init(tgn10);
774
775 return &tgn10->base;
776 }
777
778 static const struct encoder_feature_support link_enc_feature = {
779 .max_hdmi_deep_color = COLOR_DEPTH_121212,
780 .max_hdmi_pixel_clock = 600000,
781 .hdmi_ycbcr420_supported = true,
782 .dp_ycbcr420_supported = false,
783 .flags.bits.IS_HBR2_CAPABLE = true,
784 .flags.bits.IS_HBR3_CAPABLE = true,
785 .flags.bits.IS_TPS3_CAPABLE = true,
786 .flags.bits.IS_TPS4_CAPABLE = true
787 };
788
dcn10_link_encoder_create(const struct encoder_init_data * enc_init_data)789 struct link_encoder *dcn10_link_encoder_create(
790 const struct encoder_init_data *enc_init_data)
791 {
792 struct dcn10_link_encoder *enc10 =
793 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
794 int link_regs_id;
795
796 if (!enc10)
797 return NULL;
798
799 link_regs_id =
800 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
801
802 dcn10_link_encoder_construct(enc10,
803 enc_init_data,
804 &link_enc_feature,
805 &link_enc_regs[link_regs_id],
806 &link_enc_aux_regs[enc_init_data->channel - 1],
807 &link_enc_hpd_regs[enc_init_data->hpd_source],
808 &le_shift,
809 &le_mask);
810
811 return &enc10->base;
812 }
813
dcn10_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)814 struct clock_source *dcn10_clock_source_create(
815 struct dc_context *ctx,
816 struct dc_bios *bios,
817 enum clock_source_id id,
818 const struct dce110_clk_src_regs *regs,
819 bool dp_clk_src)
820 {
821 struct dce110_clk_src *clk_src =
822 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
823
824 if (!clk_src)
825 return NULL;
826
827 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
828 regs, &cs_shift, &cs_mask)) {
829 clk_src->base.dp_clk_src = dp_clk_src;
830 return &clk_src->base;
831 }
832
833 kfree(clk_src);
834 BREAK_TO_DEBUGGER();
835 return NULL;
836 }
837
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)838 static void read_dce_straps(
839 struct dc_context *ctx,
840 struct resource_straps *straps)
841 {
842 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
843 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
844 }
845
create_audio(struct dc_context * ctx,unsigned int inst)846 static struct audio *create_audio(
847 struct dc_context *ctx, unsigned int inst)
848 {
849 return dce_audio_create(ctx, inst,
850 &audio_regs[inst], &audio_shift, &audio_mask);
851 }
852
dcn10_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)853 static struct stream_encoder *dcn10_stream_encoder_create(
854 enum engine_id eng_id,
855 struct dc_context *ctx)
856 {
857 struct dcn10_stream_encoder *enc1 =
858 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
859
860 if (!enc1)
861 return NULL;
862
863 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
864 &stream_enc_regs[eng_id],
865 &se_shift, &se_mask);
866 return &enc1->base;
867 }
868
869 static const struct dce_hwseq_registers hwseq_reg = {
870 HWSEQ_DCN1_REG_LIST()
871 };
872
873 static const struct dce_hwseq_shift hwseq_shift = {
874 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
875 };
876
877 static const struct dce_hwseq_mask hwseq_mask = {
878 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
879 };
880
dcn10_hwseq_create(struct dc_context * ctx)881 static struct dce_hwseq *dcn10_hwseq_create(
882 struct dc_context *ctx)
883 {
884 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
885
886 if (hws) {
887 hws->ctx = ctx;
888 hws->regs = &hwseq_reg;
889 hws->shifts = &hwseq_shift;
890 hws->masks = &hwseq_mask;
891 hws->wa.DEGVIDCN10_253 = true;
892 hws->wa.false_optc_underflow = true;
893 hws->wa.DEGVIDCN10_254 = true;
894 }
895 return hws;
896 }
897
898 static const struct resource_create_funcs res_create_funcs = {
899 .read_dce_straps = read_dce_straps,
900 .create_audio = create_audio,
901 .create_stream_encoder = dcn10_stream_encoder_create,
902 .create_hwseq = dcn10_hwseq_create,
903 };
904
905 static const struct resource_create_funcs res_create_maximus_funcs = {
906 .read_dce_straps = NULL,
907 .create_audio = NULL,
908 .create_stream_encoder = NULL,
909 .create_hwseq = dcn10_hwseq_create,
910 };
911
dcn10_clock_source_destroy(struct clock_source ** clk_src)912 void dcn10_clock_source_destroy(struct clock_source **clk_src)
913 {
914 kfree(TO_DCE110_CLK_SRC(*clk_src));
915 *clk_src = NULL;
916 }
917
dcn10_pp_smu_create(struct dc_context * ctx)918 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
919 {
920 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
921
922 if (!pp_smu)
923 return pp_smu;
924
925 dm_pp_get_funcs(ctx, pp_smu);
926 return pp_smu;
927 }
928
dcn10_resource_destruct(struct dcn10_resource_pool * pool)929 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
930 {
931 unsigned int i;
932
933 for (i = 0; i < pool->base.stream_enc_count; i++) {
934 if (pool->base.stream_enc[i] != NULL) {
935 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
936 pool->base.stream_enc[i] = NULL;
937 }
938 }
939
940 if (pool->base.mpc != NULL) {
941 kfree(TO_DCN10_MPC(pool->base.mpc));
942 pool->base.mpc = NULL;
943 }
944
945 if (pool->base.hubbub != NULL) {
946 kfree(pool->base.hubbub);
947 pool->base.hubbub = NULL;
948 }
949
950 for (i = 0; i < pool->base.pipe_count; i++) {
951 if (pool->base.opps[i] != NULL)
952 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
953
954 if (pool->base.dpps[i] != NULL)
955 dcn10_dpp_destroy(&pool->base.dpps[i]);
956
957 if (pool->base.ipps[i] != NULL)
958 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
959
960 if (pool->base.hubps[i] != NULL) {
961 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
962 pool->base.hubps[i] = NULL;
963 }
964
965 if (pool->base.irqs != NULL) {
966 dal_irq_service_destroy(&pool->base.irqs);
967 }
968
969 if (pool->base.timing_generators[i] != NULL) {
970 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
971 pool->base.timing_generators[i] = NULL;
972 }
973 }
974
975 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
976 if (pool->base.engines[i] != NULL)
977 dce110_engine_destroy(&pool->base.engines[i]);
978 if (pool->base.hw_i2cs[i] != NULL) {
979 kfree(pool->base.hw_i2cs[i]);
980 pool->base.hw_i2cs[i] = NULL;
981 }
982 if (pool->base.sw_i2cs[i] != NULL) {
983 kfree(pool->base.sw_i2cs[i]);
984 pool->base.sw_i2cs[i] = NULL;
985 }
986 }
987
988 for (i = 0; i < pool->base.audio_count; i++) {
989 if (pool->base.audios[i])
990 dce_aud_destroy(&pool->base.audios[i]);
991 }
992
993 for (i = 0; i < pool->base.clk_src_count; i++) {
994 if (pool->base.clock_sources[i] != NULL) {
995 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
996 pool->base.clock_sources[i] = NULL;
997 }
998 }
999
1000 if (pool->base.dp_clock_source != NULL) {
1001 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
1002 pool->base.dp_clock_source = NULL;
1003 }
1004
1005 if (pool->base.abm != NULL)
1006 dce_abm_destroy(&pool->base.abm);
1007
1008 if (pool->base.dmcu != NULL)
1009 dce_dmcu_destroy(&pool->base.dmcu);
1010
1011 kfree(pool->base.pp_smu);
1012 }
1013
dcn10_hubp_create(struct dc_context * ctx,uint32_t inst)1014 static struct hubp *dcn10_hubp_create(
1015 struct dc_context *ctx,
1016 uint32_t inst)
1017 {
1018 struct dcn10_hubp *hubp1 =
1019 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
1020
1021 if (!hubp1)
1022 return NULL;
1023
1024 dcn10_hubp_construct(hubp1, ctx, inst,
1025 &hubp_regs[inst], &hubp_shift, &hubp_mask);
1026 return &hubp1->base;
1027 }
1028
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1029 static void get_pixel_clock_parameters(
1030 const struct pipe_ctx *pipe_ctx,
1031 struct pixel_clk_params *pixel_clk_params)
1032 {
1033 const struct dc_stream_state *stream = pipe_ctx->stream;
1034 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1035 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1036 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1037 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1038 /* TODO: un-hardcode*/
1039 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1040 LINK_RATE_REF_FREQ_IN_KHZ;
1041 pixel_clk_params->flags.ENABLE_SS = 0;
1042 pixel_clk_params->color_depth =
1043 stream->timing.display_color_depth;
1044 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1045 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1046
1047 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1048 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1049
1050 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1051 pixel_clk_params->requested_pix_clk_100hz /= 2;
1052 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1053 pixel_clk_params->requested_pix_clk_100hz *= 2;
1054
1055 }
1056
build_clamping_params(struct dc_stream_state * stream)1057 static void build_clamping_params(struct dc_stream_state *stream)
1058 {
1059 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1060 stream->clamping.c_depth = stream->timing.display_color_depth;
1061 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1062 }
1063
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1064 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1065 {
1066
1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1068
1069 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1070 pipe_ctx->clock_source,
1071 &pipe_ctx->stream_res.pix_clk_params,
1072 &pipe_ctx->pll_settings);
1073
1074 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1075
1076 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1077 &pipe_ctx->stream->bit_depth_params);
1078 build_clamping_params(pipe_ctx->stream);
1079 }
1080
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1081 static enum dc_status build_mapped_resource(
1082 const struct dc *dc,
1083 struct dc_state *context,
1084 struct dc_stream_state *stream)
1085 {
1086 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1087
1088 /*TODO Seems unneeded anymore */
1089 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1090 if (stream != NULL && old_context->streams[i] != NULL) {
1091 todo: shouldn't have to copy missing parameter here
1092 resource_build_bit_depth_reduction_params(stream,
1093 &stream->bit_depth_params);
1094 stream->clamping.pixel_encoding =
1095 stream->timing.pixel_encoding;
1096
1097 resource_build_bit_depth_reduction_params(stream,
1098 &stream->bit_depth_params);
1099 build_clamping_params(stream);
1100
1101 continue;
1102 }
1103 }
1104 */
1105
1106 if (!pipe_ctx)
1107 return DC_ERROR_UNEXPECTED;
1108
1109 build_pipe_hw_param(pipe_ctx);
1110 return DC_OK;
1111 }
1112
dcn10_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1113 enum dc_status dcn10_add_stream_to_ctx(
1114 struct dc *dc,
1115 struct dc_state *new_ctx,
1116 struct dc_stream_state *dc_stream)
1117 {
1118 enum dc_status result = DC_ERROR_UNEXPECTED;
1119
1120 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1121
1122 if (result == DC_OK)
1123 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1124
1125
1126 if (result == DC_OK)
1127 result = build_mapped_resource(dc, new_ctx, dc_stream);
1128
1129 return result;
1130 }
1131
dcn10_acquire_idle_pipe_for_layer(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)1132 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
1133 struct dc_state *context,
1134 const struct resource_pool *pool,
1135 struct dc_stream_state *stream)
1136 {
1137 struct resource_context *res_ctx = &context->res_ctx;
1138 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1139 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1140
1141 if (!head_pipe) {
1142 ASSERT(0);
1143 return NULL;
1144 }
1145
1146 if (!idle_pipe)
1147 return NULL;
1148
1149 idle_pipe->stream = head_pipe->stream;
1150 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1151 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1152 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1153
1154 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1155 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1156 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1157 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1158
1159 return idle_pipe;
1160 }
1161
dcn10_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)1162 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1163 const struct dc_dcc_surface_param *input,
1164 struct dc_surface_dcc_cap *output)
1165 {
1166 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1167 dc->res_pool->hubbub,
1168 input,
1169 output);
1170 }
1171
dcn10_destroy_resource_pool(struct resource_pool ** pool)1172 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1173 {
1174 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1175
1176 dcn10_resource_destruct(dcn10_pool);
1177 kfree(dcn10_pool);
1178 *pool = NULL;
1179 }
1180
dcn10_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)1181 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1182 {
1183 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1184 && caps->max_video_width != 0
1185 && plane_state->src_rect.width > caps->max_video_width)
1186 return DC_FAIL_SURFACE_VALIDATE;
1187
1188 return DC_OK;
1189 }
1190
dcn10_validate_global(struct dc * dc,struct dc_state * context)1191 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1192 {
1193 int i, j;
1194 bool video_down_scaled = false;
1195 bool video_large = false;
1196 bool desktop_large = false;
1197 bool dcc_disabled = false;
1198
1199 for (i = 0; i < context->stream_count; i++) {
1200 if (context->stream_status[i].plane_count == 0)
1201 continue;
1202
1203 if (context->stream_status[i].plane_count > 2)
1204 return DC_FAIL_UNSUPPORTED_1;
1205
1206 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1207 struct dc_plane_state *plane =
1208 context->stream_status[i].plane_states[j];
1209
1210
1211 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1212
1213 if (plane->src_rect.width > plane->dst_rect.width ||
1214 plane->src_rect.height > plane->dst_rect.height)
1215 video_down_scaled = true;
1216
1217 if (plane->src_rect.width >= 3840)
1218 video_large = true;
1219
1220 } else {
1221 if (plane->src_rect.width >= 3840)
1222 desktop_large = true;
1223 if (!plane->dcc.enable)
1224 dcc_disabled = true;
1225 }
1226 }
1227 }
1228
1229 /*
1230 * Workaround: On DCN10 there is UMC issue that causes underflow when
1231 * playing 4k video on 4k desktop with video downscaled and single channel
1232 * memory
1233 */
1234 if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1235 dc->dcn_soc->number_of_channels == 1)
1236 return DC_FAIL_SURFACE_VALIDATE;
1237
1238 return DC_OK;
1239 }
1240
dcn10_get_default_swizzle_mode(struct dc_plane_state * plane_state)1241 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)
1242 {
1243 enum dc_status result = DC_OK;
1244
1245 enum surface_pixel_format surf_pix_format = plane_state->format;
1246 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1247
1248 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1249
1250 if (bpp == 64)
1251 swizzle = DC_SW_64KB_D;
1252 else
1253 swizzle = DC_SW_64KB_S;
1254
1255 plane_state->tiling_info.gfx9.swizzle = swizzle;
1256 return result;
1257 }
1258
dcn10_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1259 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1260 struct resource_context *res_ctx,
1261 const struct resource_pool *pool,
1262 struct dc_stream_state *stream)
1263 {
1264 int i;
1265 int j = -1;
1266 struct dc_link *link = stream->link;
1267
1268 for (i = 0; i < pool->stream_enc_count; i++) {
1269 if (!res_ctx->is_stream_enc_acquired[i] &&
1270 pool->stream_enc[i]) {
1271 /* Store first available for MST second display
1272 * in daisy chain use case
1273 */
1274 j = i;
1275 if (pool->stream_enc[i]->id ==
1276 link->link_enc->preferred_engine)
1277 return pool->stream_enc[i];
1278 }
1279 }
1280
1281 /*
1282 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1283 */
1284
1285 if (j >= 0)
1286 return pool->stream_enc[j];
1287
1288 return NULL;
1289 }
1290
1291 static const struct dc_cap_funcs cap_funcs = {
1292 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1293 };
1294
1295 static const struct resource_funcs dcn10_res_pool_funcs = {
1296 .destroy = dcn10_destroy_resource_pool,
1297 .link_enc_create = dcn10_link_encoder_create,
1298 .validate_bandwidth = dcn_validate_bandwidth,
1299 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1300 .validate_plane = dcn10_validate_plane,
1301 .validate_global = dcn10_validate_global,
1302 .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1303 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode,
1304 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1305 };
1306
read_pipe_fuses(struct dc_context * ctx)1307 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1308 {
1309 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1310 /* RV1 support max 4 pipes */
1311 value = value & 0xf;
1312 return value;
1313 }
1314
dcn10_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn10_resource_pool * pool)1315 static bool dcn10_resource_construct(
1316 uint8_t num_virtual_links,
1317 struct dc *dc,
1318 struct dcn10_resource_pool *pool)
1319 {
1320 int i;
1321 int j;
1322 struct dc_context *ctx = dc->ctx;
1323 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1324
1325 ctx->dc_bios->regs = &bios_regs;
1326
1327 if (ctx->dce_version == DCN_VERSION_1_01)
1328 pool->base.res_cap = &rv2_res_cap;
1329 else
1330 pool->base.res_cap = &res_cap;
1331 pool->base.funcs = &dcn10_res_pool_funcs;
1332
1333 /*
1334 * TODO fill in from actual raven resource when we create
1335 * more than virtual encoder
1336 */
1337
1338 /*************************************************
1339 * Resource + asic cap harcoding *
1340 *************************************************/
1341 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1342
1343 /* max pipe num for ASIC before check pipe fuses */
1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1345
1346 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1347 pool->base.pipe_count = 3;
1348 dc->caps.max_video_width = 3840;
1349 dc->caps.max_downscale_ratio = 200;
1350 dc->caps.i2c_speed_in_khz = 100;
1351 dc->caps.max_cursor_size = 256;
1352 dc->caps.max_slave_planes = 1;
1353 dc->caps.is_apu = true;
1354 dc->caps.post_blend_color_processing = false;
1355 dc->caps.extended_aux_timeout_support = false;
1356
1357 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1358 dc->caps.force_dp_tps4_for_cp2520 = true;
1359
1360 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1361 dc->debug = debug_defaults_drv;
1362 else
1363 dc->debug = debug_defaults_diags;
1364
1365 /*************************************************
1366 * Create resources *
1367 *************************************************/
1368
1369 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1370 dcn10_clock_source_create(ctx, ctx->dc_bios,
1371 CLOCK_SOURCE_COMBO_PHY_PLL0,
1372 &clk_src_regs[0], false);
1373 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1374 dcn10_clock_source_create(ctx, ctx->dc_bios,
1375 CLOCK_SOURCE_COMBO_PHY_PLL1,
1376 &clk_src_regs[1], false);
1377 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1378 dcn10_clock_source_create(ctx, ctx->dc_bios,
1379 CLOCK_SOURCE_COMBO_PHY_PLL2,
1380 &clk_src_regs[2], false);
1381
1382 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1383 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1384 dcn10_clock_source_create(ctx, ctx->dc_bios,
1385 CLOCK_SOURCE_COMBO_PHY_PLL3,
1386 &clk_src_regs[3], false);
1387 }
1388
1389 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1390
1391 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1392 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1393
1394 pool->base.dp_clock_source =
1395 dcn10_clock_source_create(ctx, ctx->dc_bios,
1396 CLOCK_SOURCE_ID_DP_DTO,
1397 /* todo: not reuse phy_pll registers */
1398 &clk_src_regs[0], true);
1399
1400 for (i = 0; i < pool->base.clk_src_count; i++) {
1401 if (pool->base.clock_sources[i] == NULL) {
1402 dm_error("DC: failed to create clock sources!\n");
1403 BREAK_TO_DEBUGGER();
1404 goto fail;
1405 }
1406 }
1407
1408 pool->base.dmcu = dcn10_dmcu_create(ctx,
1409 &dmcu_regs,
1410 &dmcu_shift,
1411 &dmcu_mask);
1412 if (pool->base.dmcu == NULL) {
1413 dm_error("DC: failed to create dmcu!\n");
1414 BREAK_TO_DEBUGGER();
1415 goto fail;
1416 }
1417
1418 pool->base.abm = dce_abm_create(ctx,
1419 &abm_regs,
1420 &abm_shift,
1421 &abm_mask);
1422 if (pool->base.abm == NULL) {
1423 dm_error("DC: failed to create abm!\n");
1424 BREAK_TO_DEBUGGER();
1425 goto fail;
1426 }
1427
1428 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1429 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1430 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1431
1432 if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1433 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
1434 struct dcn_ip_params *dcn_ip = dc->dcn_ip;
1435 struct display_mode_lib *dml = &dc->dml;
1436
1437 dml->ip.max_num_dpp = 3;
1438 /* TODO how to handle 23.84? */
1439 dcn_soc->dram_clock_change_latency = 23;
1440 dcn_ip->max_num_dpp = 3;
1441 }
1442 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1443 dc->dcn_soc->urgent_latency = 3;
1444 dc->debug.disable_dmcu = true;
1445 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1446 }
1447
1448
1449 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1450 ASSERT(dc->dcn_soc->number_of_channels < 3);
1451 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1452 dc->dcn_soc->number_of_channels = 2;
1453
1454 if (dc->dcn_soc->number_of_channels == 1) {
1455 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1456 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1457 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1458 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1459 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1460 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1461 }
1462 }
1463
1464 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1465
1466 /*
1467 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1468 * implemented. So AZ D3 should work.For issue 197007. *
1469 */
1470 if (pool->base.pp_smu != NULL
1471 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1472 dc->debug.az_endpoint_mute_only = false;
1473
1474 if (!dc->debug.disable_pplib_clock_request)
1475 dcn_bw_update_from_pplib(dc);
1476 dcn_bw_sync_calcs_and_dml(dc);
1477 if (!dc->debug.disable_pplib_wm_range) {
1478 dc->res_pool = &pool->base;
1479 dcn_bw_notify_pplib_of_wm_ranges(dc);
1480 }
1481
1482 {
1483 struct irq_service_init_data init_data;
1484 init_data.ctx = dc->ctx;
1485 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1486 if (!pool->base.irqs)
1487 goto fail;
1488 }
1489
1490 /* index to valid pipe resource */
1491 j = 0;
1492 /* mem input -> ipp -> dpp -> opp -> TG */
1493 for (i = 0; i < pool->base.pipe_count; i++) {
1494 /* if pipe is disabled, skip instance of HW pipe,
1495 * i.e, skip ASIC register instance
1496 */
1497 if ((pipe_fuses & (1 << i)) != 0)
1498 continue;
1499
1500 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1501 if (pool->base.hubps[j] == NULL) {
1502 BREAK_TO_DEBUGGER();
1503 dm_error(
1504 "DC: failed to create memory input!\n");
1505 goto fail;
1506 }
1507
1508 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1509 if (pool->base.ipps[j] == NULL) {
1510 BREAK_TO_DEBUGGER();
1511 dm_error(
1512 "DC: failed to create input pixel processor!\n");
1513 goto fail;
1514 }
1515
1516 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1517 if (pool->base.dpps[j] == NULL) {
1518 BREAK_TO_DEBUGGER();
1519 dm_error(
1520 "DC: failed to create dpp!\n");
1521 goto fail;
1522 }
1523
1524 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1525 if (pool->base.opps[j] == NULL) {
1526 BREAK_TO_DEBUGGER();
1527 dm_error(
1528 "DC: failed to create output pixel processor!\n");
1529 goto fail;
1530 }
1531
1532 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1533 ctx, i);
1534 if (pool->base.timing_generators[j] == NULL) {
1535 BREAK_TO_DEBUGGER();
1536 dm_error("DC: failed to create tg!\n");
1537 goto fail;
1538 }
1539 /* check next valid pipe */
1540 j++;
1541 }
1542
1543 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1544 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1545 if (pool->base.engines[i] == NULL) {
1546 BREAK_TO_DEBUGGER();
1547 dm_error(
1548 "DC:failed to create aux engine!!\n");
1549 goto fail;
1550 }
1551 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1552 if (pool->base.hw_i2cs[i] == NULL) {
1553 BREAK_TO_DEBUGGER();
1554 dm_error(
1555 "DC:failed to create hw i2c!!\n");
1556 goto fail;
1557 }
1558 pool->base.sw_i2cs[i] = NULL;
1559 }
1560
1561 /* valid pipe num */
1562 pool->base.pipe_count = j;
1563 pool->base.timing_generator_count = j;
1564
1565 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1566 * the value may be changed
1567 */
1568 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1569 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1570
1571 pool->base.mpc = dcn10_mpc_create(ctx);
1572 if (pool->base.mpc == NULL) {
1573 BREAK_TO_DEBUGGER();
1574 dm_error("DC: failed to create mpc!\n");
1575 goto fail;
1576 }
1577
1578 pool->base.hubbub = dcn10_hubbub_create(ctx);
1579 if (pool->base.hubbub == NULL) {
1580 BREAK_TO_DEBUGGER();
1581 dm_error("DC: failed to create hubbub!\n");
1582 goto fail;
1583 }
1584
1585 if (!resource_construct(num_virtual_links, dc, &pool->base,
1586 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1587 &res_create_funcs : &res_create_maximus_funcs)))
1588 goto fail;
1589
1590 dcn10_hw_sequencer_construct(dc);
1591 dc->caps.max_planes = pool->base.pipe_count;
1592
1593 for (i = 0; i < dc->caps.max_planes; ++i)
1594 dc->caps.planes[i] = plane_cap;
1595
1596 dc->cap_funcs = cap_funcs;
1597
1598 return true;
1599
1600 fail:
1601
1602 dcn10_resource_destruct(pool);
1603
1604 return false;
1605 }
1606
dcn10_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1607 struct resource_pool *dcn10_create_resource_pool(
1608 const struct dc_init_data *init_data,
1609 struct dc *dc)
1610 {
1611 struct dcn10_resource_pool *pool =
1612 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1613
1614 if (!pool)
1615 return NULL;
1616
1617 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1618 return &pool->base;
1619
1620 kfree(pool);
1621 BREAK_TO_DEBUGGER();
1622 return NULL;
1623 }
1624