1 /* $NetBSD: amdgpu_dce80_timing_generator.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce80_timing_generator.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31 #include "dm_services.h"
32
33 /* include DCE8 register header files */
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
36
37 #include "dc_types.h"
38
39 #include "include/grph_object_id.h"
40 #include "include/logger_interface.h"
41 #include "../dce110/dce110_timing_generator.h"
42 #include "dce80_timing_generator.h"
43
44 #include "timing_generator.h"
45
46 enum black_color_format {
47 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
48 BLACK_COLOR_FORMAT_RGB_LIMITED,
49 BLACK_COLOR_FORMAT_YUV_TV,
50 BLACK_COLOR_FORMAT_YUV_CV,
51 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
52
53 BLACK_COLOR_FORMAT_COUNT
54 };
55
56 static const struct dce110_timing_generator_offsets reg_offsets[] = {
57 {
58 .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
59 .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
60 },
61 {
62 .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
63 .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
64 },
65 {
66 .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
67 .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
68 },
69 {
70 .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
71 .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
72 },
73 {
74 .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
75 .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
76 },
77 {
78 .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
79 .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
80 }
81 };
82
83 #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
84
85 #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
86 #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
87
88 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
89 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
90 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
91
program_pix_dur(struct timing_generator * tg,uint32_t pix_clk_100hz)92 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
93 {
94 uint64_t pix_dur;
95 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
96 + DCE110TG_FROM_TG(tg)->offsets.dmif;
97 uint32_t value = dm_read_reg(tg->ctx, addr);
98
99 if (pix_clk_100hz == 0)
100 return;
101
102 pix_dur = div_u64(10000000000ull, pix_clk_100hz);
103
104 set_reg_field_value(
105 value,
106 pix_dur,
107 DPG_PIPE_ARBITRATION_CONTROL1,
108 PIXEL_DURATION);
109
110 dm_write_reg(tg->ctx, addr, value);
111 }
112
program_timing(struct timing_generator * tg,const struct dc_crtc_timing * timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,const enum signal_type signal,bool use_vbios)113 static void program_timing(struct timing_generator *tg,
114 const struct dc_crtc_timing *timing,
115 int vready_offset,
116 int vstartup_start,
117 int vupdate_offset,
118 int vupdate_width,
119 const enum signal_type signal,
120 bool use_vbios)
121 {
122 if (!use_vbios)
123 program_pix_dur(tg, timing->pix_clk_100hz);
124
125 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
126 }
127
dce80_timing_generator_enable_advanced_request(struct timing_generator * tg,bool enable,const struct dc_crtc_timing * timing)128 static void dce80_timing_generator_enable_advanced_request(
129 struct timing_generator *tg,
130 bool enable,
131 const struct dc_crtc_timing *timing)
132 {
133 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
134 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
135 uint32_t value = dm_read_reg(tg->ctx, addr);
136
137 if (enable) {
138 set_reg_field_value(
139 value,
140 0,
141 CRTC_START_LINE_CONTROL,
142 CRTC_LEGACY_REQUESTOR_EN);
143 } else {
144 set_reg_field_value(
145 value,
146 1,
147 CRTC_START_LINE_CONTROL,
148 CRTC_LEGACY_REQUESTOR_EN);
149 }
150
151 if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
152 set_reg_field_value(
153 value,
154 3,
155 CRTC_START_LINE_CONTROL,
156 CRTC_ADVANCED_START_LINE_POSITION);
157 set_reg_field_value(
158 value,
159 0,
160 CRTC_START_LINE_CONTROL,
161 CRTC_PREFETCH_EN);
162 } else {
163 set_reg_field_value(
164 value,
165 4,
166 CRTC_START_LINE_CONTROL,
167 CRTC_ADVANCED_START_LINE_POSITION);
168 set_reg_field_value(
169 value,
170 1,
171 CRTC_START_LINE_CONTROL,
172 CRTC_PREFETCH_EN);
173 }
174
175 set_reg_field_value(
176 value,
177 1,
178 CRTC_START_LINE_CONTROL,
179 CRTC_PROGRESSIVE_START_LINE_EARLY);
180
181 set_reg_field_value(
182 value,
183 1,
184 CRTC_START_LINE_CONTROL,
185 CRTC_INTERLACE_START_LINE_EARLY);
186
187 dm_write_reg(tg->ctx, addr, value);
188 }
189
190 static const struct timing_generator_funcs dce80_tg_funcs = {
191 .validate_timing = dce110_tg_validate_timing,
192 .program_timing = program_timing,
193 .enable_crtc = dce110_timing_generator_enable_crtc,
194 .disable_crtc = dce110_timing_generator_disable_crtc,
195 .is_counter_moving = dce110_timing_generator_is_counter_moving,
196 .get_position = dce110_timing_generator_get_position,
197 .get_frame_count = dce110_timing_generator_get_vblank_counter,
198 .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
199 .set_early_control = dce110_timing_generator_set_early_control,
200 .wait_for_state = dce110_tg_wait_for_state,
201 .set_blank = dce110_tg_set_blank,
202 .is_blanked = dce110_tg_is_blanked,
203 .set_colors = dce110_tg_set_colors,
204 .set_overscan_blank_color =
205 dce110_timing_generator_set_overscan_color_black,
206 .set_blank_color = dce110_timing_generator_program_blank_color,
207 .disable_vga = dce110_timing_generator_disable_vga,
208 .did_triggered_reset_occur =
209 dce110_timing_generator_did_triggered_reset_occur,
210 .setup_global_swap_lock =
211 dce110_timing_generator_setup_global_swap_lock,
212 .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
213 .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
214 .tear_down_global_swap_lock =
215 dce110_timing_generator_tear_down_global_swap_lock,
216 .set_drr = dce110_timing_generator_set_drr,
217 .set_static_screen_control =
218 dce110_timing_generator_set_static_screen_control,
219 .set_test_pattern = dce110_timing_generator_set_test_pattern,
220 .arm_vert_intr = dce110_arm_vert_intr,
221
222 /* DCE8.0 overrides */
223 .enable_advanced_request =
224 dce80_timing_generator_enable_advanced_request,
225 .configure_crc = dce110_configure_crc,
226 .get_crc = dce110_get_crc,
227 };
228
dce80_timing_generator_construct(struct dce110_timing_generator * tg110,struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)229 void dce80_timing_generator_construct(
230 struct dce110_timing_generator *tg110,
231 struct dc_context *ctx,
232 uint32_t instance,
233 const struct dce110_timing_generator_offsets *offsets)
234 {
235 tg110->controller_id = CONTROLLER_ID_D0 + instance;
236 tg110->base.inst = instance;
237 tg110->offsets = *offsets;
238 tg110->derived_offsets = reg_offsets[instance];
239
240 tg110->base.funcs = &dce80_tg_funcs;
241
242 tg110->base.ctx = ctx;
243 tg110->base.bp = ctx->dc_bios;
244
245 tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
246 tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
247
248 tg110->min_h_blank = 56;
249 tg110->min_h_front_porch = 4;
250 tg110->min_h_back_porch = 4;
251 }
252
253